From: Luke Kenneth Casson Leighton Date: Mon, 24 Aug 2020 14:13:31 +0000 (+0000) Subject: update to latest test_issuer.il X-Git-Tag: partial-core-ls180-gdsii~82 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=08dcfbd0092dbd9a53c0aaa98057be161d4fff23;p=soclayout.git update to latest test_issuer.il --- diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il index 3943305..b9a3441 100644 --- a/experiments9/non_generated/test_issuer.il +++ b/experiments9/non_generated/test_issuer.il @@ -1,8 +1,195 @@ attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec19" -module \dec19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.p" +module \p + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.n" +module \n + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.p" +module \p$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.n" +module \n$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.input" +module \input + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -15,40 +202,54 @@ module \dec19 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \alu_op__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -122,1447 +323,246 @@ module \dec19 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \alu_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \alu_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 31 \alu_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \alu_op__write_cr0$13 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 10 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $24 + end process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] + assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch { \alu_op__invert_in } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + case 1'1 + assign \a $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" + case + assign \a \ra + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch$1 process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \function_unit 11'00010000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \function_unit 11'00000000010 - end + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \a sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \form 5'01001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \form 5'00111 - end + assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \b \rb sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \internal_op 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \internal_op 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \internal_op 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \internal_op 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \internal_op 7'0100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \internal_op 7'1000110 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \internal_op 7'0000000 - end + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \b + assign \rb$21 \rb sync init end process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \in1_sel 3'011 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in1_sel 3'000 + assign \xer_ca$23 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:56" + attribute \nmigen.decoding "ZERO/0" + case 2'00 + assign \xer_ca$23 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:58" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \xer_ca$23 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" + attribute \nmigen.decoding "CA/2" + case 2'10 + assign \xer_ca$23 \xer_ca end sync init end process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \in2_sel 4'1100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in2_sel 4'0000 + assign \xer_so$22 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" + switch { \alu_op__oe__oe_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" + case 1'1 + assign \xer_so$22 \xer_so end sync init end process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \in3_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in3_sel 2'00 - end + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \out_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \out_sel 2'00 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \cr_in 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \cr_in 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \cr_out 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \ldst_len 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \upd 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \rc_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \cry_in 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \asmcode 8'01101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \asmcode 8'00100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \asmcode 8'00100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \asmcode 8'00100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \asmcode 8'00101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \asmcode 8'00101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \asmcode 8'00101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \asmcode 8'00101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \asmcode 8'00101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \asmcode 8'00010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \asmcode 8'00010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \asmcode 8'00011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \asmcode 8'10001111 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \inv_a 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \inv_out 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \cry_out 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \br 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \sgn_ext 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \rsrv 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \is_32b 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \sgn 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \lk 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000000000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100000001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010000001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0100100001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011100001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000100001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0111000001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0110100001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0011000001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000010000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'1000110000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0010010110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 10'0000010010 - assign \sgl_pipe 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgl_pipe 1'1 - end - sync init - end - process $group_25 - assign \opcode_switch$1 5'00000 - assign \opcode_switch$1 \opcode_in [5:1] + assign \alu_op__insn_type$2 7'0000000 + assign \alu_op__fn_unit$3 11'00000000000 + assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__imm_ok$5 1'0 + assign \alu_op__rc__rc$6 1'0 + assign \alu_op__rc__rc_ok$7 1'0 + assign \alu_op__oe__oe$8 1'0 + assign \alu_op__oe__oe_ok$9 1'0 + assign \alu_op__invert_in$10 1'0 + assign \alu_op__zero_a$11 1'0 + assign \alu_op__invert_out$12 1'0 + assign \alu_op__write_cr0$13 1'0 + assign \alu_op__input_carry$14 2'00 + assign \alu_op__output_carry$15 1'0 + assign \alu_op__is_32bit$16 1'0 + assign \alu_op__is_signed$17 1'0 + assign \alu_op__data_len$18 4'0000 + assign \alu_op__insn$19 32'00000000000000000000000000000000 + assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec30" -module \dec30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.main" +module \main + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -1575,40 +575,54 @@ module \dec30 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \alu_op__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -1682,1014 +696,1002 @@ module \dec30 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \alu_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \alu_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 31 \alu_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \alu_op__write_cr0$13 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 4 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 42 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 43 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 44 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 45 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 46 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 47 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 50 \xer_so$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" + wire width 1 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:53" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:53" + cell $not $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn [21] + connect \Y $24 + end process $group_0 - assign \opcode_switch 4'0000 - assign \opcode_switch \opcode_in [4:1] + assign \is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + switch { $22 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + case 1'1 + assign \is_32bit $24 + end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" + wire width 64 \a_i process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \function_unit 11'00000001000 + assign \a_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + switch { \is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + case 1'1 + assign \a_i { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" + case + assign \a_i \ra end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" + wire width 64 \b_i process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \form 5'10101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \form 5'10101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \form 5'10100 + assign \b_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + switch { \is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + case 1'1 + assign \b_i { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" + case + assign \b_i \rb end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" + wire width 66 \add_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" + wire width 1 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" + cell $eq $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + cell $eq $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + cell $or $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $26 + connect \B $28 + connect \Y $30 + end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \internal_op 7'0111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \internal_op 7'0111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \internal_op 7'0111010 + assign \add_a 66'000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch { $30 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + case 1'1 + assign \add_a { 1'0 \a_i \xer_ca [0] } end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:58" + wire width 66 \add_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" + cell $eq $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + cell $eq $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + cell $or $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $32 + connect \B $34 + connect \Y $36 + end process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \in1_sel 3'000 + assign \add_b 66'000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch { $36 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + case 1'1 + assign \add_b { 1'0 \b_i 1'1 } end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" + wire width 66 \add_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" + cell $eq $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + cell $eq $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + cell $or $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $38 + connect \B $40 + connect \Y $42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" + wire width 67 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" + wire width 67 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" + cell $add $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 66 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 67 + connect \A \add_a + connect \B \add_b + connect \Y $45 + end + connect $44 $45 process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \in2_sel 4'0001 + assign \add_o 66'000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch { $42 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + case 1'1 + assign \add_o $44 [65:0] end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + cell $eq $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 1'1 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" + cell $eq $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 2'10 + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + cell $eq $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 3'100 + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:136" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" + wire width 8 \eqs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:136" + cell $reduce_or $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $53 + end process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \in3_sel 2'01 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + assign \o \add_o [64:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + assign \o \add_o [64:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + switch { $47 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + case 1'1 + assign \o { { \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] } \ra [7:0] } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" + switch { $49 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" + case 1'1 + assign \o { { \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] } \ra [15:0] } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + switch { $51 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + case 1'1 + assign \o { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + assign \o [0] $53 end sync init end process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \out_sel 2'10 + assign \o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + assign \o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + assign \o_ok 1'0 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" + wire width 2 \ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + cell $xor $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [32] + connect \B \b_i [32] + connect \Y $55 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + cell $xor $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B $55 + connect \Y $57 + end process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \cr_in 3'000 + assign \ca 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + assign \ca [0] \add_o [65] + assign \ca [1] $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 end sync init end process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \cr_out 3'001 + assign \xer_ca$20 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + assign \xer_ca$20 \ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 end sync init end process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \ldst_len 4'0000 + assign \xer_ca_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + assign \xer_ca_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + wire width 2 \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [0] + connect \B \add_o [64] + connect \Y $59 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire width 1 $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [63] + connect \B \b_i [63] + connect \Y $62 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $not $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $62 + connect \Y $61 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $and $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $59 + connect \B $61 + connect \Y $65 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [1] + connect \B \add_o [32] + connect \Y $67 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire width 1 $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [31] + connect \B \b_i [31] + connect \Y $70 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $not $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $70 + connect \Y $69 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $and $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $67 + connect \B $69 + connect \Y $73 + end process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \upd 2'00 + assign \ov 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + assign \ov [0] $65 + assign \ov [1] $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 end sync init end process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \rc_sel 2'10 + assign \xer_ov 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + assign \xer_ov \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 end sync init end process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \cry_in 2'00 + assign \xer_ov_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + assign \xer_ov_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" + wire width 8 \src1 process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \asmcode 8'10010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \asmcode 8'10010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \asmcode 8'10010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \asmcode 8'10010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \asmcode 8'10010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \asmcode 8'10010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \asmcode 8'10010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \asmcode 8'10010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \asmcode 8'10010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \asmcode 8'10010001 + assign \src1 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + assign \src1 \ra [7:0] end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + cell $eq $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [7:0] + connect \Y $75 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + cell $eq $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [15:8] + connect \Y $77 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + cell $eq $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [23:16] + connect \Y $79 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + cell $eq $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [31:24] + connect \Y $81 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + cell $eq $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [39:32] + connect \Y $83 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + wire width 1 $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + cell $eq $86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [47:40] + connect \Y $85 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + cell $eq $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [55:48] + connect \Y $87 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:135" + cell $eq $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [63:56] + connect \Y $89 + end process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \inv_a 1'0 + assign \eqs 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + assign \eqs [0] $75 + assign \eqs [1] $77 + assign \eqs [2] $79 + assign \eqs [3] $81 + assign \eqs [4] $83 + assign \eqs [5] $85 + assign \eqs [6] $87 + assign \eqs [7] $89 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:138" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:138" + cell $reduce_or $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $91 + end process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \inv_out 1'0 + assign \cr_a 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + assign \cr_a { 1'0 $91 2'00 } end sync init end process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \cry_out 1'0 + assign \cr_a_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:80" + switch \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:85" + attribute \nmigen.decoding "OP_CMP/10" + case 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + attribute \nmigen.decoding "OP_ADD/2" + case 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:118" + attribute \nmigen.decoding "OP_EXTS/31" + case 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + attribute \nmigen.decoding "OP_CMPEQB/12" + case 7'0001100 + assign \cr_a_ok 1'1 end sync init end process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \br 1'0 - end + assign \xer_so$21 1'0 + assign \xer_so$21 \xer_so sync init end process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \sgn_ext 1'0 - end + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'0111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 4'1001 - assign \sgl_pipe 1'0 - end + assign \alu_op__insn_type$2 7'0000000 + assign \alu_op__fn_unit$3 11'00000000000 + assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__imm_ok$5 1'0 + assign \alu_op__rc__rc$6 1'0 + assign \alu_op__rc__rc_ok$7 1'0 + assign \alu_op__oe__oe$8 1'0 + assign \alu_op__oe__oe_ok$9 1'0 + assign \alu_op__invert_in$10 1'0 + assign \alu_op__zero_a$11 1'0 + assign \alu_op__invert_out$12 1'0 + assign \alu_op__write_cr0$13 1'0 + assign \alu_op__input_carry$14 2'00 + assign \alu_op__output_carry$15 1'0 + assign \alu_op__is_32bit$16 1'0 + assign \alu_op__is_signed$17 1'0 + assign \alu_op__data_len$18 4'0000 + assign \alu_op__insn$19 32'00000000000000000000000000000000 + assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub10" -module \dec_sub10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1" +module \pipe1 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -2702,40 +1704,124 @@ module \dec_sub10 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 6 \alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 8 \alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 12 \alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__write_cr0$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -2809,1014 +1895,151 @@ module \dec_sub10 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 36 \alu_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 37 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 38 \alu_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 39 \alu_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 41 \alu_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 43 \alu_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 47 \alu_op__write_cr0$13 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \function_unit 11'00000000010 - end - sync init - end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \form 5'10001 - end - sync init - end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \internal_op 7'0000010 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in1_sel 3'001 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in2_sel 4'0000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \out_sel 2'01 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cry_in 2'10 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \asmcode 8'00000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \asmcode 8'00001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'00000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \asmcode 8'00000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \asmcode 8'00000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \asmcode 8'00000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \asmcode 8'00001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \asmcode 8'00001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \asmcode 8'00001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \asmcode 8'00001110 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cry_out 1'1 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \lk 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 48 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 54 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 56 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 57 \xer_ca$21 + cell \p$1 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgl_pipe 1'0 - end - sync init + cell \n$2 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub28" -module \dec_sub28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -3829,40 +2052,54 @@ module \dec_sub28 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \input_alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$22 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -3936,1014 +2173,191 @@ module \dec_sub28 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type$23 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \input_alu_op__fn_unit$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__imm$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__imm_data__imm_ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__rc__rc_ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__oe__oe_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__zero_a$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__write_cr0$34 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \function_unit 11'00000010000 - end - sync init - end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \form 5'01000 - end - sync init - end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \internal_op 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \internal_op 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \internal_op 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \internal_op 7'1000011 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \in1_sel 3'100 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \out_sel 2'10 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'00001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \asmcode 8'00010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \asmcode 8'00011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \asmcode 8'00011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \asmcode 8'01000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \asmcode 8'10000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \asmcode 8'10000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \asmcode 8'10000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \asmcode 8'10000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \asmcode 8'11001010 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \sgl_pipe 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__output_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_alu_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \input_xer_so$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$44 + cell \input \input + connect \muxid \input_muxid + connect \alu_op__insn_type \input_alu_op__insn_type + connect \alu_op__fn_unit \input_alu_op__fn_unit + connect \alu_op__imm_data__imm \input_alu_op__imm_data__imm + connect \alu_op__imm_data__imm_ok \input_alu_op__imm_data__imm_ok + connect \alu_op__rc__rc \input_alu_op__rc__rc + connect \alu_op__rc__rc_ok \input_alu_op__rc__rc_ok + connect \alu_op__oe__oe \input_alu_op__oe__oe + connect \alu_op__oe__oe_ok \input_alu_op__oe__oe_ok + connect \alu_op__invert_in \input_alu_op__invert_in + connect \alu_op__zero_a \input_alu_op__zero_a + connect \alu_op__invert_out \input_alu_op__invert_out + connect \alu_op__write_cr0 \input_alu_op__write_cr0 + connect \alu_op__input_carry \input_alu_op__input_carry + connect \alu_op__output_carry \input_alu_op__output_carry + connect \alu_op__is_32bit \input_alu_op__is_32bit + connect \alu_op__is_signed \input_alu_op__is_signed + connect \alu_op__data_len \input_alu_op__data_len + connect \alu_op__insn \input_alu_op__insn + connect \ra \input_ra + connect \rb \input_rb + connect \xer_so \input_xer_so + connect \xer_ca \input_xer_ca + connect \muxid$1 \input_muxid$22 + connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 + connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 + connect \alu_op__imm_data__imm$4 \input_alu_op__imm_data__imm$25 + connect \alu_op__imm_data__imm_ok$5 \input_alu_op__imm_data__imm_ok$26 + connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 + connect \alu_op__rc__rc_ok$7 \input_alu_op__rc__rc_ok$28 + connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 + connect \alu_op__oe__oe_ok$9 \input_alu_op__oe__oe_ok$30 + connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 + connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 + connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 + connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 + connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 + connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 + connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 + connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 + connect \alu_op__data_len$18 \input_alu_op__data_len$39 + connect \alu_op__insn$19 \input_alu_op__insn$40 + connect \ra$20 \input_ra$41 + connect \rb$21 \input_rb$42 + connect \xer_so$22 \input_xer_so$43 + connect \xer_ca$23 \input_xer_ca$44 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub0" -module \dec_sub0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -4956,40 +2370,54 @@ module \dec_sub0 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \main_alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$45 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -5063,582 +2491,849 @@ module \dec_sub0 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type$46 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \main_alu_op__fn_unit$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__imm$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__imm_data__imm_ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__rc__rc_ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__oe__oe_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__write_cr0$57 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_alu_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \main_xer_ca$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_xer_so$65 + cell \main \main + connect \muxid \main_muxid + connect \alu_op__insn_type \main_alu_op__insn_type + connect \alu_op__fn_unit \main_alu_op__fn_unit + connect \alu_op__imm_data__imm \main_alu_op__imm_data__imm + connect \alu_op__imm_data__imm_ok \main_alu_op__imm_data__imm_ok + connect \alu_op__rc__rc \main_alu_op__rc__rc + connect \alu_op__rc__rc_ok \main_alu_op__rc__rc_ok + connect \alu_op__oe__oe \main_alu_op__oe__oe + connect \alu_op__oe__oe_ok \main_alu_op__oe__oe_ok + connect \alu_op__invert_in \main_alu_op__invert_in + connect \alu_op__zero_a \main_alu_op__zero_a + connect \alu_op__invert_out \main_alu_op__invert_out + connect \alu_op__write_cr0 \main_alu_op__write_cr0 + connect \alu_op__input_carry \main_alu_op__input_carry + connect \alu_op__output_carry \main_alu_op__output_carry + connect \alu_op__is_32bit \main_alu_op__is_32bit + connect \alu_op__is_signed \main_alu_op__is_signed + connect \alu_op__data_len \main_alu_op__data_len + connect \alu_op__insn \main_alu_op__insn + connect \ra \main_ra + connect \rb \main_rb + connect \xer_so \main_xer_so + connect \xer_ca \main_xer_ca + connect \muxid$1 \main_muxid$45 + connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 + connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 + connect \alu_op__imm_data__imm$4 \main_alu_op__imm_data__imm$48 + connect \alu_op__imm_data__imm_ok$5 \main_alu_op__imm_data__imm_ok$49 + connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 + connect \alu_op__rc__rc_ok$7 \main_alu_op__rc__rc_ok$51 + connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 + connect \alu_op__oe__oe_ok$9 \main_alu_op__oe__oe_ok$53 + connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 + connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 + connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 + connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 + connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 + connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 + connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 + connect \alu_op__data_len$18 \main_alu_op__data_len$62 + connect \alu_op__insn$19 \main_alu_op__insn$63 + connect \o \main_o + connect \o_ok \main_o_ok + connect \cr_a \main_cr_a + connect \cr_a_ok \main_cr_a_ok + connect \xer_ca$20 \main_xer_ca$64 + connect \xer_ca_ok \main_xer_ca_ok + connect \xer_ov \main_xer_ov + connect \xer_ov_ok \main_xer_ov_ok + connect \xer_so$21 \main_xer_so$65 + end process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] + assign \input_muxid 2'00 + assign \input_muxid \muxid$1 sync init end process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \function_unit 11'00001000000 - end + assign \input_alu_op__insn_type 7'0000000 + assign \input_alu_op__fn_unit 11'00000000000 + assign \input_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_alu_op__imm_data__imm_ok 1'0 + assign \input_alu_op__rc__rc 1'0 + assign \input_alu_op__rc__rc_ok 1'0 + assign \input_alu_op__oe__oe 1'0 + assign \input_alu_op__oe__oe_ok 1'0 + assign \input_alu_op__invert_in 1'0 + assign \input_alu_op__zero_a 1'0 + assign \input_alu_op__invert_out 1'0 + assign \input_alu_op__write_cr0 1'0 + assign \input_alu_op__input_carry 2'00 + assign \input_alu_op__output_carry 1'0 + assign \input_alu_op__is_32bit 1'0 + assign \input_alu_op__is_signed 1'0 + assign \input_alu_op__data_len 4'0000 + assign \input_alu_op__insn 32'00000000000000000000000000000000 + assign { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in { \input_alu_op__oe__oe_ok \input_alu_op__oe__oe } { \input_alu_op__rc__rc_ok \input_alu_op__rc__rc } { \input_alu_op__imm_data__imm_ok \input_alu_op__imm_data__imm } \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } sync init end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \form 5'11000 - end + process $group_19 + assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_ra \ra sync init end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \internal_op 7'0001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \internal_op 7'0111011 - end + process $group_20 + assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_rb \rb sync init end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in1_sel 3'000 - end + process $group_21 + assign \input_xer_so 1'0 + assign \input_xer_so \xer_so$20 sync init end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in2_sel 4'0000 - end + process $group_22 + assign \input_xer_ca 2'00 + assign \input_xer_ca \xer_ca$21 sync init end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in3_sel 2'00 - end + process $group_23 + assign \main_muxid 2'00 + assign \main_muxid \input_muxid$22 sync init end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \out_sel 2'01 - end + process $group_24 + assign \main_alu_op__insn_type 7'0000000 + assign \main_alu_op__fn_unit 11'00000000000 + assign \main_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_alu_op__imm_data__imm_ok 1'0 + assign \main_alu_op__rc__rc 1'0 + assign \main_alu_op__rc__rc_ok 1'0 + assign \main_alu_op__oe__oe 1'0 + assign \main_alu_op__oe__oe_ok 1'0 + assign \main_alu_op__invert_in 1'0 + assign \main_alu_op__zero_a 1'0 + assign \main_alu_op__invert_out 1'0 + assign \main_alu_op__write_cr0 1'0 + assign \main_alu_op__input_carry 2'00 + assign \main_alu_op__output_carry 1'0 + assign \main_alu_op__is_32bit 1'0 + assign \main_alu_op__is_signed 1'0 + assign \main_alu_op__data_len 4'0000 + assign \main_alu_op__insn 32'00000000000000000000000000000000 + assign { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in { \main_alu_op__oe__oe_ok \main_alu_op__oe__oe } { \main_alu_op__rc__rc_ok \main_alu_op__rc__rc } { \main_alu_op__imm_data__imm_ok \main_alu_op__imm_data__imm } \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 { \input_alu_op__oe__oe_ok$30 \input_alu_op__oe__oe$29 } { \input_alu_op__rc__rc_ok$28 \input_alu_op__rc__rc$27 } { \input_alu_op__imm_data__imm_ok$26 \input_alu_op__imm_data__imm$25 } \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } sync init end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_in 3'011 - end + process $group_42 + assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_ra \input_ra$41 sync init end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_out 3'000 - end + process $group_43 + assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_rb \input_rb$42 sync init end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \ldst_len 4'0000 - end + process $group_44 + assign \main_xer_so 1'0 + assign \main_xer_so \input_xer_so$43 sync init end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \upd 2'00 - end + process $group_45 + assign \main_xer_ca 2'00 + assign \main_xer_ca \input_xer_ca$44 sync init end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rc_sel 2'00 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$66 + process $group_46 + assign \p_valid_i$66 1'0 + assign \p_valid_i$66 \p_valid_i sync init end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_in 2'00 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_47 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i sync init end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'00011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \asmcode 8'00011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \asmcode 8'00011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \asmcode 8'10011001 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$66 + connect \B \p_ready_o + connect \Y $67 + end + process $group_48 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $67 sync init end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_a 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$69 + process $group_49 + assign \muxid$69 2'00 + assign \muxid$69 \main_muxid$45 sync init end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_out 1'0 - end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$70 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_op__fn_unit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__imm$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__imm_data__imm_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__rc__rc$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__rc__rc_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__oe__oe$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__oe__oe_ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__invert_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__zero_a$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__write_cr0$81 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__output_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__is_32bit$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__is_signed$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$87 + process $group_50 + assign \alu_op__insn_type$70 7'0000000 + assign \alu_op__fn_unit$71 11'00000000000 + assign \alu_op__imm_data__imm$72 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__imm_ok$73 1'0 + assign \alu_op__rc__rc$74 1'0 + assign \alu_op__rc__rc_ok$75 1'0 + assign \alu_op__oe__oe$76 1'0 + assign \alu_op__oe__oe_ok$77 1'0 + assign \alu_op__invert_in$78 1'0 + assign \alu_op__zero_a$79 1'0 + assign \alu_op__invert_out$80 1'0 + assign \alu_op__write_cr0$81 1'0 + assign \alu_op__input_carry$82 2'00 + assign \alu_op__output_carry$83 1'0 + assign \alu_op__is_32bit$84 1'0 + assign \alu_op__is_signed$85 1'0 + assign \alu_op__data_len$86 4'0000 + assign \alu_op__insn$87 32'00000000000000000000000000000000 + assign { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__oe_ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__rc_ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__imm_ok$73 \alu_op__imm_data__imm$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 { \main_alu_op__oe__oe_ok$53 \main_alu_op__oe__oe$52 } { \main_alu_op__rc__rc_ok$51 \main_alu_op__rc__rc$50 } { \main_alu_op__imm_data__imm_ok$49 \main_alu_op__imm_data__imm$48 } \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } sync init end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_out 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$89 + process $group_68 + assign \o$88 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$89 1'0 + assign { \o_ok$89 \o$88 } { \main_o_ok \main_o } sync init end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$91 + process $group_70 + assign \cr_a$90 4'0000 + assign \cr_a_ok$91 1'0 + assign { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$93 + process $group_72 + assign \xer_ca$92 2'00 + assign \xer_ca_ok$93 1'0 + assign { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$95 + process $group_74 + assign \xer_ov$94 2'00 + assign \xer_ov_ok$95 1'0 + assign { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$98 + process $group_76 + assign \xer_so$96 1'0 + assign \xer_so_ok$97 1'0 + assign { \xer_so_ok$97 \xer_so$96 } { \xer_so_ok$98 \main_xer_so$65 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_78 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 end sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn_ext 1'0 + process $group_79 + assign \muxid$next \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$next \muxid$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$next \muxid$69 end sync init + update \muxid 2'00 + sync posedge \coresync_clk + update \muxid \muxid$next end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rsrv 1'0 + process $group_80 + assign \alu_op__insn_type$next \alu_op__insn_type + assign \alu_op__fn_unit$next \alu_op__fn_unit + assign \alu_op__imm_data__imm$next \alu_op__imm_data__imm + assign \alu_op__imm_data__imm_ok$next \alu_op__imm_data__imm_ok + assign \alu_op__rc__rc$next \alu_op__rc__rc + assign \alu_op__rc__rc_ok$next \alu_op__rc__rc_ok + assign \alu_op__oe__oe$next \alu_op__oe__oe + assign \alu_op__oe__oe_ok$next \alu_op__oe__oe_ok + assign \alu_op__invert_in$next \alu_op__invert_in + assign \alu_op__zero_a$next \alu_op__zero_a + assign \alu_op__invert_out$next \alu_op__invert_out + assign \alu_op__write_cr0$next \alu_op__write_cr0 + assign \alu_op__input_carry$next \alu_op__input_carry + assign \alu_op__output_carry$next \alu_op__output_carry + assign \alu_op__is_32bit$next \alu_op__is_32bit + assign \alu_op__is_signed$next \alu_op__is_signed + assign \alu_op__data_len$next \alu_op__data_len + assign \alu_op__insn$next \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \alu_op__insn$next \alu_op__data_len$next \alu_op__is_signed$next \alu_op__is_32bit$next \alu_op__output_carry$next \alu_op__input_carry$next \alu_op__write_cr0$next \alu_op__invert_out$next \alu_op__zero_a$next \alu_op__invert_in$next { \alu_op__oe__oe_ok$next \alu_op__oe__oe$next } { \alu_op__rc__rc_ok$next \alu_op__rc__rc$next } { \alu_op__imm_data__imm_ok$next \alu_op__imm_data__imm$next } \alu_op__fn_unit$next \alu_op__insn_type$next } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__oe_ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__rc_ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__imm_ok$73 \alu_op__imm_data__imm$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \alu_op__insn$next \alu_op__data_len$next \alu_op__is_signed$next \alu_op__is_32bit$next \alu_op__output_carry$next \alu_op__input_carry$next \alu_op__write_cr0$next \alu_op__invert_out$next \alu_op__zero_a$next \alu_op__invert_in$next { \alu_op__oe__oe_ok$next \alu_op__oe__oe$next } { \alu_op__rc__rc_ok$next \alu_op__rc__rc$next } { \alu_op__imm_data__imm_ok$next \alu_op__imm_data__imm$next } \alu_op__fn_unit$next \alu_op__insn_type$next } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__oe_ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__rc_ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__imm_ok$73 \alu_op__imm_data__imm$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__imm_ok$next 1'0 + assign \alu_op__rc__rc$next 1'0 + assign \alu_op__rc__rc_ok$next 1'0 + assign \alu_op__oe__oe$next 1'0 + assign \alu_op__oe__oe_ok$next 1'0 + end + sync init + update \alu_op__insn_type 7'0000000 + update \alu_op__fn_unit 11'00000000000 + update \alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_op__imm_data__imm_ok 1'0 + update \alu_op__rc__rc 1'0 + update \alu_op__rc__rc_ok 1'0 + update \alu_op__oe__oe 1'0 + update \alu_op__oe__oe_ok 1'0 + update \alu_op__invert_in 1'0 + update \alu_op__zero_a 1'0 + update \alu_op__invert_out 1'0 + update \alu_op__write_cr0 1'0 + update \alu_op__input_carry 2'00 + update \alu_op__output_carry 1'0 + update \alu_op__is_32bit 1'0 + update \alu_op__is_signed 1'0 + update \alu_op__data_len 4'0000 + update \alu_op__insn 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \alu_op__insn_type \alu_op__insn_type$next + update \alu_op__fn_unit \alu_op__fn_unit$next + update \alu_op__imm_data__imm \alu_op__imm_data__imm$next + update \alu_op__imm_data__imm_ok \alu_op__imm_data__imm_ok$next + update \alu_op__rc__rc \alu_op__rc__rc$next + update \alu_op__rc__rc_ok \alu_op__rc__rc_ok$next + update \alu_op__oe__oe \alu_op__oe__oe$next + update \alu_op__oe__oe_ok \alu_op__oe__oe_ok$next + update \alu_op__invert_in \alu_op__invert_in$next + update \alu_op__zero_a \alu_op__zero_a$next + update \alu_op__invert_out \alu_op__invert_out$next + update \alu_op__write_cr0 \alu_op__write_cr0$next + update \alu_op__input_carry \alu_op__input_carry$next + update \alu_op__output_carry \alu_op__output_carry$next + update \alu_op__is_32bit \alu_op__is_32bit$next + update \alu_op__is_signed \alu_op__is_signed$next + update \alu_op__data_len \alu_op__data_len$next + update \alu_op__insn \alu_op__insn$next + end + process $group_98 + assign \o$next \o + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$next } { \o_ok$89 \o$88 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$next } { \o_ok$89 \o$88 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \o_ok$next 1'0 end sync init + update \o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 + sync posedge \coresync_clk + update \o \o$next + update \o_ok \o_ok$next end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \is_32b 1'0 + process $group_100 + assign \cr_a$next \cr_a + assign \cr_a_ok$next \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$91 \cr_a$90 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$91 \cr_a$90 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cr_a_ok$next 1'0 end sync init + update \cr_a 4'0000 + update \cr_a_ok 1'0 + sync posedge \coresync_clk + update \cr_a \cr_a$next + update \cr_a_ok \cr_a_ok$next end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn 1'0 + process $group_102 + assign \xer_ca$next \xer_ca + assign \xer_ca_ok$next \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$93 \xer_ca$92 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$93 \xer_ca$92 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ca_ok$next 1'0 end sync init + update \xer_ca 2'00 + update \xer_ca_ok 1'0 + sync posedge \coresync_clk + update \xer_ca \xer_ca$next + update \xer_ca_ok \xer_ca_ok$next end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \lk 1'0 + process $group_104 + assign \xer_ov$next \xer_ov + assign \xer_ov_ok$next \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$95 \xer_ov$94 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$95 \xer_ov$94 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ov_ok$next 1'0 end sync init + update \xer_ov 2'00 + update \xer_ov_ok 1'0 + sync posedge \coresync_clk + update \xer_ov \xer_ov$next + update \xer_ov_ok \xer_ov_ok$next end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgl_pipe 1'0 + process $group_106 + assign \xer_so$next \xer_so + assign \xer_so_ok$next \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$97 \xer_so$96 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$97 \xer_so$96 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_so_ok$next 1'0 end + sync init + update \xer_so 1'0 + update \xer_so_ok 1'0 + sync posedge \coresync_clk + update \xer_so \xer_so$next + update \xer_so_ok \xer_so_ok$next + end + process $group_108 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_109 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data sync init end + connect \xer_so_ok$98 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub26" -module \dec_sub26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.p" +module \p$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.n" +module \n$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.output" +module \output + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -5651,40 +3346,58 @@ module \dec_sub26 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \alu_op__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 23 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 24 \xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 25 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -5758,1374 +3471,526 @@ module \dec_sub26 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 26 \alu_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 27 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 28 \alu_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \alu_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 31 \alu_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \alu_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 36 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \alu_op__write_cr0$13 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 38 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 42 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 43 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 44 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 45 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 46 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 47 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 48 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 49 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 50 \xer_ov$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 51 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 52 \xer_so$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 53 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" + wire width 65 \o$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + wire width 65 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + wire width 64 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + cell $not $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + cell $pos $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A $28 + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $31 + end + process $group_0 + assign \o$26 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + switch { \alu_op__invert_out } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + case 1'1 + assign \o$26 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + case + assign \o$26 $31 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + wire width 64 \target + process $group_1 + assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \target \o$26 [63:0] + sync init + end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \form 5'10000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \form 5'10000 - end + assign \xer_ca$23 2'00 + assign \xer_ca$23 \xer_ca sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \internal_op 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \internal_op 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \internal_op 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \internal_op 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \internal_op 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \internal_op 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \internal_op 7'0111101 - end + assign \xer_ca_ok 1'0 + assign \xer_ca_ok \alu_op__output_carry sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + wire width 1 \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + cell $eq $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $33 + end process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in1_sel 3'000 - end + assign \is_cmp 1'0 + assign \is_cmp $33 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + wire width 1 \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + cell $eq $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001100 + connect \Y $35 + end process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in2_sel 4'1010 - end + assign \is_cmpeqb 1'0 + assign \is_cmpeqb $35 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + wire width 1 \msb_test process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in3_sel 2'01 - end + assign \msb_test 1'0 + assign \msb_test \target [63] sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 1 \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + cell $reduce_bool $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $37 + end process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \out_sel 2'10 - end + assign \is_nzero 1'0 + assign \is_nzero $37 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + wire width 1 \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $not $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $and $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $39 + connect \Y $41 + end process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cr_in 3'000 + assign \is_positive 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_positive \msb_test + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_positive $41 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" + wire width 1 \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $not $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $and $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $43 + connect \Y $45 + end process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cr_out 3'001 + assign \is_negative 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_negative $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_negative \msb_test end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + cell $not $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $47 + end process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \ldst_len 4'0000 + assign \cr0 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + switch { \is_cmpeqb } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + case 1'1 + assign \cr0 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + case + assign \cr0 { \is_negative \is_positive $47 \xer_so$25 } end sync init end process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \upd 2'00 - end + assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o$20 \o$26 [63:0] sync init end process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \rc_sel 2'10 - end + assign \o_ok$21 1'0 + assign \o_ok$21 \o_ok sync init end process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cry_in 2'00 - end + assign \cr_a$22 4'0000 + assign \cr_a$22 \cr0 sync init end process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \asmcode 8'00100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'00100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \asmcode 8'00100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \asmcode 8'00100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \asmcode 8'01000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \asmcode 8'01000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \asmcode 8'01000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \asmcode 8'01000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \asmcode 8'10001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \asmcode 8'10001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \asmcode 8'10001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \asmcode 8'10001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \asmcode 8'10001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \asmcode 8'10011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \asmcode 8'10011110 - end + assign \cr_a_ok 1'0 + assign \cr_a_ok \alu_op__write_cr0 sync init end process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \inv_a 1'0 - end + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \inv_out 1'0 - end + assign \alu_op__insn_type$2 7'0000000 + assign \alu_op__fn_unit$3 11'00000000000 + assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__imm_ok$5 1'0 + assign \alu_op__rc__rc$6 1'0 + assign \alu_op__rc__rc_ok$7 1'0 + assign \alu_op__oe__oe$8 1'0 + assign \alu_op__oe__oe_ok$9 1'0 + assign \alu_op__invert_in$10 1'0 + assign \alu_op__zero_a$11 1'0 + assign \alu_op__invert_out$12 1'0 + assign \alu_op__write_cr0$13 1'0 + assign \alu_op__input_carry$14 2'00 + assign \alu_op__output_carry$15 1'0 + assign \alu_op__is_32bit$16 1'0 + assign \alu_op__is_signed$17 1'0 + assign \alu_op__data_len$18 4'0000 + assign \alu_op__insn$19 32'00000000000000000000000000000000 + assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } sync init end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cry_out 1'1 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" + wire width 1 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + cell $and $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__oe_ok + connect \Y $49 + end + process $group_34 + assign \oe 1'0 + assign \oe $49 sync init end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" + wire width 1 \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" + cell $or $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $51 + end + process $group_35 + assign \so 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \so $51 end sync init end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgn_ext 1'0 + process $group_36 + assign \xer_so$25 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_so$25 \so end sync init end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \rsrv 1'0 + process $group_37 + assign \xer_so_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_so_ok 1'1 end sync init end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \is_32b 1'0 + process $group_38 + assign \xer_ov$24 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_ov$24 \xer_ov end sync init end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgn 1'1 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgl_pipe 1'0 + process $group_39 + assign \xer_ov_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_ov_ok 1'1 end sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub19" -module \dec_sub19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2" +module \pipe2 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \alu_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -7138,40 +4003,72 @@ module \dec_sub19 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \alu_op__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -7245,582 +4142,219 @@ module \dec_sub19 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 37 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \alu_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \alu_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \alu_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \alu_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__invert_out$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__write_cr0$13$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \function_unit 11'10000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \function_unit 11'10000000000 - end - sync init - end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \form 5'01010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \form 5'01010 - end - sync init - end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \internal_op 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \internal_op 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \internal_op 7'0110001 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in1_sel 3'100 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in2_sel 4'0000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \out_sel 2'11 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \rc_sel 2'00 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'01101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \asmcode 8'01101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \asmcode 8'01101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \asmcode 8'01110111 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \lk 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 48 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 54 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 55 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 56 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 57 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 58 \xer_ca$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 59 \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 60 \xer_ov$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 61 \xer_ov_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$27$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 62 \xer_so$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$28$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 63 \xer_so_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$29$next + cell \p$3 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgl_pipe 1'0 - end - sync init + cell \n$4 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub22" -module \dec_sub22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -7833,40 +4367,58 @@ module \dec_sub22 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \output_alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$30 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -7940,1374 +4492,782 @@ module \dec_sub22 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type$31 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \output_alu_op__fn_unit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__imm$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__imm_data__imm_ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__rc__rc$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__rc__rc_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__oe__oe$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__oe__oe_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__invert_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__zero_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__invert_out$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__write_cr0$42 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__output_carry$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__is_32bit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_alu_op__is_signed$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_o_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so_ok + cell \output \output + connect \muxid \output_muxid + connect \alu_op__insn_type \output_alu_op__insn_type + connect \alu_op__fn_unit \output_alu_op__fn_unit + connect \alu_op__imm_data__imm \output_alu_op__imm_data__imm + connect \alu_op__imm_data__imm_ok \output_alu_op__imm_data__imm_ok + connect \alu_op__rc__rc \output_alu_op__rc__rc + connect \alu_op__rc__rc_ok \output_alu_op__rc__rc_ok + connect \alu_op__oe__oe \output_alu_op__oe__oe + connect \alu_op__oe__oe_ok \output_alu_op__oe__oe_ok + connect \alu_op__invert_in \output_alu_op__invert_in + connect \alu_op__zero_a \output_alu_op__zero_a + connect \alu_op__invert_out \output_alu_op__invert_out + connect \alu_op__write_cr0 \output_alu_op__write_cr0 + connect \alu_op__input_carry \output_alu_op__input_carry + connect \alu_op__output_carry \output_alu_op__output_carry + connect \alu_op__is_32bit \output_alu_op__is_32bit + connect \alu_op__is_signed \output_alu_op__is_signed + connect \alu_op__data_len \output_alu_op__data_len + connect \alu_op__insn \output_alu_op__insn + connect \o \output_o + connect \o_ok \output_o_ok + connect \cr_a \output_cr_a + connect \xer_ca \output_xer_ca + connect \xer_ov \output_xer_ov + connect \xer_so \output_xer_so + connect \muxid$1 \output_muxid$30 + connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 + connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 + connect \alu_op__imm_data__imm$4 \output_alu_op__imm_data__imm$33 + connect \alu_op__imm_data__imm_ok$5 \output_alu_op__imm_data__imm_ok$34 + connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 + connect \alu_op__rc__rc_ok$7 \output_alu_op__rc__rc_ok$36 + connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 + connect \alu_op__oe__oe_ok$9 \output_alu_op__oe__oe_ok$38 + connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 + connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 + connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 + connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 + connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 + connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 + connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 + connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 + connect \alu_op__data_len$18 \output_alu_op__data_len$47 + connect \alu_op__insn$19 \output_alu_op__insn$48 + connect \o$20 \output_o$49 + connect \o_ok$21 \output_o_ok$50 + connect \cr_a$22 \output_cr_a$51 + connect \cr_a_ok \output_cr_a_ok + connect \xer_ca$23 \output_xer_ca$52 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_ov$24 \output_xer_ov$53 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so$25 \output_xer_so$54 + connect \xer_so_ok \output_xer_so_ok + end process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] + assign \output_muxid 2'00 + assign \output_muxid \muxid sync init end process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \function_unit 11'00000000010 - end + assign \output_alu_op__insn_type 7'0000000 + assign \output_alu_op__fn_unit 11'00000000000 + assign \output_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_alu_op__imm_data__imm_ok 1'0 + assign \output_alu_op__rc__rc 1'0 + assign \output_alu_op__rc__rc_ok 1'0 + assign \output_alu_op__oe__oe 1'0 + assign \output_alu_op__oe__oe_ok 1'0 + assign \output_alu_op__invert_in 1'0 + assign \output_alu_op__zero_a 1'0 + assign \output_alu_op__invert_out 1'0 + assign \output_alu_op__write_cr0 1'0 + assign \output_alu_op__input_carry 2'00 + assign \output_alu_op__output_carry 1'0 + assign \output_alu_op__is_32bit 1'0 + assign \output_alu_op__is_signed 1'0 + assign \output_alu_op__data_len 4'0000 + assign \output_alu_op__insn 32'00000000000000000000000000000000 + assign { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in { \output_alu_op__oe__oe_ok \output_alu_op__oe__oe } { \output_alu_op__rc__rc_ok \output_alu_op__rc__rc } { \output_alu_op__imm_data__imm_ok \output_alu_op__imm_data__imm } \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } sync init end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \form 5'01000 - end + process $group_19 + assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_o_ok 1'0 + assign { \output_o_ok \output_o } { \o_ok \o } sync init end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \internal_op 7'0100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \internal_op 7'0000001 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$55 + process $group_21 + assign \output_cr_a 4'0000 + assign \cr_a_ok$55 1'0 + assign { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } sync init end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in1_sel 3'000 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$56 + process $group_23 + assign \output_xer_ca 2'00 + assign \xer_ca_ok$56 1'0 + assign { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } sync init end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in2_sel 4'0000 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$57 + process $group_25 + assign \output_xer_ov 2'00 + assign \xer_ov_ok$57 1'0 + assign { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } sync init end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in3_sel 2'00 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$58 + process $group_27 + assign \output_xer_so 1'0 + assign \xer_so_ok$58 1'0 + assign { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } sync init end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \out_sel 2'00 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$59 + process $group_29 + assign \p_valid_i$59 1'0 + assign \p_valid_i$59 \p_valid_i sync init end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cr_in 3'000 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_30 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i sync init end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cr_out 3'000 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$59 + connect \B \p_ready_o + connect \Y $60 + end + process $group_31 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $60 sync init end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \ldst_len 4'0000 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$62 + process $group_32 + assign \muxid$62 2'00 + assign \muxid$62 \output_muxid$30 sync init end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \upd 2'00 - end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$63 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_op__fn_unit$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__imm$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__imm_data__imm_ok$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__rc__rc$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__rc__rc_ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__oe__oe$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__oe__oe_ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__invert_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__zero_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__invert_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__write_cr0$74 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__output_carry$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__is_32bit$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__is_signed$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$80 + process $group_33 + assign \alu_op__insn_type$63 7'0000000 + assign \alu_op__fn_unit$64 11'00000000000 + assign \alu_op__imm_data__imm$65 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__imm_ok$66 1'0 + assign \alu_op__rc__rc$67 1'0 + assign \alu_op__rc__rc_ok$68 1'0 + assign \alu_op__oe__oe$69 1'0 + assign \alu_op__oe__oe_ok$70 1'0 + assign \alu_op__invert_in$71 1'0 + assign \alu_op__zero_a$72 1'0 + assign \alu_op__invert_out$73 1'0 + assign \alu_op__write_cr0$74 1'0 + assign \alu_op__input_carry$75 2'00 + assign \alu_op__output_carry$76 1'0 + assign \alu_op__is_32bit$77 1'0 + assign \alu_op__is_signed$78 1'0 + assign \alu_op__data_len$79 4'0000 + assign \alu_op__insn$80 32'00000000000000000000000000000000 + assign { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__oe_ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__rc_ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__imm_ok$66 \alu_op__imm_data__imm$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 { \output_alu_op__oe__oe_ok$38 \output_alu_op__oe__oe$37 } { \output_alu_op__rc__rc_ok$36 \output_alu_op__rc__rc$35 } { \output_alu_op__imm_data__imm_ok$34 \output_alu_op__imm_data__imm$33 } \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } sync init end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \rc_sel 2'00 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$82 + process $group_51 + assign \o$81 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$82 1'0 + assign { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } sync init end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$84 + process $group_53 + assign \cr_a$83 4'0000 + assign \cr_a_ok$84 1'0 + assign { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$86 + process $group_55 + assign \xer_ca$85 2'00 + assign \xer_ca_ok$86 1'0 + assign { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$88 + process $group_57 + assign \xer_ov$87 2'00 + assign \xer_ov_ok$88 1'0 + assign { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$90 + process $group_59 + assign \xer_so$89 1'0 + assign \xer_so_ok$90 1'0 + assign { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_61 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 end sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \asmcode 8'00101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \asmcode 8'00101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \asmcode 8'00110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \asmcode 8'00110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \asmcode 8'01001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'01001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \asmcode 8'01011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \asmcode 8'01100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \asmcode 8'10100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \asmcode 8'10101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \asmcode 8'10101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \asmcode 8'10110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \asmcode 8'10110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \asmcode 8'10110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \asmcode 8'11000101 + process $group_62 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$62 end sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \inv_a 1'0 + process $group_63 + assign \alu_op__insn_type$2$next \alu_op__insn_type$2 + assign \alu_op__fn_unit$3$next \alu_op__fn_unit$3 + assign \alu_op__imm_data__imm$4$next \alu_op__imm_data__imm$4 + assign \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm_ok$5 + assign \alu_op__rc__rc$6$next \alu_op__rc__rc$6 + assign \alu_op__rc__rc_ok$7$next \alu_op__rc__rc_ok$7 + assign \alu_op__oe__oe$8$next \alu_op__oe__oe$8 + assign \alu_op__oe__oe_ok$9$next \alu_op__oe__oe_ok$9 + assign \alu_op__invert_in$10$next \alu_op__invert_in$10 + assign \alu_op__zero_a$11$next \alu_op__zero_a$11 + assign \alu_op__invert_out$12$next \alu_op__invert_out$12 + assign \alu_op__write_cr0$13$next \alu_op__write_cr0$13 + assign \alu_op__input_carry$14$next \alu_op__input_carry$14 + assign \alu_op__output_carry$15$next \alu_op__output_carry$15 + assign \alu_op__is_32bit$16$next \alu_op__is_32bit$16 + assign \alu_op__is_signed$17$next \alu_op__is_signed$17 + assign \alu_op__data_len$18$next \alu_op__data_len$18 + assign \alu_op__insn$19$next \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_in$10$next { \alu_op__oe__oe_ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__rc_ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__oe_ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__rc_ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__imm_ok$66 \alu_op__imm_data__imm$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_in$10$next { \alu_op__oe__oe_ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__rc_ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__oe_ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__rc_ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__imm_ok$66 \alu_op__imm_data__imm$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__imm_ok$5$next 1'0 + assign \alu_op__rc__rc$6$next 1'0 + assign \alu_op__rc__rc_ok$7$next 1'0 + assign \alu_op__oe__oe$8$next 1'0 + assign \alu_op__oe__oe_ok$9$next 1'0 end sync init + update \alu_op__insn_type$2 7'0000000 + update \alu_op__fn_unit$3 11'00000000000 + update \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_op__imm_data__imm_ok$5 1'0 + update \alu_op__rc__rc$6 1'0 + update \alu_op__rc__rc_ok$7 1'0 + update \alu_op__oe__oe$8 1'0 + update \alu_op__oe__oe_ok$9 1'0 + update \alu_op__invert_in$10 1'0 + update \alu_op__zero_a$11 1'0 + update \alu_op__invert_out$12 1'0 + update \alu_op__write_cr0$13 1'0 + update \alu_op__input_carry$14 2'00 + update \alu_op__output_carry$15 1'0 + update \alu_op__is_32bit$16 1'0 + update \alu_op__is_signed$17 1'0 + update \alu_op__data_len$18 4'0000 + update \alu_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \alu_op__insn_type$2 \alu_op__insn_type$2$next + update \alu_op__fn_unit$3 \alu_op__fn_unit$3$next + update \alu_op__imm_data__imm$4 \alu_op__imm_data__imm$4$next + update \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm_ok$5$next + update \alu_op__rc__rc$6 \alu_op__rc__rc$6$next + update \alu_op__rc__rc_ok$7 \alu_op__rc__rc_ok$7$next + update \alu_op__oe__oe$8 \alu_op__oe__oe$8$next + update \alu_op__oe__oe_ok$9 \alu_op__oe__oe_ok$9$next + update \alu_op__invert_in$10 \alu_op__invert_in$10$next + update \alu_op__zero_a$11 \alu_op__zero_a$11$next + update \alu_op__invert_out$12 \alu_op__invert_out$12$next + update \alu_op__write_cr0$13 \alu_op__write_cr0$13$next + update \alu_op__input_carry$14 \alu_op__input_carry$14$next + update \alu_op__output_carry$15 \alu_op__output_carry$15$next + update \alu_op__is_32bit$16 \alu_op__is_32bit$16$next + update \alu_op__is_signed$17 \alu_op__is_signed$17$next + update \alu_op__data_len$18 \alu_op__data_len$18$next + update \alu_op__insn$19 \alu_op__insn$19$next end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \inv_out 1'0 + process $group_81 + assign \o$20$next \o$20 + assign \o_ok$21$next \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$21$next \o$20$next } { \o_ok$82 \o$81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$21$next \o$20$next } { \o_ok$82 \o$81 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \o_ok$21$next 1'0 end sync init + update \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok$21 1'0 + sync posedge \coresync_clk + update \o$20 \o$20$next + update \o_ok$21 \o_ok$21$next end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cry_out 1'0 + process $group_83 + assign \cr_a$22$next \cr_a$22 + assign \cr_a_ok$23$next \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$84 \cr_a$83 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$84 \cr_a$83 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cr_a_ok$23$next 1'0 end sync init + update \cr_a$22 4'0000 + update \cr_a_ok$23 1'0 + sync posedge \coresync_clk + update \cr_a$22 \cr_a$22$next + update \cr_a_ok$23 \cr_a_ok$23$next end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \br 1'0 + process $group_85 + assign \xer_ca$24$next \xer_ca$24 + assign \xer_ca_ok$25$next \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ca_ok$25$next \xer_ca$24$next } { \xer_ca_ok$86 \xer_ca$85 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ca_ok$25$next \xer_ca$24$next } { \xer_ca_ok$86 \xer_ca$85 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ca_ok$25$next 1'0 end sync init + update \xer_ca$24 2'00 + update \xer_ca_ok$25 1'0 + sync posedge \coresync_clk + update \xer_ca$24 \xer_ca$24$next + update \xer_ca_ok$25 \xer_ca_ok$25$next end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgn_ext 1'0 + process $group_87 + assign \xer_ov$26$next \xer_ov$26 + assign \xer_ov_ok$27$next \xer_ov_ok$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ov_ok$27$next \xer_ov$26$next } { \xer_ov_ok$88 \xer_ov$87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ov_ok$27$next \xer_ov$26$next } { \xer_ov_ok$88 \xer_ov$87 } end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ov_ok$27$next 1'0 end sync init + update \xer_ov$26 2'00 + update \xer_ov_ok$27 1'0 + sync posedge \coresync_clk + update \xer_ov$26 \xer_ov$26$next + update \xer_ov_ok$27 \xer_ov_ok$27$next end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \is_32b 1'0 + process $group_89 + assign \xer_so$28$next \xer_so$28 + assign \xer_so_ok$29$next \xer_so_ok$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_so_ok$29$next \xer_so$28$next } { \xer_so_ok$90 \xer_so$89 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_so_ok$29$next \xer_so$28$next } { \xer_so_ok$90 \xer_so$89 } end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_so_ok$29$next 1'0 end sync init + update \xer_so$28 1'0 + update \xer_so_ok$29 1'0 + sync posedge \coresync_clk + update \xer_so$28 \xer_so$28$next + update \xer_so_ok$29 \xer_so_ok$29$next end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \lk 1'0 - end + process $group_91 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy sync init end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgl_pipe 1'1 - end + process $group_92 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub9" -module \dec_sub9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0" +module \alu_alu0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 5 \xer_so_ok + attribute \src "simple/issuer.py:102" + wire width 1 input 6 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 8 \n_ready_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \alu_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -9320,40 +5280,80 @@ module \dec_sub9 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 10 \alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 11 \alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \alu_op__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 21 \alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 22 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 23 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 24 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 25 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 26 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 27 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 28 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 29 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 30 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 32 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 33 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 34 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 35 \xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 36 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 37 \p_ready_o + cell \p \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -9427,1492 +5427,788 @@ module \dec_sub9 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe1_alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe1_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe1_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid$3 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe1_alu_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__imm$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__imm_data__imm_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__rc__rc$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__rc__rc_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__oe__oe$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__oe__oe_ok$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__invert_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__zero_a$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__write_cr0$15 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_alu_op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe1_xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$23 + cell \pipe1 \pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \n_valid_o \pipe1_n_valid_o + connect \n_ready_i \pipe1_n_ready_i + connect \muxid \pipe1_muxid + connect \alu_op__insn_type \pipe1_alu_op__insn_type + connect \alu_op__fn_unit \pipe1_alu_op__fn_unit + connect \alu_op__imm_data__imm \pipe1_alu_op__imm_data__imm + connect \alu_op__imm_data__imm_ok \pipe1_alu_op__imm_data__imm_ok + connect \alu_op__rc__rc \pipe1_alu_op__rc__rc + connect \alu_op__rc__rc_ok \pipe1_alu_op__rc__rc_ok + connect \alu_op__oe__oe \pipe1_alu_op__oe__oe + connect \alu_op__oe__oe_ok \pipe1_alu_op__oe__oe_ok + connect \alu_op__invert_in \pipe1_alu_op__invert_in + connect \alu_op__zero_a \pipe1_alu_op__zero_a + connect \alu_op__invert_out \pipe1_alu_op__invert_out + connect \alu_op__write_cr0 \pipe1_alu_op__write_cr0 + connect \alu_op__input_carry \pipe1_alu_op__input_carry + connect \alu_op__output_carry \pipe1_alu_op__output_carry + connect \alu_op__is_32bit \pipe1_alu_op__is_32bit + connect \alu_op__is_signed \pipe1_alu_op__is_signed + connect \alu_op__data_len \pipe1_alu_op__data_len + connect \alu_op__insn \pipe1_alu_op__insn + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \xer_ca \pipe1_xer_ca + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_ov \pipe1_xer_ov + connect \xer_ov_ok \pipe1_xer_ov_ok + connect \xer_so \pipe1_xer_so + connect \xer_so_ok \pipe1_xer_so_ok + connect \p_valid_i \pipe1_p_valid_i + connect \p_ready_o \pipe1_p_ready_o + connect \muxid$1 \pipe1_muxid$3 + connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 + connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 + connect \alu_op__imm_data__imm$4 \pipe1_alu_op__imm_data__imm$6 + connect \alu_op__imm_data__imm_ok$5 \pipe1_alu_op__imm_data__imm_ok$7 + connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 + connect \alu_op__rc__rc_ok$7 \pipe1_alu_op__rc__rc_ok$9 + connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 + connect \alu_op__oe__oe_ok$9 \pipe1_alu_op__oe__oe_ok$11 + connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 + connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 + connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 + connect \alu_op__write_cr0$13 \pipe1_alu_op__write_cr0$15 + connect \alu_op__input_carry$14 \pipe1_alu_op__input_carry$16 + connect \alu_op__output_carry$15 \pipe1_alu_op__output_carry$17 + connect \alu_op__is_32bit$16 \pipe1_alu_op__is_32bit$18 + connect \alu_op__is_signed$17 \pipe1_alu_op__is_signed$19 + connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 + connect \alu_op__insn$19 \pipe1_alu_op__insn$21 + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \xer_so$20 \pipe1_xer_so$22 + connect \xer_ca$21 \pipe1_xer_ca$23 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe2_alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe2_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type$25 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe2_alu_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__imm$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__imm_data__imm_ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__rc__rc_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__oe__oe_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__write_cr0$36 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_alu_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe2_alu_op__data_len$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_ca_ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ov$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_ov_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_so$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_so_ok$52 + cell \pipe2 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe2_p_valid_i + connect \p_ready_o \pipe2_p_ready_o + connect \muxid \pipe2_muxid + connect \alu_op__insn_type \pipe2_alu_op__insn_type + connect \alu_op__fn_unit \pipe2_alu_op__fn_unit + connect \alu_op__imm_data__imm \pipe2_alu_op__imm_data__imm + connect \alu_op__imm_data__imm_ok \pipe2_alu_op__imm_data__imm_ok + connect \alu_op__rc__rc \pipe2_alu_op__rc__rc + connect \alu_op__rc__rc_ok \pipe2_alu_op__rc__rc_ok + connect \alu_op__oe__oe \pipe2_alu_op__oe__oe + connect \alu_op__oe__oe_ok \pipe2_alu_op__oe__oe_ok + connect \alu_op__invert_in \pipe2_alu_op__invert_in + connect \alu_op__zero_a \pipe2_alu_op__zero_a + connect \alu_op__invert_out \pipe2_alu_op__invert_out + connect \alu_op__write_cr0 \pipe2_alu_op__write_cr0 + connect \alu_op__input_carry \pipe2_alu_op__input_carry + connect \alu_op__output_carry \pipe2_alu_op__output_carry + connect \alu_op__is_32bit \pipe2_alu_op__is_32bit + connect \alu_op__is_signed \pipe2_alu_op__is_signed + connect \alu_op__data_len \pipe2_alu_op__data_len + connect \alu_op__insn \pipe2_alu_op__insn + connect \o \pipe2_o + connect \o_ok \pipe2_o_ok + connect \cr_a \pipe2_cr_a + connect \cr_a_ok \pipe2_cr_a_ok + connect \xer_ca \pipe2_xer_ca + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ov \pipe2_xer_ov + connect \xer_ov_ok \pipe2_xer_ov_ok + connect \xer_so \pipe2_xer_so + connect \xer_so_ok \pipe2_xer_so_ok + connect \n_valid_o \pipe2_n_valid_o + connect \n_ready_i \pipe2_n_ready_i + connect \muxid$1 \pipe2_muxid$24 + connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 + connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 + connect \alu_op__imm_data__imm$4 \pipe2_alu_op__imm_data__imm$27 + connect \alu_op__imm_data__imm_ok$5 \pipe2_alu_op__imm_data__imm_ok$28 + connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 + connect \alu_op__rc__rc_ok$7 \pipe2_alu_op__rc__rc_ok$30 + connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 + connect \alu_op__oe__oe_ok$9 \pipe2_alu_op__oe__oe_ok$32 + connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 + connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 + connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 + connect \alu_op__write_cr0$13 \pipe2_alu_op__write_cr0$36 + connect \alu_op__input_carry$14 \pipe2_alu_op__input_carry$37 + connect \alu_op__output_carry$15 \pipe2_alu_op__output_carry$38 + connect \alu_op__is_32bit$16 \pipe2_alu_op__is_32bit$39 + connect \alu_op__is_signed$17 \pipe2_alu_op__is_signed$40 + connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 + connect \alu_op__insn$19 \pipe2_alu_op__insn$42 + connect \o$20 \pipe2_o$43 + connect \o_ok$21 \pipe2_o_ok$44 + connect \cr_a$22 \pipe2_cr_a$45 + connect \cr_a_ok$23 \pipe2_cr_a_ok$46 + connect \xer_ca$24 \pipe2_xer_ca$47 + connect \xer_ca_ok$25 \pipe2_xer_ca_ok$48 + connect \xer_ov$26 \pipe2_xer_ov$49 + connect \xer_ov_ok$27 \pipe2_xer_ov_ok$50 + connect \xer_so$28 \pipe2_xer_so$51 + connect \xer_so_ok$29 \pipe2_xer_so_ok$52 + end process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] + assign \pipe2_p_valid_i 1'0 + assign \pipe2_p_valid_i \pipe1_n_valid_o sync init end process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \function_unit 11'00100000000 - end + assign \pipe1_n_ready_i 1'0 + assign \pipe1_n_ready_i \pipe2_p_ready_o sync init end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \form 5'10001 - end + assign \pipe2_muxid 2'00 + assign \pipe2_muxid \pipe1_muxid sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \internal_op 7'0110010 - end + assign \pipe2_alu_op__insn_type 7'0000000 + assign \pipe2_alu_op__fn_unit 11'00000000000 + assign \pipe2_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe2_alu_op__imm_data__imm_ok 1'0 + assign \pipe2_alu_op__rc__rc 1'0 + assign \pipe2_alu_op__rc__rc_ok 1'0 + assign \pipe2_alu_op__oe__oe 1'0 + assign \pipe2_alu_op__oe__oe_ok 1'0 + assign \pipe2_alu_op__invert_in 1'0 + assign \pipe2_alu_op__zero_a 1'0 + assign \pipe2_alu_op__invert_out 1'0 + assign \pipe2_alu_op__write_cr0 1'0 + assign \pipe2_alu_op__input_carry 2'00 + assign \pipe2_alu_op__output_carry 1'0 + assign \pipe2_alu_op__is_32bit 1'0 + assign \pipe2_alu_op__is_signed 1'0 + assign \pipe2_alu_op__data_len 4'0000 + assign \pipe2_alu_op__insn 32'00000000000000000000000000000000 + assign { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in { \pipe2_alu_op__oe__oe_ok \pipe2_alu_op__oe__oe } { \pipe2_alu_op__rc__rc_ok \pipe2_alu_op__rc__rc } { \pipe2_alu_op__imm_data__imm_ok \pipe2_alu_op__imm_data__imm } \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in { \pipe1_alu_op__oe__oe_ok \pipe1_alu_op__oe__oe } { \pipe1_alu_op__rc__rc_ok \pipe1_alu_op__rc__rc } { \pipe1_alu_op__imm_data__imm_ok \pipe1_alu_op__imm_data__imm } \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } sync init end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in1_sel 3'001 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \out_sel 2'01 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cr_out 3'001 - end + process $group_21 + assign \pipe2_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe2_o_ok 1'0 + assign { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } sync init end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \ldst_len 4'0000 - end + process $group_23 + assign \pipe2_cr_a 4'0000 + assign \pipe2_cr_a_ok 1'0 + assign { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } sync init end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \upd 2'00 - end + process $group_25 + assign \pipe2_xer_ca 2'00 + assign \pipe2_xer_ca_ok 1'0 + assign { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } sync init end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \rc_sel 2'10 - end + process $group_27 + assign \pipe2_xer_ov 2'00 + assign \pipe2_xer_ov_ok 1'0 + assign { \pipe2_xer_ov_ok \pipe2_xer_ov } { \pipe1_xer_ov_ok \pipe1_xer_ov } sync init end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cry_in 2'00 - end + process $group_29 + assign \pipe2_xer_so 1'0 + assign \pipe2_xer_so_ok 1'0 + assign { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } sync init end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \asmcode 8'00110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \asmcode 8'00110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \asmcode 8'00110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \asmcode 8'00110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \asmcode 8'00111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \asmcode 8'00111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \asmcode 8'00110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \asmcode 8'00111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \asmcode 8'01110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \asmcode 8'01110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \asmcode 8'01111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'01111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \asmcode 8'01111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \asmcode 8'01111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \asmcode 8'01111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \asmcode 8'01111101 - end + process $group_31 + assign \pipe1_p_valid_i 1'0 + assign \pipe1_p_valid_i \p_valid_i sync init end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \inv_a 1'0 - end + process $group_32 + assign \p_ready_o 1'0 + assign \p_ready_o \pipe1_p_ready_o sync init end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \inv_out 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + process $group_33 + assign \pipe1_muxid$3 2'00 + assign \pipe1_muxid$3 \muxid sync init end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cry_out 1'0 - end + process $group_34 + assign \pipe1_alu_op__insn_type$4 7'0000000 + assign \pipe1_alu_op__fn_unit$5 11'00000000000 + assign \pipe1_alu_op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe1_alu_op__imm_data__imm_ok$7 1'0 + assign \pipe1_alu_op__rc__rc$8 1'0 + assign \pipe1_alu_op__rc__rc_ok$9 1'0 + assign \pipe1_alu_op__oe__oe$10 1'0 + assign \pipe1_alu_op__oe__oe_ok$11 1'0 + assign \pipe1_alu_op__invert_in$12 1'0 + assign \pipe1_alu_op__zero_a$13 1'0 + assign \pipe1_alu_op__invert_out$14 1'0 + assign \pipe1_alu_op__write_cr0$15 1'0 + assign \pipe1_alu_op__input_carry$16 2'00 + assign \pipe1_alu_op__output_carry$17 1'0 + assign \pipe1_alu_op__is_32bit$18 1'0 + assign \pipe1_alu_op__is_signed$19 1'0 + assign \pipe1_alu_op__data_len$20 4'0000 + assign \pipe1_alu_op__insn$21 32'00000000000000000000000000000000 + assign { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 { \pipe1_alu_op__oe__oe_ok$11 \pipe1_alu_op__oe__oe$10 } { \pipe1_alu_op__rc__rc_ok$9 \pipe1_alu_op__rc__rc$8 } { \pipe1_alu_op__imm_data__imm_ok$7 \pipe1_alu_op__imm_data__imm$6 } \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } sync init end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \br 1'0 - end + process $group_52 + assign \pipe1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe1_ra \ra sync init end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgn_ext 1'0 - end + process $group_53 + assign \pipe1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe1_rb \rb sync init end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \rsrv 1'0 - end + process $group_54 + assign \pipe1_xer_so$22 1'0 + assign \pipe1_xer_so$22 \xer_so$1 sync init end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \is_32b 1'0 - end + process $group_55 + assign \pipe1_xer_ca$23 2'00 + assign \pipe1_xer_ca$23 \xer_ca$2 sync init end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgn 1'1 - end + process $group_56 + assign \n_valid_o 1'0 + assign \n_valid_o \pipe2_n_valid_o sync init end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \lk 1'0 - end + process $group_57 + assign \pipe2_n_ready_i 1'0 + assign \pipe2_n_ready_i \n_ready_i sync init end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgl_pipe 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$53 + process $group_58 + assign \muxid$53 2'00 + assign \muxid$53 \pipe2_muxid$24 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub11" -module \dec_sub11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -10986,1446 +6282,1207 @@ module \dec_sub11 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$54 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_op__fn_unit$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__imm$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__imm_data__imm_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__rc__rc_ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__oe__oe$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__oe__oe_ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__invert_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__zero_a$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__invert_out$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__write_cr0$65 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__output_carry$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$71 + process $group_59 + assign \alu_op__insn_type$54 7'0000000 + assign \alu_op__fn_unit$55 11'00000000000 + assign \alu_op__imm_data__imm$56 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__imm_ok$57 1'0 + assign \alu_op__rc__rc$58 1'0 + assign \alu_op__rc__rc_ok$59 1'0 + assign \alu_op__oe__oe$60 1'0 + assign \alu_op__oe__oe_ok$61 1'0 + assign \alu_op__invert_in$62 1'0 + assign \alu_op__zero_a$63 1'0 + assign \alu_op__invert_out$64 1'0 + assign \alu_op__write_cr0$65 1'0 + assign \alu_op__input_carry$66 2'00 + assign \alu_op__output_carry$67 1'0 + assign \alu_op__is_32bit$68 1'0 + assign \alu_op__is_signed$69 1'0 + assign \alu_op__data_len$70 4'0000 + assign \alu_op__insn$71 32'00000000000000000000000000000000 + assign { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 { \alu_op__oe__oe_ok$61 \alu_op__oe__oe$60 } { \alu_op__rc__rc_ok$59 \alu_op__rc__rc$58 } { \alu_op__imm_data__imm_ok$57 \alu_op__imm_data__imm$56 } \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 { \pipe2_alu_op__oe__oe_ok$32 \pipe2_alu_op__oe__oe$31 } { \pipe2_alu_op__rc__rc_ok$30 \pipe2_alu_op__rc__rc$29 } { \pipe2_alu_op__imm_data__imm_ok$28 \pipe2_alu_op__imm_data__imm$27 } \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } sync init end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \function_unit 11'00100000000 - end + process $group_77 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'0 + assign { \o_ok \o } { \pipe2_o_ok$44 \pipe2_o$43 } sync init end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \form 5'10001 - end + process $group_79 + assign \cr_a 4'0000 + assign \cr_a_ok 1'0 + assign { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$46 \pipe2_cr_a$45 } sync init end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \internal_op 7'0110010 - end + process $group_81 + assign \xer_ca 2'00 + assign \xer_ca_ok 1'0 + assign { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$48 \pipe2_xer_ca$47 } sync init end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in1_sel 3'001 - end + process $group_83 + assign \xer_ov 2'00 + assign \xer_ov_ok 1'0 + assign { \xer_ov_ok \xer_ov } { \pipe2_xer_ov_ok$50 \pipe2_xer_ov$49 } sync init end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in2_sel 4'0001 - end + process $group_85 + assign \xer_so 1'0 + assign \xer_so_ok 1'0 + assign { \xer_so_ok \xer_so } { \pipe2_xer_so_ok$52 \pipe2_xer_so$51 } sync init end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in3_sel 2'00 - end - sync init + connect \muxid 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l" +module \src_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $1 end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \out_sel 2'01 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B $1 + connect \Y $3 end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cr_in 3'000 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $3 + connect \B \s_src + connect \Y $5 end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cr_out 3'001 + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 4'0000 end sync init + update \q_int 4'0000 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \ldst_len 4'0000 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $9 + connect \B \s_src + connect \Y $11 + end + process $group_1 + assign \q_src 4'0000 + assign \q_src $11 sync init end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \upd 2'00 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \Y $13 + end + process $group_2 + assign \qn_src 4'0000 + assign \qn_src $13 sync init end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \rc_sel 2'10 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_src 4'0000 + assign \qlq_src $15 sync init end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cry_in 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l" +module \opc_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_opc + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \asmcode 8'00111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \asmcode 8'00111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \asmcode 8'00111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \asmcode 8'00111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \asmcode 8'01000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \asmcode 8'01000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \asmcode 8'00111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \asmcode 8'01000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \asmcode 8'01110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \asmcode 8'01110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \asmcode 8'01111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'01111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \asmcode 8'01111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \asmcode 8'01111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \asmcode 8'01111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \asmcode 8'10000000 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_opc + connect \Y $11 + end + process $group_1 + assign \q_opc 1'0 + assign \q_opc $11 sync init end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \inv_a 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $13 + end + process $group_2 + assign \qn_opc 1'0 + assign \qn_opc $13 sync init end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \inv_out 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_opc 1'0 + assign \qlq_opc $15 sync init end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cry_out 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l" +module \req_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $3 + connect \B \s_req + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 5'00000 end sync init + update \q_int 5'00000 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \br 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $9 + connect \B \s_req + connect \Y $11 + end + process $group_1 + assign \q_req 5'00000 + assign \q_req $11 sync init end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgn_ext 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $13 + end + process $group_2 + assign \qn_req 5'00000 + assign \qn_req $13 sync init end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \rsrv 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 5 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_req 5'00000 + assign \qlq_req $15 sync init end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \is_32b 1'1 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l" +module \rst_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rst + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rst + connect \Y $11 + end + process $group_1 + assign \q_rst 1'0 + assign \q_rst $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $13 + end + process $group_2 + assign \qn_rst 1'0 + assign \qn_rst $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rst 1'0 + assign \qlq_rst $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l" +module \rok_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rdok + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rdok + connect \Y $11 + end + process $group_1 + assign \q_rdok 1'0 + assign \q_rdok $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $13 + end + process $group_2 + assign \qn_rdok 1'0 + assign \qn_rdok $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rdok 1'0 + assign \qlq_rdok $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l" +module \alui_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alui + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alui + connect \Y $11 + end + process $group_1 + assign \q_alui 1'0 + assign \q_alui $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $13 + end + process $group_2 + assign \qn_alui 1'0 + assign \qn_alui $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alui 1'0 + assign \qlq_alui $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_l" +module \alu_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alu + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alu + connect \Y $11 + end + process $group_1 + assign \q_alu 1'0 + assign \q_alu $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $13 + end + process $group_2 + assign \qn_alu 1'0 + assign \qn_alu $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alu 1'0 + assign \qlq_alu $15 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub27" -module \dec_sub27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0" +module \alu0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_alu0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -12438,40 +7495,92 @@ module \dec_sub27 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_alu0__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \oper_i_alu_alu0__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \oper_i_alu_alu0__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \oper_i_alu_alu0__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \oper_i_alu_alu0__write_cr0 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_alu_alu0__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_alu0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 24 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 input 26 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 27 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 28 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 33 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 34 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 35 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 36 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 37 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 output 39 \dest5_o + attribute \src "simple/issuer.py:102" + wire width 1 input 40 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \alu_alu0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \alu_alu0_n_ready_i attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -12545,628 +7654,1958 @@ module \dec_sub27 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_alu0_alu_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_alu0_alu_op__insn_type$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_alu0_alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_alu0_alu_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_alu0_alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_alu0_alu_op__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__write_cr0$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_alu0_alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_alu0_alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_alu0_alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_alu0_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_alu0_alu_op__data_len$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_alu0_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_alu0_alu_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_alu0_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_alu0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_alu0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_alu0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \alu_alu0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_alu0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_alu0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \alu_alu0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_alu0_xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \alu_alu0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \alu_alu0_p_ready_o + cell \alu_alu0 \alu_alu0 + connect \coresync_clk \coresync_clk + connect \o_ok \o_ok + connect \cr_a_ok \cr_a_ok + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov_ok \xer_ov_ok + connect \xer_so_ok \xer_so_ok + connect \coresync_rst \coresync_rst + connect \n_valid_o \alu_alu0_n_valid_o + connect \n_ready_i \alu_alu0_n_ready_i + connect \alu_op__insn_type \alu_alu0_alu_op__insn_type + connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit + connect \alu_op__imm_data__imm \alu_alu0_alu_op__imm_data__imm + connect \alu_op__imm_data__imm_ok \alu_alu0_alu_op__imm_data__imm_ok + connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc + connect \alu_op__rc__rc_ok \alu_alu0_alu_op__rc__rc_ok + connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe + connect \alu_op__oe__oe_ok \alu_alu0_alu_op__oe__oe_ok + connect \alu_op__invert_in \alu_alu0_alu_op__invert_in + connect \alu_op__zero_a \alu_alu0_alu_op__zero_a + connect \alu_op__invert_out \alu_alu0_alu_op__invert_out + connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 + connect \alu_op__input_carry \alu_alu0_alu_op__input_carry + connect \alu_op__output_carry \alu_alu0_alu_op__output_carry + connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit + connect \alu_op__is_signed \alu_alu0_alu_op__is_signed + connect \alu_op__data_len \alu_alu0_alu_op__data_len + connect \alu_op__insn \alu_alu0_alu_op__insn + connect \o \alu_alu0_o + connect \cr_a \alu_alu0_cr_a + connect \xer_ca \alu_alu0_xer_ca + connect \xer_ov \alu_alu0_xer_ov + connect \xer_so \alu_alu0_xer_so + connect \ra \alu_alu0_ra + connect \rb \alu_alu0_rb + connect \xer_so$1 \alu_alu0_xer_so$1 + connect \xer_ca$2 \alu_alu0_xer_ca$2 + connect \p_valid_i \alu_alu0_p_valid_i + connect \p_ready_o \alu_alu0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \src_l_q_src + cell \src_l \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_src \src_l_s_src + connect \r_src \src_l_r_src + connect \q_src \src_l_q_src + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \opc_l_q_opc + cell \opc_l \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_opc \opc_l_s_opc + connect \r_opc \opc_l_r_opc + connect \q_opc \opc_l_q_opc + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_r_req$next + cell \req_l \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \s_req \req_l_s_req + connect \r_req \req_l_r_req + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst$next + cell \rst_l \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_rst \rst_l_s_rst + connect \r_rst \rst_l_r_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok$next + cell \rok_l \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \s_rdok \rok_l_s_rdok + connect \r_rdok \rok_l_r_rdok + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alui_l_s_alui + cell \alui_l \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_s_alu + cell \alu_l \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 4 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 4 $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $6 + connect \B \cu_rd__go_i + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B $5 + connect \Y $11 + end process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] + assign \all_rd 1'0 + assign \all_rd $11 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly$next process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \function_unit 11'00000001000 - end + assign \all_rd_dly$next \all_rd_dly + assign \all_rd_dly$next \all_rd sync init + update \all_rd_dly 1'0 + sync posedge \coresync_clk + update \all_rd_dly \all_rd_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B $13 + connect \Y $15 end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \form 5'10000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \form 5'10000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \form 5'01000 - end + assign \all_rd_rise 1'0 + assign \all_rd_rise $15 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire width 1 \all_rd_pulse process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \internal_op 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \internal_op 7'0111101 - end + assign \all_rd_pulse 1'0 + assign \all_rd_pulse \all_rd_rise sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire width 1 \alu_done process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in1_sel 3'000 - end + assign \alu_done 1'0 + assign \alu_done \alu_alu0_n_valid_o sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly$next process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in2_sel 4'0001 - end + assign \alu_done_dly$next \alu_done_dly + assign \alu_done_dly$next \alu_done sync init + update \alu_done_dly 1'0 + sync posedge \coresync_clk + update \alu_done_dly \alu_done_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B $17 + connect \Y $19 end process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in3_sel 2'01 - end + assign \alu_done_rise 1'0 + assign \alu_done_rise $19 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire width 1 \alu_pulse process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \out_sel 2'10 - end + assign \alu_pulse 1'0 + assign \alu_pulse \alu_done_rise sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 5 \alu_pulsem process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_in 3'000 - end + assign \alu_pulsem 5'00000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 5 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $21 + end process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_out 3'001 + assign \prev_wr_go$next \prev_wr_go + assign \prev_wr_go$next $21 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \prev_wr_go$next 5'00000 end sync init + update \prev_wr_go 5'00000 + sync posedge \coresync_clk + update \prev_wr_go \prev_wr_go$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire width 1 \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 5 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 5 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wrmask_o + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 5 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__rel_o + connect \B $25 + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A $27 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B $23 + connect \Y $31 end process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \ldst_len 4'0000 - end + assign \cu_done_o 1'0 + assign \cu_done_o $31 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $33 + connect \B $35 + connect \Y $37 + end process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \upd 2'00 - end + assign \wr_any 1'0 + assign \wr_any $37 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire width 1 \req_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_n_ready_i + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B $39 + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 5 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $43 + connect \B 1'0 + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $41 + connect \B $45 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $49 + connect \B \alu_alu0_n_ready_i + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $51 + connect \B \alu_alu0_n_valid_o + connect \Y $53 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $53 + connect \B \cu_busy_o + connect \Y $55 + end process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rc_sel 2'10 + assign \req_done 1'0 + assign \req_done $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch { $55 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + case 1'1 + assign \req_done 1'1 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire width 1 \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire width 1 \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $57 + end process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_in 2'00 - end + assign \reset 1'0 + assign \reset $57 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire width 1 \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $59 + end process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \asmcode 8'01000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'10011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \asmcode 8'10011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \asmcode 8'10100001 - end + assign \rst_r 1'0 + assign \rst_r $59 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 5 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 5 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $61 + end process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_a 1'0 - end + assign \reset_w 5'00000 + assign \reset_w $61 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 4 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 4 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $63 + end process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_out 1'0 - end + assign \reset_r 4'0000 + assign \reset_r $63 sync init end process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_out 1'0 + assign \rok_l_s_rdok$next \rok_l_s_rdok + assign \rok_l_s_rdok$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_s_rdok$next 1'0 end sync init + update \rok_l_s_rdok 1'0 + sync posedge \coresync_clk + update \rok_l_s_rdok \rok_l_s_rdok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_n_valid_o + connect \B \cu_busy_o + connect \Y $65 end process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \br 1'0 + assign \rok_l_r_rdok$next \rok_l_r_rdok + assign \rok_l_r_rdok$next $65 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_r_rdok$next 1'1 end sync init + update \rok_l_r_rdok 1'1 + sync posedge \coresync_clk + update \rok_l_r_rdok \rok_l_r_rdok$next end process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn_ext 1'0 + assign \rst_l_s_rst$next \rst_l_s_rst + assign \rst_l_s_rst$next \all_rd + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_s_rst$next 1'0 end sync init + update \rst_l_s_rst 1'0 + sync posedge \coresync_clk + update \rst_l_s_rst \rst_l_s_rst$next end process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rsrv 1'0 + assign \rst_l_r_rst$next \rst_l_r_rst + assign \rst_l_r_rst$next \rst_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_r_rst$next 1'1 end sync init + update \rst_l_r_rst 1'1 + sync posedge \coresync_clk + update \rst_l_r_rst \rst_l_r_rst$next end process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \is_32b 1'0 + assign \opc_l_s_opc$next \opc_l_s_opc + assign \opc_l_s_opc$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_s_opc$next 1'0 end sync init + update \opc_l_s_opc 1'0 + sync posedge \coresync_clk + update \opc_l_s_opc \opc_l_s_opc$next end process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn 1'0 + assign \opc_l_r_opc$next \opc_l_r_opc + assign \opc_l_r_opc$next \req_done + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_r_opc$next 1'1 end sync init + update \opc_l_r_opc 1'1 + sync posedge \coresync_clk + update \opc_l_r_opc \opc_l_r_opc$next end process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \lk 1'0 + assign \src_l_s_src$next \src_l_s_src + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_s_src$next 4'0000 end sync init + update \src_l_s_src 4'0000 + sync posedge \coresync_clk + update \src_l_s_src \src_l_s_src$next end process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgl_pipe 1'0 + assign \src_l_r_src$next \src_l_r_src + assign \src_l_r_src$next \reset_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_r_src$next 4'1111 end sync init + update \src_l_r_src 4'1111 + sync posedge \coresync_clk + update \src_l_r_src \src_l_r_src$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub15" -module \dec_sub15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 5 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $67 + end + process $group_25 + assign \req_l_s_req$next \req_l_s_req + assign \req_l_s_req$next $67 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_s_req$next 5'00000 + end + sync init + update \req_l_s_req 5'00000 + sync posedge \coresync_clk + update \req_l_s_req \req_l_s_req$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 5 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $69 + end + process $group_26 + assign \req_l_r_req$next \req_l_r_req + assign \req_l_r_req$next $69 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_r_req$next 5'11111 + end + sync init + update \req_l_r_req 5'11111 + sync posedge \coresync_clk + update \req_l_r_req \req_l_r_req$next + end + process $group_27 + assign \alu_alu0_alu_op__insn_type$next \alu_alu0_alu_op__insn_type + assign \alu_alu0_alu_op__fn_unit$next \alu_alu0_alu_op__fn_unit + assign \alu_alu0_alu_op__imm_data__imm$next \alu_alu0_alu_op__imm_data__imm + assign \alu_alu0_alu_op__imm_data__imm_ok$next \alu_alu0_alu_op__imm_data__imm_ok + assign \alu_alu0_alu_op__rc__rc$next \alu_alu0_alu_op__rc__rc + assign \alu_alu0_alu_op__rc__rc_ok$next \alu_alu0_alu_op__rc__rc_ok + assign \alu_alu0_alu_op__oe__oe$next \alu_alu0_alu_op__oe__oe + assign \alu_alu0_alu_op__oe__oe_ok$next \alu_alu0_alu_op__oe__oe_ok + assign \alu_alu0_alu_op__invert_in$next \alu_alu0_alu_op__invert_in + assign \alu_alu0_alu_op__zero_a$next \alu_alu0_alu_op__zero_a + assign \alu_alu0_alu_op__invert_out$next \alu_alu0_alu_op__invert_out + assign \alu_alu0_alu_op__write_cr0$next \alu_alu0_alu_op__write_cr0 + assign \alu_alu0_alu_op__input_carry$next \alu_alu0_alu_op__input_carry + assign \alu_alu0_alu_op__output_carry$next \alu_alu0_alu_op__output_carry + assign \alu_alu0_alu_op__is_32bit$next \alu_alu0_alu_op__is_32bit + assign \alu_alu0_alu_op__is_signed$next \alu_alu0_alu_op__is_signed + assign \alu_alu0_alu_op__data_len$next \alu_alu0_alu_op__data_len + assign \alu_alu0_alu_op__insn$next \alu_alu0_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + case 1'1 + assign { \alu_alu0_alu_op__insn$next \alu_alu0_alu_op__data_len$next \alu_alu0_alu_op__is_signed$next \alu_alu0_alu_op__is_32bit$next \alu_alu0_alu_op__output_carry$next \alu_alu0_alu_op__input_carry$next \alu_alu0_alu_op__write_cr0$next \alu_alu0_alu_op__invert_out$next \alu_alu0_alu_op__zero_a$next \alu_alu0_alu_op__invert_in$next { \alu_alu0_alu_op__oe__oe_ok$next \alu_alu0_alu_op__oe__oe$next } { \alu_alu0_alu_op__rc__rc_ok$next \alu_alu0_alu_op__rc__rc$next } { \alu_alu0_alu_op__imm_data__imm_ok$next \alu_alu0_alu_op__imm_data__imm$next } \alu_alu0_alu_op__fn_unit$next \alu_alu0_alu_op__insn_type$next } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in { \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe } { \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc } { \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm } \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_alu0_alu_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_alu0_alu_op__imm_data__imm_ok$next 1'0 + assign \alu_alu0_alu_op__rc__rc$next 1'0 + assign \alu_alu0_alu_op__rc__rc_ok$next 1'0 + assign \alu_alu0_alu_op__oe__oe$next 1'0 + assign \alu_alu0_alu_op__oe__oe_ok$next 1'0 + end + sync init + update \alu_alu0_alu_op__insn_type 7'0000000 + update \alu_alu0_alu_op__fn_unit 11'00000000000 + update \alu_alu0_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_alu0_alu_op__imm_data__imm_ok 1'0 + update \alu_alu0_alu_op__rc__rc 1'0 + update \alu_alu0_alu_op__rc__rc_ok 1'0 + update \alu_alu0_alu_op__oe__oe 1'0 + update \alu_alu0_alu_op__oe__oe_ok 1'0 + update \alu_alu0_alu_op__invert_in 1'0 + update \alu_alu0_alu_op__zero_a 1'0 + update \alu_alu0_alu_op__invert_out 1'0 + update \alu_alu0_alu_op__write_cr0 1'0 + update \alu_alu0_alu_op__input_carry 2'00 + update \alu_alu0_alu_op__output_carry 1'0 + update \alu_alu0_alu_op__is_32bit 1'0 + update \alu_alu0_alu_op__is_signed 1'0 + update \alu_alu0_alu_op__data_len 4'0000 + update \alu_alu0_alu_op__insn 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn_type \alu_alu0_alu_op__insn_type$next + update \alu_alu0_alu_op__fn_unit \alu_alu0_alu_op__fn_unit$next + update \alu_alu0_alu_op__imm_data__imm \alu_alu0_alu_op__imm_data__imm$next + update \alu_alu0_alu_op__imm_data__imm_ok \alu_alu0_alu_op__imm_data__imm_ok$next + update \alu_alu0_alu_op__rc__rc \alu_alu0_alu_op__rc__rc$next + update \alu_alu0_alu_op__rc__rc_ok \alu_alu0_alu_op__rc__rc_ok$next + update \alu_alu0_alu_op__oe__oe \alu_alu0_alu_op__oe__oe$next + update \alu_alu0_alu_op__oe__oe_ok \alu_alu0_alu_op__oe__oe_ok$next + update \alu_alu0_alu_op__invert_in \alu_alu0_alu_op__invert_in$next + update \alu_alu0_alu_op__zero_a \alu_alu0_alu_op__zero_a$next + update \alu_alu0_alu_op__invert_out \alu_alu0_alu_op__invert_out$next + update \alu_alu0_alu_op__write_cr0 \alu_alu0_alu_op__write_cr0$next + update \alu_alu0_alu_op__input_carry \alu_alu0_alu_op__input_carry$next + update \alu_alu0_alu_op__output_carry \alu_alu0_alu_op__output_carry$next + update \alu_alu0_alu_op__is_32bit \alu_alu0_alu_op__is_32bit$next + update \alu_alu0_alu_op__is_signed \alu_alu0_alu_op__is_signed$next + update \alu_alu0_alu_op__data_len \alu_alu0_alu_op__data_len$next + update \alu_alu0_alu_op__insn \alu_alu0_alu_op__insn$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok$next + process $group_45 + assign \data_r0__o$next \data_r0__o + assign \data_r0__o_ok$next \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_alu0_o } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r0__o_ok$next 1'0 + end + sync init + update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0__o_ok 1'0 + sync posedge \coresync_clk + update \data_r0__o \data_r0__o$next + update \data_r0__o_ok \data_r0__o_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__cr_a_ok$next + process $group_47 + assign \data_r1__cr_a$next \data_r1__cr_a + assign \data_r1__cr_a_ok$next \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } { \cr_a_ok \alu_alu0_cr_a } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r1__cr_a_ok$next 1'0 + end + sync init + update \data_r1__cr_a 4'0000 + update \data_r1__cr_a_ok 1'0 + sync posedge \coresync_clk + update \data_r1__cr_a \data_r1__cr_a$next + update \data_r1__cr_a_ok \data_r1__cr_a_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__xer_ca_ok$next + process $group_49 + assign \data_r2__xer_ca$next \data_r2__xer_ca + assign \data_r2__xer_ca_ok$next \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } { \xer_ca_ok \alu_alu0_xer_ca } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } 3'000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r2__xer_ca_ok$next 1'0 + end + sync init + update \data_r2__xer_ca 2'00 + update \data_r2__xer_ca_ok 1'0 + sync posedge \coresync_clk + update \data_r2__xer_ca \data_r2__xer_ca$next + update \data_r2__xer_ca_ok \data_r2__xer_ca_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r3__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r3__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_ov_ok$next + process $group_51 + assign \data_r3__xer_ov$next \data_r3__xer_ov + assign \data_r3__xer_ov_ok$next \data_r3__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r3__xer_ov_ok$next \data_r3__xer_ov$next } { \xer_ov_ok \alu_alu0_xer_ov } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r3__xer_ov_ok$next \data_r3__xer_ov$next } 3'000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r3__xer_ov_ok$next 1'0 + end + sync init + update \data_r3__xer_ov 2'00 + update \data_r3__xer_ov_ok 1'0 + sync posedge \coresync_clk + update \data_r3__xer_ov \data_r3__xer_ov$next + update \data_r3__xer_ov_ok \data_r3__xer_ov_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r4__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r4__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r4__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r4__xer_so_ok$next + process $group_53 + assign \data_r4__xer_so$next \data_r4__xer_so + assign \data_r4__xer_so_ok$next \data_r4__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r4__xer_so_ok$next \data_r4__xer_so$next } { \xer_so_ok \alu_alu0_xer_so } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r4__xer_so_ok$next \data_r4__xer_so$next } 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r4__xer_so_ok$next 1'0 + end + sync init + update \data_r4__xer_so 1'0 + update \data_r4__xer_so_ok 1'0 + sync posedge \coresync_clk + update \data_r4__xer_so \data_r4__xer_so$next + update \data_r4__xer_so_ok \data_r4__xer_so_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $71 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ca_ok + connect \B \cu_busy_o + connect \Y $75 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $77 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $79 + end + process $group_55 + assign \cu_wrmask_o 5'00000 + assign \cu_wrmask_o { $79 $77 $75 $73 $71 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $82 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__zero_a + connect \Y $81 + end + process $group_56 + assign \src_sel 1'0 + assign \src_sel $81 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $84 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_alu0_alu_op__zero_a + connect \Y $83 + end + process $group_57 + assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm $83 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire width 1 \src_sel$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire width 1 $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $87 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__imm_data__imm_ok + connect \Y $86 + end + process $group_58 + assign \src_sel$85 1'0 + assign \src_sel$85 $86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $90 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_alu0_alu_op__imm_data__imm + connect \S \alu_alu0_alu_op__imm_data__imm_ok + connect \Y $89 + end + process $group_59 + assign \src_or_imm$88 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm$88 $89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $92 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $91 + end + process $group_60 + assign \alu_alu0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_alu0_ra $91 + sync init + end + process $group_61 + assign \src_r0$next \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r0$next \src_or_imm + end + sync init + update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r0 \src_r0$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $94 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$88 + connect \S \src_sel$85 + connect \Y $93 + end + process $group_62 + assign \alu_alu0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_alu0_rb $93 + sync init + end + process $group_63 + assign \src_r1$next \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel$85 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r1$next \src_or_imm$88 + end + sync init + update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r1 \src_r1$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $96 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $95 + end + process $group_64 + assign \alu_alu0_xer_so$1 1'0 + assign \alu_alu0_xer_so$1 $95 + sync init + end + process $group_65 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r2$next \src3_i + end + sync init + update \src_r2 1'0 + sync posedge \coresync_clk + update \src_r2 \src_r2$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $98 + parameter \WIDTH 2 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $97 + end + process $group_66 + assign \alu_alu0_xer_ca$2 2'00 + assign \alu_alu0_xer_ca$2 $97 + sync init + end + process $group_67 + assign \src_r3$next \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [3] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r3$next \src4_i + end + sync init + update \src_r3 2'00 + sync posedge \coresync_clk + update \src_r3 \src_r3$next + end + process $group_68 + assign \alu_alu0_p_valid_i 1'0 + assign \alu_alu0_p_valid_i \alui_l_q_alui + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire width 1 $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $99 + end + process $group_69 + assign \alui_l_r_alui$next \alui_l_r_alui + assign \alui_l_r_alui$next $99 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alui_l_r_alui$next 1'1 + end + sync init + update \alui_l_r_alui 1'1 + sync posedge \coresync_clk + update \alui_l_r_alui \alui_l_r_alui$next + end + process $group_70 + assign \alui_l_s_alui 1'0 + assign \alui_l_s_alui \all_rd_pulse + sync init + end + process $group_71 + assign \alu_alu0_n_ready_i 1'0 + assign \alu_alu0_n_ready_i \alu_l_q_alu + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $101 + end + process $group_72 + assign \alu_l_r_alu$next \alu_l_r_alu + assign \alu_l_r_alu$next $101 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_l_r_alu$next 1'1 + end + sync init + update \alu_l_r_alu 1'1 + sync posedge \coresync_clk + update \alu_l_r_alu \alu_l_r_alu$next + end + process $group_73 + assign \alu_l_s_alu 1'0 + assign \alu_l_s_alu \all_rd_pulse + sync init + end + process $group_74 + assign \cu_busy_o 1'0 + assign \cu_busy_o \opc_l_q_opc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $103 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_alu_op__zero_a + connect \Y $105 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_alu_op__imm_data__imm_ok + connect \Y $107 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $103 + connect \B { 1'1 1'1 $107 $105 } + connect \Y $109 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rdmaskn_i + connect \Y $111 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $109 + connect \B $111 + connect \Y $113 + end + process $group_75 + assign \cu_rd__rel_o 4'0000 + assign \cu_rd__rel_o $113 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire width 1 \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $115 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $117 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $119 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $121 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $123 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 5 $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B { $115 $117 $119 $121 $123 } + connect \Y $125 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 5 $127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $125 + connect \B \cu_wrmask_o + connect \Y $127 + end + process $group_76 + assign \cu_wr__rel_o 5'00000 + assign \cu_wr__rel_o $127 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $129 + end + process $group_77 + assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $129 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $131 + end + process $group_78 + assign \dest2_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $131 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $133 + end + process $group_79 + assign \dest3_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $133 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $135 + end + process $group_80 + assign \dest4_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $135 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest4_o { \data_r3__xer_ov_ok \data_r3__xer_ov } [1:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [4] + connect \B \cu_busy_o + connect \Y $137 + end + process $group_81 + assign \dest5_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $137 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest5_o { \data_r4__xer_so_ok \data_r4__xer_so } [0] + end + sync init + end + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.p" +module \p$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.n" +module \n$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.p" +module \p$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.n" +module \n$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.main" +module \main$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -13240,2644 +9679,1063 @@ module \dec_sub15 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \function_unit 11'00001000000 - end - sync init - end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \cr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \cr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \cr_op__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \cr_op__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 6 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 7 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 8 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 9 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 10 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 12 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 13 \cr_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 14 \cr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 15 \cr_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 16 \cr_op__read_cr_whole$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 17 \cr_op__write_cr_whole$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 18 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 19 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 output 20 \full_cr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 21 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 22 \cr_a$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 23 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:51" + wire width 32 \mask + process $group_0 + assign \mask 32'00000000000000000000000000000000 + assign \mask { { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] } } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 5 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A \cr_a + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:104" + wire width 1 \bit_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 2 \bt + process $group_1 + assign \cr_a$8 4'0000 + assign \cr_a_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + assign { \cr_a_ok \cr_a$8 } $9 + assign \cr_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + assign \cr_a$8 \cr_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" + switch \bt + case 2'00 + assign { \cr_a_ok \cr_a$8 } [0] \bit_o + case 2'01 + assign { \cr_a_ok \cr_a$8 } [1] \bit_o + case 2'10 + assign { \cr_a_ok \cr_a$8 } [2] \bit_o + case 2'-- + assign { \cr_a_ok \cr_a$8 } [3] \bit_o + end + switch { } + case + assign \cr_a_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:77" + wire width 4 \lut process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \internal_op 7'0100011 + assign \lut 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + assign \lut \cr_op__insn [9:6] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" + wire width 3 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" + cell $sub $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B { \cr_op__insn [25] \cr_op__insn [24] \cr_op__insn [23] \cr_op__insn [22] \cr_op__insn [21] } [1:0] + connect \Y $12 + end + connect $11 $12 process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in1_sel 3'010 + assign \bt 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + assign \bt $11 [1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:89" + wire width 2 \ba + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" + wire width 3 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" + cell $sub $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B { \cr_op__insn [20] \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] } [1:0] + connect \Y $15 + end + connect $14 $15 process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in2_sel 4'0001 + assign \ba 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + assign \ba $14 [1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:90" + wire width 2 \bb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:95" + wire width 3 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:95" + wire width 3 $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:95" + cell $sub $19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B { \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] \cr_op__insn [11] } [1:0] + connect \Y $18 + end + connect $17 $18 process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in3_sel 2'00 + assign \bb 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + assign \bb $17 [1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:98" + wire width 1 \bit_a process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \out_sel 2'01 + assign \bit_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + switch \ba + case 2'00 + assign \bit_a \cr_a [0] + case 2'01 + assign \bit_a \cr_a [1] + case 2'10 + assign \bit_a \cr_a [2] + case 2'-- + assign \bit_a \cr_a [3] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + wire width 1 \bit_b process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cr_in 3'101 + assign \bit_b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:101" + switch \bb + case 2'00 + assign \bit_b \cr_b [0] + case 2'01 + assign \bit_b \cr_b [1] + case 2'10 + assign \bit_b \cr_b [2] + case 2'-- + assign \bit_b \cr_b [3] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:106" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:106" + cell $mux $21 + parameter \WIDTH 1 + connect \A \lut [1] + connect \B \lut [3] + connect \S \bit_a + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:107" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:107" + cell $mux $23 + parameter \WIDTH 1 + connect \A \lut [0] + connect \B \lut [2] + connect \S \bit_a + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:107" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:107" + cell $mux $25 + parameter \WIDTH 1 + connect \A $22 + connect \B $20 + connect \S \bit_b + connect \Y $24 + end process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cr_out 3'000 + assign \bit_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + assign \bit_o $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" + wire width 32 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \ra [31:0] + connect \B \mask + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" + wire width 32 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" + cell $not $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \mask + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" + cell $and $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \full_cr + connect \B $28 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" + wire width 32 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $26 + connect \B $30 + connect \Y $32 + end process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \ldst_len 4'0000 + assign \full_cr$7 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + assign \full_cr$7 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \upd 2'00 + assign \full_cr_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + assign \full_cr_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:128" + wire width 1 \move_one process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \rc_sel 2'00 + assign \move_one 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + assign \move_one \cr_op__insn [20] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cry_in 2'00 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:134" + wire width 64 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:134" + wire width 32 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:134" + cell $and $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \full_cr + connect \B \mask + connect \Y $35 end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \asmcode 8'01001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:134" + cell $pos $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A $35 + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \full_cr + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154" + wire width 65 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154" + wire width 64 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:150" + wire width 1 \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154" + cell $mux $42 + parameter \WIDTH 64 + connect \A \rb + connect \B \ra + connect \S \cr_bit + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154" + cell $pos $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A $41 + connect \Y $40 + end + process $group_13 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:132" + switch { \move_one } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:132" + case 1'1 + assign \o $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" + case + assign \o $38 + end + switch { } + case + assign \o_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + assign { \o_ok \o } $40 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:158" + switch { \cr_a [2] \cr_a [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:158" + case 2'-1 + assign \o 64'1111111111111111111111111111111111111111111111111111111111111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:160" + case 2'1- + assign \o 64'0000000000000000000000000000000000000000000000000000000000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:162" + case + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + end + switch { } + case + assign \o_ok 1'1 + end end sync init end process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \inv_a 1'0 + assign \cr_bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:59" + switch \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:61" + attribute \nmigen.decoding "OP_MCRF/42" + case 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + attribute \nmigen.decoding "OP_CROP/69" + case 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" + attribute \nmigen.decoding "OP_MTCRF/48" + case 7'0110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" + attribute \nmigen.decoding "OP_MFCR/45" + case 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:142" + attribute \nmigen.decoding "OP_ISEL/35" + case 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:151" + switch { \cr_op__insn [10] \cr_op__insn [9] \cr_op__insn [8] \cr_op__insn [7] \cr_op__insn [6] } [1:0] + case 2'00 + assign \cr_bit \cr_a [3] + case 2'01 + assign \cr_bit \cr_a [2] + case 2'10 + assign \cr_bit \cr_a [1] + case 2'-- + assign \cr_bit \cr_a [0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:157" + attribute \nmigen.decoding "OP_SETB/59" + case 7'0111011 end sync init end process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \inv_out 1'0 - end + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cry_out 1'0 - end + assign \cr_op__insn_type$2 7'0000000 + assign \cr_op__fn_unit$3 11'00000000000 + assign \cr_op__insn$4 32'00000000000000000000000000000000 + assign \cr_op__read_cr_whole$5 1'0 + assign \cr_op__write_cr_whole$6 1'0 + assign { \cr_op__write_cr_whole$6 \cr_op__read_cr_whole$5 \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } sync init end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \br 1'0 - end - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe" +module \pipe + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \cr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \cr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \cr_op__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \cr_op__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 12 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 13 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 14 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 15 \cr_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 16 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 17 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 20 \cr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \cr_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 21 \cr_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 22 \cr_op__read_cr_whole$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \cr_op__read_cr_whole$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 23 \cr_op__write_cr_whole$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \cr_op__write_cr_whole$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 25 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 output 26 \full_cr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \full_cr$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 27 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \full_cr_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 28 \cr_a$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 29 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$next + cell \p$7 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgn_ext 1'0 - end - sync init + cell \n$8 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgl_pipe 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub20" -module \dec_sub20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -15951,726 +10809,8 @@ module \dec_sub20 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \form 5'01000 - end - sync init - end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \internal_op 7'0100110 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in1_sel 3'010 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in3_sel 2'01 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \out_sel 2'00 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \ldst_len 4'1000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \rc_sel 2'00 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \asmcode 8'01001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \asmcode 8'01010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \asmcode 8'01010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \asmcode 8'01011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'01100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \asmcode 8'10101001 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \br 1'1 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgl_pipe 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub21" -module \dec_sub21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -16683,40 +10823,28 @@ module \dec_sub21 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \main_cr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_cr_op__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_cr_op__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \main_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$9 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -16790,1269 +10918,151 @@ module \dec_sub21 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type$10 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \main_cr_op__fn_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_cr_op__read_cr_whole$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_cr_op__write_cr_whole$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \main_full_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \main_cr_a$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_cr_a_ok + cell \main$9 \main + connect \muxid \main_muxid + connect \cr_op__insn_type \main_cr_op__insn_type + connect \cr_op__fn_unit \main_cr_op__fn_unit + connect \cr_op__insn \main_cr_op__insn + connect \cr_op__read_cr_whole \main_cr_op__read_cr_whole + connect \cr_op__write_cr_whole \main_cr_op__write_cr_whole + connect \ra \main_ra + connect \rb \main_rb + connect \full_cr \main_full_cr + connect \cr_a \main_cr_a + connect \cr_b \main_cr_b + connect \cr_c \main_cr_c + connect \muxid$1 \main_muxid$9 + connect \cr_op__insn_type$2 \main_cr_op__insn_type$10 + connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$11 + connect \cr_op__insn$4 \main_cr_op__insn$12 + connect \cr_op__read_cr_whole$5 \main_cr_op__read_cr_whole$13 + connect \cr_op__write_cr_whole$6 \main_cr_op__write_cr_whole$14 + connect \o \main_o + connect \o_ok \main_o_ok + connect \full_cr$7 \main_full_cr$15 + connect \full_cr_ok \main_full_cr_ok + connect \cr_a$8 \main_cr_a$16 + connect \cr_a_ok \main_cr_a_ok + end process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] + assign \main_muxid 2'00 + assign \main_muxid \muxid sync init end process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \form 5'01000 - end - sync init - end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \internal_op 7'0100110 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in1_sel 3'010 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in2_sel 4'0001 - end + assign \main_cr_op__insn_type 7'0000000 + assign \main_cr_op__fn_unit 11'00000000000 + assign \main_cr_op__insn 32'00000000000000000000000000000000 + assign \main_cr_op__read_cr_whole 1'0 + assign \main_cr_op__write_cr_whole 1'0 + assign { \main_cr_op__write_cr_whole \main_cr_op__read_cr_whole \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } sync init end process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \in3_sel 2'01 - end + assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_ra \ra sync init end process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \out_sel 2'00 - end + assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_rb \rb sync init end process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_in 3'000 - end + assign \main_full_cr 32'00000000000000000000000000000000 + assign \main_full_cr \full_cr sync init end process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cr_out 3'000 - end + assign \main_cr_a 4'0000 + assign \main_cr_a \cr_a sync init end process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \ldst_len 4'0100 - end + assign \main_cr_b 4'0000 + assign \main_cr_b \cr_b sync init end process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \upd 2'10 - end + assign \main_cr_c 4'0000 + assign \main_cr_c \cr_c sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$17 process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rc_sel 2'00 - end + assign \p_valid_i$17 1'0 + assign \p_valid_i$17 \p_valid_i sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_in 2'00 - end + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$17 + connect \B \p_ready_o + connect \Y $18 + end process $group_14 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_a 1'0 - end + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $18 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$20 process $group_15 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \inv_out 1'0 - end - sync init - end - process $group_16 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \cry_out 1'0 - end - sync init - end - process $group_17 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \br 1'0 - end - sync init - end - process $group_18 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn_ext 1'0 - end - sync init - end - process $group_19 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \rsrv 1'0 - end - sync init - end - process $group_20 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \is_32b 1'0 - end - sync init - end - process $group_21 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgn 1'0 - end - sync init - end - process $group_22 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \lk 1'0 - end - sync init - end - process $group_23 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - assign \sgl_pipe 1'1 - end - sync init - end - process $group_24 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \asmcode 8'01010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'01010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \asmcode 8'01100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \asmcode 8'01100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \asmcode 8'10101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \asmcode 8'10101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11100 - end + assign \muxid$20 2'00 + assign \muxid$20 \main_muxid$9 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub23" -module \dec_sub23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -18126,1348 +11136,236 @@ module \dec_sub23 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \form 5'01000 - end - sync init - end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \internal_op 7'0100110 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in1_sel 3'010 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in3_sel 2'01 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \out_sel 2'00 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_out 3'000 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$21 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \cr_op__fn_unit$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \cr_op__read_cr_whole$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \cr_op__write_cr_whole$25 + process $group_16 + assign \cr_op__insn_type$21 7'0000000 + assign \cr_op__fn_unit$22 11'00000000000 + assign \cr_op__insn$23 32'00000000000000000000000000000000 + assign \cr_op__read_cr_whole$24 1'0 + assign \cr_op__write_cr_whole$25 1'0 + assign { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 } { \main_cr_op__write_cr_whole$14 \main_cr_op__read_cr_whole$13 \main_cr_op__insn$12 \main_cr_op__fn_unit$11 \main_cr_op__insn_type$10 } sync init end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \ldst_len 4'0100 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$27 + process $group_21 + assign \o$26 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$27 1'0 + assign { \o_ok$27 \o$26 } { \main_o_ok \main_o } sync init end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \upd 2'00 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \full_cr$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \full_cr_ok$29 + process $group_23 + assign \full_cr$28 32'00000000000000000000000000000000 + assign \full_cr_ok$29 1'0 + assign { \full_cr_ok$29 \full_cr$28 } { \main_full_cr_ok \main_full_cr$15 } sync init end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rc_sel 2'00 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$31 + process $group_25 + assign \cr_a$30 4'0000 + assign \cr_a_ok$31 1'0 + assign { \cr_a_ok$31 \cr_a$30 } { \main_cr_a_ok \main_cr_a$16 } sync init end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_27 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \asmcode 8'01001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \asmcode 8'01010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \asmcode 8'01011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \asmcode 8'01011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \asmcode 8'01011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \asmcode 8'01100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \asmcode 8'01101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'01101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \asmcode 8'10100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \asmcode 8'10100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \asmcode 8'10110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \asmcode 8'10110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \asmcode 8'10111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \asmcode 8'10111001 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 end sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_a 1'0 + process $group_28 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$20 end sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_out 1'0 + process $group_29 + assign \cr_op__insn_type$2$next \cr_op__insn_type$2 + assign \cr_op__fn_unit$3$next \cr_op__fn_unit$3 + assign \cr_op__insn$4$next \cr_op__insn$4 + assign \cr_op__read_cr_whole$5$next \cr_op__read_cr_whole$5 + assign \cr_op__write_cr_whole$6$next \cr_op__write_cr_whole$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_op__write_cr_whole$6$next \cr_op__read_cr_whole$5$next \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_op__write_cr_whole$6$next \cr_op__read_cr_whole$5$next \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 } end sync init + update \cr_op__insn_type$2 7'0000000 + update \cr_op__fn_unit$3 11'00000000000 + update \cr_op__insn$4 32'00000000000000000000000000000000 + update \cr_op__read_cr_whole$5 1'0 + update \cr_op__write_cr_whole$6 1'0 + sync posedge \coresync_clk + update \cr_op__insn_type$2 \cr_op__insn_type$2$next + update \cr_op__fn_unit$3 \cr_op__fn_unit$3$next + update \cr_op__insn$4 \cr_op__insn$4$next + update \cr_op__read_cr_whole$5 \cr_op__read_cr_whole$5$next + update \cr_op__write_cr_whole$6 \cr_op__write_cr_whole$6$next end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_out 1'0 + process $group_34 + assign \o$next \o + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$next } { \o_ok$27 \o$26 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$next } { \o_ok$27 \o$26 } end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \o_ok$next 1'0 end sync init + update \o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 + sync posedge \coresync_clk + update \o \o$next + update \o_ok \o_ok$next end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn_ext 1'0 + process $group_36 + assign \full_cr$7$next \full_cr$7 + assign \full_cr_ok$next \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \full_cr_ok$next \full_cr$7$next } { \full_cr_ok$29 \full_cr$28 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \full_cr_ok$next \full_cr$7$next } { \full_cr_ok$29 \full_cr$28 } end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \full_cr_ok$next 1'0 end sync init + update \full_cr$7 32'00000000000000000000000000000000 + update \full_cr_ok 1'0 + sync posedge \coresync_clk + update \full_cr$7 \full_cr$7$next + update \full_cr_ok \full_cr_ok$next end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \is_32b 1'0 + process $group_38 + assign \cr_a$8$next \cr_a$8 + assign \cr_a_ok$next \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$next \cr_a$8$next } { \cr_a_ok$31 \cr_a$30 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$next \cr_a$8$next } { \cr_a_ok$31 \cr_a$30 } end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cr_a_ok$next 1'0 end sync init + update \cr_a$8 4'0000 + update \cr_a_ok 1'0 + sync posedge \coresync_clk + update \cr_a$8 \cr_a$8$next + update \cr_a_ok \cr_a_ok$next end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \lk 1'0 - end + process $group_40 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy sync init end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'01100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgl_pipe 1'1 - end + process $group_41 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub16" -module \dec_sub16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0" +module \alu_cr0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \cr_a_ok + attribute \src "simple/issuer.py:102" + wire width 1 input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 6 \n_ready_i attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -19541,366 +11439,139 @@ module \dec_sub16 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \function_unit 11'00001000000 - end - sync init - end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \form 5'01010 - end - sync init - end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \internal_op 7'0110000 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in1_sel 3'100 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in2_sel 4'0000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \out_sel 2'00 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_in 3'110 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_out 3'100 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rc_sel 2'00 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \asmcode 8'01110100 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \lk 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \cr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 8 \cr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 9 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \cr_op__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \cr_op__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 12 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 output 13 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 14 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 15 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 16 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 17 \full_cr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 18 \cr_a$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 19 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 20 \cr_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 21 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 22 \p_ready_o + cell \p$5 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgl_pipe 1'0 - end - sync init + cell \n$6 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub18" -module \dec_sub18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -19913,40 +11584,32 @@ module \dec_sub18 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_cr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_cr_op__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_cr_op__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \pipe_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -20020,484 +11683,145 @@ module \dec_sub18 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_cr_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_cr_op__read_cr_whole$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_cr_op__write_cr_whole$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \pipe_full_cr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe_cr_a$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_cr_a_ok + cell \pipe \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_p_valid_i + connect \p_ready_o \pipe_p_ready_o + connect \muxid \pipe_muxid + connect \cr_op__insn_type \pipe_cr_op__insn_type + connect \cr_op__fn_unit \pipe_cr_op__fn_unit + connect \cr_op__insn \pipe_cr_op__insn + connect \cr_op__read_cr_whole \pipe_cr_op__read_cr_whole + connect \cr_op__write_cr_whole \pipe_cr_op__write_cr_whole + connect \ra \pipe_ra + connect \rb \pipe_rb + connect \full_cr \pipe_full_cr + connect \cr_a \pipe_cr_a + connect \cr_b \pipe_cr_b + connect \cr_c \pipe_cr_c + connect \n_valid_o \pipe_n_valid_o + connect \n_ready_i \pipe_n_ready_i + connect \muxid$1 \pipe_muxid$3 + connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 + connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 + connect \cr_op__insn$4 \pipe_cr_op__insn$6 + connect \cr_op__read_cr_whole$5 \pipe_cr_op__read_cr_whole$7 + connect \cr_op__write_cr_whole$6 \pipe_cr_op__write_cr_whole$8 + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \full_cr$7 \pipe_full_cr$9 + connect \full_cr_ok \pipe_full_cr_ok + connect \cr_a$8 \pipe_cr_a$10 + connect \cr_a_ok \pipe_cr_a_ok + end process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] + assign \pipe_p_valid_i 1'0 + assign \pipe_p_valid_i \p_valid_i sync init end process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \function_unit 11'00010000000 - end + assign \p_ready_o 1'0 + assign \p_ready_o \pipe_p_ready_o sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \form 5'01000 - end + assign \pipe_muxid 2'00 + assign \pipe_muxid \muxid sync init end process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \internal_op 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \internal_op 7'1001010 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in1_sel 3'100 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in2_sel 4'0000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \out_sel 2'00 - end + assign \pipe_cr_op__insn_type 7'0000000 + assign \pipe_cr_op__fn_unit 11'00000000000 + assign \pipe_cr_op__insn 32'00000000000000000000000000000000 + assign \pipe_cr_op__read_cr_whole 1'0 + assign \pipe_cr_op__write_cr_whole 1'0 + assign { \pipe_cr_op__write_cr_whole \pipe_cr_op__read_cr_whole \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } sync init end process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_in 3'000 - end + assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_ra \ra sync init end process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_out 3'000 - end + assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_rb \rb sync init end process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \ldst_len 4'0000 - end + assign \pipe_full_cr 32'00000000000000000000000000000000 + assign \pipe_full_cr \full_cr$1 sync init end process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \upd 2'00 - end + assign \pipe_cr_a 4'0000 + assign \pipe_cr_a \cr_a$2 sync init end process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rc_sel 2'00 - end + assign \pipe_cr_b 4'0000 + assign \pipe_cr_b \cr_b sync init end process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_in 2'00 - end + assign \pipe_cr_c 4'0000 + assign \pipe_cr_c \cr_c sync init end process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \asmcode 8'01110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \asmcode 8'01110101 - end + assign \n_valid_o 1'0 + assign \n_valid_o \pipe_n_valid_o sync init end process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_a 1'0 - end + assign \pipe_n_ready_i 1'0 + assign \pipe_n_ready_i \n_ready_i sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$11 process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgl_pipe 1'1 - end + assign \muxid$11 2'00 + assign \muxid$11 \pipe_muxid$3 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub8" -module \dec_sub8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -20571,1204 +11895,1077 @@ module \dec_sub8 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \cr_op__fn_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \cr_op__read_cr_whole$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \cr_op__write_cr_whole$16 + process $group_17 + assign \cr_op__insn_type$12 7'0000000 + assign \cr_op__fn_unit$13 11'00000000000 + assign \cr_op__insn$14 32'00000000000000000000000000000000 + assign \cr_op__read_cr_whole$15 1'0 + assign \cr_op__write_cr_whole$16 1'0 + assign { \cr_op__write_cr_whole$16 \cr_op__read_cr_whole$15 \cr_op__insn$14 \cr_op__fn_unit$13 \cr_op__insn_type$12 } { \pipe_cr_op__write_cr_whole$8 \pipe_cr_op__read_cr_whole$7 \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } sync init end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \function_unit 11'00000000010 - end + process $group_22 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'0 + assign { \o_ok \o } { \pipe_o_ok \pipe_o } sync init end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \form 5'10001 - end + process $group_24 + assign \full_cr 32'00000000000000000000000000000000 + assign \full_cr_ok 1'0 + assign { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$9 } sync init end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \internal_op 7'0000010 - end + process $group_26 + assign \cr_a 4'0000 + assign \cr_a_ok 1'0 + assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$10 } sync init end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in1_sel 3'001 - end - sync init + connect \muxid 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l" +module \src_l$10 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $1 end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in2_sel 4'0000 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B $1 + connect \Y $3 end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \in3_sel 2'00 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $3 + connect \B \s_src + connect \Y $5 end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \out_sel 2'01 + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 6'000000 end sync init + update \q_int 6'000000 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cr_in 3'000 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $7 end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cr_out 3'001 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B $7 + connect \Y $9 end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \ldst_len 4'0000 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $9 + connect \B \s_src + connect \Y $11 end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \upd 2'00 - end + process $group_1 + assign \q_src 6'000000 + assign \q_src $11 sync init end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \rc_sel 2'10 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 6 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \Y $13 end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cry_in 2'10 - end + process $group_2 + assign \qn_src 6'000000 + assign \qn_src $13 sync init end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \asmcode 8'10000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \asmcode 8'10000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \asmcode 8'10111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \asmcode 8'11000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'10111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \asmcode 8'10111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \asmcode 8'10111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \asmcode 8'10111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \asmcode 8'11000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \asmcode 8'11000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \asmcode 8'11000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \asmcode 8'11000100 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 6 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 6 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \B \q_int + connect \Y $15 end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \inv_a 1'1 - end + process $group_3 + assign \qlq_src 6'000000 + assign \qlq_src $15 sync init end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \inv_out 1'0 - end - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l" +module \opc_l$11 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $1 end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \cry_out 1'1 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \br 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_opc + connect \Y $5 end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgn_ext 1'0 + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \rsrv 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $7 end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \is_32b 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgn 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_opc + connect \Y $11 + end + process $group_1 + assign \q_opc 1'0 + assign \q_opc $11 sync init end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \lk 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $13 + end + process $group_2 + assign \qn_opc 1'0 + assign \qn_opc $13 sync init end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10110 - assign \sgl_pipe 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_opc 1'0 + assign \qlq_opc $15 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub24" -module \dec_sub24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l" +module \req_l$12 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $3 + connect \B \s_req + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 3'000 + end + sync init + update \q_int 3'000 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $9 + connect \B \s_req + connect \Y $11 + end + process $group_1 + assign \q_req 3'000 + assign \q_req $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $13 + end + process $group_2 + assign \qn_req 3'000 + assign \qn_req $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_req 3'000 + assign \qlq_req $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l" +module \rst_l$13 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rst + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rst + connect \Y $11 + end + process $group_1 + assign \q_rst 1'0 + assign \q_rst $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $13 + end + process $group_2 + assign \qn_rst 1'0 + assign \qn_rst $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rst 1'0 + assign \qlq_rst $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l" +module \rok_l$14 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rdok + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rdok + connect \Y $11 + end + process $group_1 + assign \q_rdok 1'0 + assign \q_rdok $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $13 + end + process $group_2 + assign \qn_rdok 1'0 + assign \qn_rdok $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rdok 1'0 + assign \qlq_rdok $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l" +module \alui_l$15 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alui + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alui + connect \Y $11 + end + process $group_1 + assign \q_alui 1'0 + assign \q_alui $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $13 + end + process $group_2 + assign \qn_alui 1'0 + assign \qn_alui $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alui 1'0 + assign \qlq_alui $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l" +module \alu_l$16 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alu + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alu + connect \Y $11 + end + process $group_1 + assign \q_alu 1'0 + assign \q_alu $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $13 + end + process $group_2 + assign \qn_alu 1'0 + assign \qn_alu $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alu 1'0 + assign \qlq_alu $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0" +module \cr0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -21842,582 +13039,8 @@ module \dec_sub24 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \function_unit 11'00000001000 - end - sync init - end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \form 5'01000 - end - sync init - end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \internal_op 7'0111101 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in1_sel 3'000 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \in3_sel 2'01 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \out_sel 2'10 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'10011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \asmcode 8'10011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \asmcode 8'10100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \asmcode 8'10100010 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \is_32b 1'1 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'11001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'10000 - assign \sgl_pipe 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub4" -module \dec_sub4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_cr0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -22430,40 +13053,58 @@ module \dec_sub4 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \oper_i_alu_cr0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \oper_i_alu_cr0__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \oper_i_alu_cr0__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 input 6 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 output 7 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 8 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 9 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 10 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 11 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 12 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 input 13 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 14 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 15 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 16 \src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 17 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 18 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 19 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 20 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 21 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 output 22 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 23 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 24 \dest3_o + attribute \src "simple/issuer.py:102" + wire width 1 input 25 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \alu_cr0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \alu_cr0_n_ready_i attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -22537,441 +13178,1726 @@ module \dec_sub4 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 5 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_cr0_cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_cr0_cr_op__insn_type$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_cr0_cr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_cr0_cr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_cr0_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_cr0_cr_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_cr0_cr_op__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_cr0_cr_op__read_cr_whole$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_cr0_cr_op__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_cr0_cr_op__write_cr_whole$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_cr0_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \alu_cr0_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_cr0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_cr0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_cr0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \alu_cr0_full_cr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \alu_cr0_cr_a$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \alu_cr0_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \alu_cr0_cr_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \alu_cr0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \alu_cr0_p_ready_o + cell \alu_cr0 \alu_cr0 + connect \coresync_clk \coresync_clk + connect \o_ok \o_ok + connect \full_cr_ok \full_cr_ok + connect \cr_a_ok \cr_a_ok + connect \coresync_rst \coresync_rst + connect \n_valid_o \alu_cr0_n_valid_o + connect \n_ready_i \alu_cr0_n_ready_i + connect \cr_op__insn_type \alu_cr0_cr_op__insn_type + connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit + connect \cr_op__insn \alu_cr0_cr_op__insn + connect \cr_op__read_cr_whole \alu_cr0_cr_op__read_cr_whole + connect \cr_op__write_cr_whole \alu_cr0_cr_op__write_cr_whole + connect \o \alu_cr0_o + connect \full_cr \alu_cr0_full_cr + connect \cr_a \alu_cr0_cr_a + connect \ra \alu_cr0_ra + connect \rb \alu_cr0_rb + connect \full_cr$1 \alu_cr0_full_cr$1 + connect \cr_a$2 \alu_cr0_cr_a$2 + connect \cr_b \alu_cr0_cr_b + connect \cr_c \alu_cr0_cr_c + connect \p_valid_i \alu_cr0_p_valid_i + connect \p_ready_o \alu_cr0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 \src_l_q_src + cell \src_l$10 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_src \src_l_s_src + connect \r_src \src_l_r_src + connect \q_src \src_l_q_src + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \opc_l_q_opc + cell \opc_l$11 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_opc \opc_l_s_opc + connect \r_opc \opc_l_r_opc + connect \q_opc \opc_l_q_opc + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req$next + cell \req_l$12 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \s_req \req_l_s_req + connect \r_req \req_l_r_req + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst$next + cell \rst_l$13 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_rst \rst_l_s_rst + connect \r_rst \rst_l_r_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok$next + cell \rok_l$14 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \s_rdok \rok_l_s_rdok + connect \r_rdok \rok_l_r_rdok + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alui_l_s_alui + cell \alui_l$15 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_s_alu + cell \alu_l$16 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 6 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__rel_o + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 6 $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $6 + connect \B \cu_rd__go_i + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B $5 + connect \Y $11 + end process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] + assign \all_rd 1'0 + assign \all_rd $11 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly$next process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \function_unit 11'00010000000 - end + assign \all_rd_dly$next \all_rd_dly + assign \all_rd_dly$next \all_rd sync init + update \all_rd_dly 1'0 + sync posedge \coresync_clk + update \all_rd_dly \all_rd_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B $13 + connect \Y $15 end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \form 5'01000 - end + assign \all_rd_rise 1'0 + assign \all_rd_rise $15 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire width 1 \all_rd_pulse process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \internal_op 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \internal_op 7'0111111 - end + assign \all_rd_pulse 1'0 + assign \all_rd_pulse \all_rd_rise sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire width 1 \alu_done process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in1_sel 3'001 - end + assign \alu_done 1'0 + assign \alu_done \alu_cr0_n_valid_o sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly$next process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in2_sel 4'0001 - end + assign \alu_done_dly$next \alu_done_dly + assign \alu_done_dly$next \alu_done sync init + update \alu_done_dly 1'0 + sync posedge \coresync_clk + update \alu_done_dly \alu_done_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B $17 + connect \Y $19 end process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \in3_sel 2'00 - end + assign \alu_done_rise 1'0 + assign \alu_done_rise $19 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire width 1 \alu_pulse process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \out_sel 2'00 - end + assign \alu_pulse 1'0 + assign \alu_pulse \alu_done_rise sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 3 \alu_pulsem process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_in 3'000 - end + assign \alu_pulsem 3'000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 3 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $21 + end process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cr_out 3'000 + assign \prev_wr_go$next \prev_wr_go + assign \prev_wr_go$next $21 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \prev_wr_go$next 3'000 end sync init + update \prev_wr_go 3'000 + sync posedge \coresync_clk + update \prev_wr_go \prev_wr_go$next end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \ldst_len 4'0000 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire width 1 \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 3 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $25 end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \upd 2'00 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__rel_o + connect \B $25 + connect \Y $27 end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rc_sel 2'00 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $27 + connect \Y $24 end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_in 2'00 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \asmcode 8'11000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \asmcode 8'11001000 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B $23 + connect \Y $31 end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_a 1'0 - end + process $group_10 + assign \cu_done_o 1'0 + assign \cu_done_o $31 sync init end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \inv_out 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $33 end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \cry_out 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $35 end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \br 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $33 + connect \B $35 + connect \Y $37 end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn_ext 1'0 - end + process $group_11 + assign \wr_any 1'0 + assign \wr_any $37 sync init end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \rsrv 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire width 1 \req_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_ready_i + connect \Y $39 end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \is_32b 1'1 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B $39 + connect \Y $41 end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgn 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 3 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $43 end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \lk 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $43 + connect \B 1'0 + connect \Y $45 end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 5'00000 - assign \sgl_pipe 1'1 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $41 + connect \B $45 + connect \Y $47 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31" -module \dec31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $49 + connect \B \alu_cr0_n_ready_i + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $51 + connect \B \alu_cr0_n_valid_o + connect \Y $53 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $53 + connect \B \cu_busy_o + connect \Y $55 + end + process $group_12 + assign \req_done 1'0 + assign \req_done $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch { $55 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + case 1'1 + assign \req_done 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire width 1 \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire width 1 \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $57 + end + process $group_13 + assign \reset 1'0 + assign \reset $57 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire width 1 \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $59 + end + process $group_14 + assign \rst_r 1'0 + assign \rst_r $59 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 3 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 3 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $61 + end + process $group_15 + assign \reset_w 3'000 + assign \reset_w $61 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 6 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 6 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $63 + end + process $group_16 + assign \reset_r 6'000000 + assign \reset_r $63 + sync init + end + process $group_17 + assign \rok_l_s_rdok$next \rok_l_s_rdok + assign \rok_l_s_rdok$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_s_rdok$next 1'0 + end + sync init + update \rok_l_s_rdok 1'0 + sync posedge \coresync_clk + update \rok_l_s_rdok \rok_l_s_rdok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_valid_o + connect \B \cu_busy_o + connect \Y $65 + end + process $group_18 + assign \rok_l_r_rdok$next \rok_l_r_rdok + assign \rok_l_r_rdok$next $65 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_r_rdok$next 1'1 + end + sync init + update \rok_l_r_rdok 1'1 + sync posedge \coresync_clk + update \rok_l_r_rdok \rok_l_r_rdok$next + end + process $group_19 + assign \rst_l_s_rst$next \rst_l_s_rst + assign \rst_l_s_rst$next \all_rd + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_s_rst$next 1'0 + end + sync init + update \rst_l_s_rst 1'0 + sync posedge \coresync_clk + update \rst_l_s_rst \rst_l_s_rst$next + end + process $group_20 + assign \rst_l_r_rst$next \rst_l_r_rst + assign \rst_l_r_rst$next \rst_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_r_rst$next 1'1 + end + sync init + update \rst_l_r_rst 1'1 + sync posedge \coresync_clk + update \rst_l_r_rst \rst_l_r_rst$next + end + process $group_21 + assign \opc_l_s_opc$next \opc_l_s_opc + assign \opc_l_s_opc$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_s_opc$next 1'0 + end + sync init + update \opc_l_s_opc 1'0 + sync posedge \coresync_clk + update \opc_l_s_opc \opc_l_s_opc$next + end + process $group_22 + assign \opc_l_r_opc$next \opc_l_r_opc + assign \opc_l_r_opc$next \req_done + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_r_opc$next 1'1 + end + sync init + update \opc_l_r_opc 1'1 + sync posedge \coresync_clk + update \opc_l_r_opc \opc_l_r_opc$next + end + process $group_23 + assign \src_l_s_src$next \src_l_s_src + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_s_src$next 6'000000 + end + sync init + update \src_l_s_src 6'000000 + sync posedge \coresync_clk + update \src_l_s_src \src_l_s_src$next + end + process $group_24 + assign \src_l_r_src$next \src_l_r_src + assign \src_l_r_src$next \reset_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_r_src$next 6'111111 + end + sync init + update \src_l_r_src 6'111111 + sync posedge \coresync_clk + update \src_l_r_src \src_l_r_src$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 3 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $67 + end + process $group_25 + assign \req_l_s_req$next \req_l_s_req + assign \req_l_s_req$next $67 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_s_req$next 3'000 + end + sync init + update \req_l_s_req 3'000 + sync posedge \coresync_clk + update \req_l_s_req \req_l_s_req$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 3 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $69 + end + process $group_26 + assign \req_l_r_req$next \req_l_r_req + assign \req_l_r_req$next $69 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_r_req$next 3'111 + end + sync init + update \req_l_r_req 3'111 + sync posedge \coresync_clk + update \req_l_r_req \req_l_r_req$next + end + process $group_27 + assign \alu_cr0_cr_op__insn_type$next \alu_cr0_cr_op__insn_type + assign \alu_cr0_cr_op__fn_unit$next \alu_cr0_cr_op__fn_unit + assign \alu_cr0_cr_op__insn$next \alu_cr0_cr_op__insn + assign \alu_cr0_cr_op__read_cr_whole$next \alu_cr0_cr_op__read_cr_whole + assign \alu_cr0_cr_op__write_cr_whole$next \alu_cr0_cr_op__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + case 1'1 + assign { \alu_cr0_cr_op__write_cr_whole$next \alu_cr0_cr_op__read_cr_whole$next \alu_cr0_cr_op__insn$next \alu_cr0_cr_op__fn_unit$next \alu_cr0_cr_op__insn_type$next } { \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + end + sync init + update \alu_cr0_cr_op__insn_type 7'0000000 + update \alu_cr0_cr_op__fn_unit 11'00000000000 + update \alu_cr0_cr_op__insn 32'00000000000000000000000000000000 + update \alu_cr0_cr_op__read_cr_whole 1'0 + update \alu_cr0_cr_op__write_cr_whole 1'0 + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn_type \alu_cr0_cr_op__insn_type$next + update \alu_cr0_cr_op__fn_unit \alu_cr0_cr_op__fn_unit$next + update \alu_cr0_cr_op__insn \alu_cr0_cr_op__insn$next + update \alu_cr0_cr_op__read_cr_whole \alu_cr0_cr_op__read_cr_whole$next + update \alu_cr0_cr_op__write_cr_whole \alu_cr0_cr_op__write_cr_whole$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok$next + process $group_32 + assign \data_r0__o$next \data_r0__o + assign \data_r0__o_ok$next \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_cr0_o } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r0__o_ok$next 1'0 + end + sync init + update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0__o_ok 1'0 + sync posedge \coresync_clk + update \data_r0__o \data_r0__o$next + update \data_r0__o_ok \data_r0__o_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 32 \data_r1__full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 32 \data_r1__full_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__full_cr_ok$next + process $group_34 + assign \data_r1__full_cr$next \data_r1__full_cr + assign \data_r1__full_cr_ok$next \data_r1__full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r1__full_cr_ok$next \data_r1__full_cr$next } { \full_cr_ok \alu_cr0_full_cr } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r1__full_cr_ok$next \data_r1__full_cr$next } 33'000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r1__full_cr_ok$next 1'0 + end + sync init + update \data_r1__full_cr 32'00000000000000000000000000000000 + update \data_r1__full_cr_ok 1'0 + sync posedge \coresync_clk + update \data_r1__full_cr \data_r1__full_cr$next + update \data_r1__full_cr_ok \data_r1__full_cr_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r2__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r2__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__cr_a_ok$next + process $group_36 + assign \data_r2__cr_a$next \data_r2__cr_a + assign \data_r2__cr_a_ok$next \data_r2__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r2__cr_a_ok$next \data_r2__cr_a$next } { \cr_a_ok \alu_cr0_cr_a } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r2__cr_a_ok$next \data_r2__cr_a$next } 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r2__cr_a_ok$next 1'0 + end + sync init + update \data_r2__cr_a 4'0000 + update \data_r2__cr_a_ok 1'0 + sync posedge \coresync_clk + update \data_r2__cr_a \data_r2__cr_a$next + update \data_r2__cr_a_ok \data_r2__cr_a_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $71 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \full_cr_ok + connect \B \cu_busy_o + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $75 + end + process $group_38 + assign \cu_wrmask_o 3'000 + assign \cu_wrmask_o { $75 $73 $71 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $78 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $77 + end + process $group_39 + assign \alu_cr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_cr0_ra $77 + sync init + end + process $group_40 + assign \src_r0$next \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [0] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r0$next \src1_i + end + sync init + update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r0 \src_r0$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $80 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $79 + end + process $group_41 + assign \alu_cr0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_cr0_rb $79 + sync init + end + process $group_42 + assign \src_r1$next \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [1] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r1$next \src2_i + end + sync init + update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r1 \src_r1$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 32 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 32 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 32 $81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $82 + parameter \WIDTH 32 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $81 + end + process $group_43 + assign \alu_cr0_full_cr$1 32'00000000000000000000000000000000 + assign \alu_cr0_full_cr$1 $81 + sync init + end + process $group_44 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r2$next \src3_i + end + sync init + update \src_r2 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r2 \src_r2$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 $83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $84 + parameter \WIDTH 4 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $83 + end + process $group_45 + assign \alu_cr0_cr_a$2 4'0000 + assign \alu_cr0_cr_a$2 $83 + sync init + end + process $group_46 + assign \src_r3$next \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [3] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r3$next \src4_i + end + sync init + update \src_r3 4'0000 + sync posedge \coresync_clk + update \src_r3 \src_r3$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r4$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 $85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $86 + parameter \WIDTH 4 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $85 + end + process $group_47 + assign \alu_cr0_cr_b 4'0000 + assign \alu_cr0_cr_b $85 + sync init + end + process $group_48 + assign \src_r4$next \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [4] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r4$next \src5_i + end + sync init + update \src_r4 4'0000 + sync posedge \coresync_clk + update \src_r4 \src_r4$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r5$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 $87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $88 + parameter \WIDTH 4 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $87 + end + process $group_49 + assign \alu_cr0_cr_c 4'0000 + assign \alu_cr0_cr_c $87 + sync init + end + process $group_50 + assign \src_r5$next \src_r5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [5] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r5$next \src6_i + end + sync init + update \src_r5 4'0000 + sync posedge \coresync_clk + update \src_r5 \src_r5$next + end + process $group_51 + assign \alu_cr0_p_valid_i 1'0 + assign \alu_cr0_p_valid_i \alui_l_q_alui + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $89 + end + process $group_52 + assign \alui_l_r_alui$next \alui_l_r_alui + assign \alui_l_r_alui$next $89 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alui_l_r_alui$next 1'1 + end + sync init + update \alui_l_r_alui 1'1 + sync posedge \coresync_clk + update \alui_l_r_alui \alui_l_r_alui$next + end + process $group_53 + assign \alui_l_s_alui 1'0 + assign \alui_l_s_alui \all_rd_pulse + sync init + end + process $group_54 + assign \alu_cr0_n_ready_i 1'0 + assign \alu_cr0_n_ready_i \alu_l_q_alu + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $91 + end + process $group_55 + assign \alu_l_r_alu$next \alu_l_r_alu + assign \alu_l_r_alu$next $91 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_l_r_alu$next 1'1 + end + sync init + update \alu_l_r_alu 1'1 + sync posedge \coresync_clk + update \alu_l_r_alu \alu_l_r_alu$next + end + process $group_56 + assign \alu_l_s_alu 1'0 + assign \alu_l_s_alu \all_rd_pulse + sync init + end + process $group_57 + assign \cu_busy_o 1'0 + assign \cu_busy_o \opc_l_q_opc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $93 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $93 + connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 } + connect \Y $95 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rdmaskn_i + connect \Y $97 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $95 + connect \B $97 + connect \Y $99 + end + process $group_58 + assign \cu_rd__rel_o 6'000000 + assign \cu_rd__rel_o $99 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire width 1 \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $101 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $103 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $105 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B { $101 $103 $105 } + connect \Y $107 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $107 + connect \B \cu_wrmask_o + connect \Y $109 + end + process $group_59 + assign \cu_wr__rel_o 3'000 + assign \cu_wr__rel_o $109 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $111 + end + process $group_60 + assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $111 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $113 + end + process $group_61 + assign \dest2_o 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $113 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest2_o { \data_r1__full_cr_ok \data_r1__full_cr } [31:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $115 + end + process $group_62 + assign \dest3_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $115 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest3_o { \data_r2__cr_a_ok \data_r2__cr_a } [3:0] + end + sync init + end + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.p" +module \p$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.n" +module \n$18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.p" +module \p$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.n" +module \n$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.main" +module \main$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 1 \br_op__cia + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \br_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" attribute \enum_value_00000000100 "LDST" attribute \enum_value_00000001000 "SHIFT_ROT" attribute \enum_value_00000010000 "LOGICAL" @@ -22981,40 +14907,28 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 3 \br_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 4 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \br_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \br_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 12 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 13 \br_op__cia$2 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -23088,115 +15002,8 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub10_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 14 \br_op__insn_type$3 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -23209,40 +15016,534 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub10_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub10_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 15 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \br_op__insn$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 17 \br_op__imm_data__imm$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 18 \br_op__imm_data__imm_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 19 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 20 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 21 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 22 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 23 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 24 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 25 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 26 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" + wire width 64 \br_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $eq $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \br_op__insn_type + connect \B 7'0001000 + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $or $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A { \br_op__insn [1] } + connect \B $12 + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87" + wire width 64 \br_imm_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + wire width 65 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + wire width 65 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \br_imm_addr + connect \B \br_op__cia + connect \Y $17 + end + connect $16 $17 + process $group_0 + assign \br_addr 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + case 1'1 + assign \br_addr \br_imm_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:94" + case + assign \br_addr $16 [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:105" + wire width 2 \bi + process $group_1 + assign \bi 2'00 + assign \bi { \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] } [1:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:106" + wire width 1 \cr_bit + process $group_2 + assign \cr_bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:108" + switch \bi + case 2'00 + assign \cr_bit \cr_a [3] + case 2'01 + assign \cr_bit \cr_a [2] + case 2'10 + assign \cr_bit \cr_a [1] + case 2'-- + assign \cr_bit \cr_a [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:111" + wire width 1 \ctr_write + process $group_3 + assign \ctr_write 1'0 + assign \ctr_write 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + case + assign \ctr_write 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" + wire width 1 \bc_taken + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \B { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [3] + connect \Y $19 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" + cell $or $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $19 + connect \B { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4] + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" + cell $eq $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4:3] + connect \B 1'0 + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + cell $eq $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4:3] + connect \B 1'1 + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + cell $eq $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4] + connect \B 1'1 + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:131" + wire width 1 \ctr_zero_bo1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:134" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:134" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:134" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:134" + cell $and $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B $29 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $and $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \cr_bit + connect \Y $33 + end + process $group_4 + assign \bc_taken 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + case 1'1 + assign \bc_taken $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" + switch { $27 $25 $23 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" + case 3'--1 + assign \bc_taken $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + case 3'-1- + assign \bc_taken $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + case 3'1-- + assign \bc_taken \ctr_zero_bo1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + wire width 64 \ctr_n + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + wire width 65 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + wire width 65 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $sub $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \fast1 + connect \B 1'1 + connect \Y $36 + end + connect $35 $36 + process $group_5 + assign \ctr_n 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + case + assign \ctr_n $35 [63:0] + end + sync init + end + process $group_6 + assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + case + assign \fast1$10 \ctr_n + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + wire width 64 \ctr_m + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 64 $38 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \fast1 [31:0] + connect \Y $38 + end + process $group_7 + assign \ctr_m 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:126" + switch { \br_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:126" + case 1'1 + assign \ctr_m $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:128" + case + assign \ctr_m \fast1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" + cell $reduce_or $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \ctr_m + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" + cell $xor $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [1] + connect \B $40 + connect \Y $42 + end + process $group_8 + assign \ctr_zero_bo1 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118" + case + assign \ctr_zero_bo1 $42 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + cell $not $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A { \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] \br_op__insn [1] } [5] + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + cell $and $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A { \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] \br_op__insn [1] } [9] + connect \B $44 + connect \Y $46 + end + process $group_9 + assign \br_imm_addr 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + switch \br_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:143" + attribute \nmigen.decoding "OP_B/6" + case 7'0000110 + assign \br_imm_addr { { { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] } { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } } 2'00 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:148" + attribute \nmigen.decoding "OP_BC/7" + case 7'0000111 + assign \br_imm_addr { { { { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] } { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } } 2'00 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:154" + attribute \nmigen.decoding "OP_BCREG/8" + case 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + switch { $46 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:156" + case 1'1 + assign \br_imm_addr { \fast1 [63:2] 2'00 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" + case + assign \br_imm_addr { \fast2 [63:2] 2'00 } + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" + wire width 1 \br_taken + process $group_10 + assign \br_taken 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + switch \br_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:143" + attribute \nmigen.decoding "OP_B/6" + case 7'0000110 + assign \br_taken 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:148" + attribute \nmigen.decoding "OP_BC/7" + case 7'0000111 + assign \br_taken \bc_taken + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:154" + attribute \nmigen.decoding "OP_BCREG/8" + case 7'0001000 + assign \br_taken \bc_taken + end + sync init + end + process $group_11 + assign \fast1_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + switch \br_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:143" + attribute \nmigen.decoding "OP_B/6" + case 7'0000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:148" + attribute \nmigen.decoding "OP_BC/7" + case 7'0000111 + assign \fast1_ok \ctr_write + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:154" + attribute \nmigen.decoding "OP_BCREG/8" + case 7'0001000 + assign \fast1_ok \ctr_write + end + sync init + end + process $group_12 + assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \nia \br_addr + sync init + end + process $group_13 + assign \nia_ok 1'0 + assign \nia_ok \br_taken + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:171" + wire width 65 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:171" + wire width 65 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:171" + cell $add $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \br_op__cia + connect \B 3'100 + connect \Y $49 + end + connect $48 $49 + process $group_14 + assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:168" + switch { \br_op__lk } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:168" + case 1'1 + assign \fast2$11 $48 [63:0] + end + sync init + end + process $group_15 + assign \fast2_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:168" + switch { \br_op__lk } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:168" + case 1'1 + assign \fast2_ok 1'1 + end + sync init + end + process $group_16 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_17 + assign \br_op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \br_op__insn_type$3 7'0000000 + assign \br_op__fn_unit$4 11'00000000000 + assign \br_op__insn$5 32'00000000000000000000000000000000 + assign \br_op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \br_op__imm_data__imm_ok$7 1'0 + assign \br_op__lk$8 1'0 + assign \br_op__is_32bit$9 1'0 + assign { \br_op__is_32bit$9 \br_op__lk$8 { \br_op__imm_data__imm_ok$7 \br_op__imm_data__imm$6 } \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe" +module \pipe$19 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \br_op__cia attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -23316,142 +15617,8 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub10_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub10_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub10_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub10_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub10_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub10_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub10_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub10_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub10_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub10_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub10_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub10_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub10_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub10_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub10_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub10_asmcode - cell \dec_sub10 \dec_sub10 - connect \opcode_in \dec_sub10_opcode_in - connect \function_unit \dec_sub10_function_unit - connect \form \dec_sub10_form - connect \internal_op \dec_sub10_internal_op - connect \in1_sel \dec_sub10_in1_sel - connect \in2_sel \dec_sub10_in2_sel - connect \in3_sel \dec_sub10_in3_sel - connect \out_sel \dec_sub10_out_sel - connect \cr_in \dec_sub10_cr_in - connect \cr_out \dec_sub10_cr_out - connect \rc_sel \dec_sub10_rc_sel - connect \ldst_len \dec_sub10_ldst_len - connect \upd \dec_sub10_upd - connect \cry_in \dec_sub10_cry_in - connect \inv_a \dec_sub10_inv_a - connect \inv_out \dec_sub10_inv_out - connect \cry_out \dec_sub10_cry_out - connect \br \dec_sub10_br - connect \sgn_ext \dec_sub10_sgn_ext - connect \rsrv \dec_sub10_rsrv - connect \is_32b \dec_sub10_is_32b - connect \sgn \dec_sub10_sgn - connect \lk \dec_sub10_lk - connect \sgl_pipe \dec_sub10_sgl_pipe - connect \asmcode \dec_sub10_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub28_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \br_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -23464,40 +15631,36 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub28_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub28_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 7 \br_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 8 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \br_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \br_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 16 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 17 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \br_op__cia$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -23571,142 +15734,10 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub28_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub28_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub28_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub28_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub28_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub28_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub28_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub28_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub28_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub28_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub28_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub28_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub28_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub28_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub28_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub28_asmcode - cell \dec_sub28 \dec_sub28 - connect \opcode_in \dec_sub28_opcode_in - connect \function_unit \dec_sub28_function_unit - connect \form \dec_sub28_form - connect \internal_op \dec_sub28_internal_op - connect \in1_sel \dec_sub28_in1_sel - connect \in2_sel \dec_sub28_in2_sel - connect \in3_sel \dec_sub28_in3_sel - connect \out_sel \dec_sub28_out_sel - connect \cr_in \dec_sub28_cr_in - connect \cr_out \dec_sub28_cr_out - connect \rc_sel \dec_sub28_rc_sel - connect \ldst_len \dec_sub28_ldst_len - connect \upd \dec_sub28_upd - connect \cry_in \dec_sub28_cry_in - connect \inv_a \dec_sub28_inv_a - connect \inv_out \dec_sub28_inv_out - connect \cry_out \dec_sub28_cry_out - connect \br \dec_sub28_br - connect \sgn_ext \dec_sub28_sgn_ext - connect \rsrv \dec_sub28_rsrv - connect \is_32b \dec_sub28_is_32b - connect \sgn \dec_sub28_sgn - connect \lk \dec_sub28_lk - connect \sgl_pipe \dec_sub28_sgl_pipe - connect \asmcode \dec_sub28_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub0_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$3$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -23719,40 +15750,66 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub0_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub0_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 21 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \br_op__fn_unit$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \br_op__insn$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 23 \br_op__imm_data__imm$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__imm$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 24 \br_op__imm_data__imm_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \br_op__imm_data__imm_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 25 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \br_op__lk$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 26 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \br_op__is_32bit$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 27 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 28 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 29 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 30 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fast2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 31 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 32 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \nia_ok$next + cell \p$20 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$21 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -23826,142 +15883,8 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub0_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub0_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub0_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub0_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub0_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub0_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub0_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub0_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub0_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub0_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub0_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub0_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub0_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub0_asmcode - cell \dec_sub0 \dec_sub0 - connect \opcode_in \dec_sub0_opcode_in - connect \function_unit \dec_sub0_function_unit - connect \form \dec_sub0_form - connect \internal_op \dec_sub0_internal_op - connect \in1_sel \dec_sub0_in1_sel - connect \in2_sel \dec_sub0_in2_sel - connect \in3_sel \dec_sub0_in3_sel - connect \out_sel \dec_sub0_out_sel - connect \cr_in \dec_sub0_cr_in - connect \cr_out \dec_sub0_cr_out - connect \rc_sel \dec_sub0_rc_sel - connect \ldst_len \dec_sub0_ldst_len - connect \upd \dec_sub0_upd - connect \cry_in \dec_sub0_cry_in - connect \inv_a \dec_sub0_inv_a - connect \inv_out \dec_sub0_inv_out - connect \cry_out \dec_sub0_cry_out - connect \br \dec_sub0_br - connect \sgn_ext \dec_sub0_sgn_ext - connect \rsrv \dec_sub0_rsrv - connect \is_32b \dec_sub0_is_32b - connect \sgn \dec_sub0_sgn - connect \lk \dec_sub0_lk - connect \sgl_pipe \dec_sub0_sgl_pipe - connect \asmcode \dec_sub0_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub26_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -23974,40 +15897,28 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub26_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub26_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \main_br_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_br_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia$13 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -24081,142 +15992,8 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub26_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub26_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub26_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub26_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub26_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub26_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub26_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub26_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub26_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub26_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub26_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub26_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub26_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub26_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub26_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub26_asmcode - cell \dec_sub26 \dec_sub26 - connect \opcode_in \dec_sub26_opcode_in - connect \function_unit \dec_sub26_function_unit - connect \form \dec_sub26_form - connect \internal_op \dec_sub26_internal_op - connect \in1_sel \dec_sub26_in1_sel - connect \in2_sel \dec_sub26_in2_sel - connect \in3_sel \dec_sub26_in3_sel - connect \out_sel \dec_sub26_out_sel - connect \cr_in \dec_sub26_cr_in - connect \cr_out \dec_sub26_cr_out - connect \rc_sel \dec_sub26_rc_sel - connect \ldst_len \dec_sub26_ldst_len - connect \upd \dec_sub26_upd - connect \cry_in \dec_sub26_cry_in - connect \inv_a \dec_sub26_inv_a - connect \inv_out \dec_sub26_inv_out - connect \cry_out \dec_sub26_cry_out - connect \br \dec_sub26_br - connect \sgn_ext \dec_sub26_sgn_ext - connect \rsrv \dec_sub26_rsrv - connect \is_32b \dec_sub26_is_32b - connect \sgn \dec_sub26_sgn - connect \lk \dec_sub26_lk - connect \sgl_pipe \dec_sub26_sgl_pipe - connect \asmcode \dec_sub26_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type$14 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -24229,40 +16006,134 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub19_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub19_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \main_br_op__fn_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__imm$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_br_op__imm_data__imm_ok$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_br_op__lk$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_br_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast1$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast2$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_nia_ok + cell \main$22 \main + connect \muxid \main_muxid + connect \br_op__cia \main_br_op__cia + connect \br_op__insn_type \main_br_op__insn_type + connect \br_op__fn_unit \main_br_op__fn_unit + connect \br_op__insn \main_br_op__insn + connect \br_op__imm_data__imm \main_br_op__imm_data__imm + connect \br_op__imm_data__imm_ok \main_br_op__imm_data__imm_ok + connect \br_op__lk \main_br_op__lk + connect \br_op__is_32bit \main_br_op__is_32bit + connect \fast1 \main_fast1 + connect \fast2 \main_fast2 + connect \cr_a \main_cr_a + connect \muxid$1 \main_muxid$12 + connect \br_op__cia$2 \main_br_op__cia$13 + connect \br_op__insn_type$3 \main_br_op__insn_type$14 + connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 + connect \br_op__insn$5 \main_br_op__insn$16 + connect \br_op__imm_data__imm$6 \main_br_op__imm_data__imm$17 + connect \br_op__imm_data__imm_ok$7 \main_br_op__imm_data__imm_ok$18 + connect \br_op__lk$8 \main_br_op__lk$19 + connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok + connect \nia \main_nia + connect \nia_ok \main_nia_ok + end + process $group_0 + assign \main_muxid 2'00 + assign \main_muxid \muxid + sync init + end + process $group_1 + assign \main_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_br_op__insn_type 7'0000000 + assign \main_br_op__fn_unit 11'00000000000 + assign \main_br_op__insn 32'00000000000000000000000000000000 + assign \main_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_br_op__imm_data__imm_ok 1'0 + assign \main_br_op__lk 1'0 + assign \main_br_op__is_32bit 1'0 + assign { \main_br_op__is_32bit \main_br_op__lk { \main_br_op__imm_data__imm_ok \main_br_op__imm_data__imm } \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + sync init + end + process $group_9 + assign \main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_fast1 \fast1 + sync init + end + process $group_10 + assign \main_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_fast2 \fast2 + sync init + end + process $group_11 + assign \main_cr_a 4'0000 + assign \main_cr_a \cr_a + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$23 + process $group_12 + assign \p_valid_i$23 1'0 + assign \p_valid_i$23 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_13 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$23 + connect \B \p_ready_o + connect \Y $24 + end + process $group_14 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $24 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$26 + process $group_15 + assign \muxid$26 2'00 + assign \muxid$26 \main_muxid$12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$27 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -24336,142 +16207,8 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub19_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub19_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub19_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub19_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub19_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub19_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub19_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub19_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub19_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub19_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub19_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub19_asmcode - cell \dec_sub19 \dec_sub19 - connect \opcode_in \dec_sub19_opcode_in - connect \function_unit \dec_sub19_function_unit - connect \form \dec_sub19_form - connect \internal_op \dec_sub19_internal_op - connect \in1_sel \dec_sub19_in1_sel - connect \in2_sel \dec_sub19_in2_sel - connect \in3_sel \dec_sub19_in3_sel - connect \out_sel \dec_sub19_out_sel - connect \cr_in \dec_sub19_cr_in - connect \cr_out \dec_sub19_cr_out - connect \rc_sel \dec_sub19_rc_sel - connect \ldst_len \dec_sub19_ldst_len - connect \upd \dec_sub19_upd - connect \cry_in \dec_sub19_cry_in - connect \inv_a \dec_sub19_inv_a - connect \inv_out \dec_sub19_inv_out - connect \cry_out \dec_sub19_cry_out - connect \br \dec_sub19_br - connect \sgn_ext \dec_sub19_sgn_ext - connect \rsrv \dec_sub19_rsrv - connect \is_32b \dec_sub19_is_32b - connect \sgn \dec_sub19_sgn - connect \lk \dec_sub19_lk - connect \sgl_pipe \dec_sub19_sgl_pipe - connect \asmcode \dec_sub19_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub22_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$28 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -24484,40 +16221,246 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub22_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub22_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \br_op__fn_unit$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__imm$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \br_op__imm_data__imm_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \br_op__lk$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \br_op__is_32bit$34 + process $group_16 + assign \br_op__cia$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \br_op__insn_type$28 7'0000000 + assign \br_op__fn_unit$29 11'00000000000 + assign \br_op__insn$30 32'00000000000000000000000000000000 + assign \br_op__imm_data__imm$31 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \br_op__imm_data__imm_ok$32 1'0 + assign \br_op__lk$33 1'0 + assign \br_op__is_32bit$34 1'0 + assign { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 { \main_br_op__imm_data__imm_ok$18 \main_br_op__imm_data__imm$17 } \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fast1_ok$36 + process $group_24 + assign \fast1$35 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1_ok$36 1'0 + assign { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fast2_ok$38 + process $group_26 + assign \fast2$37 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2_ok$38 1'0 + assign { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \nia$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \nia_ok$40 + process $group_28 + assign \nia$39 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \nia_ok$40 1'0 + assign { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_30 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_31 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$26 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_32 + assign \br_op__cia$2$next \br_op__cia$2 + assign \br_op__insn_type$3$next \br_op__insn_type$3 + assign \br_op__fn_unit$4$next \br_op__fn_unit$4 + assign \br_op__insn$5$next \br_op__insn$5 + assign \br_op__imm_data__imm$6$next \br_op__imm_data__imm$6 + assign \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm_ok$7 + assign \br_op__lk$8$next \br_op__lk$8 + assign \br_op__is_32bit$9$next \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \br_op__imm_data__imm$6$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \br_op__imm_data__imm_ok$7$next 1'0 + end + sync init + update \br_op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000 + update \br_op__insn_type$3 7'0000000 + update \br_op__fn_unit$4 11'00000000000 + update \br_op__insn$5 32'00000000000000000000000000000000 + update \br_op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000 + update \br_op__imm_data__imm_ok$7 1'0 + update \br_op__lk$8 1'0 + update \br_op__is_32bit$9 1'0 + sync posedge \coresync_clk + update \br_op__cia$2 \br_op__cia$2$next + update \br_op__insn_type$3 \br_op__insn_type$3$next + update \br_op__fn_unit$4 \br_op__fn_unit$4$next + update \br_op__insn$5 \br_op__insn$5$next + update \br_op__imm_data__imm$6 \br_op__imm_data__imm$6$next + update \br_op__imm_data__imm_ok$7 \br_op__imm_data__imm_ok$7$next + update \br_op__lk$8 \br_op__lk$8$next + update \br_op__is_32bit$9 \br_op__is_32bit$9$next + end + process $group_40 + assign \fast1$10$next \fast1$10 + assign \fast1_ok$next \fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$36 \fast1$35 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$36 \fast1$35 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \fast1_ok$next 1'0 + end + sync init + update \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast1_ok 1'0 + sync posedge \coresync_clk + update \fast1$10 \fast1$10$next + update \fast1_ok \fast1_ok$next + end + process $group_42 + assign \fast2$11$next \fast2$11 + assign \fast2_ok$next \fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$38 \fast2$37 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$38 \fast2$37 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \fast2_ok$next 1'0 + end + sync init + update \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast2_ok 1'0 + sync posedge \coresync_clk + update \fast2$11 \fast2$11$next + update \fast2_ok \fast2_ok$next + end + process $group_44 + assign \nia$next \nia + assign \nia_ok$next \nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \nia_ok$next \nia$next } { \nia_ok$40 \nia$39 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \nia_ok$next \nia$next } { \nia_ok$40 \nia$39 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \nia_ok$next 1'0 + end + sync init + update \nia 64'0000000000000000000000000000000000000000000000000000000000000000 + update \nia_ok 1'0 + sync posedge \coresync_clk + update \nia \nia$next + update \nia_ok \nia_ok$next + end + process $group_46 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_47 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0" +module \alu_branch0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \nia_ok + attribute \src "simple/issuer.py:102" + wire width 1 input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \br_op__cia attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -24591,142 +16534,8 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub22_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub22_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub22_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub22_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub22_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub22_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub22_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub22_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub22_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub22_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub22_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub22_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub22_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub22_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub22_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub22_asmcode - cell \dec_sub22 \dec_sub22 - connect \opcode_in \dec_sub22_opcode_in - connect \function_unit \dec_sub22_function_unit - connect \form \dec_sub22_form - connect \internal_op \dec_sub22_internal_op - connect \in1_sel \dec_sub22_in1_sel - connect \in2_sel \dec_sub22_in2_sel - connect \in3_sel \dec_sub22_in3_sel - connect \out_sel \dec_sub22_out_sel - connect \cr_in \dec_sub22_cr_in - connect \cr_out \dec_sub22_cr_out - connect \rc_sel \dec_sub22_rc_sel - connect \ldst_len \dec_sub22_ldst_len - connect \upd \dec_sub22_upd - connect \cry_in \dec_sub22_cry_in - connect \inv_a \dec_sub22_inv_a - connect \inv_out \dec_sub22_inv_out - connect \cry_out \dec_sub22_cry_out - connect \br \dec_sub22_br - connect \sgn_ext \dec_sub22_sgn_ext - connect \rsrv \dec_sub22_rsrv - connect \is_32b \dec_sub22_is_32b - connect \sgn \dec_sub22_sgn - connect \lk \dec_sub22_lk - connect \sgl_pipe \dec_sub22_sgl_pipe - connect \asmcode \dec_sub22_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub9_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \br_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -24739,295 +16548,50 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub9_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub9_form - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub9_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub9_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub9_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub9_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub9_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub9_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub9_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub9_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub9_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub9_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub9_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub9_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub9_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub9_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub9_asmcode - cell \dec_sub9 \dec_sub9 - connect \opcode_in \dec_sub9_opcode_in - connect \function_unit \dec_sub9_function_unit - connect \form \dec_sub9_form - connect \internal_op \dec_sub9_internal_op - connect \in1_sel \dec_sub9_in1_sel - connect \in2_sel \dec_sub9_in2_sel - connect \in3_sel \dec_sub9_in3_sel - connect \out_sel \dec_sub9_out_sel - connect \cr_in \dec_sub9_cr_in - connect \cr_out \dec_sub9_cr_out - connect \rc_sel \dec_sub9_rc_sel - connect \ldst_len \dec_sub9_ldst_len - connect \upd \dec_sub9_upd - connect \cry_in \dec_sub9_cry_in - connect \inv_a \dec_sub9_inv_a - connect \inv_out \dec_sub9_inv_out - connect \cry_out \dec_sub9_cry_out - connect \br \dec_sub9_br - connect \sgn_ext \dec_sub9_sgn_ext - connect \rsrv \dec_sub9_rsrv - connect \is_32b \dec_sub9_is_32b - connect \sgn \dec_sub9_sgn - connect \lk \dec_sub9_lk - connect \sgl_pipe \dec_sub9_sgl_pipe - connect \asmcode \dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 9 \br_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 10 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 11 \br_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \br_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 15 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 16 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 17 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 20 \cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 21 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 22 \p_ready_o + cell \p$17 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub11_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub11_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub11_form + cell \n$18 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -25101,142 +16665,8 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub11_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub11_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub11_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub11_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub11_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub11_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub11_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub11_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub11_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub11_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub11_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub11_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub11_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub11_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub11_asmcode - cell \dec_sub11 \dec_sub11 - connect \opcode_in \dec_sub11_opcode_in - connect \function_unit \dec_sub11_function_unit - connect \form \dec_sub11_form - connect \internal_op \dec_sub11_internal_op - connect \in1_sel \dec_sub11_in1_sel - connect \in2_sel \dec_sub11_in2_sel - connect \in3_sel \dec_sub11_in3_sel - connect \out_sel \dec_sub11_out_sel - connect \cr_in \dec_sub11_cr_in - connect \cr_out \dec_sub11_cr_out - connect \rc_sel \dec_sub11_rc_sel - connect \ldst_len \dec_sub11_ldst_len - connect \upd \dec_sub11_upd - connect \cry_in \dec_sub11_cry_in - connect \inv_a \dec_sub11_inv_a - connect \inv_out \dec_sub11_inv_out - connect \cry_out \dec_sub11_cry_out - connect \br \dec_sub11_br - connect \sgn_ext \dec_sub11_sgn_ext - connect \rsrv \dec_sub11_rsrv - connect \is_32b \dec_sub11_is_32b - connect \sgn \dec_sub11_sgn - connect \lk \dec_sub11_lk - connect \sgl_pipe \dec_sub11_sgl_pipe - connect \asmcode \dec_sub11_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub27_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -25249,40 +16679,32 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub27_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub27_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_br_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_br_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia$4 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -25356,142 +16778,8 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub27_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub27_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub27_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub27_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub27_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub27_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub27_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub27_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub27_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub27_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub27_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub27_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub27_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub27_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub27_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub27_asmcode - cell \dec_sub27 \dec_sub27 - connect \opcode_in \dec_sub27_opcode_in - connect \function_unit \dec_sub27_function_unit - connect \form \dec_sub27_form - connect \internal_op \dec_sub27_internal_op - connect \in1_sel \dec_sub27_in1_sel - connect \in2_sel \dec_sub27_in2_sel - connect \in3_sel \dec_sub27_in3_sel - connect \out_sel \dec_sub27_out_sel - connect \cr_in \dec_sub27_cr_in - connect \cr_out \dec_sub27_cr_out - connect \rc_sel \dec_sub27_rc_sel - connect \ldst_len \dec_sub27_ldst_len - connect \upd \dec_sub27_upd - connect \cry_in \dec_sub27_cry_in - connect \inv_a \dec_sub27_inv_a - connect \inv_out \dec_sub27_inv_out - connect \cry_out \dec_sub27_cry_out - connect \br \dec_sub27_br - connect \sgn_ext \dec_sub27_sgn_ext - connect \rsrv \dec_sub27_rsrv - connect \is_32b \dec_sub27_is_32b - connect \sgn \dec_sub27_sgn - connect \lk \dec_sub27_lk - connect \sgl_pipe \dec_sub27_sgl_pipe - connect \asmcode \dec_sub27_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub15_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type$5 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -25504,40 +16792,128 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub15_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub15_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_br_op__fn_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__imm$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_br_op__imm_data__imm_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_br_op__lk$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_br_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast2$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_nia_ok + cell \pipe$19 \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_p_valid_i + connect \p_ready_o \pipe_p_ready_o + connect \muxid \pipe_muxid + connect \br_op__cia \pipe_br_op__cia + connect \br_op__insn_type \pipe_br_op__insn_type + connect \br_op__fn_unit \pipe_br_op__fn_unit + connect \br_op__insn \pipe_br_op__insn + connect \br_op__imm_data__imm \pipe_br_op__imm_data__imm + connect \br_op__imm_data__imm_ok \pipe_br_op__imm_data__imm_ok + connect \br_op__lk \pipe_br_op__lk + connect \br_op__is_32bit \pipe_br_op__is_32bit + connect \fast1 \pipe_fast1 + connect \fast2 \pipe_fast2 + connect \cr_a \pipe_cr_a + connect \n_valid_o \pipe_n_valid_o + connect \n_ready_i \pipe_n_ready_i + connect \muxid$1 \pipe_muxid$3 + connect \br_op__cia$2 \pipe_br_op__cia$4 + connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 + connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 + connect \br_op__insn$5 \pipe_br_op__insn$7 + connect \br_op__imm_data__imm$6 \pipe_br_op__imm_data__imm$8 + connect \br_op__imm_data__imm_ok$7 \pipe_br_op__imm_data__imm_ok$9 + connect \br_op__lk$8 \pipe_br_op__lk$10 + connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 + connect \fast1$10 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \fast2$11 \pipe_fast2$13 + connect \fast2_ok \pipe_fast2_ok + connect \nia \pipe_nia + connect \nia_ok \pipe_nia_ok + end + process $group_0 + assign \pipe_p_valid_i 1'0 + assign \pipe_p_valid_i \p_valid_i + sync init + end + process $group_1 + assign \p_ready_o 1'0 + assign \p_ready_o \pipe_p_ready_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + process $group_2 + assign \pipe_muxid 2'00 + assign \pipe_muxid \muxid + sync init + end + process $group_3 + assign \pipe_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_br_op__insn_type 7'0000000 + assign \pipe_br_op__fn_unit 11'00000000000 + assign \pipe_br_op__insn 32'00000000000000000000000000000000 + assign \pipe_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_br_op__imm_data__imm_ok 1'0 + assign \pipe_br_op__lk 1'0 + assign \pipe_br_op__is_32bit 1'0 + assign { \pipe_br_op__is_32bit \pipe_br_op__lk { \pipe_br_op__imm_data__imm_ok \pipe_br_op__imm_data__imm } \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + sync init + end + process $group_11 + assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_fast1 \fast1$1 + sync init + end + process $group_12 + assign \pipe_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_fast2 \fast2$2 + sync init + end + process $group_13 + assign \pipe_cr_a 4'0000 + assign \pipe_cr_a \cr_a + sync init + end + process $group_14 + assign \n_valid_o 1'0 + assign \n_valid_o \pipe_n_valid_o + sync init + end + process $group_15 + assign \pipe_n_ready_i 1'0 + assign \pipe_n_ready_i \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$14 + process $group_16 + assign \muxid$14 2'00 + assign \muxid$14 \pipe_muxid$3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$15 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -25611,142 +16987,8 @@ module \dec31 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub15_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub15_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub15_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub15_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub15_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub15_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub15_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub15_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub15_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub15_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub15_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub15_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub15_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub15_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub15_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub15_asmcode - cell \dec_sub15 \dec_sub15 - connect \opcode_in \dec_sub15_opcode_in - connect \function_unit \dec_sub15_function_unit - connect \form \dec_sub15_form - connect \internal_op \dec_sub15_internal_op - connect \in1_sel \dec_sub15_in1_sel - connect \in2_sel \dec_sub15_in2_sel - connect \in3_sel \dec_sub15_in3_sel - connect \out_sel \dec_sub15_out_sel - connect \cr_in \dec_sub15_cr_in - connect \cr_out \dec_sub15_cr_out - connect \rc_sel \dec_sub15_rc_sel - connect \ldst_len \dec_sub15_ldst_len - connect \upd \dec_sub15_upd - connect \cry_in \dec_sub15_cry_in - connect \inv_a \dec_sub15_inv_a - connect \inv_out \dec_sub15_inv_out - connect \cry_out \dec_sub15_cry_out - connect \br \dec_sub15_br - connect \sgn_ext \dec_sub15_sgn_ext - connect \rsrv \dec_sub15_rsrv - connect \is_32b \dec_sub15_is_32b - connect \sgn \dec_sub15_sgn - connect \lk \dec_sub15_lk - connect \sgl_pipe \dec_sub15_sgl_pipe - connect \asmcode \dec_sub15_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub20_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$16 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -25759,3606 +17001,1147 @@ module \dec31 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub20_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute 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\enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub20_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub20_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub20_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - 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assign \br_op__is_32bit$22 1'0 + assign { \br_op__is_32bit$22 \br_op__lk$21 { \br_op__imm_data__imm_ok$20 \br_op__imm_data__imm$19 } \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 { \pipe_br_op__imm_data__imm_ok$9 \pipe_br_op__imm_data__imm$8 } \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub21_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute 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attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub16_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub16_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub16_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src 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connect \internal_op \dec_sub18_internal_op - connect \in1_sel \dec_sub18_in1_sel - connect \in2_sel \dec_sub18_in2_sel - connect \in3_sel \dec_sub18_in3_sel - connect \out_sel \dec_sub18_out_sel - connect \cr_in \dec_sub18_cr_in - connect \cr_out \dec_sub18_cr_out - connect \rc_sel \dec_sub18_rc_sel - connect \ldst_len \dec_sub18_ldst_len - connect \upd \dec_sub18_upd - connect \cry_in \dec_sub18_cry_in - connect \inv_a \dec_sub18_inv_a - connect \inv_out \dec_sub18_inv_out - connect \cry_out \dec_sub18_cry_out - connect \br \dec_sub18_br - connect \sgn_ext \dec_sub18_sgn_ext - connect \rsrv \dec_sub18_rsrv - connect \is_32b \dec_sub18_is_32b - connect \sgn \dec_sub18_sgn - connect \lk \dec_sub18_lk - connect \sgl_pipe \dec_sub18_sgl_pipe - connect \asmcode \dec_sub18_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub8_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - 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\enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub8_form - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub8_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub8_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub8_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub8_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub8_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub8_cr_in - attribute \enum_base_type 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\dec_sub8_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub8_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub8_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub8_asmcode - cell \dec_sub8 \dec_sub8 - connect \opcode_in \dec_sub8_opcode_in - connect \function_unit \dec_sub8_function_unit - connect \form \dec_sub8_form - connect \internal_op \dec_sub8_internal_op - connect \in1_sel \dec_sub8_in1_sel - connect \in2_sel \dec_sub8_in2_sel - connect \in3_sel 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wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub24_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 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attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub24_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub24_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub24_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub24_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub24_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub24_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub24_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub24_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub24_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub24_asmcode - cell \dec_sub24 \dec_sub24 - connect \opcode_in \dec_sub24_opcode_in - connect \function_unit \dec_sub24_function_unit - connect \form \dec_sub24_form - connect \internal_op \dec_sub24_internal_op - connect \in1_sel \dec_sub24_in1_sel - connect \in2_sel \dec_sub24_in2_sel - connect \in3_sel \dec_sub24_in3_sel - connect \out_sel \dec_sub24_out_sel - connect \cr_in \dec_sub24_cr_in - connect \cr_out \dec_sub24_cr_out - connect \rc_sel \dec_sub24_rc_sel - connect \ldst_len \dec_sub24_ldst_len - connect \upd \dec_sub24_upd - connect \cry_in \dec_sub24_cry_in - connect \inv_a \dec_sub24_inv_a - connect \inv_out \dec_sub24_inv_out - connect \cry_out \dec_sub24_cry_out - connect \br \dec_sub24_br - connect \sgn_ext \dec_sub24_sgn_ext - connect \rsrv \dec_sub24_rsrv - connect \is_32b \dec_sub24_is_32b - connect \sgn \dec_sub24_sgn - connect \lk \dec_sub24_lk - connect \sgl_pipe \dec_sub24_sgl_pipe - connect \asmcode \dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec_sub4_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec_sub4_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec_sub4_form - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec_sub4_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec_sub4_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec_sub4_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec_sub4_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec_sub4_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec_sub4_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec_sub4_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec_sub4_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec_sub4_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec_sub4_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub4_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub4_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub4_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub4_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub4_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec_sub4_asmcode - cell \dec_sub4 \dec_sub4 - connect \opcode_in \dec_sub4_opcode_in - connect \function_unit \dec_sub4_function_unit - connect \form \dec_sub4_form - connect \internal_op \dec_sub4_internal_op - connect \in1_sel \dec_sub4_in1_sel - connect \in2_sel \dec_sub4_in2_sel - connect \in3_sel \dec_sub4_in3_sel - connect \out_sel \dec_sub4_out_sel - connect \cr_in \dec_sub4_cr_in - connect \cr_out \dec_sub4_cr_out - connect \rc_sel \dec_sub4_rc_sel - connect \ldst_len \dec_sub4_ldst_len - connect \upd \dec_sub4_upd - connect \cry_in \dec_sub4_cry_in - connect \inv_a \dec_sub4_inv_a - connect \inv_out \dec_sub4_inv_out - connect \cry_out \dec_sub4_cry_out - connect \br \dec_sub4_br - connect \sgn_ext \dec_sub4_sgn_ext - connect \rsrv \dec_sub4_rsrv - connect \is_32b \dec_sub4_is_32b - connect \sgn \dec_sub4_sgn - connect \lk \dec_sub4_lk - connect \sgl_pipe \dec_sub4_sgl_pipe - connect \asmcode \dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $3 + connect \B \s_src + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 10 \opcode_switch process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274" - wire width 5 \opc_in - process $group_1 - assign \opc_in 5'00000 - assign \opc_in \opcode_switch [4:0] - sync init - end - process $group_2 - assign \dec_sub10_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub10_opcode_in \opcode_in - sync init - end - process $group_3 - assign \dec_sub28_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub28_opcode_in \opcode_in - sync init - end - process $group_4 - assign \dec_sub0_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub0_opcode_in \opcode_in + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 3'000 + end sync init + update \q_int 3'000 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_5 - assign \dec_sub26_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub26_opcode_in \opcode_in - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $7 end - process $group_6 - assign \dec_sub19_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub19_opcode_in \opcode_in - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $7 + connect \Y $9 end - process $group_7 - assign \dec_sub22_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub22_opcode_in \opcode_in - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $9 + connect \B \s_src + connect \Y $11 end - process $group_8 - assign \dec_sub9_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub9_opcode_in \opcode_in + process $group_1 + assign \q_src 3'000 + assign \q_src $11 sync init end - process $group_9 - assign \dec_sub11_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub11_opcode_in \opcode_in - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $13 end - process $group_10 - assign \dec_sub27_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub27_opcode_in \opcode_in + process $group_2 + assign \qn_src 3'000 + assign \qn_src $13 sync init end - process $group_11 - assign \dec_sub15_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub15_opcode_in \opcode_in - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $15 end - process $group_12 - assign \dec_sub20_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub20_opcode_in \opcode_in + process $group_3 + assign \qlq_src 3'000 + assign \qlq_src $15 sync init end - process $group_13 - assign \dec_sub21_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub21_opcode_in \opcode_in - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l" +module \opc_l$24 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $1 end - process $group_14 - assign \dec_sub23_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub23_opcode_in \opcode_in - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 end - process $group_15 - assign \dec_sub16_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub16_opcode_in \opcode_in - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_opc + connect \Y $5 end - process $group_16 - assign \dec_sub18_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub18_opcode_in \opcode_in + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_17 - assign \dec_sub8_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub8_opcode_in \opcode_in - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $7 end - process $group_18 - assign \dec_sub24_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub24_opcode_in \opcode_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_opc + connect \Y $11 + end + process $group_1 + assign \q_opc 1'0 + assign \q_opc $11 sync init end - process $group_19 - assign \dec_sub4_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub4_opcode_in \opcode_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $13 + end + process $group_2 + assign \qn_opc 1'0 + assign \qn_opc $13 sync init end - process $group_20 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \function_unit \dec_sub10_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \function_unit \dec_sub28_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \function_unit \dec_sub0_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \function_unit \dec_sub26_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \function_unit \dec_sub19_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \function_unit \dec_sub22_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \function_unit \dec_sub9_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \function_unit \dec_sub11_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \function_unit \dec_sub27_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \function_unit \dec_sub15_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \function_unit \dec_sub20_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \function_unit \dec_sub21_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \function_unit \dec_sub23_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \function_unit \dec_sub16_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \function_unit \dec_sub18_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \function_unit \dec_sub8_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \function_unit \dec_sub24_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \function_unit \dec_sub4_function_unit - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_opc 1'0 + assign \qlq_opc $15 sync init end - process $group_21 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \form \dec_sub10_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \form \dec_sub28_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \form \dec_sub0_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \form \dec_sub26_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \form \dec_sub19_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \form \dec_sub22_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \form \dec_sub9_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \form \dec_sub11_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \form \dec_sub27_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \form \dec_sub15_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \form \dec_sub20_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \form \dec_sub21_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \form \dec_sub23_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \form \dec_sub16_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \form \dec_sub18_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \form \dec_sub8_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \form \dec_sub24_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \form \dec_sub4_form +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l" +module \req_l$25 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $3 + connect \B \s_req + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 3'000 end sync init + update \q_int 3'000 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_22 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \internal_op \dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \internal_op \dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \internal_op \dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \internal_op \dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \internal_op \dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \internal_op \dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \internal_op \dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \internal_op \dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \internal_op \dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \internal_op \dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \internal_op \dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \internal_op \dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \internal_op \dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \internal_op \dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \internal_op \dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \internal_op \dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \internal_op \dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \internal_op \dec_sub4_internal_op - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $9 + connect \B \s_req + connect \Y $11 + end + process $group_1 + assign \q_req 3'000 + assign \q_req $11 sync init end - process $group_23 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \in1_sel \dec_sub10_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \in1_sel \dec_sub28_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \in1_sel \dec_sub0_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \in1_sel \dec_sub26_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \in1_sel \dec_sub19_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \in1_sel \dec_sub22_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \in1_sel \dec_sub9_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \in1_sel \dec_sub11_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \in1_sel \dec_sub27_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \in1_sel \dec_sub15_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \in1_sel \dec_sub20_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \in1_sel \dec_sub21_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \in1_sel \dec_sub23_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \in1_sel \dec_sub16_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \in1_sel \dec_sub18_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \in1_sel \dec_sub8_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \in1_sel \dec_sub24_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \in1_sel \dec_sub4_in1_sel - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $13 + end + process $group_2 + assign \qn_req 3'000 + assign \qn_req $13 sync init end - process $group_24 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \in2_sel \dec_sub10_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \in2_sel \dec_sub28_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \in2_sel \dec_sub0_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \in2_sel \dec_sub26_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \in2_sel \dec_sub19_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \in2_sel \dec_sub22_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \in2_sel \dec_sub9_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \in2_sel \dec_sub11_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \in2_sel \dec_sub27_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \in2_sel \dec_sub15_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \in2_sel \dec_sub20_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \in2_sel \dec_sub21_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \in2_sel \dec_sub23_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \in2_sel \dec_sub16_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \in2_sel \dec_sub18_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \in2_sel \dec_sub8_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \in2_sel \dec_sub24_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \in2_sel \dec_sub4_in2_sel - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_req 3'000 + assign \qlq_req $15 sync init end - process $group_25 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \in3_sel \dec_sub10_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \in3_sel \dec_sub28_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \in3_sel \dec_sub0_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \in3_sel \dec_sub26_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \in3_sel \dec_sub19_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \in3_sel \dec_sub22_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \in3_sel \dec_sub9_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \in3_sel \dec_sub11_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \in3_sel \dec_sub27_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \in3_sel \dec_sub15_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \in3_sel \dec_sub20_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \in3_sel \dec_sub21_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \in3_sel \dec_sub23_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \in3_sel \dec_sub16_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \in3_sel \dec_sub18_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \in3_sel \dec_sub8_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \in3_sel \dec_sub24_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \in3_sel \dec_sub4_in3_sel +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l" +module \rst_l$26 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rst + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_26 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \out_sel \dec_sub10_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \out_sel \dec_sub28_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \out_sel \dec_sub0_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \out_sel \dec_sub26_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \out_sel \dec_sub19_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \out_sel \dec_sub22_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \out_sel \dec_sub9_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \out_sel \dec_sub11_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \out_sel \dec_sub27_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \out_sel \dec_sub15_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \out_sel \dec_sub20_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \out_sel \dec_sub21_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \out_sel \dec_sub23_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \out_sel \dec_sub16_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \out_sel \dec_sub18_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \out_sel \dec_sub8_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \out_sel \dec_sub24_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \out_sel \dec_sub4_out_sel - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rst + connect \Y $11 + end + process $group_1 + assign \q_rst 1'0 + assign \q_rst $11 sync init end - process $group_27 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \cr_in \dec_sub10_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \cr_in \dec_sub28_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \cr_in \dec_sub0_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \cr_in \dec_sub26_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \cr_in \dec_sub19_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \cr_in \dec_sub22_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \cr_in \dec_sub9_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \cr_in \dec_sub11_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \cr_in \dec_sub27_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \cr_in \dec_sub15_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \cr_in \dec_sub20_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \cr_in \dec_sub21_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \cr_in \dec_sub23_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \cr_in \dec_sub16_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \cr_in \dec_sub18_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \cr_in \dec_sub8_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \cr_in \dec_sub24_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \cr_in \dec_sub4_cr_in - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $13 + end + process $group_2 + assign \qn_rst 1'0 + assign \qn_rst $13 sync init end - process $group_28 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \cr_out \dec_sub10_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \cr_out \dec_sub28_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \cr_out \dec_sub0_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \cr_out \dec_sub26_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \cr_out \dec_sub19_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \cr_out \dec_sub22_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \cr_out \dec_sub9_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \cr_out \dec_sub11_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \cr_out \dec_sub27_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \cr_out \dec_sub15_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \cr_out \dec_sub20_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \cr_out \dec_sub21_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \cr_out \dec_sub23_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \cr_out \dec_sub16_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \cr_out \dec_sub18_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \cr_out \dec_sub8_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \cr_out \dec_sub24_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \cr_out \dec_sub4_cr_out - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rst 1'0 + assign \qlq_rst $15 sync init end - process $group_29 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \rc_sel \dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \rc_sel \dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \rc_sel \dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \rc_sel \dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \rc_sel \dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \rc_sel \dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \rc_sel \dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \rc_sel \dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \rc_sel \dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \rc_sel \dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \rc_sel \dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \rc_sel \dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \rc_sel \dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \rc_sel \dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \rc_sel \dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \rc_sel \dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \rc_sel \dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \rc_sel \dec_sub4_rc_sel +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l" +module \rok_l$27 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rdok + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_30 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \ldst_len \dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \ldst_len \dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \ldst_len \dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \ldst_len \dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \ldst_len \dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \ldst_len \dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \ldst_len \dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \ldst_len \dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \ldst_len \dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \ldst_len \dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \ldst_len \dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \ldst_len \dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \ldst_len \dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \ldst_len \dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \ldst_len \dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \ldst_len \dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \ldst_len \dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \ldst_len \dec_sub4_ldst_len - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rdok + connect \Y $11 + end + process $group_1 + assign \q_rdok 1'0 + assign \q_rdok $11 sync init end - process $group_31 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \upd \dec_sub10_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \upd \dec_sub28_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \upd \dec_sub0_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \upd \dec_sub26_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \upd \dec_sub19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \upd \dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \upd \dec_sub9_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \upd \dec_sub11_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \upd \dec_sub27_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \upd \dec_sub15_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \upd \dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \upd \dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \upd \dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \upd \dec_sub16_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \upd \dec_sub18_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \upd \dec_sub8_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \upd \dec_sub24_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \upd \dec_sub4_upd - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $13 + end + process $group_2 + assign \qn_rdok 1'0 + assign \qn_rdok $13 sync init end - process $group_32 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \cry_in \dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \cry_in \dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \cry_in \dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \cry_in \dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \cry_in \dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \cry_in \dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \cry_in \dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \cry_in \dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \cry_in \dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \cry_in \dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \cry_in \dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \cry_in \dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \cry_in \dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \cry_in \dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \cry_in \dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \cry_in \dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \cry_in \dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \cry_in \dec_sub4_cry_in - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $15 end - process $group_33 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \inv_a \dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \inv_a \dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \inv_a \dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \inv_a \dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \inv_a \dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \inv_a \dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \inv_a \dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \inv_a \dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \inv_a \dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \inv_a \dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \inv_a \dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \inv_a \dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \inv_a \dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \inv_a \dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \inv_a \dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \inv_a \dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \inv_a \dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \inv_a \dec_sub4_inv_a - end + process $group_3 + assign \qlq_rdok 1'0 + assign \qlq_rdok $15 sync init end - process $group_34 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \inv_out \dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \inv_out \dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \inv_out \dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \inv_out \dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \inv_out \dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \inv_out \dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \inv_out \dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \inv_out \dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \inv_out \dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \inv_out \dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \inv_out \dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \inv_out \dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \inv_out \dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \inv_out \dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \inv_out \dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \inv_out \dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \inv_out \dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \inv_out \dec_sub4_inv_out - end - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l" +module \alui_l$28 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $1 end - process $group_35 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \cry_out \dec_sub10_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \cry_out \dec_sub28_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \cry_out \dec_sub0_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \cry_out \dec_sub26_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \cry_out \dec_sub19_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \cry_out \dec_sub22_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \cry_out \dec_sub9_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \cry_out \dec_sub11_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \cry_out \dec_sub27_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \cry_out \dec_sub15_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \cry_out \dec_sub20_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \cry_out \dec_sub21_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \cry_out \dec_sub23_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \cry_out \dec_sub16_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \cry_out \dec_sub18_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \cry_out \dec_sub8_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \cry_out \dec_sub24_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \cry_out \dec_sub4_cry_out - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 end - process $group_36 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \br \dec_sub10_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \br \dec_sub28_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \br \dec_sub0_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \br \dec_sub26_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \br \dec_sub19_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \br \dec_sub22_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \br \dec_sub9_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \br \dec_sub11_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \br \dec_sub27_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \br \dec_sub15_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \br \dec_sub20_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \br \dec_sub21_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \br \dec_sub23_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \br \dec_sub16_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \br \dec_sub18_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \br \dec_sub8_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \br \dec_sub24_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \br \dec_sub4_br + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alui + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_37 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \sgn_ext \dec_sub10_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \sgn_ext \dec_sub28_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \sgn_ext \dec_sub0_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \sgn_ext \dec_sub26_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \sgn_ext \dec_sub19_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \sgn_ext \dec_sub22_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \sgn_ext \dec_sub9_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \sgn_ext \dec_sub11_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \sgn_ext \dec_sub27_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \sgn_ext \dec_sub15_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \sgn_ext \dec_sub20_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \sgn_ext \dec_sub21_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \sgn_ext \dec_sub23_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \sgn_ext \dec_sub16_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \sgn_ext \dec_sub18_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \sgn_ext \dec_sub8_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \sgn_ext \dec_sub24_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \sgn_ext \dec_sub4_sgn_ext - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alui + connect \Y $11 + end + process $group_1 + assign \q_alui 1'0 + assign \q_alui $11 sync init end - process $group_38 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \rsrv \dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \rsrv \dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \rsrv \dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \rsrv \dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \rsrv \dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \rsrv \dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \rsrv \dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \rsrv \dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \rsrv \dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \rsrv \dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \rsrv \dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \rsrv \dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \rsrv \dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \rsrv \dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \rsrv \dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \rsrv \dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \rsrv \dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \rsrv \dec_sub4_rsrv - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $13 + end + process $group_2 + assign \qn_alui 1'0 + assign \qn_alui $13 sync init end - process $group_39 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \is_32b \dec_sub10_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \is_32b \dec_sub28_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \is_32b \dec_sub0_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \is_32b \dec_sub26_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \is_32b \dec_sub19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \is_32b \dec_sub22_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \is_32b \dec_sub9_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \is_32b \dec_sub11_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \is_32b \dec_sub27_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \is_32b \dec_sub15_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \is_32b \dec_sub20_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \is_32b \dec_sub21_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \is_32b \dec_sub23_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \is_32b \dec_sub16_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \is_32b \dec_sub18_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \is_32b \dec_sub8_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \is_32b \dec_sub24_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \is_32b \dec_sub4_is_32b - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alui 1'0 + assign \qlq_alui $15 sync init end - process $group_40 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \sgn \dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \sgn \dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \sgn \dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \sgn \dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \sgn \dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \sgn \dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \sgn \dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \sgn \dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \sgn \dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \sgn \dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \sgn \dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \sgn \dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \sgn \dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \sgn \dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \sgn \dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \sgn \dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \sgn \dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \sgn \dec_sub4_sgn +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l" +module \alu_l$29 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alu + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - process $group_41 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \lk \dec_sub10_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \lk \dec_sub28_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \lk \dec_sub0_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \lk \dec_sub26_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \lk \dec_sub19_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \lk \dec_sub22_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \lk \dec_sub9_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \lk \dec_sub11_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \lk \dec_sub27_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \lk \dec_sub15_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \lk \dec_sub20_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \lk \dec_sub21_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \lk \dec_sub23_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \lk \dec_sub16_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \lk \dec_sub18_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \lk \dec_sub8_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \lk \dec_sub24_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \lk \dec_sub4_lk - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alu + connect \Y $11 + end + process $group_1 + assign \q_alu 1'0 + assign \q_alu $11 sync init end - process $group_42 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \sgl_pipe \dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \sgl_pipe \dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \sgl_pipe \dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \sgl_pipe \dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \sgl_pipe \dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \sgl_pipe \dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \sgl_pipe \dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \sgl_pipe \dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \sgl_pipe \dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \sgl_pipe \dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \sgl_pipe \dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \sgl_pipe \dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \sgl_pipe \dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \sgl_pipe \dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \sgl_pipe \dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \sgl_pipe \dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \sgl_pipe \dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \sgl_pipe \dec_sub4_sgl_pipe - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $13 + end + process $group_2 + assign \qn_alu 1'0 + assign \qn_alu $13 sync init end - process $group_43 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:277" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01010 - assign \asmcode \dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11100 - assign \asmcode \dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00000 - assign \asmcode \dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11010 - assign \asmcode \dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10011 - assign \asmcode \dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10110 - assign \asmcode \dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01001 - assign \asmcode \dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01011 - assign \asmcode \dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11011 - assign \asmcode \dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01111 - assign \asmcode \dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10100 - assign \asmcode \dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10101 - assign \asmcode \dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10111 - assign \asmcode \dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10000 - assign \asmcode \dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'10010 - assign \asmcode \dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'01000 - assign \asmcode \dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'11000 - assign \asmcode \dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:287" - case 5'00100 - assign \asmcode \dec_sub4_asmcode - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alu 1'0 + assign \qlq_alu $15 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec58" -module \dec58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0" +module \branch0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 1 \oper_i_alu_branch0__cia + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \oper_i_alu_branch0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -29371,40 +18154,60 @@ module \dec58 attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 3 \oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 4 \oper_i_alu_branch0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \oper_i_alu_branch0__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \oper_i_alu_branch0__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \oper_i_alu_branch0__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 input 9 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 output 10 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 11 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 12 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 13 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 14 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 15 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 16 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 17 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 18 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 19 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 20 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 21 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 22 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 23 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 24 \dest3_o + attribute \src "simple/issuer.py:102" + wire width 1 input 25 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \alu_branch0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \alu_branch0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_branch0_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_branch0_br_op__cia$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -29478,1127 +18281,1611 @@ module \dec58 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 2 \opcode_switch - process $group_0 - assign \opcode_switch 2'00 - assign \opcode_switch \opcode_in [1:0] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \function_unit 11'00000000100 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_branch0_br_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_branch0_br_op__insn_type$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_branch0_br_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_branch0_br_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_branch0_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_branch0_br_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_branch0_br_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_branch0_br_op__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_branch0_br_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_branch0_br_op__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_branch0_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_branch0_br_op__lk$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_branch0_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_branch0_br_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_branch0_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_branch0_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_branch0_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_branch0_fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_branch0_fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \alu_branch0_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \alu_branch0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \alu_branch0_p_ready_o + cell \alu_branch0 \alu_branch0 + connect \coresync_clk \coresync_clk + connect \fast1_ok \fast1_ok + connect \fast2_ok \fast2_ok + connect \nia_ok \nia_ok + connect \coresync_rst \coresync_rst + connect \n_valid_o \alu_branch0_n_valid_o + connect \n_ready_i \alu_branch0_n_ready_i + connect \br_op__cia \alu_branch0_br_op__cia + connect \br_op__insn_type \alu_branch0_br_op__insn_type + connect \br_op__fn_unit \alu_branch0_br_op__fn_unit + connect \br_op__insn \alu_branch0_br_op__insn + connect \br_op__imm_data__imm \alu_branch0_br_op__imm_data__imm + connect \br_op__imm_data__imm_ok \alu_branch0_br_op__imm_data__imm_ok + connect \br_op__lk \alu_branch0_br_op__lk + connect \br_op__is_32bit \alu_branch0_br_op__is_32bit + connect \fast1 \alu_branch0_fast1 + connect \fast2 \alu_branch0_fast2 + connect \nia \alu_branch0_nia + connect \fast1$1 \alu_branch0_fast1$1 + connect \fast2$2 \alu_branch0_fast2$2 + connect \cr_a \alu_branch0_cr_a + connect \p_valid_i \alu_branch0_p_valid_i + connect \p_ready_o \alu_branch0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + cell \src_l$23 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_src \src_l_s_src + connect \r_src \src_l_r_src + connect \q_src \src_l_q_src + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \opc_l_q_opc + cell \opc_l$24 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_opc \opc_l_s_opc + connect \r_opc \opc_l_r_opc + connect \q_opc \opc_l_q_opc + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req$next + cell \req_l$25 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \s_req \req_l_s_req + connect \r_req \req_l_r_req + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst$next + cell \rst_l$26 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_rst \rst_l_s_rst + connect \r_rst \rst_l_r_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok$next + cell \rok_l$27 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \s_rdok \rok_l_s_rdok + connect \r_rdok \rok_l_r_rdok + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alui_l_s_alui + cell \alui_l$28 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_s_alu + cell \alu_l$29 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $6 + connect \B \cu_rd__go_i + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B $5 + connect \Y $11 + end + process $group_0 + assign \all_rd 1'0 + assign \all_rd $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly$next + process $group_1 + assign \all_rd_dly$next \all_rd_dly + assign \all_rd_dly$next \all_rd sync init + update \all_rd_dly 1'0 + sync posedge \coresync_clk + update \all_rd_dly \all_rd_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B $13 + connect \Y $15 end process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \form 5'00101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \form 5'00101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \form 5'00101 - end + assign \all_rd_rise 1'0 + assign \all_rd_rise $15 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire width 1 \all_rd_pulse process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \internal_op 7'0100101 - end + assign \all_rd_pulse 1'0 + assign \all_rd_pulse \all_rd_rise sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire width 1 \alu_done process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \in1_sel 3'010 - end + assign \alu_done 1'0 + assign \alu_done \alu_branch0_n_valid_o sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly$next process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \in2_sel 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \in2_sel 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \in2_sel 4'1000 - end + assign \alu_done_dly$next \alu_done_dly + assign \alu_done_dly$next \alu_done sync init + update \alu_done_dly 1'0 + sync posedge \coresync_clk + update \alu_done_dly \alu_done_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B $17 + connect \Y $19 end process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \in3_sel 2'00 - end + assign \alu_done_rise 1'0 + assign \alu_done_rise $19 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire width 1 \alu_pulse process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \out_sel 2'01 - end + assign \alu_pulse 1'0 + assign \alu_pulse \alu_done_rise sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 3 \alu_pulsem process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \cr_in 3'000 - end + assign \alu_pulsem 3'000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 3 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $21 + end process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \cr_out 3'000 + assign \prev_wr_go$next \prev_wr_go + assign \prev_wr_go$next $21 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \prev_wr_go$next 3'000 end sync init + update \prev_wr_go 3'000 + sync posedge \coresync_clk + update \prev_wr_go \prev_wr_go$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire width 1 \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 3 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__rel_o + connect \B $25 + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $27 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B $23 + connect \Y $31 end process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \ldst_len 4'0100 - end + assign \cu_done_o 1'0 + assign \cu_done_o $31 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $33 + connect \B $35 + connect \Y $37 + end process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \upd 2'00 - end + assign \wr_any 1'0 + assign \wr_any $37 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire width 1 \req_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_ready_i + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B $39 + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 3 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $43 + connect \B 1'0 + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $41 + connect \B $45 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $49 + connect \B \alu_branch0_n_ready_i + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $51 + connect \B \alu_branch0_n_valid_o + connect \Y $53 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $53 + connect \B \cu_busy_o + connect \Y $55 + end process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \rc_sel 2'00 + assign \req_done 1'0 + assign \req_done $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch { $55 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + case 1'1 + assign \req_done 1'1 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire width 1 \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire width 1 \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $57 + end process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \cry_in 2'00 - end + assign \reset 1'0 + assign \reset $57 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire width 1 \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $59 + end process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \asmcode 8'01010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \asmcode 8'01010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \asmcode 8'01100001 - end + assign \rst_r 1'0 + assign \rst_r $59 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 3 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 3 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $61 + end process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \inv_a 1'0 - end + assign \reset_w 3'000 + assign \reset_w $61 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 3 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $63 + end process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \inv_out 1'0 - end + assign \reset_r 3'000 + assign \reset_r $63 sync init end process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \cry_out 1'0 + assign \rok_l_s_rdok$next \rok_l_s_rdok + assign \rok_l_s_rdok$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_s_rdok$next 1'0 end sync init + update \rok_l_s_rdok 1'0 + sync posedge \coresync_clk + update \rok_l_s_rdok \rok_l_s_rdok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_valid_o + connect \B \cu_busy_o + connect \Y $65 end process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \br 1'0 + assign \rok_l_r_rdok$next \rok_l_r_rdok + assign \rok_l_r_rdok$next $65 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_r_rdok$next 1'1 end sync init + update \rok_l_r_rdok 1'1 + sync posedge \coresync_clk + update \rok_l_r_rdok \rok_l_r_rdok$next end process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \sgn_ext 1'1 + assign \rst_l_s_rst$next \rst_l_s_rst + assign \rst_l_s_rst$next \all_rd + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_s_rst$next 1'0 end sync init + update \rst_l_s_rst 1'0 + sync posedge \coresync_clk + update \rst_l_s_rst \rst_l_s_rst$next end process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \rsrv 1'0 + assign \rst_l_r_rst$next \rst_l_r_rst + assign \rst_l_r_rst$next \rst_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_r_rst$next 1'1 end sync init + update \rst_l_r_rst 1'1 + sync posedge \coresync_clk + update \rst_l_r_rst \rst_l_r_rst$next end process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \is_32b 1'0 + assign \opc_l_s_opc$next \opc_l_s_opc + assign \opc_l_s_opc$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_s_opc$next 1'0 end sync init + update \opc_l_s_opc 1'0 + sync posedge \coresync_clk + update \opc_l_s_opc \opc_l_s_opc$next end process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \sgn 1'0 + assign \opc_l_r_opc$next \opc_l_r_opc + assign \opc_l_r_opc$next \req_done + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_r_opc$next 1'1 end sync init + update \opc_l_r_opc 1'1 + sync posedge \coresync_clk + update \opc_l_r_opc \opc_l_r_opc$next end process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \lk 1'0 + assign \src_l_s_src$next \src_l_s_src + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_s_src$next 3'000 end sync init + update \src_l_s_src 3'000 + sync posedge \coresync_clk + update \src_l_s_src \src_l_s_src$next end process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'10 - assign \sgl_pipe 1'1 + assign \src_l_r_src$next \src_l_r_src + assign \src_l_r_src$next \reset_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_r_src$next 3'111 end sync init + update \src_l_r_src 3'111 + sync posedge \coresync_clk + update \src_l_r_src \src_l_r_src$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec62" -module \dec62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 1 \function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 output 2 \form - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 3 \internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 4 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 5 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 6 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 7 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 10 \rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 12 \upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 13 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 15 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 20 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 23 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 output 24 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 2 \opcode_switch - process $group_0 - assign \opcode_switch 2'00 - assign \opcode_switch \opcode_in [1:0] - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 3 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $67 end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \function_unit 11'00000000100 + process $group_25 + assign \req_l_s_req$next \req_l_s_req + assign \req_l_s_req$next $67 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_s_req$next 3'000 end sync init + update \req_l_s_req 3'000 + sync posedge \coresync_clk + update \req_l_s_req \req_l_s_req$next end - process $group_2 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \form 5'00101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \form 5'00101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 3 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $69 + end + process $group_26 + assign \req_l_r_req$next \req_l_r_req + assign \req_l_r_req$next $69 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_r_req$next 3'111 end sync init + update \req_l_r_req 3'111 + sync posedge \coresync_clk + update \req_l_r_req \req_l_r_req$next end - process $group_3 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \internal_op 7'0100110 + process $group_27 + assign \alu_branch0_br_op__cia$next \alu_branch0_br_op__cia + assign \alu_branch0_br_op__insn_type$next \alu_branch0_br_op__insn_type + assign \alu_branch0_br_op__fn_unit$next \alu_branch0_br_op__fn_unit + assign \alu_branch0_br_op__insn$next \alu_branch0_br_op__insn + assign \alu_branch0_br_op__imm_data__imm$next \alu_branch0_br_op__imm_data__imm + assign \alu_branch0_br_op__imm_data__imm_ok$next \alu_branch0_br_op__imm_data__imm_ok + assign \alu_branch0_br_op__lk$next \alu_branch0_br_op__lk + assign \alu_branch0_br_op__is_32bit$next \alu_branch0_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + case 1'1 + assign { \alu_branch0_br_op__is_32bit$next \alu_branch0_br_op__lk$next { \alu_branch0_br_op__imm_data__imm_ok$next \alu_branch0_br_op__imm_data__imm$next } \alu_branch0_br_op__insn$next \alu_branch0_br_op__fn_unit$next \alu_branch0_br_op__insn_type$next \alu_branch0_br_op__cia$next } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk { \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm } \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_branch0_br_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_branch0_br_op__imm_data__imm_ok$next 1'0 end sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \in1_sel 3'010 + update \alu_branch0_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_branch0_br_op__insn_type 7'0000000 + update \alu_branch0_br_op__fn_unit 11'00000000000 + update \alu_branch0_br_op__insn 32'00000000000000000000000000000000 + update \alu_branch0_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_branch0_br_op__imm_data__imm_ok 1'0 + update \alu_branch0_br_op__lk 1'0 + update \alu_branch0_br_op__is_32bit 1'0 + sync posedge \coresync_clk + update \alu_branch0_br_op__cia \alu_branch0_br_op__cia$next + update \alu_branch0_br_op__insn_type \alu_branch0_br_op__insn_type$next + update \alu_branch0_br_op__fn_unit \alu_branch0_br_op__fn_unit$next + update \alu_branch0_br_op__insn \alu_branch0_br_op__insn$next + update \alu_branch0_br_op__imm_data__imm \alu_branch0_br_op__imm_data__imm$next + update \alu_branch0_br_op__imm_data__imm_ok \alu_branch0_br_op__imm_data__imm_ok$next + update \alu_branch0_br_op__lk \alu_branch0_br_op__lk$next + update \alu_branch0_br_op__is_32bit \alu_branch0_br_op__is_32bit$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__fast1_ok$next + process $group_35 + assign \data_r0__fast1$next \data_r0__fast1 + assign \data_r0__fast1_ok$next \data_r0__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r0__fast1_ok$next \data_r0__fast1$next } { \fast1_ok \alu_branch0_fast1 } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r0__fast1_ok$next \data_r0__fast1$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r0__fast1_ok$next 1'0 end sync init + update \data_r0__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0__fast1_ok 1'0 + sync posedge \coresync_clk + update \data_r0__fast1 \data_r0__fast1$next + update \data_r0__fast1_ok \data_r0__fast1_ok$next end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \in2_sel 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \in2_sel 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__fast2_ok$next + process $group_37 + assign \data_r1__fast2$next \data_r1__fast2 + assign \data_r1__fast2_ok$next \data_r1__fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r1__fast2_ok$next \data_r1__fast2$next } { \fast2_ok \alu_branch0_fast2 } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r1__fast2_ok$next \data_r1__fast2$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r1__fast2_ok$next 1'0 end sync init + update \data_r1__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r1__fast2_ok 1'0 + sync posedge \coresync_clk + update \data_r1__fast2 \data_r1__fast2$next + update \data_r1__fast2_ok \data_r1__fast2_ok$next end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__nia_ok$next + process $group_39 + assign \data_r2__nia$next \data_r2__nia + assign \data_r2__nia_ok$next \data_r2__nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r2__nia_ok$next \data_r2__nia$next } { \nia_ok \alu_branch0_nia } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r2__nia_ok$next \data_r2__nia$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r2__nia_ok$next 1'0 end sync init + update \data_r2__nia 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r2__nia_ok 1'0 + sync posedge \coresync_clk + update \data_r2__nia \data_r2__nia$next + update \data_r2__nia_ok \data_r2__nia_ok$next end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \out_sel 2'00 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast1_ok + connect \B \cu_busy_o + connect \Y $71 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast2_ok + connect \B \cu_busy_o + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nia_ok + connect \B \cu_busy_o + connect \Y $75 + end + process $group_41 + assign \cu_wrmask_o 3'000 + assign \cu_wrmask_o { $75 $73 $71 } sync init end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \cr_in 3'000 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $78 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_branch0_br_op__imm_data__imm_ok + connect \Y $77 + end + process $group_42 + assign \src_sel 1'0 + assign \src_sel $77 sync init end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \cr_out 3'000 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $80 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_branch0_br_op__imm_data__imm + connect \S \alu_branch0_br_op__imm_data__imm_ok + connect \Y $79 + end + process $group_43 + assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm $79 sync init end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \ldst_len 4'1000 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $82 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $81 + end + process $group_44 + assign \alu_branch0_fast1$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_branch0_fast1$1 $81 sync init end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \upd 2'01 + process $group_45 + assign \src_r0$next \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [0] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r0$next \src1_i end sync init + update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r0 \src_r0$next end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \rc_sel 2'00 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $84 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $83 + end + process $group_46 + assign \alu_branch0_fast2$2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_branch0_fast2$2 $83 sync init end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \cry_in 2'00 + process $group_47 + assign \src_r1$next \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r1$next \src_or_imm end sync init + update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r1 \src_r1$next end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \asmcode 8'10101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \asmcode 8'10101011 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 4 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 4 $85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $86 + parameter \WIDTH 4 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $85 + end + process $group_48 + assign \alu_branch0_cr_a 4'0000 + assign \alu_branch0_cr_a $85 sync init end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \inv_a 1'0 + process $group_49 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r2$next \src3_i end sync init + update \src_r2 4'0000 + sync posedge \coresync_clk + update \src_r2 \src_r2$next end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \inv_out 1'0 - end + process $group_50 + assign \alu_branch0_p_valid_i 1'0 + assign \alu_branch0_p_valid_i \alui_l_q_alui sync init end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $87 + end + process $group_51 + assign \alui_l_r_alui$next \alui_l_r_alui + assign \alui_l_r_alui$next $87 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alui_l_r_alui$next 1'1 end sync init + update \alui_l_r_alui 1'1 + sync posedge \coresync_clk + update \alui_l_r_alui \alui_l_r_alui$next end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \br 1'0 - end + process $group_52 + assign \alui_l_s_alui 1'0 + assign \alui_l_s_alui \all_rd_pulse sync init end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \sgn_ext 1'0 - end + process $group_53 + assign \alu_branch0_n_ready_i 1'0 + assign \alu_branch0_n_ready_i \alu_l_q_alu sync init end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $89 + end + process $group_54 + assign \alu_l_r_alu$next \alu_l_r_alu + assign \alu_l_r_alu$next $89 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_l_r_alu$next 1'1 end sync init + update \alu_l_r_alu 1'1 + sync posedge \coresync_clk + update \alu_l_r_alu \alu_l_r_alu$next end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \is_32b 1'0 - end + process $group_55 + assign \alu_l_s_alu 1'0 + assign \alu_l_s_alu \all_rd_pulse sync init end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \sgn 1'0 + process $group_56 + assign \cu_busy_o 1'0 + assign \cu_busy_o \opc_l_q_opc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $91 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire width 1 $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_br_op__imm_data__imm_ok + connect \Y $93 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $91 + connect \B { 1'1 $93 1'1 } + connect \Y $95 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $97 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $95 + connect \B $97 + connect \Y $99 + end + process $group_57 + assign \cu_rd__rel_o 3'000 + assign \cu_rd__rel_o $99 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire width 1 \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $101 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $103 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $105 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B { $101 $103 $105 } + connect \Y $107 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $107 + connect \B \cu_wrmask_o + connect \Y $109 + end + process $group_58 + assign \cu_wr__rel_o 3'000 + assign \cu_wr__rel_o $109 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $111 + end + process $group_59 + assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $111 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest1_o { \data_r0__fast1_ok \data_r0__fast1 } [63:0] end sync init end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $113 + end + process $group_60 + assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $113 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest2_o { \data_r1__fast2_ok \data_r1__fast2 } [63:0] end sync init end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'00 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 2'01 - assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $115 + end + process $group_61 + assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $115 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest3_o { \data_r2__nia_ok \data_r2__nia } [63:0] end sync init end + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec" -module \dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332" - wire width 1 input 0 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331" - wire width 32 input 1 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 output 2 \opcode_in - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 output 3 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 output 4 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 5 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 output 6 \out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 output 7 \rc_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 8 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 output 9 \cr_out +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.p" +module \p$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.n" +module \n$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.p" +module \p$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.n" +module \n$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.main" +module \main$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -30672,111 +19959,8 @@ module \dec attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 output 10 \internal_op - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 output 11 \function_unit - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 output 12 \ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 13 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 14 \inv_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 output 15 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 16 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 17 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 18 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 19 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 1 output 20 \LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 21 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 output 22 \sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 output 23 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 24 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 25 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 26 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 27 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 16 output 28 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 16 output 29 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 30 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 6 output 31 \sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 24 output 32 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 1 output 33 \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 1 output 34 \OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 14 output 35 \BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 36 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 37 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 38 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 39 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 40 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 14 output 41 \DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 output 42 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 10 output 43 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 output 44 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 output 45 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 output 46 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 output 47 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \trap_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -30789,40 +19973,30 @@ module \dec attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec19_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec19_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \trap_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 12 \fast2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 13 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -30896,142 +20070,8 @@ module \dec attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec19_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec19_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec19_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec19_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec19_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec19_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec19_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec19_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec19_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec19_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec19_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec19_asmcode - cell \dec19 \dec19 - connect \opcode_in \dec19_opcode_in - connect \function_unit \dec19_function_unit - connect \form \dec19_form - connect \internal_op \dec19_internal_op - connect \in1_sel \dec19_in1_sel - connect \in2_sel \dec19_in2_sel - connect \in3_sel \dec19_in3_sel - connect \out_sel \dec19_out_sel - connect \cr_in \dec19_cr_in - connect \cr_out \dec19_cr_out - connect \rc_sel \dec19_rc_sel - connect \ldst_len \dec19_ldst_len - connect \upd \dec19_upd - connect \cry_in \dec19_cry_in - connect \inv_a \dec19_inv_a - connect \inv_out \dec19_inv_out - connect \cry_out \dec19_cry_out - connect \br \dec19_br - connect \sgn_ext \dec19_sgn_ext - connect \rsrv \dec19_rsrv - connect \is_32b \dec19_is_32b - connect \sgn \dec19_sgn - connect \lk \dec19_lk - connect \sgl_pipe \dec19_sgl_pipe - connect \asmcode \dec19_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec30_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 14 \trap_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -31044,14692 +20084,11970 @@ module \dec attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec30_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec30_form - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 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attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec30_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec30_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec30_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec30_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec30_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec30_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src 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1 \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec30_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec30_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec30_asmcode - cell \dec30 \dec30 - connect \opcode_in \dec30_opcode_in - connect \function_unit \dec30_function_unit - connect \form \dec30_form - connect \internal_op \dec30_internal_op - connect \in1_sel \dec30_in1_sel - connect \in2_sel \dec30_in2_sel - connect \in3_sel \dec30_in3_sel - connect \out_sel \dec30_out_sel - connect \cr_in \dec30_cr_in - connect \cr_out \dec30_cr_out - connect \rc_sel \dec30_rc_sel - connect \ldst_len \dec30_ldst_len - connect \upd \dec30_upd - connect \cry_in \dec30_cry_in - connect \inv_a \dec30_inv_a - connect \inv_out \dec30_inv_out - connect \cry_out \dec30_cry_out - connect \br \dec30_br - connect \sgn_ext \dec30_sgn_ext - connect \rsrv \dec30_rsrv - connect \is_32b \dec30_is_32b - connect \sgn \dec30_sgn - connect \lk \dec30_lk - connect \sgl_pipe \dec30_sgl_pipe - connect \asmcode \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 15 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \trap_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 17 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 18 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 19 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 output 20 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 21 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 25 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 26 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 27 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 28 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 29 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 30 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 31 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133" + wire width 5 \to + process $group_0 + assign \to 5'00000 + assign \to { \trap_op__insn [25] \trap_op__insn [24] \trap_op__insn [23] \trap_op__insn [22] \trap_op__insn [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec31_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec31_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec31_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec31_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec31_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec31_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec31_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec31_asmcode - cell \dec31 \dec31 - connect \opcode_in \dec31_opcode_in - connect \function_unit \dec31_function_unit - connect \form \dec31_form - connect \internal_op \dec31_internal_op - connect \in1_sel \dec31_in1_sel - connect \in2_sel \dec31_in2_sel - connect \in3_sel \dec31_in3_sel - connect \out_sel \dec31_out_sel - connect \cr_in \dec31_cr_in - connect \cr_out \dec31_cr_out - connect \rc_sel \dec31_rc_sel - connect \ldst_len \dec31_ldst_len - connect \upd \dec31_upd - connect \cry_in \dec31_cry_in - connect \inv_a \dec31_inv_a - connect \inv_out \dec31_inv_out - connect \cry_out \dec31_cry_out - connect \br \dec31_br - connect \sgn_ext \dec31_sgn_ext - connect \rsrv \dec31_rsrv - connect \is_32b \dec31_is_32b - connect \sgn \dec31_sgn - connect \lk \dec31_lk - connect \sgl_pipe \dec31_sgl_pipe - connect \asmcode \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137" + wire width 64 \a_s + process $group_1 + assign \a_s 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch { \trap_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + case 1'1 + assign \a_s { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" + case + assign \a_s \ra + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec58_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec58_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec58_form - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec58_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec58_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec58_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec58_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec58_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec58_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec58_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec58_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec58_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec58_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec58_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec58_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec58_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec58_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec58_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec58_asmcode - cell \dec58 \dec58 - connect \opcode_in \dec58_opcode_in - connect \function_unit \dec58_function_unit - connect \form \dec58_form - connect \internal_op \dec58_internal_op - connect \in1_sel \dec58_in1_sel - connect \in2_sel \dec58_in2_sel - connect \in3_sel \dec58_in3_sel - connect \out_sel \dec58_out_sel - connect \cr_in \dec58_cr_in - connect \cr_out \dec58_cr_out - connect \rc_sel \dec58_rc_sel - connect \ldst_len \dec58_ldst_len - connect \upd \dec58_upd - connect \cry_in \dec58_cry_in - connect \inv_a \dec58_inv_a - connect \inv_out \dec58_inv_out - connect \cry_out \dec58_cry_out - connect \br \dec58_br - connect \sgn_ext \dec58_sgn_ext - connect \rsrv \dec58_rsrv - connect \is_32b \dec58_is_32b - connect \sgn \dec58_sgn - connect \lk \dec58_lk - connect \sgl_pipe \dec58_sgl_pipe - connect \asmcode \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" + wire width 64 \b_s + process $group_2 + assign \b_s 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch { \trap_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + case 1'1 + assign \b_s { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" + case + assign \b_s \rb + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:232" - wire width 32 \dec62_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 11 \dec62_function_unit - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \dec62_form - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 \dec62_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 3 \dec62_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 4 \dec62_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 \dec62_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 2 \dec62_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 \dec62_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 3 \dec62_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" - wire width 2 \dec62_rc_sel - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 4 \dec62_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 \dec62_upd - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" - wire width 2 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec62_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec62_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec62_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec62_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec62_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \dec62_asmcode - cell \dec62 \dec62 - connect \opcode_in \dec62_opcode_in - connect \function_unit \dec62_function_unit - connect \form \dec62_form - connect \internal_op \dec62_internal_op - connect \in1_sel \dec62_in1_sel - connect \in2_sel \dec62_in2_sel - connect \in3_sel \dec62_in3_sel - connect \out_sel \dec62_out_sel - connect \cr_in \dec62_cr_in - connect \cr_out \dec62_cr_out - connect \rc_sel \dec62_rc_sel - connect \ldst_len \dec62_ldst_len - connect \upd \dec62_upd - connect \cry_in \dec62_cry_in - connect \inv_a \dec62_inv_a - connect \inv_out \dec62_inv_out - connect \cry_out \dec62_cry_out - connect \br \dec62_br - connect \sgn_ext \dec62_sgn_ext - connect \rsrv \dec62_rsrv - connect \is_32b \dec62_is_32b - connect \sgn \dec62_sgn - connect \lk \dec62_lk - connect \sgl_pipe \dec62_sgl_pipe - connect \asmcode \dec62_asmcode - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 6 \opcode_switch - process $group_0 - assign \opcode_switch 6'000000 - assign \opcode_switch \opcode_in [31:26] - sync init - end - process $group_1 - assign \dec19_opcode_in 32'00000000000000000000000000000000 - assign \dec19_opcode_in \opcode_in - sync init - end - process $group_2 - assign \dec30_opcode_in 32'00000000000000000000000000000000 - assign \dec30_opcode_in \opcode_in - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:140" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 64 $12 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \ra [31:0] + connect \Y $12 end process $group_3 - assign \dec31_opcode_in 32'00000000000000000000000000000000 - assign \dec31_opcode_in \opcode_in + assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch { \trap_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + case 1'1 + assign \a $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" + case + assign \a \ra + end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" + wire width 64 \b + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 64 $14 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \rb [31:0] + connect \Y $14 + end process $group_4 - assign \dec58_opcode_in 32'00000000000000000000000000000000 - assign \dec58_opcode_in \opcode_in + assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch { \trap_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + case 1'1 + assign \b $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" + case + assign \b \rb + end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156" + wire width 1 \lt_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" + cell $lt $17 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $16 + end process $group_5 - assign \dec62_opcode_in 32'00000000000000000000000000000000 - assign \dec62_opcode_in \opcode_in + assign \lt_s 1'0 + assign \lt_s $16 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" + wire width 1 \gt_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + cell $gt $19 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $18 + end process $group_6 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \function_unit \dec19_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \function_unit \dec30_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \function_unit \dec31_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \function_unit \dec58_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \function_unit \dec62_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \function_unit 11'00000010000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \function_unit 11'00000000000 - end + assign \gt_s 1'0 + assign \gt_s $18 sync init end - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:122" - wire width 5 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" + wire width 1 \lt_u + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" + cell $lt $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $20 + end process $group_7 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \form \dec19_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \form \dec30_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \form \dec31_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \form \dec58_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \form \dec62_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \form 5'00011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \form 5'00010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \form 5'00010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \form 5'00001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \form 5'00010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \form 5'10011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \form 5'10011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \form 5'10011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \form 5'00100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \form 5'00000 - end + assign \lt_u 1'0 + assign \lt_u $20 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" + wire width 1 \gt_u + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" + cell $gt $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $22 + end process $group_8 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \internal_op \dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \internal_op \dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \internal_op \dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \internal_op \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \internal_op \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \internal_op 7'1001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \internal_op 7'0000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \internal_op 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \internal_op 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \internal_op 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \internal_op 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \internal_op 7'1000011 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \internal_op 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \internal_op 7'1000100 - end + assign \gt_u 1'0 + assign \gt_u $22 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" + wire width 1 \equal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" + cell $eq $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $24 + end process $group_9 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \in1_sel \dec19_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \in1_sel \dec30_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \in1_sel \dec31_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \in1_sel \dec58_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \in1_sel \dec62_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \in1_sel 3'100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \in1_sel 3'000 - end + assign \equal 1'0 + assign \equal $24 sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:170" + wire width 5 \trap_bits process $group_10 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \in2_sel \dec19_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \in2_sel \dec30_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \in2_sel \dec31_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \in2_sel \dec58_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \in2_sel \dec62_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \in2_sel 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \in2_sel 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \in2_sel 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \in2_sel 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \in2_sel 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \in2_sel 4'0100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \in2_sel 4'0000 - end + assign \trap_bits 5'00000 + assign \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + wire width 1 \should_trap + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + wire width 1 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + wire width 5 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $and $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \trap_bits + connect \B \to + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $reduce_or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A $27 + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $reduce_or $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $26 + connect \B $30 + connect \Y $32 + end process $group_11 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \in3_sel \dec19_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \in3_sel \dec30_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \in3_sel \dec31_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \in3_sel \dec58_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \in3_sel \dec62_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \in3_sel 2'00 + assign \should_trap 1'0 + assign \should_trap $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + wire width 64 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + wire width 20 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + cell $sshl $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 20 + connect \A \trap_op__trapaddr + connect \B 3'100 + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + cell $pos $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \Y_WIDTH 64 + connect \A $35 + connect \Y $34 + end + process $group_12 + assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" + attribute \nmigen.decoding "OP_TRAP/63" + case 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch { \should_trap } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + case 1'1 + assign \nia $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" + case 7'1001000, 7'1001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \nmigen.decoding "OP_MFMSR/71" + case 7'1000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + assign \nia { { { } \fast1 [63:2] } 2'00 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \nia 64'0000000000000000000000000000000000000000000000000000110000000000 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \in3_sel 2'00 + sync init + end + process $group_13 + assign \nia_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" + attribute \nmigen.decoding "OP_TRAP/63" + case 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch { \should_trap } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + case 1'1 + assign \nia_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" + case 7'1001000, 7'1001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \nmigen.decoding "OP_MFMSR/71" + case 7'1000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + assign \nia_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \nia_ok 1'1 end sync init end - process $group_12 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \out_sel \dec19_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \out_sel \dec30_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \out_sel \dec31_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \out_sel \dec58_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \out_sel \dec62_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \out_sel 2'10 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \out_sel 2'01 - end - sync init - end - process $group_13 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \cr_in \dec19_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \cr_in \dec30_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \cr_in \dec31_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \cr_in \dec58_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \cr_in \dec62_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \cr_in 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \cr_in 3'000 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:300" + wire width 65 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:300" + wire width 65 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:300" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \trap_op__cia + connect \B 3'100 + connect \Y $39 end + connect $38 $39 process $group_14 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \cr_out \dec19_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \cr_out \dec30_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \cr_out \dec31_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \cr_out \dec58_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \cr_out \dec62_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \cr_out 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \cr_out 3'000 + assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" + attribute \nmigen.decoding "OP_TRAP/63" + case 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch { \should_trap } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + case 1'1 + assign \fast1$10 \trap_op__cia + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" + case 7'1001000, 7'1001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \nmigen.decoding "OP_MFMSR/71" + case 7'1000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \fast1$10 $38 [63:0] end sync init end process $group_15 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \rc_sel \dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \rc_sel \dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \rc_sel \dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \rc_sel \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \rc_sel \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \rc_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \rc_sel 2'00 + assign \fast1_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" + attribute \nmigen.decoding "OP_TRAP/63" + case 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch { \should_trap } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + case 1'1 + assign \fast1_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" + case 7'1001000, 7'1001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \nmigen.decoding "OP_MFMSR/71" + case 7'1000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \fast1_ok 1'1 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $eq $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \B 1'0 + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" + wire width 5 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" + cell $and $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 5 + connect \A \trap_op__traptype + connect \B 2'10 + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A $44 + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" + wire width 5 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" + cell $and $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \trap_op__traptype + connect \B 1'1 + connect \Y $48 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A $48 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" + wire width 5 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" + cell $and $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A \trap_op__traptype + connect \B 4'1000 + connect \Y $52 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A $52 + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" + wire width 5 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" + cell $and $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \trap_op__traptype + connect \B 5'10000 + connect \Y $56 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A $56 + connect \Y $55 + end process $group_16 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \ldst_len \dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \ldst_len \dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \ldst_len \dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \ldst_len \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \ldst_len \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \ldst_len 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \ldst_len 4'0000 + assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" + attribute \nmigen.decoding "OP_TRAP/63" + case 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch { \should_trap } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + case 1'1 + assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2$11 [15:0] \trap_op__msr [15:0] + assign \fast2$11 [26:22] \trap_op__msr [26:22] + assign \fast2$11 [63:31] \trap_op__msr [63:31] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + switch { $41 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + case 1'1 + assign \fast2$11 [17] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" + switch { $43 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" + case 1'1 + assign \fast2$11 [18] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" + switch { $47 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" + case 1'1 + assign \fast2$11 [20] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" + switch { $51 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" + case 1'1 + assign \fast2$11 [16] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" + switch { $55 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" + case 1'1 + assign \fast2$11 [19] 1'1 + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" + case 7'1001000, 7'1001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \nmigen.decoding "OP_MFMSR/71" + case 7'1000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2$11 [15:0] \trap_op__msr [15:0] + assign \fast2$11 [26:22] \trap_op__msr [26:22] + assign \fast2$11 [63:31] \trap_op__msr [63:31] end sync init end process $group_17 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \upd \dec19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \upd \dec30_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \upd \dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \upd \dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \upd \dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \upd 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \upd 2'00 + assign \fast2_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" + attribute \nmigen.decoding "OP_TRAP/63" + case 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch { \should_trap } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + case 1'1 + assign \fast2_ok 1'1 + assign \fast2_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" + case 7'1001000, 7'1001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \nmigen.decoding "OP_MFMSR/71" + case 7'1000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \fast2_ok 1'1 end sync init end - process $group_18 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \cry_in \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \cry_in \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \cry_in \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \cry_in \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \cry_in \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \cry_in 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \cry_in 2'00 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 65 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \trap_op__msr + connect \Y $59 end - process $group_19 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \inv_a \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \inv_a \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \inv_a \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \inv_a \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \inv_a \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \inv_a 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \inv_a 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \trap_op__insn [22] \trap_op__insn [21] } + connect \Y $61 end - process $group_20 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \inv_out \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \inv_out \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \inv_out \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \inv_out \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \inv_out \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \inv_out 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \inv_out 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" + cell $eq $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn_type + connect \B 7'1001000 + connect \Y $63 end - process $group_21 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \cry_out \dec19_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \cry_out \dec30_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \cry_out \dec31_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \cry_out \dec58_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \cry_out \dec62_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \cry_out 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \cry_out 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" + cell $eq $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $65 end - process $group_22 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \br \dec19_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \br \dec30_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \br \dec31_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \br \dec58_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \br \dec62_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \br 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \br 1'0 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" + cell $eq $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ra [34:32] + connect \B 3'000 + connect \Y $67 end - process $group_23 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \sgn_ext \dec19_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \sgn_ext \dec30_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \sgn_ext \dec31_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \sgn_ext \dec58_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \sgn_ext \dec62_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \sgn_ext 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" + cell $and $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $65 + connect \B $67 + connect \Y $69 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $not $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [60] + connect \Y $71 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:267" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:267" + cell $not $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn [9] + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:280" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:280" + cell $eq $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $75 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" + cell $eq $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fast2 [34:32] + connect \B 3'000 + connect \Y $77 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" + cell $and $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $75 + connect \B $77 + connect \Y $79 + end + process $group_18 + assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \msr_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" + attribute \nmigen.decoding "OP_TRAP/63" + case 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch { \should_trap } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + case 1'1 + assign \msr \trap_op__msr + assign \msr [63] 1'1 + assign \msr [15] 1'0 + assign \msr [14] 1'0 + assign \msr [5] 1'0 + assign \msr [4] 1'0 + assign \msr [1] 1'0 + assign \msr [0] 1'1 + assign \msr [11] 1'0 + assign \msr [8] 1'0 + assign \msr [23] 1'0 + assign \msr [32] 1'0 + assign \msr [25] 1'0 + assign \msr [13] 1'0 + assign \msr [3] 1'0 + assign \msr [10] 1'0 + assign \msr [9] 1'0 + assign \msr [58] 1'0 + assign \msr_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" + case 7'1001000, 7'1001010 + assign { \msr_ok \msr } $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:212" + switch { $61 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:212" + case 1'1 + assign \msr [1] \ra [1] + assign \msr [15] \ra [15] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:216" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" + switch { $63 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" + case 1'1 + assign \msr [11:1] \ra [11:1] + assign \msr [59:13] \ra [59:13] + assign \msr [63:61] \ra [63:61] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" + switch { $69 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" + case 1'1 + assign \msr [34:32] \trap_op__msr [34:32] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:229" + case + assign \msr [11:1] \ra [11:1] + assign \msr [31:13] \ra [31:13] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" + switch { \msr [14] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" + case 1'1 + assign \msr [15] 1'1 + assign \msr [5] 1'1 + assign \msr [4] 1'1 + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + switch { $71 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + case 1'1 + assign \msr [60] \trap_op__msr [60] + assign \msr [12] \trap_op__msr [12] + end + switch { } + case + assign \msr_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \nmigen.decoding "OP_MFMSR/71" + case 7'1000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + assign \msr [15:0] \fast2 [15:0] + assign \msr [26:22] \fast2 [26:22] + assign \msr [63:31] \fast2 [63:31] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:267" + switch { $73 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:267" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" + switch { \trap_op__msr [60] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:268" + case 1'1 + assign { \msr_ok \msr } [12] \fast2 [12] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:270" + case + assign { \msr_ok \msr } [12] \trap_op__msr [12] + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" + switch { \msr [14] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" + case 1'1 + assign \msr [15] 1'1 + assign \msr [5] 1'1 + assign \msr [4] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" + switch { $79 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" + case 1'1 + assign \msr [34:32] \trap_op__msr [34:32] + end + switch { } + case + assign \msr_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \msr \trap_op__msr + assign \msr [63] 1'1 + assign \msr [15] 1'0 + assign \msr [14] 1'0 + assign \msr [5] 1'0 + assign \msr [4] 1'0 + assign \msr [1] 1'0 + assign \msr [0] 1'1 + assign \msr [11] 1'0 + assign \msr [8] 1'0 + assign \msr [23] 1'0 + assign \msr [32] 1'0 + assign \msr [25] 1'0 + assign \msr [13] 1'0 + assign \msr [3] 1'0 + assign \msr [10] 1'0 + assign \msr [9] 1'0 + assign \msr [58] 1'0 + assign \msr_ok 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \rsrv - process $group_24 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \rsrv \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \rsrv \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \rsrv \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \rsrv \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \rsrv \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \rsrv 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \rsrv 1'0 + process $group_20 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" + attribute \nmigen.decoding "OP_TRAP/63" + case 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" + case 7'1001000, 7'1001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \nmigen.decoding "OP_MFMSR/71" + case 7'1000111 + assign \o \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 end sync init end - process $group_25 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \is_32b \dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \is_32b \dec30_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \is_32b \dec31_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \is_32b \dec58_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \is_32b \dec62_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \is_32b 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \is_32b 1'0 + process $group_21 + assign \o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" + attribute \nmigen.decoding "OP_TRAP/63" + case 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" + attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" + case 7'1001000, 7'1001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" + attribute \nmigen.decoding "OP_MFMSR/71" + case 7'1000111 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:289" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 end sync init end - process $group_26 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \sgn \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \sgn \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \sgn \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \sgn \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \sgn \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \sgn 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \sgn 1'0 - end + process $group_22 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - process $group_27 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \lk \dec19_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \lk \dec30_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \lk \dec31_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \lk \dec58_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \lk \dec62_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \lk 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \lk 1'0 - end + process $group_23 + assign \trap_op__insn_type$2 7'0000000 + assign \trap_op__fn_unit$3 11'00000000000 + assign \trap_op__insn$4 32'00000000000000000000000000000000 + assign \trap_op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trap_op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trap_op__is_32bit$7 1'0 + assign \trap_op__traptype$8 5'00000 + assign \trap_op__trapaddr$9 13'0000000000000 + assign { \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" - wire width 1 \sgl_pipe - process $group_28 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \sgl_pipe \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \sgl_pipe \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \sgl_pipe \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \sgl_pipe \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \sgl_pipe \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \sgl_pipe 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \sgl_pipe 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 8 \asmcode - process $group_29 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'010011 - assign \asmcode \dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011110 - assign \asmcode \dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'011111 - assign \asmcode \dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111010 - assign \asmcode \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - case 6'111110 - assign \asmcode \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001100 - assign \asmcode 8'00000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001101 - assign \asmcode 8'00001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001110 - assign \asmcode 8'00000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001111 - assign \asmcode 8'00001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011100 - assign \asmcode 8'00010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011101 - assign \asmcode 8'00010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010010 - assign \asmcode 8'00010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010000 - assign \asmcode 8'00010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001011 - assign \asmcode 8'00011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001010 - assign \asmcode 8'00011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100010 - assign \asmcode 8'01001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100011 - assign \asmcode 8'01001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101010 - assign \asmcode 8'01010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101011 - assign \asmcode 8'01011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101000 - assign \asmcode 8'01011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101001 - assign \asmcode 8'01011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100000 - assign \asmcode 8'01100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100001 - assign \asmcode 8'01100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000111 - assign \asmcode 8'01111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011000 - assign \asmcode 8'10001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011001 - assign \asmcode 8'10001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010100 - assign \asmcode 8'10010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010101 - assign \asmcode 8'10010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'010111 - assign \asmcode 8'10011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100110 - assign \asmcode 8'10100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100111 - assign \asmcode 8'10100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101100 - assign \asmcode 8'10101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'101101 - assign \asmcode 8'10110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100100 - assign \asmcode 8'10110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'100101 - assign \asmcode 8'10110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'001000 - assign \asmcode 8'10111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000010 - assign \asmcode 8'11000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'000011 - assign \asmcode 8'11001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011010 - assign \asmcode 8'11001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 6'011011 - assign \asmcode 8'11001100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:292" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000000---------------0100000000- - assign \asmcode 8'00010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'01100000000000000000000000000000 - assign \asmcode 8'10000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:301" - case 32'000001---------------0000000011- - assign \asmcode 8'10011010 - end - sync init - end - process $group_30 - assign \opcode_switch$1 32'00000000000000000000000000000000 - assign \opcode_switch$1 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:364" - wire width 32 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:364" - cell $mux $3 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $2 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe" +module \pipe$32 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \trap_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \trap_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 input 11 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 12 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 15 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 16 \fast2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 17 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 18 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 19 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 21 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \trap_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \trap_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 23 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 24 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 25 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \trap_op__is_32bit$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 output 26 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 \trap_op__traptype$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 27 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 28 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 29 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 30 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 31 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 32 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 33 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fast2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 34 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 35 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 36 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 37 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \msr_ok$next + cell \p$33 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_31 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $2 - sync init + cell \n$34 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end - process $group_32 - assign \RS 5'00000 - assign \RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_trap_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \main_trap_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 \main_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$12 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_trap_op__insn_type$13 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \main_trap_op__fn_unit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_trap_op__insn$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__msr$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__cia$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_trap_op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 \main_trap_op__traptype$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast1$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast2$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_msr_ok + cell \main$35 \main + connect \muxid \main_muxid + connect \trap_op__insn_type \main_trap_op__insn_type + connect \trap_op__fn_unit \main_trap_op__fn_unit + connect \trap_op__insn \main_trap_op__insn + connect \trap_op__msr \main_trap_op__msr + connect \trap_op__cia \main_trap_op__cia + connect \trap_op__is_32bit \main_trap_op__is_32bit + connect \trap_op__traptype \main_trap_op__traptype + connect \trap_op__trapaddr \main_trap_op__trapaddr + connect \ra \main_ra + connect \rb \main_rb + connect \fast1 \main_fast1 + connect \fast2 \main_fast2 + connect \muxid$1 \main_muxid$12 + connect \trap_op__insn_type$2 \main_trap_op__insn_type$13 + connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$14 + connect \trap_op__insn$4 \main_trap_op__insn$15 + connect \trap_op__msr$5 \main_trap_op__msr$16 + connect \trap_op__cia$6 \main_trap_op__cia$17 + connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$18 + connect \trap_op__traptype$8 \main_trap_op__traptype$19 + connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$20 + connect \o \main_o + connect \o_ok \main_o_ok + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok + connect \nia \main_nia + connect \nia_ok \main_nia_ok + connect \msr \main_msr + connect \msr_ok \main_msr_ok end - process $group_33 - assign \RT 5'00000 - assign \RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_0 + assign \main_muxid 2'00 + assign \main_muxid \muxid sync init end - process $group_34 - assign \RA 5'00000 - assign \RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_1 + assign \main_trap_op__insn_type 7'0000000 + assign \main_trap_op__fn_unit 11'00000000000 + assign \main_trap_op__insn 32'00000000000000000000000000000000 + assign \main_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_trap_op__is_32bit 1'0 + assign \main_trap_op__traptype 5'00000 + assign \main_trap_op__trapaddr 13'0000000000000 + assign { \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } sync init end - process $group_35 - assign \RB 5'00000 - assign \RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_9 + assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_ra \ra sync init end - process $group_36 - assign \SI 16'0000000000000000 - assign \SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + process $group_10 + assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_rb \rb sync init end - process $group_37 - assign \UI 16'0000000000000000 - assign \UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + process $group_11 + assign \main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_fast1 \fast1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 1 \L - process $group_38 - assign \L 1'0 - assign \L { \opcode_in [21] } + process $group_12 + assign \main_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_fast2 \fast2 sync init end - process $group_39 - assign \SH32 5'00000 - assign \SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$23 + process $group_13 + assign \p_valid_i$23 1'0 + assign \p_valid_i$23 \p_valid_i sync init end - process $group_40 - assign \sh 6'000000 - assign \sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_14 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 \MB32 - process $group_41 - assign \MB32 5'00000 - assign \MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$23 + connect \B \p_ready_o + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 \ME32 - process $group_42 - assign \ME32 5'00000 - assign \ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + process $group_15 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $24 sync init end - process $group_43 - assign \LI 24'000000000000000000000000 - assign \LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$26 + process $group_16 + assign \muxid$26 2'00 + assign \muxid$26 \main_muxid$12 sync init end - process $group_44 - assign \LK 1'0 - assign \LK { \opcode_in [0] } + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$27 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \trap_op__fn_unit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \trap_op__is_32bit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 \trap_op__traptype$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$34 + process $group_17 + assign \trap_op__insn_type$27 7'0000000 + assign \trap_op__fn_unit$28 11'00000000000 + assign \trap_op__insn$29 32'00000000000000000000000000000000 + assign \trap_op__msr$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trap_op__cia$31 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trap_op__is_32bit$32 1'0 + assign \trap_op__traptype$33 5'00000 + assign \trap_op__trapaddr$34 13'0000000000000 + assign { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } { \main_trap_op__trapaddr$20 \main_trap_op__traptype$19 \main_trap_op__is_32bit$18 \main_trap_op__cia$17 \main_trap_op__msr$16 \main_trap_op__insn$15 \main_trap_op__fn_unit$14 \main_trap_op__insn_type$13 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 1 \AA - process $group_45 - assign \AA 1'0 - assign \AA { \opcode_in [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$36 + process $group_25 + assign \o$35 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$36 1'0 + assign { \o_ok$36 \o$35 } { \main_o_ok \main_o } sync init end - process $group_46 - assign \Rc 1'0 - assign \Rc { \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fast1_ok$38 + process $group_27 + assign \fast1$37 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1_ok$38 1'0 + assign { \fast1_ok$38 \fast1$37 } { \main_fast1_ok \main_fast1$21 } sync init end - process $group_47 - assign \OE 1'0 - assign \OE { \opcode_in [10] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fast2_ok$40 + process $group_29 + assign \fast2$39 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2_ok$40 1'0 + assign { \fast2_ok$40 \fast2$39 } { \main_fast2_ok \main_fast2$22 } sync init end - process $group_48 - assign \BD 14'00000000000000 - assign \BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \nia$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \nia_ok$42 + process $group_31 + assign \nia$41 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \nia_ok$42 1'0 + assign { \nia_ok$42 \nia$41 } { \main_nia_ok \main_nia } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 3 \BF - process $group_49 - assign \BF 3'000 - assign \BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \msr$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \msr_ok$44 + process $group_33 + assign \msr$43 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \msr_ok$44 1'0 + assign { \msr_ok$44 \msr$43 } { \main_msr_ok \main_msr } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 10 \CR - process $group_50 - assign \CR 10'0000000000 - assign \CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_51 - assign \BB 5'00000 - assign \BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_35 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next end - process $group_52 - assign \BA 5'00000 - assign \BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_36 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$26 + end sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next end - process $group_53 - assign \BT 5'00000 - assign \BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_37 + assign \trap_op__insn_type$2$next \trap_op__insn_type$2 + assign \trap_op__fn_unit$3$next \trap_op__fn_unit$3 + assign \trap_op__insn$4$next \trap_op__insn$4 + assign \trap_op__msr$5$next \trap_op__msr$5 + assign \trap_op__cia$6$next \trap_op__cia$6 + assign \trap_op__is_32bit$7$next \trap_op__is_32bit$7 + assign \trap_op__traptype$8$next \trap_op__traptype$8 + assign \trap_op__trapaddr$9$next \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \trap_op__trapaddr$9$next \trap_op__traptype$8$next \trap_op__is_32bit$7$next \trap_op__cia$6$next \trap_op__msr$5$next \trap_op__insn$4$next \trap_op__fn_unit$3$next \trap_op__insn_type$2$next } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \trap_op__trapaddr$9$next \trap_op__traptype$8$next \trap_op__is_32bit$7$next \trap_op__cia$6$next \trap_op__msr$5$next \trap_op__insn$4$next \trap_op__fn_unit$3$next \trap_op__insn_type$2$next } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } + end sync init + update \trap_op__insn_type$2 7'0000000 + update \trap_op__fn_unit$3 11'00000000000 + update \trap_op__insn$4 32'00000000000000000000000000000000 + update \trap_op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000 + update \trap_op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000 + update \trap_op__is_32bit$7 1'0 + update \trap_op__traptype$8 5'00000 + update \trap_op__trapaddr$9 13'0000000000000 + sync posedge \coresync_clk + update \trap_op__insn_type$2 \trap_op__insn_type$2$next + update \trap_op__fn_unit$3 \trap_op__fn_unit$3$next + update \trap_op__insn$4 \trap_op__insn$4$next + update \trap_op__msr$5 \trap_op__msr$5$next + update \trap_op__cia$6 \trap_op__cia$6$next + update \trap_op__is_32bit$7 \trap_op__is_32bit$7$next + update \trap_op__traptype$8 \trap_op__traptype$8$next + update \trap_op__trapaddr$9 \trap_op__trapaddr$9$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 8 \FXM - process $group_54 - assign \FXM 8'00000000 - assign \FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + process $group_45 + assign \o$next \o + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$next } { \o_ok$36 \o$35 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$next } { \o_ok$36 \o$35 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \o_ok$next 1'0 + end sync init + update \o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 + sync posedge \coresync_clk + update \o \o$next + update \o_ok \o_ok$next end - process $group_55 - assign \BO 5'00000 - assign \BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_47 + assign \fast1$10$next \fast1$10 + assign \fast1_ok$next \fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$38 \fast1$37 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$38 \fast1$37 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \fast1_ok$next 1'0 + end sync init + update \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast1_ok 1'0 + sync posedge \coresync_clk + update \fast1$10 \fast1$10$next + update \fast1_ok \fast1_ok$next end - process $group_56 - assign \BI 5'00000 - assign \BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_49 + assign \fast2$11$next \fast2$11 + assign \fast2_ok$next \fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$40 \fast2$39 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$40 \fast2$39 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \fast2_ok$next 1'0 + end sync init + update \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast2_ok 1'0 + sync posedge \coresync_clk + update \fast2$11 \fast2$11$next + update \fast2_ok \fast2_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 2 \BH - process $group_57 - assign \BH 2'00 - assign \BH { \opcode_in [12] \opcode_in [11] } + process $group_51 + assign \nia$next \nia + assign \nia_ok$next \nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \nia_ok$next \nia$next } { \nia_ok$42 \nia$41 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \nia_ok$next \nia$next } { \nia_ok$42 \nia$41 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \nia_ok$next 1'0 + end sync init + update \nia 64'0000000000000000000000000000000000000000000000000000000000000000 + update \nia_ok 1'0 + sync posedge \coresync_clk + update \nia \nia$next + update \nia_ok \nia_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 16 \D - process $group_58 - assign \D 16'0000000000000000 - assign \D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + process $group_53 + assign \msr$next \msr + assign \msr_ok$next \msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \msr_ok$next \msr$next } { \msr_ok$44 \msr$43 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \msr_ok$next \msr$next } { \msr_ok$44 \msr$43 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \msr_ok$next 1'0 + end sync init + update \msr 64'0000000000000000000000000000000000000000000000000000000000000000 + update \msr_ok 1'0 + sync posedge \coresync_clk + update \msr \msr$next + update \msr_ok \msr_ok$next end - process $group_59 - assign \DS 14'00000000000000 - assign \DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + process $group_55 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 \TO - process $group_60 - assign \TO 5'00000 - assign \TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_56 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data sync init end - process $group_61 - assign \BC 5'00000 - assign \BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0" +module \alu_trap0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 5 \msr_ok + attribute \src "simple/issuer.py:102" + wire width 1 input 6 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 8 \n_ready_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \trap_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 10 \trap_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 11 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 12 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 13 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 input 15 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 16 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 18 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 19 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 20 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 21 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 22 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 26 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 27 \p_ready_o + cell \p$30 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 \SH - process $group_62 - assign \SH 5'00000 - assign \SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + cell \n$31 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 \ME - process $group_63 - assign \ME 5'00000 - assign \ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_trap_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_trap_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 \pipe_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_trap_op__insn_type$4 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_trap_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_trap_op__insn$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__msr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__cia$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_trap_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 \pipe_trap_op__traptype$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_trap_op__trapaddr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast2$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_msr_ok + cell \pipe$32 \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_p_valid_i + connect \p_ready_o \pipe_p_ready_o + connect \muxid \pipe_muxid + connect \trap_op__insn_type \pipe_trap_op__insn_type + connect \trap_op__fn_unit \pipe_trap_op__fn_unit + connect \trap_op__insn \pipe_trap_op__insn + connect \trap_op__msr \pipe_trap_op__msr + connect \trap_op__cia \pipe_trap_op__cia + connect \trap_op__is_32bit \pipe_trap_op__is_32bit + connect \trap_op__traptype \pipe_trap_op__traptype + connect \trap_op__trapaddr \pipe_trap_op__trapaddr + connect \ra \pipe_ra + connect \rb \pipe_rb + connect \fast1 \pipe_fast1 + connect \fast2 \pipe_fast2 + connect \n_valid_o \pipe_n_valid_o + connect \n_ready_i \pipe_n_ready_i + connect \muxid$1 \pipe_muxid$3 + connect \trap_op__insn_type$2 \pipe_trap_op__insn_type$4 + connect \trap_op__fn_unit$3 \pipe_trap_op__fn_unit$5 + connect \trap_op__insn$4 \pipe_trap_op__insn$6 + connect \trap_op__msr$5 \pipe_trap_op__msr$7 + connect \trap_op__cia$6 \pipe_trap_op__cia$8 + connect \trap_op__is_32bit$7 \pipe_trap_op__is_32bit$9 + connect \trap_op__traptype$8 \pipe_trap_op__traptype$10 + connect \trap_op__trapaddr$9 \pipe_trap_op__trapaddr$11 + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \fast1$10 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \fast2$11 \pipe_fast2$13 + connect \fast2_ok \pipe_fast2_ok + connect \nia \pipe_nia + connect \nia_ok \pipe_nia_ok + connect \msr \pipe_msr + connect \msr_ok \pipe_msr_ok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 \MB - process $group_64 - assign \MB 5'00000 - assign \MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + process $group_0 + assign \pipe_p_valid_i 1'0 + assign \pipe_p_valid_i \p_valid_i sync init end - process $group_65 - assign \SPR 10'0000000000 - assign \SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_1 + assign \p_ready_o 1'0 + assign \p_ready_o \pipe_p_ready_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_A - process $group_66 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + process $group_2 + assign \pipe_muxid 2'00 + assign \pipe_muxid \muxid sync init end - process $group_67 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + process $group_3 + assign \pipe_trap_op__insn_type 7'0000000 + assign \pipe_trap_op__fn_unit 11'00000000000 + assign \pipe_trap_op__insn 32'00000000000000000000000000000000 + assign \pipe_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_trap_op__is_32bit 1'0 + assign \pipe_trap_op__traptype 5'00000 + assign \pipe_trap_op__trapaddr 13'0000000000000 + assign { \pipe_trap_op__trapaddr \pipe_trap_op__traptype \pipe_trap_op__is_32bit \pipe_trap_op__cia \pipe_trap_op__msr \pipe_trap_op__insn \pipe_trap_op__fn_unit \pipe_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } sync init end - process $group_68 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } + process $group_11 + assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_ra \ra sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_BO - process $group_69 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_12 + assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_rb \rb sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \X_CT - process $group_70 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_13 + assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_fast1 \fast1$1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 7 \X_DCMX - process $group_71 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_14 + assign \pipe_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_fast2 \fast2$2 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \X_DRM - process $group_72 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_15 + assign \n_valid_o 1'0 + assign \n_valid_o \pipe_n_valid_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_E - process $group_73 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } + process $group_16 + assign \pipe_n_ready_i 1'0 + assign \pipe_n_ready_i \n_ready_i sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \X_E_1 - process $group_74 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$14 + process $group_17 + assign \muxid$14 2'00 + assign \muxid$14 \pipe_muxid$3 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \X_EO - process $group_75 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$15 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \trap_op__fn_unit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \trap_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 \trap_op__traptype$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$22 + process $group_18 + assign \trap_op__insn_type$15 7'0000000 + assign \trap_op__fn_unit$16 11'00000000000 + assign \trap_op__insn$17 32'00000000000000000000000000000000 + assign \trap_op__msr$18 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trap_op__cia$19 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trap_op__is_32bit$20 1'0 + assign \trap_op__traptype$21 5'00000 + assign \trap_op__trapaddr$22 13'0000000000000 + assign { \trap_op__trapaddr$22 \trap_op__traptype$21 \trap_op__is_32bit$20 \trap_op__cia$19 \trap_op__msr$18 \trap_op__insn$17 \trap_op__fn_unit$16 \trap_op__insn_type$15 } { \pipe_trap_op__trapaddr$11 \pipe_trap_op__traptype$10 \pipe_trap_op__is_32bit$9 \pipe_trap_op__cia$8 \pipe_trap_op__msr$7 \pipe_trap_op__insn$6 \pipe_trap_op__fn_unit$5 \pipe_trap_op__insn_type$4 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_EO_1 - process $group_76 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_26 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'0 + assign { \o_ok \o } { \pipe_o_ok \pipe_o } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_EX - process $group_77 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } + process $group_28 + assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1_ok 1'0 + assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_FC - process $group_78 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_30 + assign \fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2_ok 1'0 + assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_FRA - process $group_79 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_32 + assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \nia_ok 1'0 + assign { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_FRAp - process $group_80 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_34 + assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \msr_ok 1'0 + assign { \msr_ok \msr } { \pipe_msr_ok \pipe_msr } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_FRB - process $group_81 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + connect \muxid 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l" +module \src_l$36 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_FRBp - process $group_82 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B $1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_FRS - process $group_83 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $3 + connect \B \s_src + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_FRSp - process $group_84 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 4'0000 + end sync init + update \q_int 4'0000 + sync posedge \coresync_clk + update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_FRT - process $group_85 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_FRTp - process $group_86 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B $7 + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \X_IH - process $group_87 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $9 + connect \B \s_src + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 8 \X_IMM8 - process $group_88 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \X_L - process $group_89 - assign \X_L 2'00 - assign \X_L { \opcode_in [22] \opcode_in [21] } + process $group_1 + assign \q_src 4'0000 + assign \q_src $11 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_L_1 - process $group_90 - assign \X_L_1 1'0 - assign \X_L_1 { \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_L_2 - process $group_91 - assign \X_L_2 1'0 - assign \X_L_2 { \opcode_in [16] } + process $group_2 + assign \qn_src 4'0000 + assign \qn_src $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \X_L_3 - process $group_92 - assign \X_L_3 2'00 - assign \X_L_3 { \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \B \q_int + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_MO - process $group_93 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_3 + assign \qlq_src 4'0000 + assign \qlq_src $15 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_NB - process $group_94 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l" +module \opc_l$37 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_PRS - process $group_95 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_R - process $group_96 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_opc + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_R_1 - process $group_97 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_RA - process $group_98 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_RB - process $group_99 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_Rc - process $group_100 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_opc + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \X_RIC - process $group_101 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } + process $group_1 + assign \q_opc 1'0 + assign \q_opc $11 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \X_RM - process $group_102 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_RO - process $group_103 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } + process $group_2 + assign \qn_opc 1'0 + assign \qn_opc $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_RS - process $group_104 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_RSp - process $group_105 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_3 + assign \qlq_opc 1'0 + assign \qlq_opc $15 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_RT - process $group_106 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l" +module \req_l$38 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_RTp - process $group_107 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B $1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_S - process $group_108 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $3 + connect \B \s_req + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_SH - process $group_109 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 5'00000 + end sync init + update \q_int 5'00000 + sync posedge \coresync_clk + update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_SI - process $group_110 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \X_SP - process $group_111 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B $7 + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \X_SR - process $group_112 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $9 + connect \B \s_req + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_SX - process $group_113 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } + process $group_1 + assign \q_req 5'00000 + assign \q_req $11 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \X_SX_S - process $group_114 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_T - process $group_115 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_2 + assign \qn_req 5'00000 + assign \qn_req $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 \X_TBR - process $group_116 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 5 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_TH - process $group_117 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_3 + assign \qlq_req 5'00000 + assign \qlq_req $15 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_TO - process $group_118 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l" +module \rst_l$39 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_TX - process $group_119 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \X_TX_T - process $group_120 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rst + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \X_U - process $group_121 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_UIM - process $group_122 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_VRS - process $group_123 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \X_VRT - process $group_124 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rst + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \X_W - process $group_125 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } + process $group_1 + assign \q_rst 1'0 + assign \q_rst $11 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \X_WC - process $group_126 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 \X_XO - process $group_127 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + process $group_2 + assign \qn_rst 1'0 + assign \qn_rst $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 8 \X_XO_1 - process $group_128 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \B_AA - process $group_129 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } + process $group_3 + assign \qlq_rst 1'0 + assign \qlq_rst $15 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 14 \B_BD - process $group_130 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l" +module \rok_l$40 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \B_BI - process $group_131 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \B_BO - process $group_132 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rdok + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \B_LK - process $group_133 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \I_AA - process $group_134 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 24 \I_LI - process $group_135 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \I_LK - process $group_136 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rdok + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX3_AX - process $group_137 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } + process $group_1 + assign \q_rdok 1'0 + assign \q_rdok $11 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX3_A - process $group_138 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \XX3_AX_A - process $group_139 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_2 + assign \qn_rdok 1'0 + assign \qn_rdok $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \XX3_BF - process $group_140 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX3_BX - process $group_141 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } + process $group_3 + assign \qlq_rdok 1'0 + assign \qlq_rdok $15 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX3_B - process $group_142 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l" +module \alui_l$41 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \XX3_BX_B - process $group_143 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \XX3_DM - process $group_144 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alui + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX3_Rc - process $group_145 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \XX3_SHW - process $group_146 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX3_TX - process $group_147 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX3_T - process $group_148 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alui + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \XX3_TX_T - process $group_149 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_1 + assign \q_alui 1'0 + assign \q_alui $11 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \XX3_XO - process $group_150 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 8 \XX3_XO_1 - process $group_151 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + process $group_2 + assign \qn_alui 1'0 + assign \qn_alui $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 9 \XX3_XO_2 - process $group_152 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX4_AX - process $group_153 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } + process $group_3 + assign \qlq_alui 1'0 + assign \qlq_alui $15 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX4_A - process $group_154 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l" +module \alu_l$42 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \XX4_AX_A - process $group_155 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX4_BX - process $group_156 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX4_B - process $group_157 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alu + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \XX4_BX_B - process $group_158 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX4_CX - process $group_159 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX4_C - process $group_160 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \XX4_CX_C - process $group_161 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alu + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX4_TX - process $group_162 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } + process $group_1 + assign \q_alu 1'0 + assign \q_alu $11 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX4_T - process $group_163 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \XX4_TX_T - process $group_164 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_2 + assign \qn_alu 1'0 + assign \qn_alu $13 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \XX4_XO - process $group_165 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XL_BA - process $group_166 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_3 + assign \qlq_alu 1'0 + assign \qlq_alu $15 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XL_BB - process $group_167 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0" +module \trap0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_trap0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \oper_i_alu_trap0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_trap0__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \oper_i_alu_trap0__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \oper_i_alu_trap0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 input 7 \oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 input 9 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 output 10 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 11 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 12 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 13 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 14 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 15 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 16 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 17 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 18 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 19 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 20 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 21 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 22 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 23 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 24 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 25 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 26 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 27 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 28 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 29 \dest5_o + attribute \src "simple/issuer.py:102" + wire width 1 input 30 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \alu_trap0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \alu_trap0_n_ready_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_trap0_trap_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_trap0_trap_op__insn_type$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_trap0_trap_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_trap0_trap_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_trap0_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_trap0_trap_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_trap0_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_trap0_trap_op__msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_trap0_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_trap0_trap_op__cia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_trap0_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_trap0_trap_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 \alu_trap0_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 5 \alu_trap0_trap_op__traptype$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_trap0_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_trap0_trap_op__trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_trap0_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_trap0_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_trap0_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_trap0_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_trap0_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_trap0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_trap0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_trap0_fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_trap0_fast2$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \alu_trap0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \alu_trap0_p_ready_o + cell \alu_trap0 \alu_trap0 + connect \coresync_clk \coresync_clk + connect \o_ok \o_ok + connect \fast1_ok \fast1_ok + connect \fast2_ok \fast2_ok + connect \nia_ok \nia_ok + connect \msr_ok \msr_ok + connect \coresync_rst \coresync_rst + connect \n_valid_o \alu_trap0_n_valid_o + connect \n_ready_i \alu_trap0_n_ready_i + connect \trap_op__insn_type \alu_trap0_trap_op__insn_type + connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit + connect \trap_op__insn \alu_trap0_trap_op__insn + connect \trap_op__msr \alu_trap0_trap_op__msr + connect \trap_op__cia \alu_trap0_trap_op__cia + connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit + connect \trap_op__traptype \alu_trap0_trap_op__traptype + connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr + connect \o \alu_trap0_o + connect \fast1 \alu_trap0_fast1 + connect \fast2 \alu_trap0_fast2 + connect \nia \alu_trap0_nia + connect \msr \alu_trap0_msr + connect \ra \alu_trap0_ra + connect \rb \alu_trap0_rb + connect \fast1$1 \alu_trap0_fast1$1 + connect \fast2$2 \alu_trap0_fast2$2 + connect \p_valid_i \alu_trap0_p_valid_i + connect \p_ready_o \alu_trap0_p_ready_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \XL_BF - process $group_168 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \src_l_q_src + cell \src_l$36 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_src \src_l_s_src + connect \r_src \src_l_r_src + connect \q_src \src_l_q_src end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \XL_BFA - process $group_169 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \opc_l_q_opc + cell \opc_l$37 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_opc \opc_l_s_opc + connect \r_opc \opc_l_r_opc + connect \q_opc \opc_l_q_opc end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \XL_BH - process $group_170 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_r_req$next + cell \req_l$38 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \s_req \req_l_s_req + connect \r_req \req_l_r_req end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XL_BI - process $group_171 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst$next + cell \rst_l$39 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_rst \rst_l_s_rst + connect \r_rst \rst_l_r_rst end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XL_BO - process $group_172 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok$next + cell \rok_l$40 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \s_rdok \rok_l_s_rdok + connect \r_rdok \rok_l_r_rdok end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XL_BO_1 - process $group_173 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alui_l_s_alui + cell \alui_l$41 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui end - process $group_174 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_s_alu + cell \alu_l$42 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XL_LK - process $group_175 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 15 \XL_OC - process $group_176 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 4 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $6 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XL_S - process $group_177 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 4 $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $6 + connect \B \cu_rd__go_i + connect \Y $8 end - process $group_178 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \A_BC - process $group_179 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B $5 + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \A_FRA - process $group_180 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_0 + assign \all_rd 1'0 + assign \all_rd $11 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \A_FRB - process $group_181 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly$next + process $group_1 + assign \all_rd_dly$next \all_rd_dly + assign \all_rd_dly$next \all_rd sync init + update \all_rd_dly 1'0 + sync posedge \coresync_clk + update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \A_FRC - process $group_182 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \A_FRT - process $group_183 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B $13 + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \A_RA - process $group_184 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_2 + assign \all_rd_rise 1'0 + assign \all_rd_rise $15 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \A_RB - process $group_185 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire width 1 \all_rd_pulse + process $group_3 + assign \all_rd_pulse 1'0 + assign \all_rd_pulse \all_rd_rise sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \A_Rc - process $group_186 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire width 1 \alu_done + process $group_4 + assign \alu_done 1'0 + assign \alu_done \alu_trap0_n_valid_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \A_RT - process $group_187 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly$next + process $group_5 + assign \alu_done_dly$next \alu_done_dly + assign \alu_done_dly$next \alu_done sync init + update \alu_done_dly 1'0 + sync posedge \coresync_clk + update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \A_XO - process $group_188 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \D_BF - process $group_189 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B $17 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 16 \D_D - process $group_190 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + process $group_6 + assign \alu_done_rise 1'0 + assign \alu_done_rise $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \D_FRS - process $group_191 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire width 1 \alu_pulse + process $group_7 + assign \alu_pulse 1'0 + assign \alu_pulse \alu_done_rise sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \D_FRT - process $group_192 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 5 \alu_pulsem + process $group_8 + assign \alu_pulsem 5'00000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \D_L - process $group_193 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 5 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \D_RA - process $group_194 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_9 + assign \prev_wr_go$next \prev_wr_go + assign \prev_wr_go$next $21 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \prev_wr_go$next 5'00000 + end sync init + update \prev_wr_go 5'00000 + sync posedge \coresync_clk + update \prev_wr_go \prev_wr_go$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \D_RS - process $group_195 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire width 1 \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 5 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 5 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wrmask_o + connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \D_RT - process $group_196 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 5 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__rel_o + connect \B $25 + connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 16 \D_SI - process $group_197 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A $27 + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \D_TO - process $group_198 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 16 \D_UI - process $group_199 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B $23 + connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \XX2_BF - process $group_200 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + process $group_10 + assign \cu_done_o 1'0 + assign \cu_done_o $31 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX2_BX - process $group_201 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX2_B - process $group_202 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $35 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \XX2_BX_B - process $group_203 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $33 + connect \B $35 + connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX2_dc - process $group_204 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } + process $group_11 + assign \wr_any 1'0 + assign \wr_any $37 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX2_dm - process $group_205 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire width 1 \req_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_ready_i + connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX2_dx - process $group_206 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B $39 + connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 7 \XX2_dc_dm_dx - process $group_207 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 5 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 7 \XX2_DCMX - process $group_208 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $43 + connect \B 1'0 + connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX2_EO - process $group_209 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $41 + connect \B $45 + connect \Y $47 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX2_RT - process $group_210 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XX2_TX - process $group_211 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $49 + connect \B \alu_trap0_n_ready_i + connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XX2_T - process $group_212 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $51 + connect \B \alu_trap0_n_valid_o + connect \Y $53 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \XX2_TX_T - process $group_213 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $53 + connect \B \cu_busy_o + connect \Y $55 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \XX2_UIM - process $group_214 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_12 + assign \req_done 1'0 + assign \req_done $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch { $55 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + case 1'1 + assign \req_done 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \XX2_UIM_1 - process $group_215 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire width 1 \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire width 1 \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $57 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 7 \XX2_XO - process $group_216 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + process $group_13 + assign \reset 1'0 + assign \reset $57 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 9 \XX2_XO_1 - process $group_217 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire width 1 \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $59 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \Z22_BF - process $group_218 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + process $group_14 + assign \rst_r 1'0 + assign \rst_r $59 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \Z22_DCM - process $group_219 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 5 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 5 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $61 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \Z22_DGM - process $group_220 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + process $group_15 + assign \reset_w 5'00000 + assign \reset_w $61 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z22_FRA - process $group_221 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 4 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 4 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $63 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z22_FRAp - process $group_222 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_16 + assign \reset_r 4'0000 + assign \reset_r $63 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z22_FRT - process $group_223 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_17 + assign \rok_l_s_rdok$next \rok_l_s_rdok + assign \rok_l_s_rdok$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_s_rdok$next 1'0 + end sync init + update \rok_l_s_rdok 1'0 + sync posedge \coresync_clk + update \rok_l_s_rdok \rok_l_s_rdok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z22_FRTp - process $group_224 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_valid_o + connect \B \cu_busy_o + connect \Y $65 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \Z22_Rc - process $group_225 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } + process $group_18 + assign \rok_l_r_rdok$next \rok_l_r_rdok + assign \rok_l_r_rdok$next $65 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_r_rdok$next 1'1 + end sync init + update \rok_l_r_rdok 1'1 + sync posedge \coresync_clk + update \rok_l_r_rdok \rok_l_r_rdok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \Z22_SH - process $group_226 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + process $group_19 + assign \rst_l_s_rst$next \rst_l_s_rst + assign \rst_l_s_rst$next \all_rd + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_s_rst$next 1'0 + end sync init + update \rst_l_s_rst 1'0 + sync posedge \coresync_clk + update \rst_l_s_rst \rst_l_s_rst$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 9 \Z22_XO - process $group_227 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + process $group_20 + assign \rst_l_r_rst$next \rst_l_r_rst + assign \rst_l_r_rst$next \rst_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_r_rst$next 1'1 + end sync init + update \rst_l_r_rst 1'1 + sync posedge \coresync_clk + update \rst_l_r_rst \rst_l_r_rst$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \EVS_BFA - process $group_228 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + process $group_21 + assign \opc_l_s_opc$next \opc_l_s_opc + assign \opc_l_s_opc$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_s_opc$next 1'0 + end sync init + update \opc_l_s_opc 1'0 + sync posedge \coresync_clk + update \opc_l_s_opc \opc_l_s_opc$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 \XFX_BHRBE - process $group_229 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_22 + assign \opc_l_r_opc$next \opc_l_r_opc + assign \opc_l_r_opc$next \req_done + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_r_opc$next 1'1 + end sync init + update \opc_l_r_opc 1'1 + sync posedge \coresync_clk + update \opc_l_r_opc \opc_l_r_opc$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XFX_DUI - process $group_230 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_23 + assign \src_l_s_src$next \src_l_s_src + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_s_src$next 4'0000 + end sync init + update \src_l_s_src 4'0000 + sync posedge \coresync_clk + update \src_l_s_src \src_l_s_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 \XFX_DUIS - process $group_231 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_24 + assign \src_l_r_src$next \src_l_r_src + assign \src_l_r_src$next \reset_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_r_src$next 4'1111 + end sync init + update \src_l_r_src 4'1111 + sync posedge \coresync_clk + update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 8 \XFX_FXM - process $group_232 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 5 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $67 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XFX_RS - process $group_233 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_25 + assign \req_l_s_req$next \req_l_s_req + assign \req_l_s_req$next $67 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_s_req$next 5'00000 + end sync init + update \req_l_s_req 5'00000 + sync posedge \coresync_clk + update \req_l_s_req \req_l_s_req$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XFX_RT - process $group_234 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 5 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $69 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 \XFX_SPR - process $group_235 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_26 + assign \req_l_r_req$next \req_l_r_req + assign \req_l_r_req$next $69 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_r_req$next 5'11111 + end sync init + update \req_l_r_req 5'11111 + sync posedge \coresync_clk + update \req_l_r_req \req_l_r_req$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 \XFX_XO - process $group_236 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + process $group_27 + assign \alu_trap0_trap_op__insn_type$next \alu_trap0_trap_op__insn_type + assign \alu_trap0_trap_op__fn_unit$next \alu_trap0_trap_op__fn_unit + assign \alu_trap0_trap_op__insn$next \alu_trap0_trap_op__insn + assign \alu_trap0_trap_op__msr$next \alu_trap0_trap_op__msr + assign \alu_trap0_trap_op__cia$next \alu_trap0_trap_op__cia + assign \alu_trap0_trap_op__is_32bit$next \alu_trap0_trap_op__is_32bit + assign \alu_trap0_trap_op__traptype$next \alu_trap0_trap_op__traptype + assign \alu_trap0_trap_op__trapaddr$next \alu_trap0_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + case 1'1 + assign { \alu_trap0_trap_op__trapaddr$next \alu_trap0_trap_op__traptype$next \alu_trap0_trap_op__is_32bit$next \alu_trap0_trap_op__cia$next \alu_trap0_trap_op__msr$next \alu_trap0_trap_op__insn$next \alu_trap0_trap_op__fn_unit$next \alu_trap0_trap_op__insn_type$next } { \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + end sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 \DX_d0 - process $group_237 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + update \alu_trap0_trap_op__insn_type 7'0000000 + update \alu_trap0_trap_op__fn_unit 11'00000000000 + update \alu_trap0_trap_op__insn 32'00000000000000000000000000000000 + update \alu_trap0_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_trap0_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_trap0_trap_op__is_32bit 1'0 + update \alu_trap0_trap_op__traptype 5'00000 + update \alu_trap0_trap_op__trapaddr 13'0000000000000 + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn_type \alu_trap0_trap_op__insn_type$next + update \alu_trap0_trap_op__fn_unit \alu_trap0_trap_op__fn_unit$next + update \alu_trap0_trap_op__insn \alu_trap0_trap_op__insn$next + update \alu_trap0_trap_op__msr \alu_trap0_trap_op__msr$next + update \alu_trap0_trap_op__cia \alu_trap0_trap_op__cia$next + update \alu_trap0_trap_op__is_32bit \alu_trap0_trap_op__is_32bit$next + update \alu_trap0_trap_op__traptype \alu_trap0_trap_op__traptype$next + update \alu_trap0_trap_op__trapaddr \alu_trap0_trap_op__trapaddr$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok$next + process $group_35 + assign \data_r0__o$next \data_r0__o + assign \data_r0__o_ok$next \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_trap0_o } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r0__o_ok$next 1'0 + end sync init + update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0__o_ok 1'0 + sync posedge \coresync_clk + update \data_r0__o \data_r0__o$next + update \data_r0__o_ok \data_r0__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DX_d1 - process $group_238 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__fast1_ok$next + process $group_37 + assign \data_r1__fast1$next \data_r1__fast1 + assign \data_r1__fast1_ok$next \data_r1__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r1__fast1_ok$next \data_r1__fast1$next } { \fast1_ok \alu_trap0_fast1 } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r1__fast1_ok$next \data_r1__fast1$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r1__fast1_ok$next 1'0 + end sync init + update \data_r1__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r1__fast1_ok 1'0 + sync posedge \coresync_clk + update \data_r1__fast1 \data_r1__fast1$next + update \data_r1__fast1_ok \data_r1__fast1_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \DX_d2 - process $group_239 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__fast2_ok$next + process $group_39 + assign \data_r2__fast2$next \data_r2__fast2 + assign \data_r2__fast2_ok$next \data_r2__fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r2__fast2_ok$next \data_r2__fast2$next } { \fast2_ok \alu_trap0_fast2 } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r2__fast2_ok$next \data_r2__fast2$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r2__fast2_ok$next 1'0 + end sync init + update \data_r2__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r2__fast2_ok 1'0 + sync posedge \coresync_clk + update \data_r2__fast2 \data_r2__fast2$next + update \data_r2__fast2_ok \data_r2__fast2_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 16 \DX_d0_d1_d2 - process $group_240 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r3__nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r3__nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__nia_ok$next + process $group_41 + assign \data_r3__nia$next \data_r3__nia + assign \data_r3__nia_ok$next \data_r3__nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r3__nia_ok$next \data_r3__nia$next } { \nia_ok \alu_trap0_nia } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r3__nia_ok$next \data_r3__nia$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r3__nia_ok$next 1'0 + end sync init + update \data_r3__nia 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r3__nia_ok 1'0 + sync posedge \coresync_clk + update \data_r3__nia \data_r3__nia$next + update \data_r3__nia_ok \data_r3__nia_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DX_RT - process $group_241 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r4__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r4__msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r4__msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r4__msr_ok$next + process $group_43 + assign \data_r4__msr$next \data_r4__msr + assign \data_r4__msr_ok$next \data_r4__msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r4__msr_ok$next \data_r4__msr$next } { \msr_ok \alu_trap0_msr } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r4__msr_ok$next \data_r4__msr$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r4__msr_ok$next 1'0 + end sync init + update \data_r4__msr 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r4__msr_ok 1'0 + sync posedge \coresync_clk + update \data_r4__msr \data_r4__msr$next + update \data_r4__msr_ok \data_r4__msr_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DX_XO - process $group_242 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $71 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 12 \DQ_DQ - process $group_243 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast1_ok + connect \B \cu_busy_o + connect \Y $73 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \DQ_PT - process $group_244 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast2_ok + connect \B \cu_busy_o + connect \Y $75 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DQ_RA - process $group_245 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nia_ok + connect \B \cu_busy_o + connect \Y $77 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DQ_RTp - process $group_246 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_ok + connect \B \cu_busy_o + connect \Y $79 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \DQ_SX - process $group_247 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } + process $group_45 + assign \cu_wrmask_o 5'00000 + assign \cu_wrmask_o { $79 $77 $75 $73 $71 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DQ_S - process $group_248 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $82 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $81 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \DQ_SX_S - process $group_249 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_46 + assign \alu_trap0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_ra $81 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \DQ_TX - process $group_250 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } + process $group_47 + assign \src_r0$next \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [0] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r0$next \src1_i + end sync init + update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r0 \src_r0$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DQ_T - process $group_251 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $84 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $83 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \DQ_TX_T - process $group_252 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_48 + assign \alu_trap0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_rb $83 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \DQ_XO - process $group_253 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + process $group_49 + assign \src_r1$next \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [1] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r1$next \src2_i + end sync init + update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r1 \src_r1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 14 \DS_DS - process $group_254 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $86 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $85 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DS_FRSp - process $group_255 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_50 + assign \alu_trap0_fast1$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_fast1$1 $85 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DS_FRTp - process $group_256 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_51 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r2$next \src3_i + end sync init + update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r2 \src_r2$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DS_RA - process $group_257 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $88 + parameter \WIDTH 64 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $87 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DS_RS - process $group_258 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_52 + assign \alu_trap0_fast2$2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_fast2$2 $87 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DS_RSp - process $group_259 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_53 + assign \src_r3$next \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [3] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r3$next \src4_i + end sync init + update \src_r3 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r3 \src_r3$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DS_RT - process $group_260 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_54 + assign \alu_trap0_p_valid_i 1'0 + assign \alu_trap0_p_valid_i \alui_l_q_alui sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DS_VRS - process $group_261 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $89 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DS_VRT - process $group_262 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_55 + assign \alui_l_r_alui$next \alui_l_r_alui + assign \alui_l_r_alui$next $89 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alui_l_r_alui$next 1'1 + end sync init + update \alui_l_r_alui 1'1 + sync posedge \coresync_clk + update \alui_l_r_alui \alui_l_r_alui$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \DS_XO - process $group_263 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } + process $group_56 + assign \alui_l_s_alui 1'0 + assign \alui_l_s_alui \all_rd_pulse sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VX_EO - process $group_264 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_57 + assign \alu_trap0_n_ready_i 1'0 + assign \alu_trap0_n_ready_i \alu_l_q_alu sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \VX_PS - process $group_265 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $91 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VX_RA - process $group_266 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_58 + assign \alu_l_r_alu$next \alu_l_r_alu + assign \alu_l_r_alu$next $91 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_l_r_alu$next 1'1 + end sync init + update \alu_l_r_alu 1'1 + sync posedge \coresync_clk + update \alu_l_r_alu \alu_l_r_alu$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VX_RT - process $group_267 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + process $group_59 + assign \alu_l_s_alu 1'0 + assign \alu_l_s_alu \all_rd_pulse sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VX_SIM - process $group_268 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_60 + assign \cu_busy_o 1'0 + assign \cu_busy_o \opc_l_q_opc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VX_UIM - process $group_269 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $93 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \VX_UIM_1 - process $group_270 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $93 + connect \B { 1'1 1'1 1'1 1'1 } + connect \Y $95 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \VX_UIM_2 - process $group_271 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rdmaskn_i + connect \Y $97 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \VX_UIM_3 - process $group_272 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $95 + connect \B $97 + connect \Y $99 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VX_VRA - process $group_273 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_61 + assign \cu_rd__rel_o 4'0000 + assign \cu_rd__rel_o $99 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VX_VRB - process $group_274 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire width 1 \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $101 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VX_VRT - process $group_275 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $103 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 \VX_XO - process $group_276 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $105 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 11 \VX_XO_1 - process $group_277 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $107 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 8 \XFL_FLM - process $group_278 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $109 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XFL_FRB - process $group_279 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 5 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B { $101 $103 $105 $107 $109 } + connect \Y $111 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XFL_L - process $group_280 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 5 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $111 + connect \B \cu_wrmask_o + connect \Y $113 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XFL_Rc - process $group_281 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } + process $group_62 + assign \cu_wr__rel_o 5'00000 + assign \cu_wr__rel_o $113 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XFL_W - process $group_282 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $115 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 \XFL_XO - process $group_283 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + process $group_63 + assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $115 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z23_FRA - process $group_284 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $117 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z23_FRAp - process $group_285 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_64 + assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $117 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest2_o { \data_r1__fast1_ok \data_r1__fast1 } [63:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z23_FRB - process $group_286 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $119 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z23_FRBp - process $group_287 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_65 + assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $119 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest3_o { \data_r2__fast2_ok \data_r2__fast2 } [63:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z23_FRT - process $group_288 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $121 + end + process $group_66 + assign \dest4_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $121 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest4_o { \data_r3__nia_ok \data_r3__nia } [63:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z23_FRTp - process $group_289 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [4] + connect \B \cu_busy_o + connect \Y $123 + end + process $group_67 + assign \dest5_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $123 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest5_o { \data_r4__msr_ok \data_r4__msr } [63:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \Z23_R - process $group_290 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.p" +module \p$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \Z23_Rc - process $group_291 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.n" +module \n$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \Z23_RMC - process $group_292 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.p" +module \p$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \Z23_TE - process $group_293 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.n" +module \n$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 8 \Z23_XO - process $group_294 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.input" +module \input$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 21 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 22 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 23 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 24 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 25 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 26 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 31 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 32 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 36 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 38 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 39 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 40 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + process $group_0 + assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \a \ra sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \MDS_IB - process $group_295 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + process $group_1 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \a sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \MDS_IS - process $group_296 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + wire width 64 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + cell $not $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rb + connect \Y $22 + end + process $group_2 + assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" + switch { \logical_op__invert_in } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" + case 1'1 + assign \b $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:44" + case + assign \b \rb + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \MDS_mb - process $group_297 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + process $group_3 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \b sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \MDS_me - process $group_298 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + process $group_4 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \MDS_RA - process $group_299 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + process $group_5 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \MDS_RB - process $group_300 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" +module \bpermd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" + wire width 64 input 0 \rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" + wire width 64 input 1 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" + wire width 64 output 2 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_0 + process $group_0 + assign \rb64_0 1'0 + assign \rb64_0 \rb [63] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \MDS_Rc - process $group_301 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_1 + process $group_1 + assign \rb64_1 1'0 + assign \rb64_1 \rb [62] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \MDS_RS - process $group_302 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_2 + process $group_2 + assign \rb64_2 1'0 + assign \rb64_2 \rb [61] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \MDS_XBI - process $group_303 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_3 + process $group_3 + assign \rb64_3 1'0 + assign \rb64_3 \rb [60] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \MDS_XBI_1 - process $group_304 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_4 + process $group_4 + assign \rb64_4 1'0 + assign \rb64_4 \rb [59] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \MDS_XO - process $group_305 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_5 + process $group_5 + assign \rb64_5 1'0 + assign \rb64_5 \rb [58] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 7 \SC_LEV - process $group_306 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_6 + process $group_6 + assign \rb64_6 1'0 + assign \rb64_6 \rb [57] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \SC_XO - process $group_307 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_7 + process $group_7 + assign \rb64_7 1'0 + assign \rb64_7 \rb [56] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \SC_XO_1 - process $group_308 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_8 + process $group_8 + assign \rb64_8 1'0 + assign \rb64_8 \rb [55] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \M_MB - process $group_309 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_9 + process $group_9 + assign \rb64_9 1'0 + assign \rb64_9 \rb [54] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \M_ME - process $group_310 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_10 + process $group_10 + assign \rb64_10 1'0 + assign \rb64_10 \rb [53] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \M_RA - process $group_311 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_11 + process $group_11 + assign \rb64_11 1'0 + assign \rb64_11 \rb [52] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \M_RB - process $group_312 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_12 + process $group_12 + assign \rb64_12 1'0 + assign \rb64_12 \rb [51] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \M_Rc - process $group_313 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_13 + process $group_13 + assign \rb64_13 1'0 + assign \rb64_13 \rb [50] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \M_RS - process $group_314 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_14 + process $group_14 + assign \rb64_14 1'0 + assign \rb64_14 \rb [49] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \M_SH - process $group_315 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_15 + process $group_15 + assign \rb64_15 1'0 + assign \rb64_15 \rb [48] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \MD_mb - process $group_316 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_16 + process $group_16 + assign \rb64_16 1'0 + assign \rb64_16 \rb [47] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \MD_me - process $group_317 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_17 + process $group_17 + assign \rb64_17 1'0 + assign \rb64_17 \rb [46] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \MD_RA - process $group_318 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_18 + process $group_18 + assign \rb64_18 1'0 + assign \rb64_18 \rb [45] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \MD_Rc - process $group_319 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_19 + process $group_19 + assign \rb64_19 1'0 + assign \rb64_19 \rb [44] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \MD_RS - process $group_320 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_20 + process $group_20 + assign \rb64_20 1'0 + assign \rb64_20 \rb [43] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \MD_sh - process $group_321 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_21 + process $group_21 + assign \rb64_21 1'0 + assign \rb64_21 \rb [42] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 \MD_XO - process $group_322 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_22 + process $group_22 + assign \rb64_22 1'0 + assign \rb64_22 \rb [41] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \all_OPCD - process $group_323 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_23 + process $group_23 + assign \rb64_23 1'0 + assign \rb64_23 \rb [40] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \all_PO - process $group_324 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_24 + process $group_24 + assign \rb64_24 1'0 + assign \rb64_24 \rb [39] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XO_OE - process $group_325 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_25 + process $group_25 + assign \rb64_25 1'0 + assign \rb64_25 \rb [38] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XO_RA - process $group_326 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_26 + process $group_26 + assign \rb64_26 1'0 + assign \rb64_26 \rb [37] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XO_RB - process $group_327 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_27 + process $group_27 + assign \rb64_27 1'0 + assign \rb64_27 \rb [36] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XO_Rc - process $group_328 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_28 + process $group_28 + assign \rb64_28 1'0 + assign \rb64_28 \rb [35] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XO_RT - process $group_329 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_29 + process $group_29 + assign \rb64_29 1'0 + assign \rb64_29 \rb [34] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 9 \XO_XO - process $group_330 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_30 + process $group_30 + assign \rb64_30 1'0 + assign \rb64_30 \rb [33] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DQE_RA - process $group_331 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_31 + process $group_31 + assign \rb64_31 1'0 + assign \rb64_31 \rb [32] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \DQE_RT - process $group_332 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_32 + process $group_32 + assign \rb64_32 1'0 + assign \rb64_32 \rb [31] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 2 \DQE_XO - process $group_333 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_33 + process $group_33 + assign \rb64_33 1'0 + assign \rb64_33 \rb [30] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \TX_RA - process $group_334 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_34 + process $group_34 + assign \rb64_34 1'0 + assign \rb64_34 \rb [29] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \TX_UI - process $group_335 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_35 + process $group_35 + assign \rb64_35 1'0 + assign \rb64_35 \rb [28] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \TX_XBI - process $group_336 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_36 + process $group_36 + assign \rb64_36 1'0 + assign \rb64_36 \rb [27] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \TX_XO - process $group_337 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_37 + process $group_37 + assign \rb64_37 1'0 + assign \rb64_37 \rb [26] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VA_RA - process $group_338 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_38 + process $group_38 + assign \rb64_38 1'0 + assign \rb64_38 \rb [25] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VA_RB - process $group_339 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_39 + process $group_39 + assign \rb64_39 1'0 + assign \rb64_39 \rb [24] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VA_RC - process $group_340 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_40 + process $group_40 + assign \rb64_40 1'0 + assign \rb64_40 \rb [23] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VA_RT - process $group_341 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_41 + process $group_41 + assign \rb64_41 1'0 + assign \rb64_41 \rb [22] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 4 \VA_SHB - process $group_342 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_42 + process $group_42 + assign \rb64_42 1'0 + assign \rb64_42 \rb [21] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VA_VRA - process $group_343 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_43 + process $group_43 + assign \rb64_43 1'0 + assign \rb64_43 \rb [20] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VA_VRB - process $group_344 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_44 + process $group_44 + assign \rb64_44 1'0 + assign \rb64_44 \rb [19] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VA_VRC - process $group_345 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_45 + process $group_45 + assign \rb64_45 1'0 + assign \rb64_45 \rb [18] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VA_VRT - process $group_346 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_46 + process $group_46 + assign \rb64_46 1'0 + assign \rb64_46 \rb [17] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \VA_XO - process $group_347 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_47 + process $group_47 + assign \rb64_47 1'0 + assign \rb64_47 \rb [16] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XS_RA - process $group_348 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_48 + process $group_48 + assign \rb64_48 1'0 + assign \rb64_48 \rb [15] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \XS_Rc - process $group_349 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_49 + process $group_49 + assign \rb64_49 1'0 + assign \rb64_49 \rb [14] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \XS_RS - process $group_350 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_50 + process $group_50 + assign \rb64_50 1'0 + assign \rb64_50 \rb [13] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 6 \XS_sh - process $group_351 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_51 + process $group_51 + assign \rb64_51 1'0 + assign \rb64_51 \rb [12] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 9 \XS_XO - process $group_352 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_52 + process $group_52 + assign \rb64_52 1'0 + assign \rb64_52 \rb [11] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 1 \VC_Rc - process $group_353 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_53 + process $group_53 + assign \rb64_53 1'0 + assign \rb64_53 \rb [10] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VC_VRA - process $group_354 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_54 + process $group_54 + assign \rb64_54 1'0 + assign \rb64_54 \rb [9] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VC_VRB - process $group_355 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_55 + process $group_55 + assign \rb64_55 1'0 + assign \rb64_55 \rb [8] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 \VC_VRT - process $group_356 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_56 + process $group_56 + assign \rb64_56 1'0 + assign \rb64_56 \rb [7] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 \VC_XO - process $group_357 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_57 + process $group_57 + assign \rb64_57 1'0 + assign \rb64_57 \rb [6] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_a.sprmap" -module \sprmap - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" - wire width 10 input 0 \spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 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attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 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\enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" - wire width 10 output 1 \spr_o - process $group_0 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61" - switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000000001 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000000011 - assign \spr_o 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000001000 - assign \spr_o 10'0000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000001001 - assign \spr_o 10'0000000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000001101 - assign \spr_o 10'0000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000010001 - assign \spr_o 10'0000000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000010010 - assign \spr_o 10'0000000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000010011 - assign \spr_o 10'0000000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000010110 - assign \spr_o 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000011010 - assign \spr_o 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000011011 - assign \spr_o 10'0000001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000011100 - assign \spr_o 10'0000001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000011101 - assign \spr_o 10'0000001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000110000 - assign \spr_o 10'0000001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000111101 - assign \spr_o 10'0000001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010000000 - assign \spr_o 10'0000001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010000001 - assign \spr_o 10'0000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010000010 - assign \spr_o 10'0000010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010000011 - assign \spr_o 10'0000010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010001000 - assign \spr_o 10'0000010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010010000 - assign \spr_o 10'0000010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010011000 - assign \spr_o 10'0000010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010011001 - assign \spr_o 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010011101 - assign \spr_o 10'0000010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010011110 - assign \spr_o 10'0000011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010011111 - assign \spr_o 10'0000011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010110000 - assign \spr_o 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010110100 - assign \spr_o 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010111010 - assign \spr_o 10'0000011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010111011 - assign \spr_o 10'0000011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010111100 - assign \spr_o 10'0000011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010111110 - assign \spr_o 10'0000011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100000000 - assign \spr_o 10'0000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100000011 - assign \spr_o 10'0000100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100001100 - assign \spr_o 10'0000100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100001101 - assign \spr_o 10'0000100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100010000 - assign \spr_o 10'0000100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100010001 - assign \spr_o 10'0000100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100010010 - assign \spr_o 10'0000100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100010011 - assign \spr_o 10'0000100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100011011 - assign \spr_o 10'0000101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100011100 - assign \spr_o 10'0000101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100011101 - assign \spr_o 10'0000101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100011110 - assign \spr_o 10'0000101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100011111 - assign \spr_o 10'0000101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110000 - assign \spr_o 10'0000101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110001 - assign \spr_o 10'0000101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110010 - assign \spr_o 10'0000101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110011 - assign \spr_o 10'0000110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110100 - assign \spr_o 10'0000110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110101 - assign \spr_o 10'0000110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110110 - assign \spr_o 10'0000110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100111001 - assign \spr_o 10'0000110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100111010 - assign \spr_o 10'0000110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100111011 - assign \spr_o 10'0000110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100111110 - assign \spr_o 10'0000110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100111111 - assign \spr_o 10'0000111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0101010000 - assign \spr_o 10'0000111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0101010001 - assign \spr_o 10'0000111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0101010010 - assign \spr_o 10'0000111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0101010011 - assign \spr_o 10'0000111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0101011101 - assign \spr_o 10'0000111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0110111110 - assign \spr_o 10'0000111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0111010000 - assign \spr_o 10'0000111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000000 - assign \spr_o 10'0001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000001 - assign \spr_o 10'0001000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000010 - assign \spr_o 10'0001000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000011 - assign \spr_o 10'0001000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000100 - assign \spr_o 10'0001000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000101 - assign \spr_o 10'0001000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000110 - assign \spr_o 10'0001000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000111 - assign \spr_o 10'0001000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100001000 - assign \spr_o 10'0001001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100001011 - assign \spr_o 10'0001001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100001100 - assign \spr_o 10'0001001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100001101 - assign \spr_o 10'0001001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100001110 - assign \spr_o 10'0001001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010000 - assign \spr_o 10'0001001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010001 - assign \spr_o 10'0001001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010010 - assign \spr_o 10'0001001111 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_60 + process $group_60 + assign \rb64_60 1'0 + assign \rb64_60 \rb [3] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_61 + process $group_61 + assign \rb64_61 1'0 + assign \rb64_61 \rb [2] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_62 + process $group_62 + assign \rb64_62 1'0 + assign \rb64_62 \rb [1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire width 1 \rb64_63 + process $group_63 + assign \rb64_63 1'0 + assign \rb64_63 \rb [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_0 + process $group_64 + assign \idx_0 8'00000000 + assign \idx_0 \rs [7:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" + wire width 64 \perm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" - cell $eq $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'001 + connect \A \idx_0 + connect \B 7'1000000 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" - cell $eq $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 + connect \A \idx_1 + connect \B 7'1000000 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - cell $ne $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 + connect \A \idx_2 + connect \B 7'1000000 connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - cell $and $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 + connect \A \idx_3 + connect \B 7'1000000 connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - cell $or $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $10 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A $1 - connect \B $7 + connect \A \idx_4 + connect \B 7'1000000 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $eq $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'100 + connect \A \idx_5 + connect \B 7'1000000 connect \Y $11 end - process $group_1 - assign \reg_a 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - case 1'1 - assign \reg_a \ra - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch { $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - case 1'1 - assign \reg_a \RS - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" - cell $eq $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'001 + connect \A \idx_6 + connect \B 7'1000000 connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" - cell $eq $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $16 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 + connect \A \idx_7 + connect \B 7'1000000 connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - cell $ne $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $15 - connect \B $17 - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - cell $or $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $13 - connect \B $19 - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - cell $eq $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'100 - connect \Y $23 - end - process $group_2 - assign \reg_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - switch { $21 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - case 1'1 - assign \reg_a_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - switch { $23 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" - case 1'1 - assign \reg_a_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - cell $eq $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - cell $eq $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \reg_a - connect \B 5'00000 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - cell $and $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $25 - connect \B $27 - connect \Y $29 - end - process $group_3 - assign \immz_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + process $group_65 + assign \perm 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" case 1'1 - assign \immz_out 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $not $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $not $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [5] - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $and $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \B $33 - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" - wire width 10 \spr - process $group_4 - assign \fast_a 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - switch { $31 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - case 1'1 - assign \fast_a 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - switch { $35 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - case 1'1 - assign \fast_a 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" - case 10'0000001001 - assign \fast_a 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" - case 10'0000001000 - assign \fast_a 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - case 10'1100101111 - assign \fast_a 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" - case 10'0000011010 - assign \fast_a 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" - case 10'0000011011 - assign \fast_a 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_0 + case 8'00000000 + assign \perm [0] \rb64_0 + case 8'00000001 + assign \perm [0] \rb64_1 + case 8'00000010 + assign \perm [0] \rb64_2 + case 8'00000011 + assign \perm [0] \rb64_3 + case 8'00000100 + assign \perm [0] \rb64_4 + case 8'00000101 + assign \perm [0] \rb64_5 + case 8'00000110 + assign \perm [0] \rb64_6 + case 8'00000111 + assign \perm [0] \rb64_7 + case 8'00001000 + assign \perm [0] \rb64_8 + case 8'00001001 + assign \perm [0] \rb64_9 + case 8'00001010 + assign \perm [0] \rb64_10 + case 8'00001011 + assign \perm [0] \rb64_11 + case 8'00001100 + assign \perm [0] \rb64_12 + case 8'00001101 + assign \perm [0] \rb64_13 + case 8'00001110 + assign \perm [0] \rb64_14 + case 8'00001111 + assign \perm [0] \rb64_15 + case 8'00010000 + assign \perm [0] \rb64_16 + case 8'00010001 + assign \perm [0] \rb64_17 + case 8'00010010 + assign \perm [0] \rb64_18 + case 8'00010011 + assign \perm [0] \rb64_19 + case 8'00010100 + assign \perm [0] \rb64_20 + case 8'00010101 + assign \perm [0] \rb64_21 + case 8'00010110 + assign \perm [0] \rb64_22 + case 8'00010111 + assign \perm [0] \rb64_23 + case 8'00011000 + assign \perm [0] \rb64_24 + case 8'00011001 + assign \perm [0] \rb64_25 + case 8'00011010 + assign \perm [0] \rb64_26 + case 8'00011011 + assign \perm [0] \rb64_27 + case 8'00011100 + assign \perm [0] \rb64_28 + case 8'00011101 + assign \perm [0] \rb64_29 + case 8'00011110 + assign \perm [0] \rb64_30 + case 8'00011111 + assign \perm [0] \rb64_31 + case 8'00100000 + assign \perm [0] \rb64_32 + case 8'00100001 + assign \perm [0] \rb64_33 + case 8'00100010 + assign \perm [0] \rb64_34 + case 8'00100011 + assign \perm [0] \rb64_35 + case 8'00100100 + assign \perm [0] \rb64_36 + case 8'00100101 + assign \perm [0] \rb64_37 + case 8'00100110 + assign \perm [0] \rb64_38 + case 8'00100111 + assign \perm [0] \rb64_39 + case 8'00101000 + assign \perm [0] \rb64_40 + case 8'00101001 + assign \perm [0] \rb64_41 + case 8'00101010 + assign \perm [0] \rb64_42 + case 8'00101011 + assign \perm [0] \rb64_43 + case 8'00101100 + assign \perm [0] \rb64_44 + case 8'00101101 + assign \perm [0] \rb64_45 + case 8'00101110 + assign \perm [0] \rb64_46 + case 8'00101111 + assign \perm [0] \rb64_47 + case 8'00110000 + assign \perm [0] \rb64_48 + case 8'00110001 + assign \perm [0] \rb64_49 + case 8'00110010 + assign \perm [0] \rb64_50 + case 8'00110011 + assign \perm [0] \rb64_51 + case 8'00110100 + assign \perm [0] \rb64_52 + case 8'00110101 + assign \perm [0] \rb64_53 + case 8'00110110 + assign \perm [0] \rb64_54 + case 8'00110111 + assign \perm [0] \rb64_55 + case 8'00111000 + assign \perm [0] \rb64_56 + case 8'00111001 + assign \perm [0] \rb64_57 + case 8'00111010 + assign \perm [0] \rb64_58 + case 8'00111011 + assign \perm [0] \rb64_59 + case 8'00111100 + assign \perm [0] \rb64_60 + case 8'00111101 + assign \perm [0] \rb64_61 + case 8'00111110 + assign \perm [0] \rb64_62 + case 8'-------- + assign \perm [0] \rb64_63 end end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $not $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [5] - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - cell $and $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \B $39 - connect \Y $41 - end - process $group_5 - assign \fast_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - switch { $37 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - case 1'1 - assign \fast_a_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - switch { $41 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" - case 1'1 - assign \fast_a_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" - case 10'0000001001 - assign \fast_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" - case 10'0000001000 - assign \fast_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - case 10'1100101111 - assign \fast_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" - case 10'0000011010 - assign \fast_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" - case 10'0000011011 - assign \fast_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_1 + case 8'00000000 + assign \perm [1] \rb64_0 + case 8'00000001 + assign \perm [1] \rb64_1 + case 8'00000010 + assign \perm [1] \rb64_2 + case 8'00000011 + assign \perm [1] \rb64_3 + case 8'00000100 + assign \perm [1] \rb64_4 + case 8'00000101 + assign \perm [1] \rb64_5 + case 8'00000110 + assign \perm [1] \rb64_6 + case 8'00000111 + assign \perm [1] \rb64_7 + case 8'00001000 + assign \perm [1] \rb64_8 + case 8'00001001 + assign \perm [1] \rb64_9 + case 8'00001010 + assign \perm [1] \rb64_10 + case 8'00001011 + assign \perm [1] \rb64_11 + case 8'00001100 + assign \perm [1] \rb64_12 + case 8'00001101 + assign \perm [1] \rb64_13 + case 8'00001110 + assign \perm [1] \rb64_14 + case 8'00001111 + assign \perm [1] \rb64_15 + case 8'00010000 + assign \perm [1] \rb64_16 + case 8'00010001 + assign \perm [1] \rb64_17 + case 8'00010010 + assign \perm [1] \rb64_18 + case 8'00010011 + assign \perm [1] \rb64_19 + case 8'00010100 + assign \perm [1] \rb64_20 + case 8'00010101 + assign \perm [1] \rb64_21 + case 8'00010110 + assign \perm [1] \rb64_22 + case 8'00010111 + assign \perm [1] \rb64_23 + case 8'00011000 + assign \perm [1] \rb64_24 + case 8'00011001 + assign \perm [1] \rb64_25 + case 8'00011010 + assign \perm [1] \rb64_26 + case 8'00011011 + assign \perm [1] \rb64_27 + case 8'00011100 + assign \perm [1] \rb64_28 + case 8'00011101 + assign \perm [1] \rb64_29 + case 8'00011110 + assign \perm [1] \rb64_30 + case 8'00011111 + assign \perm [1] \rb64_31 + case 8'00100000 + assign \perm [1] \rb64_32 + case 8'00100001 + assign \perm [1] \rb64_33 + case 8'00100010 + assign \perm [1] \rb64_34 + case 8'00100011 + assign \perm [1] \rb64_35 + case 8'00100100 + assign \perm [1] \rb64_36 + case 8'00100101 + assign \perm [1] \rb64_37 + case 8'00100110 + assign \perm [1] \rb64_38 + case 8'00100111 + assign \perm [1] \rb64_39 + case 8'00101000 + assign \perm [1] \rb64_40 + case 8'00101001 + assign \perm [1] \rb64_41 + case 8'00101010 + assign \perm [1] \rb64_42 + case 8'00101011 + assign \perm [1] \rb64_43 + case 8'00101100 + assign \perm [1] \rb64_44 + case 8'00101101 + assign \perm [1] \rb64_45 + case 8'00101110 + assign \perm [1] \rb64_46 + case 8'00101111 + assign \perm [1] \rb64_47 + case 8'00110000 + assign \perm [1] \rb64_48 + case 8'00110001 + assign \perm [1] \rb64_49 + case 8'00110010 + assign \perm [1] \rb64_50 + case 8'00110011 + assign \perm [1] \rb64_51 + case 8'00110100 + assign \perm [1] \rb64_52 + case 8'00110101 + assign \perm [1] \rb64_53 + case 8'00110110 + assign \perm [1] \rb64_54 + case 8'00110111 + assign \perm [1] \rb64_55 + case 8'00111000 + assign \perm [1] \rb64_56 + case 8'00111001 + assign \perm [1] \rb64_57 + case 8'00111010 + assign \perm [1] \rb64_58 + case 8'00111011 + assign \perm [1] \rb64_59 + case 8'00111100 + assign \perm [1] \rb64_60 + case 8'00111101 + assign \perm [1] \rb64_61 + case 8'00111110 + assign \perm [1] \rb64_62 + case 8'-------- + assign \perm [1] \rb64_63 end end - sync init - end - process $group_6 - assign \spr 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - assign \spr { \SPR [4:0] \SPR [9:5] } - end - sync init - end - process $group_7 - assign \sprmap_spr_i 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - case - assign \sprmap_spr_i \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_2 + case 8'00000000 + assign \perm [2] \rb64_0 + case 8'00000001 + assign \perm [2] \rb64_1 + case 8'00000010 + assign \perm [2] \rb64_2 + case 8'00000011 + assign \perm [2] \rb64_3 + case 8'00000100 + assign \perm [2] \rb64_4 + case 8'00000101 + assign \perm [2] \rb64_5 + case 8'00000110 + assign \perm [2] \rb64_6 + case 8'00000111 + assign \perm [2] \rb64_7 + case 8'00001000 + assign \perm [2] \rb64_8 + case 8'00001001 + assign \perm [2] \rb64_9 + case 8'00001010 + assign \perm [2] \rb64_10 + case 8'00001011 + assign \perm [2] \rb64_11 + case 8'00001100 + assign \perm [2] \rb64_12 + case 8'00001101 + assign \perm [2] \rb64_13 + case 8'00001110 + assign \perm [2] \rb64_14 + case 8'00001111 + assign \perm [2] \rb64_15 + case 8'00010000 + assign \perm [2] \rb64_16 + case 8'00010001 + assign \perm [2] \rb64_17 + case 8'00010010 + assign \perm [2] \rb64_18 + case 8'00010011 + assign \perm [2] \rb64_19 + case 8'00010100 + assign \perm [2] \rb64_20 + case 8'00010101 + assign \perm [2] \rb64_21 + case 8'00010110 + assign \perm [2] \rb64_22 + case 8'00010111 + assign \perm [2] \rb64_23 + case 8'00011000 + assign \perm [2] \rb64_24 + case 8'00011001 + assign \perm [2] \rb64_25 + case 8'00011010 + assign \perm [2] \rb64_26 + case 8'00011011 + assign \perm [2] \rb64_27 + case 8'00011100 + assign \perm [2] \rb64_28 + case 8'00011101 + assign \perm [2] \rb64_29 + case 8'00011110 + assign \perm [2] \rb64_30 + case 8'00011111 + assign \perm [2] \rb64_31 + case 8'00100000 + assign \perm [2] \rb64_32 + case 8'00100001 + assign \perm [2] \rb64_33 + case 8'00100010 + assign \perm [2] \rb64_34 + case 8'00100011 + assign \perm [2] \rb64_35 + case 8'00100100 + assign \perm [2] \rb64_36 + case 8'00100101 + assign \perm [2] \rb64_37 + case 8'00100110 + assign \perm [2] \rb64_38 + case 8'00100111 + assign \perm [2] \rb64_39 + case 8'00101000 + assign \perm [2] \rb64_40 + case 8'00101001 + assign \perm [2] \rb64_41 + case 8'00101010 + assign \perm [2] \rb64_42 + case 8'00101011 + assign \perm [2] \rb64_43 + case 8'00101100 + assign \perm [2] \rb64_44 + case 8'00101101 + assign \perm [2] \rb64_45 + case 8'00101110 + assign \perm [2] \rb64_46 + case 8'00101111 + assign \perm [2] \rb64_47 + case 8'00110000 + assign \perm [2] \rb64_48 + case 8'00110001 + assign \perm [2] \rb64_49 + case 8'00110010 + assign \perm [2] \rb64_50 + case 8'00110011 + assign \perm [2] \rb64_51 + case 8'00110100 + assign \perm [2] \rb64_52 + case 8'00110101 + assign \perm [2] \rb64_53 + case 8'00110110 + assign \perm [2] \rb64_54 + case 8'00110111 + assign \perm [2] \rb64_55 + case 8'00111000 + assign \perm [2] \rb64_56 + case 8'00111001 + assign \perm [2] \rb64_57 + case 8'00111010 + assign \perm [2] \rb64_58 + case 8'00111011 + assign \perm [2] \rb64_59 + case 8'00111100 + assign \perm [2] \rb64_60 + case 8'00111101 + assign \perm [2] \rb64_61 + case 8'00111110 + assign \perm [2] \rb64_62 + case 8'-------- + assign \perm [2] \rb64_63 end end - sync init - end - process $group_8 - assign \spr_a 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - case - assign \spr_a \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_3 + case 8'00000000 + assign \perm [3] \rb64_0 + case 8'00000001 + assign \perm [3] \rb64_1 + case 8'00000010 + assign \perm [3] \rb64_2 + case 8'00000011 + assign \perm [3] \rb64_3 + case 8'00000100 + assign \perm [3] \rb64_4 + case 8'00000101 + assign \perm [3] \rb64_5 + case 8'00000110 + assign \perm [3] \rb64_6 + case 8'00000111 + assign \perm [3] \rb64_7 + case 8'00001000 + assign \perm [3] \rb64_8 + case 8'00001001 + assign \perm [3] \rb64_9 + case 8'00001010 + assign \perm [3] \rb64_10 + case 8'00001011 + assign \perm [3] \rb64_11 + case 8'00001100 + assign \perm [3] \rb64_12 + case 8'00001101 + assign \perm [3] \rb64_13 + case 8'00001110 + assign \perm [3] \rb64_14 + case 8'00001111 + assign \perm [3] \rb64_15 + case 8'00010000 + assign \perm [3] \rb64_16 + case 8'00010001 + assign \perm [3] \rb64_17 + case 8'00010010 + assign \perm [3] \rb64_18 + case 8'00010011 + assign \perm [3] \rb64_19 + case 8'00010100 + assign \perm [3] \rb64_20 + case 8'00010101 + assign \perm [3] \rb64_21 + case 8'00010110 + assign \perm [3] \rb64_22 + case 8'00010111 + assign \perm [3] \rb64_23 + case 8'00011000 + assign \perm [3] \rb64_24 + case 8'00011001 + assign \perm [3] \rb64_25 + case 8'00011010 + assign \perm [3] \rb64_26 + case 8'00011011 + assign \perm [3] \rb64_27 + case 8'00011100 + assign \perm [3] \rb64_28 + case 8'00011101 + assign \perm [3] \rb64_29 + case 8'00011110 + assign \perm [3] \rb64_30 + case 8'00011111 + assign \perm [3] \rb64_31 + case 8'00100000 + assign \perm [3] \rb64_32 + case 8'00100001 + assign \perm [3] \rb64_33 + case 8'00100010 + assign \perm [3] \rb64_34 + case 8'00100011 + assign \perm [3] \rb64_35 + case 8'00100100 + assign \perm [3] \rb64_36 + case 8'00100101 + assign \perm [3] \rb64_37 + case 8'00100110 + assign \perm [3] \rb64_38 + case 8'00100111 + assign \perm [3] \rb64_39 + case 8'00101000 + assign \perm [3] \rb64_40 + case 8'00101001 + assign \perm [3] \rb64_41 + case 8'00101010 + assign \perm [3] \rb64_42 + case 8'00101011 + assign \perm [3] \rb64_43 + case 8'00101100 + assign \perm [3] \rb64_44 + case 8'00101101 + assign \perm [3] \rb64_45 + case 8'00101110 + assign \perm [3] \rb64_46 + case 8'00101111 + assign \perm [3] \rb64_47 + case 8'00110000 + assign \perm [3] \rb64_48 + case 8'00110001 + assign \perm [3] \rb64_49 + case 8'00110010 + assign \perm [3] \rb64_50 + case 8'00110011 + assign \perm [3] \rb64_51 + case 8'00110100 + assign \perm [3] \rb64_52 + case 8'00110101 + assign \perm [3] \rb64_53 + case 8'00110110 + assign \perm [3] \rb64_54 + case 8'00110111 + assign \perm [3] \rb64_55 + case 8'00111000 + assign \perm [3] \rb64_56 + case 8'00111001 + assign \perm [3] \rb64_57 + case 8'00111010 + assign \perm [3] \rb64_58 + case 8'00111011 + assign \perm [3] \rb64_59 + case 8'00111100 + assign \perm [3] \rb64_60 + case 8'00111101 + assign \perm [3] \rb64_61 + case 8'00111110 + assign \perm [3] \rb64_62 + case 8'-------- + assign \perm [3] \rb64_63 end end - sync init - end - process $group_9 - assign \spr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - case - assign \spr_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_4 + case 8'00000000 + assign \perm [4] \rb64_0 + case 8'00000001 + assign \perm [4] \rb64_1 + case 8'00000010 + assign \perm [4] \rb64_2 + case 8'00000011 + assign \perm [4] \rb64_3 + case 8'00000100 + assign \perm [4] \rb64_4 + case 8'00000101 + assign \perm [4] \rb64_5 + case 8'00000110 + assign \perm [4] \rb64_6 + case 8'00000111 + assign \perm [4] \rb64_7 + case 8'00001000 + assign \perm [4] \rb64_8 + case 8'00001001 + assign \perm [4] \rb64_9 + case 8'00001010 + assign \perm [4] \rb64_10 + case 8'00001011 + assign \perm [4] \rb64_11 + case 8'00001100 + assign \perm [4] \rb64_12 + case 8'00001101 + assign \perm [4] \rb64_13 + case 8'00001110 + assign \perm [4] \rb64_14 + case 8'00001111 + assign \perm [4] \rb64_15 + case 8'00010000 + assign \perm [4] \rb64_16 + case 8'00010001 + assign \perm [4] \rb64_17 + case 8'00010010 + assign \perm [4] \rb64_18 + case 8'00010011 + assign \perm [4] \rb64_19 + case 8'00010100 + assign \perm [4] \rb64_20 + case 8'00010101 + assign \perm [4] \rb64_21 + case 8'00010110 + assign \perm [4] \rb64_22 + case 8'00010111 + assign \perm [4] \rb64_23 + case 8'00011000 + assign \perm [4] \rb64_24 + case 8'00011001 + assign \perm [4] \rb64_25 + case 8'00011010 + assign \perm [4] \rb64_26 + case 8'00011011 + assign \perm [4] \rb64_27 + case 8'00011100 + assign \perm [4] \rb64_28 + case 8'00011101 + assign \perm [4] \rb64_29 + case 8'00011110 + assign \perm [4] \rb64_30 + case 8'00011111 + assign \perm [4] \rb64_31 + case 8'00100000 + assign \perm [4] \rb64_32 + case 8'00100001 + assign \perm [4] \rb64_33 + case 8'00100010 + assign \perm [4] \rb64_34 + case 8'00100011 + assign \perm [4] \rb64_35 + case 8'00100100 + assign \perm [4] \rb64_36 + case 8'00100101 + assign \perm [4] \rb64_37 + case 8'00100110 + assign \perm [4] \rb64_38 + case 8'00100111 + assign \perm [4] \rb64_39 + case 8'00101000 + assign \perm [4] \rb64_40 + case 8'00101001 + assign \perm [4] \rb64_41 + case 8'00101010 + assign \perm [4] \rb64_42 + case 8'00101011 + assign \perm [4] \rb64_43 + case 8'00101100 + assign \perm [4] \rb64_44 + case 8'00101101 + assign \perm [4] \rb64_45 + case 8'00101110 + assign \perm [4] \rb64_46 + case 8'00101111 + assign \perm [4] \rb64_47 + case 8'00110000 + assign \perm [4] \rb64_48 + case 8'00110001 + assign \perm [4] \rb64_49 + case 8'00110010 + assign \perm [4] \rb64_50 + case 8'00110011 + assign \perm [4] \rb64_51 + case 8'00110100 + assign \perm [4] \rb64_52 + case 8'00110101 + assign \perm [4] \rb64_53 + case 8'00110110 + assign \perm [4] \rb64_54 + case 8'00110111 + assign \perm [4] \rb64_55 + case 8'00111000 + assign \perm [4] \rb64_56 + case 8'00111001 + assign \perm [4] \rb64_57 + case 8'00111010 + assign \perm [4] \rb64_58 + case 8'00111011 + assign \perm [4] \rb64_59 + case 8'00111100 + assign \perm [4] \rb64_60 + case 8'00111101 + assign \perm [4] \rb64_61 + case 8'00111110 + assign \perm [4] \rb64_62 + case 8'-------- + assign \perm [4] \rb64_63 end end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_b" -module \dec_b - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170" - wire width 4 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 2 \reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \reg_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 4 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 6 \fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 7 \fast_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 8 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 9 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 16 input 10 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 16 input 11 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 12 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 6 input 13 \sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 24 input 14 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 14 input 15 \BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 14 input 16 \DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 10 input 17 \XL_XO - process $group_0 - assign \reg_b 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - assign \reg_b \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - assign \reg_b \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch { $11 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_5 + case 8'00000000 + assign \perm [5] \rb64_0 + case 8'00000001 + assign \perm [5] \rb64_1 + case 8'00000010 + assign \perm [5] \rb64_2 + case 8'00000011 + assign \perm [5] \rb64_3 + case 8'00000100 + assign \perm [5] \rb64_4 + case 8'00000101 + assign \perm [5] \rb64_5 + case 8'00000110 + assign \perm [5] \rb64_6 + case 8'00000111 + assign \perm [5] \rb64_7 + case 8'00001000 + assign \perm [5] \rb64_8 + case 8'00001001 + assign \perm [5] \rb64_9 + case 8'00001010 + assign \perm [5] \rb64_10 + case 8'00001011 + assign \perm [5] \rb64_11 + case 8'00001100 + assign \perm [5] \rb64_12 + case 8'00001101 + assign \perm [5] \rb64_13 + case 8'00001110 + assign \perm [5] \rb64_14 + case 8'00001111 + assign \perm [5] \rb64_15 + case 8'00010000 + assign \perm [5] \rb64_16 + case 8'00010001 + assign \perm [5] \rb64_17 + case 8'00010010 + assign \perm [5] \rb64_18 + case 8'00010011 + assign \perm [5] \rb64_19 + case 8'00010100 + assign \perm [5] \rb64_20 + case 8'00010101 + assign \perm [5] \rb64_21 + case 8'00010110 + assign \perm [5] \rb64_22 + case 8'00010111 + assign \perm [5] \rb64_23 + case 8'00011000 + assign \perm [5] \rb64_24 + case 8'00011001 + assign \perm [5] \rb64_25 + case 8'00011010 + assign \perm [5] \rb64_26 + case 8'00011011 + assign \perm [5] \rb64_27 + case 8'00011100 + assign \perm [5] \rb64_28 + case 8'00011101 + assign \perm [5] \rb64_29 + case 8'00011110 + assign \perm [5] \rb64_30 + case 8'00011111 + assign \perm [5] \rb64_31 + case 8'00100000 + assign \perm [5] \rb64_32 + case 8'00100001 + assign \perm [5] \rb64_33 + case 8'00100010 + assign \perm [5] \rb64_34 + case 8'00100011 + assign \perm [5] \rb64_35 + case 8'00100100 + assign \perm [5] \rb64_36 + case 8'00100101 + assign \perm [5] \rb64_37 + case 8'00100110 + assign \perm [5] \rb64_38 + case 8'00100111 + assign \perm [5] \rb64_39 + case 8'00101000 + assign \perm [5] \rb64_40 + case 8'00101001 + assign \perm [5] \rb64_41 + case 8'00101010 + assign \perm [5] \rb64_42 + case 8'00101011 + assign \perm [5] \rb64_43 + case 8'00101100 + assign \perm [5] \rb64_44 + case 8'00101101 + assign \perm [5] \rb64_45 + case 8'00101110 + assign \perm [5] \rb64_46 + case 8'00101111 + assign \perm [5] \rb64_47 + case 8'00110000 + assign \perm [5] \rb64_48 + case 8'00110001 + assign \perm [5] \rb64_49 + case 8'00110010 + assign \perm [5] \rb64_50 + case 8'00110011 + assign \perm [5] \rb64_51 + case 8'00110100 + assign \perm [5] \rb64_52 + case 8'00110101 + assign \perm [5] \rb64_53 + case 8'00110110 + assign \perm [5] \rb64_54 + case 8'00110111 + assign \perm [5] \rb64_55 + case 8'00111000 + assign \perm [5] \rb64_56 + case 8'00111001 + assign \perm [5] \rb64_57 + case 8'00111010 + assign \perm [5] \rb64_58 + case 8'00111011 + assign \perm [5] \rb64_59 + case 8'00111100 + assign \perm [5] \rb64_60 + case 8'00111101 + assign \perm [5] \rb64_61 + case 8'00111110 + assign \perm [5] \rb64_62 + case 8'-------- + assign \perm [5] \rb64_63 + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_6 + case 8'00000000 + assign \perm [6] \rb64_0 + case 8'00000001 + assign \perm [6] \rb64_1 + case 8'00000010 + assign \perm [6] \rb64_2 + case 8'00000011 + assign \perm [6] \rb64_3 + case 8'00000100 + assign \perm [6] \rb64_4 + case 8'00000101 + assign \perm [6] \rb64_5 + case 8'00000110 + assign \perm [6] \rb64_6 + case 8'00000111 + assign \perm [6] \rb64_7 + case 8'00001000 + assign \perm [6] \rb64_8 + case 8'00001001 + assign \perm [6] \rb64_9 + case 8'00001010 + assign \perm [6] \rb64_10 + case 8'00001011 + assign \perm [6] \rb64_11 + case 8'00001100 + assign \perm [6] \rb64_12 + case 8'00001101 + assign \perm [6] \rb64_13 + case 8'00001110 + assign \perm [6] \rb64_14 + case 8'00001111 + assign \perm [6] \rb64_15 + case 8'00010000 + assign \perm [6] \rb64_16 + case 8'00010001 + assign \perm [6] \rb64_17 + case 8'00010010 + assign \perm [6] \rb64_18 + case 8'00010011 + assign \perm [6] \rb64_19 + case 8'00010100 + assign \perm [6] \rb64_20 + case 8'00010101 + assign \perm [6] \rb64_21 + case 8'00010110 + assign \perm [6] \rb64_22 + case 8'00010111 + assign \perm [6] \rb64_23 + case 8'00011000 + assign \perm [6] \rb64_24 + case 8'00011001 + assign \perm [6] \rb64_25 + case 8'00011010 + assign \perm [6] \rb64_26 + case 8'00011011 + assign \perm [6] \rb64_27 + case 8'00011100 + assign \perm [6] \rb64_28 + case 8'00011101 + assign \perm [6] \rb64_29 + case 8'00011110 + assign \perm [6] \rb64_30 + case 8'00011111 + assign \perm [6] \rb64_31 + case 8'00100000 + assign \perm [6] \rb64_32 + case 8'00100001 + assign \perm [6] \rb64_33 + case 8'00100010 + assign \perm [6] \rb64_34 + case 8'00100011 + assign \perm [6] \rb64_35 + case 8'00100100 + assign \perm [6] \rb64_36 + case 8'00100101 + assign \perm [6] \rb64_37 + case 8'00100110 + assign \perm [6] \rb64_38 + case 8'00100111 + assign \perm [6] \rb64_39 + case 8'00101000 + assign \perm [6] \rb64_40 + case 8'00101001 + assign \perm [6] \rb64_41 + case 8'00101010 + assign \perm [6] \rb64_42 + case 8'00101011 + assign \perm [6] \rb64_43 + case 8'00101100 + assign \perm [6] \rb64_44 + case 8'00101101 + assign \perm [6] \rb64_45 + case 8'00101110 + assign \perm [6] \rb64_46 + case 8'00101111 + assign \perm [6] \rb64_47 + case 8'00110000 + assign \perm [6] \rb64_48 + case 8'00110001 + assign \perm [6] \rb64_49 + case 8'00110010 + assign \perm [6] \rb64_50 + case 8'00110011 + assign \perm [6] \rb64_51 + case 8'00110100 + assign \perm [6] \rb64_52 + case 8'00110101 + assign \perm [6] \rb64_53 + case 8'00110110 + assign \perm [6] \rb64_54 + case 8'00110111 + assign \perm [6] \rb64_55 + case 8'00111000 + assign \perm [6] \rb64_56 + case 8'00111001 + assign \perm [6] \rb64_57 + case 8'00111010 + assign \perm [6] \rb64_58 + case 8'00111011 + assign \perm [6] \rb64_59 + case 8'00111100 + assign \perm [6] \rb64_60 + case 8'00111101 + assign \perm [6] \rb64_61 + case 8'00111110 + assign \perm [6] \rb64_62 + case 8'-------- + assign \perm [6] \rb64_63 + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch { $15 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_7 + case 8'00000000 + assign \perm [7] \rb64_0 + case 8'00000001 + assign \perm [7] \rb64_1 + case 8'00000010 + assign \perm [7] \rb64_2 + case 8'00000011 + assign \perm [7] \rb64_3 + case 8'00000100 + assign \perm [7] \rb64_4 + case 8'00000101 + assign \perm [7] \rb64_5 + case 8'00000110 + assign \perm [7] \rb64_6 + case 8'00000111 + assign \perm [7] \rb64_7 + case 8'00001000 + assign \perm [7] \rb64_8 + case 8'00001001 + assign \perm [7] \rb64_9 + case 8'00001010 + assign \perm [7] \rb64_10 + case 8'00001011 + assign \perm [7] \rb64_11 + case 8'00001100 + assign \perm [7] \rb64_12 + case 8'00001101 + assign \perm [7] \rb64_13 + case 8'00001110 + assign \perm [7] \rb64_14 + case 8'00001111 + assign \perm [7] \rb64_15 + case 8'00010000 + assign \perm [7] \rb64_16 + case 8'00010001 + assign \perm [7] \rb64_17 + case 8'00010010 + assign \perm [7] \rb64_18 + case 8'00010011 + assign \perm [7] \rb64_19 + case 8'00010100 + assign \perm [7] \rb64_20 + case 8'00010101 + assign \perm [7] \rb64_21 + case 8'00010110 + assign \perm [7] \rb64_22 + case 8'00010111 + assign \perm [7] \rb64_23 + case 8'00011000 + assign \perm [7] \rb64_24 + case 8'00011001 + assign \perm [7] \rb64_25 + case 8'00011010 + assign \perm [7] \rb64_26 + case 8'00011011 + assign \perm [7] \rb64_27 + case 8'00011100 + assign \perm [7] \rb64_28 + case 8'00011101 + assign \perm [7] \rb64_29 + case 8'00011110 + assign \perm [7] \rb64_30 + case 8'00011111 + assign \perm [7] \rb64_31 + case 8'00100000 + assign \perm [7] \rb64_32 + case 8'00100001 + assign \perm [7] \rb64_33 + case 8'00100010 + assign \perm [7] \rb64_34 + case 8'00100011 + assign \perm [7] \rb64_35 + case 8'00100100 + assign \perm [7] \rb64_36 + case 8'00100101 + assign \perm [7] \rb64_37 + case 8'00100110 + assign \perm [7] \rb64_38 + case 8'00100111 + assign \perm [7] \rb64_39 + case 8'00101000 + assign \perm [7] \rb64_40 + case 8'00101001 + assign \perm [7] \rb64_41 + case 8'00101010 + assign \perm [7] \rb64_42 + case 8'00101011 + assign \perm [7] \rb64_43 + case 8'00101100 + assign \perm [7] \rb64_44 + case 8'00101101 + assign \perm [7] \rb64_45 + case 8'00101110 + assign \perm [7] \rb64_46 + case 8'00101111 + assign \perm [7] \rb64_47 + case 8'00110000 + assign \perm [7] \rb64_48 + case 8'00110001 + assign \perm [7] \rb64_49 + case 8'00110010 + assign \perm [7] \rb64_50 + case 8'00110011 + assign \perm [7] \rb64_51 + case 8'00110100 + assign \perm [7] \rb64_52 + case 8'00110101 + assign \perm [7] \rb64_53 + case 8'00110110 + assign \perm [7] \rb64_54 + case 8'00110111 + assign \perm [7] \rb64_55 + case 8'00111000 + assign \perm [7] \rb64_56 + case 8'00111001 + assign \perm [7] \rb64_57 + case 8'00111010 + assign \perm [7] \rb64_58 + case 8'00111011 + assign \perm [7] \rb64_59 + case 8'00111100 + assign \perm [7] \rb64_60 + case 8'00111101 + assign \perm [7] \rb64_61 + case 8'00111110 + assign \perm [7] \rb64_62 + case 8'-------- + assign \perm [7] \rb64_63 + end end sync init end - process $group_1 - assign \reg_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - assign \reg_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - assign \reg_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end + process $group_66 + assign \idx_1 8'00000000 + assign \idx_1 \rs [15:8] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - cell $pos $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \UI - connect \Y $1 + process $group_67 + assign \idx_2 8'00000000 + assign \idx_2 \rs [23:16] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" - wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" - wire width 47 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" - cell $sshl $5 + process $group_68 + assign \idx_3 8'00000000 + assign \idx_3 \rs [31:24] + sync init + end + process $group_69 + assign \idx_4 8'00000000 + assign \idx_4 \rs [39:32] + sync init + end + process $group_70 + assign \idx_5 8'00000000 + assign \idx_5 \rs [47:40] + sync init + end + process $group_71 + assign \idx_6 8'00000000 + assign \idx_6 \rs [55:48] + sync init + end + process $group_72 + assign \idx_7 8'00000000 + assign \idx_7 \rs [63:56] + sync init + end + process $group_73 + assign \ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra [7:0] \perm [7:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" +module \popcount + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" + wire width 64 input 0 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" + wire width 64 input 1 \data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" + wire width 64 output 2 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $3 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $4 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [0] } + connect \B { 1'0 \a [1] } + connect \Y $2 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A $4 - connect \Y $3 + connect $1 $2 + process $group_0 + assign \pop_2_0 2'00 + assign \pop_2_0 $1 [1:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208" - wire width 26 \li - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" - wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" - cell $not $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \Y $7 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [2] } + connect \B { 1'0 \a [3] } + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \sh - connect \Y $9 + connect $4 $5 + process $group_1 + assign \pop_2_1 2'00 + assign \pop_2_1 $4 [1:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 64 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - cell $pos $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \SH32 - connect \Y $11 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [4] } + connect \B { 1'0 \a [5] } + connect \Y $8 end + connect $7 $8 process $group_2 - assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b $11 - end + assign \pop_2_2 2'00 + assign \pop_2_2 $7 [1:0] sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [6] } + connect \B { 1'0 \a [7] } + connect \Y $11 + end + connect $10 $11 process $group_3 - assign \imm_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b_ok 1'1 - end + assign \pop_2_3 2'00 + assign \pop_2_3 $10 [1:0] sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [8] } + connect \B { 1'0 \a [9] } + connect \Y $14 + end + connect $13 $14 process $group_4 - assign \si 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \si \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end + assign \pop_2_4 2'00 + assign \pop_2_4 $13 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" - wire width 47 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" - wire width 47 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" - cell $sshl $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $18 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \SI - connect \B 5'10000 - connect \Y $14 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [10] } + connect \B { 1'0 \a [11] } + connect \Y $17 end - connect $13 $14 + connect $16 $17 process $group_5 - assign \si_hi 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \si_hi $13 [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end + assign \pop_2_5 2'00 + assign \pop_2_5 $16 [1:0] sync init end - process $group_6 - assign \ui 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \ui \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [12] } + connect \B { 1'0 \a [13] } + connect \Y $20 + end + connect $19 $20 + process $group_6 + assign \pop_2_6 2'00 + assign \pop_2_6 $19 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" - wire width 27 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" - wire width 27 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" - cell $sshl $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $24 parameter \A_SIGNED 0 - parameter \A_WIDTH 24 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \LI - connect \B 2'10 - connect \Y $17 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [14] } + connect \B { 1'0 \a [15] } + connect \Y $23 end - connect $16 $17 + connect $22 $23 process $group_7 - assign \li 26'00000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \li $16 [25:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end + assign \pop_2_7 2'00 + assign \pop_2_7 $22 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214" - wire width 17 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214" - wire width 17 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214" - cell $sshl $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 14 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \BD - connect \B 2'10 - connect \Y $20 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [16] } + connect \B { 1'0 \a [17] } + connect \Y $26 end - connect $19 $20 + connect $25 $26 process $group_8 - assign \bd 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \bd $19 [15:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end + assign \pop_2_8 2'00 + assign \pop_2_8 $25 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 17 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 17 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - cell $sshl $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $30 parameter \A_SIGNED 0 - parameter \A_WIDTH 14 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \DS - connect \B 2'10 - connect \Y $23 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [18] } + connect \B { 1'0 \a [19] } + connect \Y $29 end - connect $22 $23 + connect $28 $29 process $group_9 - assign \ds 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" - attribute \nmigen.decoding "RB/1" - case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - attribute \nmigen.decoding "RS/13" - case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \ds $22 [15:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end + assign \pop_2_9 2'00 + assign \pop_2_9 $28 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - cell $eq $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $25 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [20] } + connect \B { 1'0 \a [21] } + connect \Y $32 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - cell $not $28 + connect $31 $32 + process $group_10 + assign \pop_2_10 2'00 + assign \pop_2_10 $31 [1:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $36 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $27 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [22] } + connect \B { 1'0 \a [23] } + connect \Y $35 end - process $group_10 - assign \fast_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - switch { $25 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - switch { \XL_XO [5] $27 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - case 2'-1 - assign \fast_b 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - case 2'1- - assign \fast_b 3'010 - end - end + connect $34 $35 + process $group_11 + assign \pop_2_11 2'00 + assign \pop_2_11 $34 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - cell $eq $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $39 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $29 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [24] } + connect \B { 1'0 \a [25] } + connect \Y $38 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - cell $not $32 + connect $37 $38 + process $group_12 + assign \pop_2_12 2'00 + assign \pop_2_12 $37 [1:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $42 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $31 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [26] } + connect \B { 1'0 \a [27] } + connect \Y $41 end - process $group_11 - assign \fast_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - switch { \XL_XO [5] $31 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - case 2'-1 - assign \fast_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - case 2'1- - assign \fast_b_ok 1'1 - end - end + connect $40 $41 + process $group_13 + assign \pop_2_13 2'00 + assign \pop_2_13 $40 [1:0] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_c" -module \dec_c - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 1 \reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \reg_c_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 3 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 4 \RB - process $group_0 - assign \reg_c 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:266" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:267" - attribute \nmigen.decoding "RB/2" - case 2'10 - assign \reg_c \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - attribute \nmigen.decoding "RS/1" - case 2'01 - assign \reg_c \RS - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [28] } + connect \B { 1'0 \a [29] } + connect \Y $44 + end + connect $43 $44 + process $group_14 + assign \pop_2_14 2'00 + assign \pop_2_14 $43 [1:0] sync init end - process $group_1 - assign \reg_c_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:266" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:267" - attribute \nmigen.decoding "RB/2" - case 2'10 - assign \reg_c_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - attribute \nmigen.decoding "RS/1" - case 2'01 - assign \reg_c_ok 1'1 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [30] } + connect \B { 1'0 \a [31] } + connect \Y $47 + end + connect $46 $47 + process $group_15 + assign \pop_2_15 2'00 + assign \pop_2_15 $46 [1:0] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o.sprmap" -module \sprmap$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" - wire width 10 input 0 \spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" - wire width 10 output 1 \spr_o - process $group_0 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61" - switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000000001 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000000011 - assign \spr_o 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000001000 - assign \spr_o 10'0000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000001001 - assign \spr_o 10'0000000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000001101 - assign \spr_o 10'0000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000010001 - assign \spr_o 10'0000000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000010010 - assign \spr_o 10'0000000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000010011 - assign \spr_o 10'0000000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000010110 - assign \spr_o 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000011010 - assign \spr_o 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000011011 - assign \spr_o 10'0000001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000011100 - assign \spr_o 10'0000001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000011101 - assign \spr_o 10'0000001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000110000 - assign \spr_o 10'0000001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0000111101 - assign \spr_o 10'0000001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010000000 - assign \spr_o 10'0000001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010000001 - assign \spr_o 10'0000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010000010 - assign \spr_o 10'0000010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010000011 - assign \spr_o 10'0000010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010001000 - assign \spr_o 10'0000010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010010000 - assign \spr_o 10'0000010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010011000 - assign \spr_o 10'0000010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010011001 - assign \spr_o 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010011101 - assign \spr_o 10'0000010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010011110 - assign \spr_o 10'0000011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010011111 - assign \spr_o 10'0000011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010110000 - assign \spr_o 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010110100 - assign \spr_o 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010111010 - assign \spr_o 10'0000011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010111011 - assign \spr_o 10'0000011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010111100 - assign \spr_o 10'0000011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0010111110 - assign \spr_o 10'0000011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100000000 - assign \spr_o 10'0000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100000011 - assign \spr_o 10'0000100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100001100 - assign \spr_o 10'0000100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100001101 - assign \spr_o 10'0000100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100010000 - assign \spr_o 10'0000100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100010001 - assign \spr_o 10'0000100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100010010 - assign \spr_o 10'0000100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100010011 - assign \spr_o 10'0000100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100011011 - assign \spr_o 10'0000101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100011100 - assign \spr_o 10'0000101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100011101 - assign \spr_o 10'0000101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100011110 - assign \spr_o 10'0000101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100011111 - assign \spr_o 10'0000101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110000 - assign \spr_o 10'0000101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110001 - assign \spr_o 10'0000101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110010 - assign \spr_o 10'0000101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110011 - assign \spr_o 10'0000110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110100 - assign \spr_o 10'0000110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110101 - assign \spr_o 10'0000110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100110110 - assign \spr_o 10'0000110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100111001 - assign \spr_o 10'0000110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100111010 - assign \spr_o 10'0000110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100111011 - assign \spr_o 10'0000110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100111110 - assign \spr_o 10'0000110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0100111111 - assign \spr_o 10'0000111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0101010000 - assign \spr_o 10'0000111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0101010001 - assign \spr_o 10'0000111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0101010010 - assign \spr_o 10'0000111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0101010011 - assign \spr_o 10'0000111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0101011101 - assign \spr_o 10'0000111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0110111110 - assign \spr_o 10'0000111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'0111010000 - assign \spr_o 10'0000111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000000 - assign \spr_o 10'0001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000001 - assign \spr_o 10'0001000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000010 - assign \spr_o 10'0001000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000011 - assign \spr_o 10'0001000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000100 - assign \spr_o 10'0001000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000101 - assign \spr_o 10'0001000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000110 - assign \spr_o 10'0001000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100000111 - assign \spr_o 10'0001000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100001000 - assign \spr_o 10'0001001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100001011 - assign \spr_o 10'0001001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100001100 - assign \spr_o 10'0001001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100001101 - assign \spr_o 10'0001001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100001110 - assign \spr_o 10'0001001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010000 - assign \spr_o 10'0001001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010001 - assign \spr_o 10'0001001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010010 - assign \spr_o 10'0001001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010011 - assign \spr_o 10'0001010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010100 - assign \spr_o 10'0001010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010101 - assign \spr_o 10'0001010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010110 - assign \spr_o 10'0001010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100010111 - assign \spr_o 10'0001010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100011000 - assign \spr_o 10'0001010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100011011 - assign \spr_o 10'0001010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100011100 - assign \spr_o 10'0001010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100011101 - assign \spr_o 10'0001011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100011110 - assign \spr_o 10'0001011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100100000 - assign \spr_o 10'0001011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100100001 - assign \spr_o 10'0001011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100100010 - assign \spr_o 10'0001011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100100011 - assign \spr_o 10'0001011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100100100 - assign \spr_o 10'0001011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100100101 - assign \spr_o 10'0001011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100100110 - assign \spr_o 10'0001100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100101000 - assign \spr_o 10'0001100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100101001 - assign \spr_o 10'0001100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100101010 - assign \spr_o 10'0001100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100101011 - assign \spr_o 10'0001100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100101111 - assign \spr_o 10'0001100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100110000 - assign \spr_o 10'0001100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1100110111 - assign \spr_o 10'0001100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1101010000 - assign \spr_o 10'0001101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1101010001 - assign \spr_o 10'0001101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1101010111 - assign \spr_o 10'0001101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1110000000 - assign \spr_o 10'0001101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1110000010 - assign \spr_o 10'0001101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" - case 10'1111111111 - assign \spr_o 10'0001101101 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [32] } + connect \B { 1'0 \a [33] } + connect \Y $50 + end + connect $49 $50 + process $group_16 + assign \pop_2_16 2'00 + assign \pop_2_16 $49 [1:0] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o" -module \dec_o - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src 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\enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 4 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 6 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 7 \fast_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 8 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 9 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 10 \BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 10 input 11 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" - wire width 10 \sprmap_spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" - wire width 10 \sprmap_spr_o - cell \sprmap$1 \sprmap - connect \spr_i \sprmap_spr_i - connect \spr_o \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [34] } + connect \B { 1'0 \a [35] } + connect \Y $53 end - process $group_0 - assign \reg_o 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - assign \reg_o \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - assign \reg_o \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - end + connect $52 $53 + process $group_17 + assign \pop_2_17 2'00 + assign \pop_2_17 $52 [1:0] sync init end - process $group_1 - assign \reg_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - assign \reg_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - assign \reg_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [36] } + connect \B { 1'0 \a [37] } + connect \Y $56 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307" - wire width 10 \spr - process $group_2 - assign \spr 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - assign \spr { \SPR [4:0] \SPR [9:5] } - end + connect $55 $56 + process $group_18 + assign \pop_2_18 2'00 + assign \pop_2_18 $55 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - cell $eq $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $60 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $1 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [38] } + connect \B { 1'0 \a [39] } + connect \Y $59 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - cell $not $4 + connect $58 $59 + process $group_19 + assign \pop_2_19 2'00 + assign \pop_2_19 $58 [1:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $63 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $3 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [40] } + connect \B { 1'0 \a [41] } + connect \Y $62 end - process $group_3 - assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" - case 10'0000001001 - assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" - case 10'0000001000 - assign \fast_o 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" - case 10'1100101111 - assign \fast_o 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - case 10'0000011010 - assign \fast_o 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - case 10'0000011011 - assign \fast_o 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case - end - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" - attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8" - case 7'0000111, 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - case 1'1 - assign \fast_o 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \fast_o 3'011 - end + connect $61 $62 + process $group_20 + assign \pop_2_20 2'00 + assign \pop_2_20 $61 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - cell $eq $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $66 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $5 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [42] } + connect \B { 1'0 \a [43] } + connect \Y $65 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - cell $not $8 + connect $64 $65 + process $group_21 + assign \pop_2_21 2'00 + assign \pop_2_21 $64 [1:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $69 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $7 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [44] } + connect \B { 1'0 \a [45] } + connect \Y $68 end - process $group_4 - assign \fast_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" - case 10'0000001001 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" - case 10'0000001000 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" - case 10'1100101111 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - case 10'0000011010 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - case 10'0000011011 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case - end - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" - attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8" - case 7'0000111, 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - case 1'1 - assign \fast_o_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \fast_o_ok 1'1 - end + connect $67 $68 + process $group_22 + assign \pop_2_22 2'00 + assign \pop_2_22 $67 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - cell $eq $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $72 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $9 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [46] } + connect \B { 1'0 \a [47] } + connect \Y $71 end - process $group_5 - assign \sprmap_spr_i 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case - assign \sprmap_spr_i \spr - end - end - end + connect $70 $71 + process $group_23 + assign \pop_2_23 2'00 + assign \pop_2_23 $70 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - cell $eq $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $75 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $11 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [48] } + connect \B { 1'0 \a [49] } + connect \Y $74 end - process $group_6 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - switch { $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case - assign \spr_o \sprmap_spr_o - end - end - end + connect $73 $74 + process $group_24 + assign \pop_2_24 2'00 + assign \pop_2_24 $73 [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - cell $eq $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $78 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $13 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [50] } + connect \B { 1'0 \a [51] } + connect \Y $77 end - process $group_7 - assign \spr_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case - assign \spr_o_ok 1'1 - end - end - end + connect $76 $77 + process $group_25 + assign \pop_2_25 2'00 + assign \pop_2_25 $76 [1:0] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o2" -module \dec_o2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" - wire width 1 input 0 \lk - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 2 \reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \reg_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 4 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \fast_o_ok - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" - wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 7 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - cell $eq $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $81 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \upd - connect \B 2'01 - connect \Y $1 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [52] } + connect \B { 1'0 \a [53] } + connect \Y $80 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 6 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - cell $pos $4 + connect $79 $80 + process $group_26 + assign \pop_2_26 2'00 + assign \pop_2_26 $79 [1:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $84 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A \RA - connect \Y $3 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [54] } + connect \B { 1'0 \a [55] } + connect \Y $83 end - process $group_0 - assign \reg_o 5'00000 - assign \reg_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - case 1'1 - assign { \reg_o_ok \reg_o } $3 - assign \reg_o_ok 1'1 - end + connect $82 $83 + process $group_27 + assign \pop_2_27 2'00 + assign \pop_2_27 $82 [1:0] sync init end - process $group_2 - assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" - attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8" - case 7'0000111, 7'0000110, 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - switch { \lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - case 1'1 - assign \fast_o 3'001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \fast_o 3'100 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [56] } + connect \B { 1'0 \a [57] } + connect \Y $86 + end + connect $85 $86 + process $group_28 + assign \pop_2_28 2'00 + assign \pop_2_28 $85 [1:0] sync init end - process $group_3 - assign \fast_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" - attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8" - case 7'0000111, 7'0000110, 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - switch { \lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - case 1'1 - assign \fast_o_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \fast_o_ok 1'1 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [58] } + connect \B { 1'0 \a [59] } + connect \Y $89 + end + connect $88 $89 + process $group_29 + assign \pop_2_29 2'00 + assign \pop_2_29 $88 [1:0] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_rc" -module \dec_rc - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 1 input 3 \Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [60] } + connect \B { 1'0 \a [61] } + connect \Y $92 + end + connect $91 $92 + process $group_30 + assign \pop_2_30 2'00 + assign \pop_2_30 $91 [1:0] sync init end - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 2 \pop_2_31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 3 $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'0 \a [62] } + connect \B { 1'0 \a [63] } + connect \Y $95 + end + connect $94 $95 + process $group_31 + assign \pop_2_31 2'00 + assign \pop_2_31 $94 [1:0] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_oe" -module \dec_oe - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 1 input 4 \OE - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52" - case 7'0110011, 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:460" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \OE - end - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_0 } + connect \B { 1'0 \pop_2_1 } + connect \Y $98 + end + connect $97 $98 + process $group_32 + assign \pop_3_0 3'000 + assign \pop_3_0 $97 [2:0] sync init end - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52" - case 7'0110011, 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:460" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_2 } + connect \B { 1'0 \pop_2_3 } + connect \Y $101 + end + connect $100 $101 + process $group_33 + assign \pop_3_1 3'000 + assign \pop_3_1 $100 [2:0] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_cr_in" -module \dec_cr_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:476" - wire width 3 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 1 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 5 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 6 \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481" - wire width 1 output 7 \whole_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 8 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 9 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 10 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 11 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" - wire width 5 input 12 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 input 13 \X_BFA - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_4 } + connect \B { 1'0 \pop_2_5 } + connect \Y $104 + end + connect $103 $104 + process $group_34 + assign \pop_3_2 3'000 + assign \pop_3_2 $103 [2:0] sync init end - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_6 } + connect \B { 1'0 \pop_2_7 } + connect \Y $107 + end + connect $106 $107 + process $group_35 + assign \pop_3_3 3'000 + assign \pop_3_3 $106 [2:0] sync init end - process $group_2 - assign \whole_reg 1'0 - assign \whole_reg 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \whole_reg 1'1 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_8 } + connect \B { 1'0 \pop_2_9 } + connect \Y $110 + end + connect $109 $110 + process $group_36 + assign \pop_3_4 3'000 + assign \pop_3_4 $109 [2:0] sync init end - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_10 } + connect \B { 1'0 \pop_2_11 } + connect \Y $113 + end + connect $112 $113 + process $group_37 + assign \pop_3_5 3'000 + assign \pop_3_5 $112 [2:0] sync init end - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_12 } + connect \B { 1'0 \pop_2_13 } + connect \Y $116 + end + connect $115 $116 + process $group_38 + assign \pop_3_6 3'000 + assign \pop_3_6 $115 [2:0] sync init end - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_14 } + connect \B { 1'0 \pop_2_15 } + connect \Y $119 + end + connect $118 $119 + process $group_39 + assign \pop_3_7 3'000 + assign \pop_3_7 $118 [2:0] sync init end - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_16 } + connect \B { 1'0 \pop_2_17 } + connect \Y $122 + end + connect $121 $122 + process $group_40 + assign \pop_3_8 3'000 + assign \pop_3_8 $121 [2:0] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_cr_out" -module \dec_cr_out - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 3 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" - wire width 1 input 1 \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 2 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:531" - wire width 1 output 4 \whole_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348" - wire width 5 input 6 \XL_BT - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_18 } + connect \B { 1'0 \pop_2_19 } + connect \Y $125 + end + connect $124 $125 + process $group_41 + assign \pop_3_9 3'000 + assign \pop_3_9 $124 [2:0] sync init end - process $group_1 - assign \whole_reg 1'0 - assign \whole_reg 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \whole_reg 1'1 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_20 } + connect \B { 1'0 \pop_2_21 } + connect \Y $128 + end + connect $127 $128 + process $group_42 + assign \pop_3_10 3'000 + assign \pop_3_10 $127 [2:0] sync init end - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_22 } + connect \B { 1'0 \pop_2_23 } + connect \Y $131 + end + connect $130 $131 + process $group_43 + assign \pop_3_11 3'000 + assign \pop_3_11 $130 [2:0] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.pdecode2" -module \pdecode2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332" - wire width 1 input 0 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331" - wire width 32 input 1 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 2 \dec2_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 3 \dec2_msr - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute 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wire width 1 output 13 \zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 1 output 14 \invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 output 15 \write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 2 output 16 \input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 output 17 \output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 1 output 18 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 1 output 19 \is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" - wire width 4 output 20 \data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38" - wire width 32 output 21 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 22 \reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82" - wire width 1 output 24 \xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" - wire width 1 output 25 \read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" - wire width 1 output 26 \write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 27 \cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 28 \cr_in2_ok - attribute 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\enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \dec_a_spr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_a_spr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_a_fast_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_a_fast_a_ok - cell \dec_a \dec_a - connect \sel_in \dec_a_sel_in - connect \internal_op \dec_internal_op - connect \reg_a \dec_a_reg_a - connect \reg_a_ok \dec_a_reg_a_ok - connect \immz_out \dec_a_immz_out - connect \spr_a \dec_a_spr_a - connect \spr_a_ok \dec_a_spr_a_ok - connect \fast_a \dec_a_fast_a - connect \fast_a_ok \dec_a_fast_a_ok - connect \RS \dec_RS - connect \RA \dec_RA - connect \BO \dec_BO - connect \SPR \dec_SPR - connect \XL_XO \dec_XL_XO - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170" - wire width 4 \dec_b_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_b_reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_b_reg_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_b_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_b_imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_b_fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_b_fast_b_ok - cell \dec_b \dec_b - connect \sel_in \dec_b_sel_in - connect \internal_op \dec_internal_op - connect \reg_b \dec_b_reg_b - connect \reg_b_ok \dec_b_reg_b_ok - connect \imm_b \dec_b_imm_b - connect \imm_b_ok \dec_b_imm_b_ok - connect \fast_b \dec_b_fast_b - connect \fast_b_ok \dec_b_fast_b_ok - connect \RS \dec_RS - connect \RB \dec_RB - connect \SI \dec_SI - connect \UI \dec_UI - connect \SH32 \dec_SH32 - connect \sh \dec_sh - connect \LI \dec_LI - connect \BD \dec_BD - connect \DS \dec_DS - connect \XL_XO \dec_XL_XO - end - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" - wire width 2 \dec_c_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_c_reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_c_reg_c_ok - cell \dec_c \dec_c - connect \sel_in \dec_c_sel_in - connect \reg_c \dec_c_reg_c - connect \reg_c_ok \dec_c_reg_c_ok - connect \RS \dec_RS - connect \RB \dec_RB - end - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" - wire width 2 \dec_o_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_o_reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_o_reg_o_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \dec_o_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_o_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_o_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_o_fast_o_ok - cell \dec_o \dec_o - connect \sel_in \dec_o_sel_in - connect \internal_op \dec_internal_op - connect \reg_o \dec_o_reg_o - connect \reg_o_ok \dec_o_reg_o_ok - connect \spr_o \dec_o_spr_o - connect \spr_o_ok \dec_o_spr_o_ok - connect \fast_o \dec_o_fast_o - connect \fast_o_ok \dec_o_fast_o_ok - connect \RT \dec_RT - connect \RA \dec_RA - connect \BO \dec_BO - connect \SPR \dec_SPR - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" - wire width 1 \dec_o2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_o2_reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_o2_reg_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_o2_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_o2_fast_o_ok - cell \dec_o2 \dec_o2 - connect \lk \dec_o2_lk - connect \internal_op \dec_internal_op - connect \reg_o \dec_o2_reg_o - connect \reg_o_ok \dec_o2_reg_o_ok - connect \fast_o \dec_o2_fast_o - connect \fast_o_ok \dec_o2_fast_o_ok - connect \upd \dec_upd - connect \RA \dec_RA - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc_ok - cell \dec_rc \dec_rc - connect \sel_in \dec_rc_sel_in - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \Rc \dec_Rc - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe_ok - cell \dec_oe \dec_oe - connect \sel_in \dec_oe_sel_in - connect \internal_op \dec_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \OE \dec_OE - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:476" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_in_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_in_cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_in_cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_in_cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481" - wire width 1 \dec_cr_in_whole_reg - cell \dec_cr_in \dec_cr_in$3 - connect \sel_in \dec_cr_in_sel_in - connect \cr_bitfield \dec_cr_in_cr_bitfield - connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok - connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b - connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok - connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o - connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok - connect \whole_reg \dec_cr_in_whole_reg - connect \BB \dec_BB - connect \BA \dec_BA - connect \BT \dec_BT - connect \BI \dec_BI - connect \BC \dec_BC - connect \X_BFA \dec_X_BFA - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" - wire width 1 \dec_cr_out_rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_cr_out_cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:531" - wire width 1 \dec_cr_out_whole_reg - cell \dec_cr_out \dec_cr_out$4 - connect \sel_in \dec_cr_out_sel_in - connect \rc_in \dec_cr_out_rc_in - connect \cr_bitfield \dec_cr_out_cr_bitfield - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \whole_reg \dec_cr_out_whole_reg - connect \X_BF \dec_X_BF - connect \XL_BT \dec_XL_BT - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \rego_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fasto2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83" - wire width 1 \xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" - wire width 8 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690" - cell $eq $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $135 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0101110 - connect \Y $5 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_24 } + connect \B { 1'0 \pop_2_25 } + connect \Y $134 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" - cell $eq $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0110001 - connect \Y $7 + connect $133 $134 + process $group_44 + assign \pop_3_12 3'000 + assign \pop_3_12 $133 [2:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" - cell $eq $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $138 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0111111 - connect \Y $9 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_26 } + connect \B { 1'0 \pop_2_27 } + connect \Y $137 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:38" - wire width 1 \is_priv_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:702" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:702" - cell $and $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_priv_insn - connect \B \dec2_msr [14] - connect \Y $11 + connect $136 $137 + process $group_45 + assign \pop_3_13 3'000 + assign \pop_3_13 $136 [2:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:710" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:710" - cell $eq $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $141 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0000000 - connect \Y $13 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_28 } + connect \B { 1'0 \pop_2_29 } + connect \Y $140 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'0111111 - connect \Y $15 + connect $139 $140 + process $group_46 + assign \pop_3_14 3'000 + assign \pop_3_14 $139 [2:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - cell $eq $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 3 \pop_3_15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 4 $143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $144 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1001001 - connect \Y $17 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'0 \pop_2_30 } + connect \B { 1'0 \pop_2_31 } + connect \Y $143 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - cell $or $20 + connect $142 $143 + process $group_47 + assign \pop_3_15 3'000 + assign \pop_3_15 $142 [2:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $147 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $15 - connect \B $17 - connect \Y $19 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'0 \pop_3_0 } + connect \B { 1'0 \pop_3_1 } + connect \Y $146 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:726" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:726" - cell $eq $22 + connect $145 $146 + process $group_48 + assign \pop_4_0 4'0000 + assign \pop_4_0 $145 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'0 \pop_3_2 } + connect \B { 1'0 \pop_3_3 } + connect \Y $149 + end + connect $148 $149 + process $group_49 + assign \pop_4_1 4'0000 + assign \pop_4_1 $148 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'0 \pop_3_4 } + connect \B { 1'0 \pop_3_5 } + connect \Y $152 + end + connect $151 $152 + process $group_50 + assign \pop_4_2 4'0000 + assign \pop_4_2 $151 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'0 \pop_3_6 } + connect \B { 1'0 \pop_3_7 } + connect \Y $155 + end + connect $154 $155 + process $group_51 + assign \pop_4_3 4'0000 + assign \pop_4_3 $154 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'0 \pop_3_8 } + connect \B { 1'0 \pop_3_9 } + connect \Y $158 + end + connect $157 $158 + process $group_52 + assign \pop_4_4 4'0000 + assign \pop_4_4 $157 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'0 \pop_3_10 } + connect \B { 1'0 \pop_3_11 } + connect \Y $161 + end + connect $160 $161 + process $group_53 + assign \pop_4_5 4'0000 + assign \pop_4_5 $160 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'0 \pop_3_12 } + connect \B { 1'0 \pop_3_13 } + connect \Y $164 + end + connect $163 $164 + process $group_54 + assign \pop_4_6 4'0000 + assign \pop_4_6 $163 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 4 \pop_4_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 5 $167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'0 \pop_3_14 } + connect \B { 1'0 \pop_3_15 } + connect \Y $167 + end + connect $166 $167 + process $group_55 + assign \pop_4_7 4'0000 + assign \pop_4_7 $166 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 $169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 $170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A { 1'0 \pop_4_0 } + connect \B { 1'0 \pop_4_1 } + connect \Y $170 + end + connect $169 $170 + process $group_56 + assign \pop_5_0 5'00000 + assign \pop_5_0 $169 [4:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 $172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 $173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A { 1'0 \pop_4_2 } + connect \B { 1'0 \pop_4_3 } + connect \Y $173 + end + connect $172 $173 + process $group_57 + assign \pop_5_1 5'00000 + assign \pop_5_1 $172 [4:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 $175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 $176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A { 1'0 \pop_4_4 } + connect \B { 1'0 \pop_4_5 } + connect \Y $176 + end + connect $175 $176 + process $group_58 + assign \pop_5_2 5'00000 + assign \pop_5_2 $175 [4:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 5 \pop_5_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 $178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 6 $179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A { 1'0 \pop_4_6 } + connect \B { 1'0 \pop_4_7 } + connect \Y $179 + end + connect $178 $179 + process $group_59 + assign \pop_5_3 5'00000 + assign \pop_5_3 $178 [4:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 6 \pop_6_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 7 $181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 7 $182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A { 1'0 \pop_5_0 } + connect \B { 1'0 \pop_5_1 } + connect \Y $182 + end + connect $181 $182 + process $group_60 + assign \pop_6_0 6'000000 + assign \pop_6_0 $181 [5:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 6 \pop_6_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 7 $184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 7 $185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A { 1'0 \pop_5_2 } + connect \B { 1'0 \pop_5_3 } + connect \Y $185 + end + connect $184 $185 + process $group_61 + assign \pop_6_1 6'000000 + assign \pop_6_1 $184 [5:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 7 \pop_7_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 8 $187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + wire width 8 $188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $189 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A { 1'0 \pop_6_0 } + connect \B { 1'0 \pop_6_1 } + connect \Y $188 + end + connect $187 $188 + process $group_62 + assign \pop_7_0 7'0000000 + assign \pop_7_0 $187 [6:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + wire width 1 $190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + cell $eq $191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1000110 - connect \Y $21 + connect \A \data_len + connect \B 1'1 + connect \Y $190 end - process $group_82 - assign \insn 32'00000000000000000000000000000000 - assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \insn_type 7'0000000 - assign \fn_unit 11'00000000000 - assign \reg1 5'00000 - assign \reg1_ok 1'0 - assign \reg2 5'00000 - assign \reg2_ok 1'0 - assign \reg3 5'00000 - assign \reg3_ok 1'0 - assign \rego 5'00000 - assign \rego_ok 1'0 - assign \ea 5'00000 - assign \ea_ok 1'0 - assign \imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \imm_ok 1'0 - assign \zero_a 1'0 - assign \rc 1'0 - assign \rc_ok 1'0 - assign \oe 1'0 - assign \oe_ok 1'0 - assign \spr1 10'0000000000 - assign \spr1_ok 1'0 - assign \spro 10'0000000000 - assign \spro_ok 1'0 - assign \fast1 3'000 - assign \fast1_ok 1'0 - assign \fast2 3'000 - assign \fast2_ok 1'0 - assign \fasto1 3'000 - assign \fasto1_ok 1'0 - assign \fasto2 3'000 - assign \fasto2_ok 1'0 - assign \cr_in1 3'000 - assign \cr_in1_ok 1'0 - assign \cr_in2 3'000 - assign \cr_in2_ok 1'0 - assign \cr_in2$2 3'000 - assign \cr_in2_ok$1 1'0 - assign \cr_out 3'000 - assign \cr_out_ok 1'0 - assign \read_cr_whole 1'0 - assign \write_cr_whole 1'0 - assign \write_cr0 1'0 - assign \data_len 4'0000 - assign \invert_a 1'0 - assign \invert_out 1'0 - assign \input_carry 2'00 - assign \output_carry 1'0 - assign \is_32bit 1'0 - assign \is_signed 1'0 - assign \lk 1'0 - assign \byte_reverse 1'0 - assign \sign_extend 1'0 - assign \ldst_mode 2'00 - assign \input_cr 1'0 - assign \output_cr 1'0 - assign \xer_in 1'0 - assign \xer_out 1'0 - assign \trapaddr 13'0000000000000 - assign \asmcode 8'00000000 - assign \traptype 5'00000 - assign \insn \dec_opcode_in - assign \msr \dec2_msr - assign \cia \dec2_pc - assign \insn_type \dec_internal_op - assign \fn_unit \dec_function_unit - assign { \reg1_ok \reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } - assign { \reg2_ok \reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } - assign { \reg3_ok \reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } - assign { \rego_ok \rego } { \dec_o_reg_o_ok \dec_o_reg_o } - assign { \ea_ok \ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } - assign { \imm_ok \imm } { \dec_b_imm_b_ok \dec_b_imm_b } - assign \zero_a \dec_a_immz_out - assign { \rc_ok \rc } { \dec_rc_rc_ok \dec_rc_rc } - assign { \oe_ok \oe } { \dec_oe_oe_ok \dec_oe_oe } - assign { \spr1_ok \spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } - assign { \spro_ok \spro } { \dec_o_spr_o_ok \dec_o_spr_o } - assign { \fast1_ok \fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } - assign { \fast2_ok \fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } - assign { \fasto1_ok \fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } - assign { \fasto2_ok \fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } - assign { \cr_in1_ok \cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } - assign { \cr_in2_ok \cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } - assign { \cr_in2_ok$1 \cr_in2$2 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } - assign { \cr_out_ok \cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } - assign \read_cr_whole \dec_cr_in_whole_reg - assign \write_cr_whole \dec_cr_out_whole_reg - assign \write_cr0 \dec_cr_out_cr_bitfield_ok - assign \data_len \dec_ldst_len - assign \invert_a \dec_inv_a - assign \invert_out \dec_inv_out - assign \input_carry \dec_cry_in - assign \output_carry \dec_cry_out - assign \is_32bit \dec_is_32b - assign \is_signed \dec_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676" - switch { \dec_lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676" - case 1'1 - assign \lk \dec_LK - end - switch { } - case - assign \byte_reverse \dec_br - end - switch { } - case - assign \sign_extend \dec_sgn_ext - end - switch { } - case - assign \ldst_mode \dec_upd - end - switch { } - case - assign \input_cr \dec_cr_in [0] - end - switch { } - case - assign \output_cr \dec_cr_out [0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690" - case 1'1 - assign \xer_in 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" - case 1'1 - assign \xer_out 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" - case 1'1 - assign \trapaddr 13'0000001110000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:702" - switch { $13 $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:702" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" + wire width 1 $192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" + cell $eq $193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 3'100 + connect \Y $192 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 $194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_0 + connect \Y $194 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 $196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_1 + connect \Y $196 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 $198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_2 + connect \Y $198 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 $200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_3 + connect \Y $200 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 $202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_4 + connect \Y $202 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 $204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_5 + connect \Y $204 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 $206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_6 + connect \Y $206 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 8 $208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_7 + connect \Y $208 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 32 $210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_0 + connect \Y $210 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 32 $212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_1 + connect \Y $212 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + wire width 64 $214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \pop_7_0 + connect \Y $214 + end + process $group_63 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + switch { $192 $190 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" case 2'-1 - assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$2 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \insn \dec_opcode_in - assign \insn_type 7'0111111 - assign \fn_unit 11'00010000000 - assign \trapaddr 13'0000001110000 - assign \traptype 5'00010 - assign \msr \dec2_msr - assign \cia \dec2_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:710" + assign \o [7:0] $194 + assign \o [15:8] $196 + assign \o [23:16] $198 + assign \o [31:24] $200 + assign \o [39:32] $202 + assign \o [47:40] $204 + assign \o [55:48] $206 + assign \o [63:56] $208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" case 2'1- - assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$2 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \insn \dec_opcode_in - assign \insn_type 7'0111111 - assign \fn_unit 11'00010000000 - assign \trapaddr 13'0000001110000 - assign \traptype 5'10000 - assign \msr \dec2_msr - assign \cia \dec2_pc - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" - case 1'1 - assign \fasto1 3'011 - assign \fasto1_ok 1'1 - assign \fasto2 3'100 - assign \fasto2_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:726" - switch { $21 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:726" - case 1'1 - assign \fast1 3'011 - assign \fast1_ok 1'1 - assign \fast2 3'100 - assign \fast2_ok 1'1 + assign \o [31:0] $210 + assign \o [63:32] $212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:63" + case + assign \o $214 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78" - wire width 32 \insn_in +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" +module \clz + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" + wire width 64 input 0 \sig_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + wire width 7 output 1 \lz + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair0 + process $group_0 + assign \pair0 2'00 + assign \pair0 \sig_in [1:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_0 process $group_1 - assign \insn_in 32'00000000000000000000000000000000 - assign \insn_in \dec_opcode_in + assign \cnt_1_0 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_0 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_0 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_0 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" - wire width 32 \insn_in$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair2 process $group_2 - assign \insn_in$23 32'00000000000000000000000000000000 - assign \insn_in$23 \dec_opcode_in + assign \pair2 2'00 + assign \pair2 \sig_in [3:2] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 32 \insn_in$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_1 process $group_3 - assign \insn_in$24 32'00000000000000000000000000000000 - assign \insn_in$24 \dec_opcode_in + assign \cnt_1_1 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_1 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_1 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_1 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:287" - wire width 32 \insn_in$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair4 process $group_4 - assign \insn_in$25 32'00000000000000000000000000000000 - assign \insn_in$25 \dec_opcode_in + assign \pair4 2'00 + assign \pair4 \sig_in [5:4] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" - wire width 32 \insn_in$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_2 process $group_5 - assign \insn_in$26 32'00000000000000000000000000000000 - assign \insn_in$26 \dec_opcode_in + assign \cnt_1_2 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_2 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_2 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_2 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair6 process $group_6 - assign \insn_in$27 32'00000000000000000000000000000000 - assign \insn_in$27 \dec_opcode_in + assign \pair6 2'00 + assign \pair6 \sig_in [7:6] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_3 process $group_7 - assign \insn_in$28 32'00000000000000000000000000000000 - assign \insn_in$28 \dec_opcode_in + assign \cnt_1_3 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_3 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_3 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_3 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" - wire width 32 \insn_in$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair8 process $group_8 - assign \insn_in$29 32'00000000000000000000000000000000 - assign \insn_in$29 \dec_opcode_in + assign \pair8 2'00 + assign \pair8 \sig_in [9:8] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" - wire width 32 \insn_in$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_4 process $group_9 - assign \insn_in$30 32'00000000000000000000000000000000 - assign \insn_in$30 \dec_opcode_in + assign \cnt_1_4 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_4 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_4 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_4 2'00 + end sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair10 process $group_10 - assign \dec_a_sel_in 3'000 - assign \dec_a_sel_in \dec_in1_sel + assign \pair10 2'00 + assign \pair10 \sig_in [11:10] sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_5 process $group_11 - assign \dec_b_sel_in 4'0000 - assign \dec_b_sel_in \dec_in2_sel + assign \cnt_1_5 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_5 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_5 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_5 2'00 + end sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair12 process $group_12 - assign \dec_c_sel_in 2'00 - assign \dec_c_sel_in \dec_in3_sel + assign \pair12 2'00 + assign \pair12 \sig_in [13:12] sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_6 process $group_13 - assign \dec_o_sel_in 2'00 - assign \dec_o_sel_in \dec_out_sel + assign \cnt_1_6 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_6 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_6 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_6 2'00 + end sync init end - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" - wire width 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair14 process $group_14 - assign \sel_in 2'00 - assign \sel_in \dec_out_sel + assign \pair14 2'00 + assign \pair14 \sig_in [15:14] sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_7 process $group_15 - assign \dec_o2_lk 1'0 - assign \dec_o2_lk \lk + assign \cnt_1_7 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_7 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_7 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_7 2'00 + end sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair16 process $group_16 - assign \dec_rc_sel_in 2'00 - assign \dec_rc_sel_in \dec_rc_sel + assign \pair16 2'00 + assign \pair16 \sig_in [17:16] sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_8 process $group_17 - assign \dec_oe_sel_in 2'00 - assign \dec_oe_sel_in \dec_rc_sel + assign \cnt_1_8 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_8 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_8 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_8 2'00 + end sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair18 process $group_18 - assign \dec_cr_in_sel_in 3'000 - assign \dec_cr_in_sel_in \dec_cr_in + assign \pair18 2'00 + assign \pair18 \sig_in [19:18] sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_9 process $group_19 - assign \dec_cr_out_sel_in 3'000 - assign \dec_cr_out_sel_in \dec_cr_out + assign \cnt_1_9 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_9 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_9 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_9 2'00 + end sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair20 process $group_20 - assign \dec_cr_out_rc_in 1'0 - assign \dec_cr_out_rc_in \dec_rc_rc + assign \pair20 2'00 + assign \pair20 \sig_in [21:20] sync init end - process $group_81 - assign \is_priv_insn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:39" - switch \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" - attribute \nmigen.decoding "OP_ATTN/5|OP_MFMSR/71|OP_MTMSRD/72|OP_MTMSR/74|OP_RFID/70" - case 7'0000101, 7'1000111, 7'1001000, 7'1001010, 7'1000110 - assign \is_priv_insn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45" - attribute \nmigen.decoding "OP_MFSPR/46|OP_MTSPR/49" - case 7'0101110, 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:46" - switch { \insn [20] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:46" - case 1'1 - assign \is_priv_insn 1'1 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_10 + process $group_21 + assign \cnt_1_10 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_10 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_10 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_10 2'00 end sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.p" -module \p - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair22 + process $group_22 + assign \pair22 2'00 + assign \pair22 \sig_in [23:22] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.n" -module \n - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_11 + process $group_23 + assign \cnt_1_11 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_11 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_11 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_11 2'00 + end + sync init end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair24 + process $group_24 + assign \pair24 2'00 + assign \pair24 \sig_in [25:24] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.p" -module \p$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_12 + process $group_25 + assign \cnt_1_12 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_12 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_12 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_12 2'00 + end + sync init end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair26 + process $group_26 + assign \pair26 2'00 + assign \pair26 \sig_in [27:26] sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.n" -module \n$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_13 + process $group_27 + assign \cnt_1_13 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_13 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_13 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_13 2'00 + end sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.input" -module \input - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \alu_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \alu_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \alu_op__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \alu_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 25 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \alu_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \alu_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \alu_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \alu_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \alu_op__invert_a$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \alu_op__write_cr0$13 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 36 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 40 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 43 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 44 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 output 45 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24" - wire width 64 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24" - cell $not $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair28 + process $group_28 + assign \pair28 2'00 + assign \pair28 \sig_in [29:28] + sync init end - process $group_0 - assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23" - switch { \alu_op__invert_a } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23" - case 1'1 - assign \a $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_14 + process $group_29 + assign \cnt_1_14 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_14 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_14 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" case - assign \a \ra + assign \cnt_1_14 2'00 end sync init end - process $group_1 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair30 + process $group_30 + assign \pair30 2'00 + assign \pair30 \sig_in [31:30] sync init end - process $group_2 - assign \xer_ca$23 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36" - switch \alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37" - attribute \nmigen.decoding "ZERO/0" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_15 + process $group_31 + assign \cnt_1_15 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" case 2'00 - assign \xer_ca$23 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - attribute \nmigen.decoding "ONE/1" + assign \cnt_1_15 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" case 2'01 - assign \xer_ca$23 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" - attribute \nmigen.decoding "CA/2" - case 2'10 - assign \xer_ca$23 \xer_ca + assign \cnt_1_15 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_15 2'00 end sync init end - process $group_3 - assign \xer_so$22 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47" - switch { \alu_op__oe__oe_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47" - case 1'1 - assign \xer_so$22 \xer_so - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair32 + process $group_32 + assign \pair32 2'00 + assign \pair32 \sig_in [33:32] sync init end - process $group_4 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_16 + process $group_33 + assign \cnt_1_16 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_16 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_16 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_16 2'00 + end sync init end - process $group_5 - assign \alu_op__insn_type$2 7'0000000 - assign \alu_op__fn_unit$3 11'00000000000 - assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$5 1'0 - assign \alu_op__rc__rc$6 1'0 - assign \alu_op__rc__rc_ok$7 1'0 - assign \alu_op__oe__oe$8 1'0 - assign \alu_op__oe__oe_ok$9 1'0 - assign \alu_op__invert_a$10 1'0 - assign \alu_op__zero_a$11 1'0 - assign \alu_op__invert_out$12 1'0 - assign \alu_op__write_cr0$13 1'0 - assign \alu_op__input_carry$14 2'00 - assign \alu_op__output_carry$15 1'0 - assign \alu_op__is_32bit$16 1'0 - assign \alu_op__is_signed$17 1'0 - assign \alu_op__data_len$18 4'0000 - assign \alu_op__insn$19 32'00000000000000000000000000000000 - assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_a$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair34 + process $group_34 + assign \pair34 2'00 + assign \pair34 \sig_in [35:34] sync init end - process $group_23 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_17 + process $group_35 + assign \cnt_1_17 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_17 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_17 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_17 2'00 + end sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.main" -module \main - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \alu_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \alu_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \alu_op__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \alu_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 25 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \alu_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \alu_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \alu_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \alu_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \alu_op__invert_a$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \alu_op__write_cr0$13 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 36 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 40 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 42 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 43 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 44 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 45 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 46 \xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 50 \xer_so$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:39" - wire width 1 \is_32bit - process $group_0 - assign \is_32bit 1'0 - assign \is_32bit \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair36 + process $group_36 + assign \pair36 2'00 + assign \pair36 \sig_in [37:36] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:40" - wire width 1 \sign_bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:42" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:42" - cell $mux $23 - parameter \WIDTH 1 - connect \A \ra [63] - connect \B \ra [31] - connect \S \is_32bit - connect \Y $22 - end - process $group_1 - assign \sign_bit 1'0 - assign \sign_bit $22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_18 + process $group_37 + assign \cnt_1_18 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_18 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_18 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_18 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:46" - wire width 66 \add_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49" - cell $eq $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair38 + process $group_38 + assign \pair38 2'00 + assign \pair38 \sig_in [39:38] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - cell $eq $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_19 + process $group_39 + assign \cnt_1_19 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair38 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_19 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_19 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_19 2'00 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \B $26 - connect \Y $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair40 + process $group_40 + assign \pair40 2'00 + assign \pair40 \sig_in [41:40] + sync init end - process $group_2 - assign \add_a 66'000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - switch { $28 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - case 1'1 - assign \add_a { 1'0 \ra \xer_ca [0] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_20 + process $group_41 + assign \cnt_1_20 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_20 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_20 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_20 2'00 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:47" - wire width 66 \add_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49" - cell $eq $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair42 + process $group_42 + assign \pair42 2'00 + assign \pair42 \sig_in [43:42] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - cell $eq $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_21 + process $group_43 + assign \cnt_1_21 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_21 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_21 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_21 2'00 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - cell $or $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $30 - connect \B $32 - connect \Y $34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair44 + process $group_44 + assign \pair44 2'00 + assign \pair44 \sig_in [45:44] + sync init end - process $group_3 - assign \add_b 66'000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - switch { $34 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - case 1'1 - assign \add_b { 1'0 \rb 1'1 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_22 + process $group_45 + assign \cnt_1_22 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_22 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_22 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_22 2'00 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:48" - wire width 66 \add_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49" - cell $eq $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $36 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - cell $eq $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $38 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair46 + process $group_46 + assign \pair46 2'00 + assign \pair46 \sig_in [47:46] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - cell $or $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $36 - connect \B $38 - connect \Y $40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_23 + process $group_47 + assign \cnt_1_23 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_23 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_23 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_23 2'00 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" - wire width 67 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" - wire width 67 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" - cell $add $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 66 - parameter \B_SIGNED 0 - parameter \B_WIDTH 66 - parameter \Y_WIDTH 67 - connect \A \add_a - connect \B \add_b - connect \Y $43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair48 + process $group_48 + assign \pair48 2'00 + assign \pair48 \sig_in [49:48] + sync init end - connect $42 $43 - process $group_4 - assign \add_o 66'000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - switch { $40 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - case 1'1 - assign \add_o $42 [65:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_24 + process $group_49 + assign \cnt_1_24 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_24 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_24 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_24 2'00 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" - cell $eq $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 1'1 - connect \Y $45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair50 + process $group_50 + assign \pair50 2'00 + assign \pair50 \sig_in [51:50] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" - cell $eq $48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_25 + process $group_51 + assign \cnt_1_25 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_25 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_25 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_25 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair52 + process $group_52 + assign \pair52 2'00 + assign \pair52 \sig_in [53:52] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_26 + process $group_53 + assign \cnt_1_26 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_26 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_26 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_26 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair54 + process $group_54 + assign \pair54 2'00 + assign \pair54 \sig_in [55:54] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_27 + process $group_55 + assign \cnt_1_27 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_27 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_27 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_27 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair56 + process $group_56 + assign \pair56 2'00 + assign \pair56 \sig_in [57:56] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_28 + process $group_57 + assign \cnt_1_28 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_28 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_28 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_28 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair58 + process $group_58 + assign \pair58 2'00 + assign \pair58 \sig_in [59:58] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_29 + process $group_59 + assign \cnt_1_29 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_29 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_29 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_29 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair60 + process $group_60 + assign \pair60 2'00 + assign \pair60 \sig_in [61:60] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_30 + process $group_61 + assign \cnt_1_30 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_30 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_30 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_30 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair62 + process $group_62 + assign \pair62 2'00 + assign \pair62 \sig_in [63:62] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_31 + process $group_63 + assign \cnt_1_31 2'00 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + case 2'00 + assign \cnt_1_31 2'10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" + case 2'01 + assign \cnt_1_31 2'01 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + case + assign \cnt_1_31 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 2'10 - connect \Y $47 + connect \A \cnt_1_1 [1] + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" - cell $eq $50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 3'100 - connect \Y $49 + connect \A \cnt_1_0 [1] + connect \B 1'1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - wire width 8 \eqs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115" - cell $reduce_or $52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $51 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_0 [0] } + connect \Y $5 end - process $group_5 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - assign \o \add_o [64:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \o \add_o [64:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" - switch { $45 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" - case 1'1 - assign \o { { \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] } \ra [7:0] } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" - switch { $47 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" - case 1'1 - assign \o { { \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] } \ra [15:0] } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" - switch { $49 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" + process $group_64 + assign \cnt_2_0 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" case 1'1 - assign \o { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } + assign \cnt_2_0 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_0 $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \o [0] $51 - end - sync init - end - process $group_6 - assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_0 { 1'0 \cnt_1_1 } end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - wire width 2 \ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:84" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:84" - cell $xor $54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [32] - connect \B \rb [32] - connect \Y $53 + connect \A \cnt_1_3 [1] + connect \B 1'1 + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:84" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:84" - cell $xor $56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \add_o [33] - connect \B $53 - connect \Y $55 - end - process $group_7 - assign \ca 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \ca [0] \add_o [65] - assign \ca [1] $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init + connect \A \cnt_1_2 [1] + connect \B 1'1 + connect \Y $9 end - process $group_8 - assign \xer_ca$20 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \xer_ca$20 \ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_2 [0] } + connect \Y $11 end - process $group_9 - assign \xer_ca_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \xer_ca_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 + process $group_65 + assign \cnt_2_2 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_2 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_2 $11 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_2 { 1'0 \cnt_1_3 } end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:88" - wire width 2 \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - cell $xor $58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ca [0] - connect \B \add_o [64] - connect \Y $57 + connect \A \cnt_1_5 [1] + connect \B 1'1 + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - wire width 1 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - cell $xor $61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [63] - connect \B \rb [63] - connect \Y $60 + connect \A \cnt_1_4 [1] + connect \B 1'1 + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - cell $not $62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_4 [0] } + connect \Y $17 + end + process $group_66 + assign \cnt_2_4 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $15 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_4 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_4 $17 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_4 { 1'0 \cnt_1_5 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $60 - connect \Y $59 + connect \A \cnt_1_7 [1] + connect \B 1'1 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - cell $and $64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $57 - connect \B $59 - connect \Y $63 + connect \A \cnt_1_6 [1] + connect \B 1'1 + connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - cell $xor $66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_6 [0] } + connect \Y $23 + end + process $group_67 + assign \cnt_2_6 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $19 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $21 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_6 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_6 $23 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_6 { 1'0 \cnt_1_7 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $26 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ca [1] - connect \B \add_o [32] - connect \Y $65 + connect \A \cnt_1_9 [1] + connect \B 1'1 + connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - wire width 1 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - cell $xor $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [31] - connect \B \rb [31] - connect \Y $68 + connect \A \cnt_1_8 [1] + connect \B 1'1 + connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - cell $not $70 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_8 [0] } + connect \Y $29 + end + process $group_68 + assign \cnt_2_8 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $27 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_8 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_8 $29 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_8 { 1'0 \cnt_1_9 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $68 - connect \Y $67 + connect \A \cnt_1_11 [1] + connect \B 1'1 + connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16" - cell $and $72 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $65 - connect \B $67 - connect \Y $71 - end - process $group_10 - assign \ov 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \ov [0] $63 - assign \ov [1] $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - process $group_11 - assign \xer_ov 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \xer_ov \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init + connect \A \cnt_1_10 [1] + connect \B 1'1 + connect \Y $33 end - process $group_12 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \xer_ov_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_10 [0] } + connect \Y $35 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:111" - wire width 8 \src1 - process $group_13 - assign \src1 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \src1 \ra [7:0] + process $group_69 + assign \cnt_2_10 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $31 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $33 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_10 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_10 $35 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_10 { 1'0 \cnt_1_11 } end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $eq $74 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $38 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [7:0] - connect \Y $73 + connect \A \cnt_1_13 [1] + connect \B 1'1 + connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $eq $76 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $40 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [15:8] - connect \Y $75 + connect \A \cnt_1_12 [1] + connect \B 1'1 + connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $eq $78 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $42 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_12 [0] } + connect \Y $41 + end + process $group_70 + assign \cnt_2_12 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $37 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $39 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_12 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_12 $41 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_12 { 1'0 \cnt_1_13 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [23:16] - connect \Y $77 + connect \A \cnt_1_15 [1] + connect \B 1'1 + connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $eq $80 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $46 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [31:24] - connect \Y $79 + connect \A \cnt_1_14 [1] + connect \B 1'1 + connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $eq $82 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $48 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_14 [0] } + connect \Y $47 + end + process $group_71 + assign \cnt_2_14 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $43 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $45 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_14 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_14 $47 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_14 { 1'0 \cnt_1_15 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [39:32] - connect \Y $81 + connect \A \cnt_1_17 [1] + connect \B 1'1 + connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $eq $84 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $52 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [47:40] - connect \Y $83 + connect \A \cnt_1_16 [1] + connect \B 1'1 + connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $eq $86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $54 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_16 [0] } + connect \Y $53 + end + process $group_72 + assign \cnt_2_16 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $49 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $51 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_16 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_16 $53 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_16 { 1'0 \cnt_1_17 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [55:48] - connect \Y $85 + connect \A \cnt_1_19 [1] + connect \B 1'1 + connect \Y $55 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $eq $88 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $58 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [63:56] - connect \Y $87 + connect \A \cnt_1_18 [1] + connect \B 1'1 + connect \Y $57 end - process $group_14 - assign \eqs 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \eqs [0] $73 - assign \eqs [1] $75 - assign \eqs [2] $77 - assign \eqs [3] $79 - assign \eqs [4] $81 - assign \eqs [5] $83 - assign \eqs [6] $85 - assign \eqs [7] $87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_18 [0] } + connect \Y $59 + end + process $group_73 + assign \cnt_2_18 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $55 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $57 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_18 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_18 $59 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_18 { 1'0 \cnt_1_19 } end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" - cell $reduce_or $90 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $62 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $89 + connect \A \cnt_1_21 [1] + connect \B 1'1 + connect \Y $61 end - process $group_15 - assign \cr_a 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \cr_a { 1'0 $89 2'00 } - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_20 [1] + connect \B 1'1 + connect \Y $63 end - process $group_16 - assign \cr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:64" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:75" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \cr_a_ok 1'1 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_20 [0] } + connect \Y $65 end - process $group_17 - assign \xer_so$21 1'0 - assign \xer_so$21 \xer_so + process $group_74 + assign \cnt_2_20 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $61 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $63 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_20 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_20 $65 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_20 { 1'0 \cnt_1_21 } + end sync init end - process $group_18 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_23 [1] + connect \B 1'1 + connect \Y $67 end - process $group_19 - assign \alu_op__insn_type$2 7'0000000 - assign \alu_op__fn_unit$3 11'00000000000 - assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$5 1'0 - assign \alu_op__rc__rc$6 1'0 - assign \alu_op__rc__rc_ok$7 1'0 - assign \alu_op__oe__oe$8 1'0 - assign \alu_op__oe__oe_ok$9 1'0 - assign \alu_op__invert_a$10 1'0 - assign \alu_op__zero_a$11 1'0 - assign \alu_op__invert_out$12 1'0 - assign \alu_op__write_cr0$13 1'0 - assign \alu_op__input_carry$14 2'00 - assign \alu_op__output_carry$15 1'0 - assign \alu_op__is_32bit$16 1'0 - assign \alu_op__is_signed$17 1'0 - assign \alu_op__data_len$18 4'0000 - assign \alu_op__insn$19 32'00000000000000000000000000000000 - assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_a$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_22 [1] + connect \B 1'1 + connect \Y $69 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_22 [0] } + connect \Y $71 + end + process $group_75 + assign \cnt_2_22 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $67 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $69 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_22 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_22 $71 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_22 { 1'0 \cnt_1_23 } + end sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.output" -module \output - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \alu_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \alu_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \alu_op__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 23 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 24 \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 25 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 26 \alu_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 27 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 28 \alu_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \alu_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \alu_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \alu_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \alu_op__invert_a$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \alu_op__write_cr0$13 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 38 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 42 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 43 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 44 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 45 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 46 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 50 \xer_ov$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 51 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 52 \xer_so$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 53 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 65 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 64 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $not $29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $74 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $28 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_25 [1] + connect \B 1'1 + connect \Y $73 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $pos $30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $76 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A $28 - connect \Y $27 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_24 [1] + connect \B 1'1 + connect \Y $75 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $78 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $31 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_24 [0] } + connect \Y $77 end - process $group_0 - assign \o$26 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" - switch { \alu_op__invert_out } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + process $group_76 + assign \cnt_2_24 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $73 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" case 1'1 - assign \o$26 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_24 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_24 $77 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" case - assign \o$26 $31 + assign \cnt_2_24 { 1'0 \cnt_1_25 } end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" - wire width 64 \target - process $group_1 - assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$26 [63:0] - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_27 [1] + connect \B 1'1 + connect \Y $79 end - process $group_2 - assign \xer_ca$23 2'00 - assign \xer_ca$23 \xer_ca - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_26 [1] + connect \B 1'1 + connect \Y $81 end - process $group_3 - assign \xer_ca_ok 1'0 - assign \xer_ca_ok \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_26 [0] } + connect \Y $83 + end + process $group_77 + assign \cnt_2_26 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $79 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_26 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_26 $83 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_26 { 1'0 \cnt_1_27 } + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" - wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $86 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $33 - end - process $group_4 - assign \is_cmp 1'0 - assign \is_cmp $33 - sync init + connect \A \cnt_1_29 [1] + connect \B 1'1 + connect \Y $85 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" - wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $88 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001100 - connect \Y $35 + connect \A \cnt_1_28 [1] + connect \B 1'1 + connect \Y $87 end - process $group_5 - assign \is_cmpeqb 1'0 - assign \is_cmpeqb $35 - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_28 [0] } + connect \Y $89 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" - wire width 1 \msb_test - process $group_6 - assign \msb_test 1'0 - assign \msb_test \target [63] + process $group_78 + assign \cnt_2_28 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $85 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_28 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_28 $89 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_28 { 1'0 \cnt_1_29 } + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $38 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $92 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \target - connect \Y $37 + connect \A \cnt_1_31 [1] + connect \B 1'1 + connect \Y $91 end - process $group_7 - assign \is_nzero 1'0 - assign \is_nzero $37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_30 [1] + connect \B 1'1 + connect \Y $93 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 $95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { 1'1 \cnt_1_30 [0] } + connect \Y $95 + end + process $group_79 + assign \cnt_2_30 3'000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $91 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $93 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_2_30 { 1'1 { 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_2_30 $95 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_2_30 { 1'0 \cnt_1_31 } + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" - wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $98 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $39 + connect \A \cnt_2_2 [2] + connect \B 1'1 + connect \Y $97 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $39 - connect \Y $41 + connect \A \cnt_2_0 [2] + connect \B 1'1 + connect \Y $99 end - process $group_8 - assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 $101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'1 \cnt_2_0 [1:0] } + connect \Y $101 + end + process $group_80 + assign \cnt_3_0 4'0000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $97 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $99 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_3_0 { 1'1 { 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_3_0 $101 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" case - assign \is_positive $41 + assign \cnt_3_0 { 1'0 \cnt_2_2 } end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $43 + connect \A \cnt_2_6 [2] + connect \B 1'1 + connect \Y $103 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $43 - connect \Y $45 + connect \A \cnt_2_4 [2] + connect \B 1'1 + connect \Y $105 end - process $group_9 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 $107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'1 \cnt_2_4 [1:0] } + connect \Y $107 + end + process $group_81 + assign \cnt_3_2 4'0000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $103 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" case 1'1 - assign \is_negative $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $105 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_3_2 { 1'1 { 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_3_2 $107 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" case - assign \is_negative \msb_test + assign \cnt_3_2 { 1'0 \cnt_2_6 } end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - cell $not $48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $47 + connect \A \cnt_2_10 [2] + connect \B 1'1 + connect \Y $109 end - process $group_10 - assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_8 [2] + connect \B 1'1 + connect \Y $111 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 $113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'1 \cnt_2_8 [1:0] } + connect \Y $113 + end + process $group_82 + assign \cnt_3_4 4'0000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $109 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" case 1'1 - assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $111 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_3_4 { 1'1 { 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_3_4 $113 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" case - assign \cr0 { \is_negative \is_positive $47 \xer_so$25 } + assign \cnt_3_4 { 1'0 \cnt_2_10 } end sync init end - process $group_11 - assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$20 \o$26 [63:0] - sync init - end - process $group_12 - assign \o_ok$21 1'0 - assign \o_ok$21 \o_ok - sync init - end - process $group_13 - assign \cr_a$22 4'0000 - assign \cr_a$22 \cr0 - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_14 [2] + connect \B 1'1 + connect \Y $115 end - process $group_14 - assign \cr_a_ok 1'0 - assign \cr_a_ok \alu_op__write_cr0 - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_12 [2] + connect \B 1'1 + connect \Y $117 end - process $group_15 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 $119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'1 \cnt_2_12 [1:0] } + connect \Y $119 end - process $group_16 - assign \alu_op__insn_type$2 7'0000000 - assign \alu_op__fn_unit$3 11'00000000000 - assign \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$5 1'0 - assign \alu_op__rc__rc$6 1'0 - assign \alu_op__rc__rc_ok$7 1'0 - assign \alu_op__oe__oe$8 1'0 - assign \alu_op__oe__oe_ok$9 1'0 - assign \alu_op__invert_a$10 1'0 - assign \alu_op__zero_a$11 1'0 - assign \alu_op__invert_out$12 1'0 - assign \alu_op__write_cr0$13 1'0 - assign \alu_op__input_carry$14 2'00 - assign \alu_op__output_carry$15 1'0 - assign \alu_op__is_32bit$16 1'0 - assign \alu_op__is_signed$17 1'0 - assign \alu_op__data_len$18 4'0000 - assign \alu_op__insn$19 32'00000000000000000000000000000000 - assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_a$10 { \alu_op__oe__oe_ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__rc_ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } + process $group_83 + assign \cnt_3_6 4'0000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $115 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $117 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_3_6 { 1'1 { 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_3_6 $119 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_3_6 { 1'0 \cnt_2_14 } + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" - wire width 1 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - cell $and $50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_op__oe__oe - connect \B \alu_op__oe__oe_ok - connect \Y $49 - end - process $group_34 - assign \oe 1'0 - assign \oe $49 - sync init + connect \A \cnt_2_18 [2] + connect \B 1'1 + connect \Y $121 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" - wire width 1 \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - cell $or $52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $51 + connect \A \cnt_2_16 [2] + connect \B 1'1 + connect \Y $123 end - process $group_35 - assign \so 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \so $51 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 $125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'1 \cnt_2_16 [1:0] } + connect \Y $125 end - process $group_36 - assign \xer_so$25 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + process $group_84 + assign \cnt_3_8 4'0000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $121 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" case 1'1 - assign \xer_so$25 \so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $123 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_3_8 { 1'1 { 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_3_8 $125 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_3_8 { 1'0 \cnt_2_18 } end sync init end - process $group_37 - assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_so_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_22 [2] + connect \B 1'1 + connect \Y $127 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_20 [2] + connect \B 1'1 + connect \Y $129 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 $131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'1 \cnt_2_20 [1:0] } + connect \Y $131 + end + process $group_85 + assign \cnt_3_10 4'0000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $127 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $129 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_3_10 { 1'1 { 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_3_10 $131 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_3_10 { 1'0 \cnt_2_22 } end sync init end - process $group_38 - assign \xer_ov$24 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $133 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_26 [2] + connect \B 1'1 + connect \Y $133 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $135 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_24 [2] + connect \B 1'1 + connect \Y $135 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 $137 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'1 \cnt_2_24 [1:0] } + connect \Y $137 + end + process $group_86 + assign \cnt_3_12 4'0000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $133 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" case 1'1 - assign \xer_ov$24 \xer_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $135 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_3_12 { 1'1 { 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_3_12 $137 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_3_12 { 1'0 \cnt_2_26 } end sync init end - process $group_39 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $139 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_30 [2] + connect \B 1'1 + connect \Y $139 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $141 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_28 [2] + connect \B 1'1 + connect \Y $141 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 4 $143 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A { 1'1 \cnt_2_28 [1:0] } + connect \Y $143 + end + process $group_87 + assign \cnt_3_14 4'0000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $139 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" case 1'1 - assign \xer_ov_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $141 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_3_14 { 1'1 { 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_3_14 $143 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_3_14 { 1'0 \cnt_2_30 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $145 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_2 [3] + connect \B 1'1 + connect \Y $145 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $147 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_0 [3] + connect \B 1'1 + connect \Y $147 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 5 $149 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'1 \cnt_3_0 [2:0] } + connect \Y $149 + end + process $group_88 + assign \cnt_4_0 5'00000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $145 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $147 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_4_0 { 1'1 { 1'0 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_4_0 $149 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_4_0 { 1'0 \cnt_3_2 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $151 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_6 [3] + connect \B 1'1 + connect \Y $151 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $153 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_4 [3] + connect \B 1'1 + connect \Y $153 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 5 $155 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'1 \cnt_3_4 [2:0] } + connect \Y $155 + end + process $group_89 + assign \cnt_4_2 5'00000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $151 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $153 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_4_2 { 1'1 { 1'0 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_4_2 $155 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_4_2 { 1'0 \cnt_3_6 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $157 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_10 [3] + connect \B 1'1 + connect \Y $157 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $159 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_8 [3] + connect \B 1'1 + connect \Y $159 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 5 $161 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'1 \cnt_3_8 [2:0] } + connect \Y $161 + end + process $group_90 + assign \cnt_4_4 5'00000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $157 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $159 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_4_4 { 1'1 { 1'0 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_4_4 $161 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_4_4 { 1'0 \cnt_3_10 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $163 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_14 [3] + connect \B 1'1 + connect \Y $163 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $165 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_12 [3] + connect \B 1'1 + connect \Y $165 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 5 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A { 1'1 \cnt_3_12 [2:0] } + connect \Y $167 + end + process $group_91 + assign \cnt_4_6 5'00000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $163 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $165 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_4_6 { 1'1 { 1'0 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_4_6 $167 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_4_6 { 1'0 \cnt_3_14 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 6 \cnt_5_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_2 [4] + connect \B 1'1 + connect \Y $169 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $171 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_0 [4] + connect \B 1'1 + connect \Y $171 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 6 $173 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A { 1'1 \cnt_4_0 [3:0] } + connect \Y $173 + end + process $group_92 + assign \cnt_5_0 6'000000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $169 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $171 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_5_0 { 1'1 { 1'0 1'0 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_5_0 $173 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_5_0 { 1'0 \cnt_4_2 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 6 \cnt_5_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $175 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_6 [4] + connect \B 1'1 + connect \Y $175 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $177 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_4 [4] + connect \B 1'1 + connect \Y $177 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 6 $179 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A { 1'1 \cnt_4_4 [3:0] } + connect \Y $179 + end + process $group_93 + assign \cnt_5_2 6'000000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $175 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $177 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_5_2 { 1'1 { 1'0 1'0 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_5_2 $179 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_5_2 { 1'0 \cnt_4_6 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 7 \cnt_6_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire width 1 $181 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_2 [5] + connect \B 1'1 + connect \Y $181 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire width 1 $183 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_0 [5] + connect \B 1'1 + connect \Y $183 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 7 $185 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A { 1'1 \cnt_5_0 [4:0] } + connect \Y $185 + end + process $group_94 + assign \cnt_6_0 7'0000000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch { $181 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch { $183 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + case 1'1 + assign \cnt_6_0 { 1'1 { 1'0 1'0 1'0 1'0 1'0 1'0 } } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + case + assign \cnt_6_0 $185 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + case + assign \cnt_6_0 { 1'0 \cnt_5_2 } end sync init end + process $group_95 + assign \lz 7'0000000 + assign \lz \cnt_6_0 + sync init + end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe" -module \pipe - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main" +module \main$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -45804,7 +32122,7 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \alu_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -45818,59 +32136,49 @@ module \pipe attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \alu_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__imm_data__imm_ok + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \alu_op__rc__rc + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \alu_op__rc__rc_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \alu_op__oe__oe + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \alu_op__oe__oe_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \alu_op__invert_a + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \alu_op__zero_a + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \alu_op__invert_out + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \alu_op__write_cr0 + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 17 \alu_op__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \alu_op__output_carry + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \alu_op__is_32bit + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \alu_op__is_signed + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \alu_op__data_len + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 25 \xer_so + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 26 \xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 27 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 28 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 29 \muxid$1 + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next + wire width 2 output 21 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -45945,9 +32253,7 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 30 \alu_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$2$next + wire width 7 output 22 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -45961,1320 +32267,1589 @@ module \pipe attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 31 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 32 \alu_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \alu_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \alu_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \alu_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe_ok$9$next + wire width 11 output 23 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \alu_op__invert_a$10 + wire width 64 output 24 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_a$10$next + wire width 1 output 25 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \alu_op__zero_a$11 + wire width 1 output 26 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__zero_a$11$next + wire width 1 output 27 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \alu_op__invert_out$12 + wire width 1 output 28 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_out$12$next + wire width 1 output 29 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \alu_op__write_cr0$13 + wire width 1 output 30 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__write_cr0$13$next + wire width 1 output 31 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 42 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \alu_op__is_32bit$16 + wire width 2 output 32 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_32bit$16$next + wire width 1 output 33 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \alu_op__is_signed$17 + wire width 1 output 34 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_signed$17$next + wire width 1 output 35 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 46 \alu_op__data_len$18 + wire width 1 output 36 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$18$next + wire width 1 output 37 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 47 \alu_op__insn$19 + wire width 4 output 38 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 48 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 50 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 51 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 52 \xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 53 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 54 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 55 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 56 \xer_so$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$21$next + wire width 32 output 39 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 57 \xer_so_ok + wire width 64 output 40 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$next - cell \p$2 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o + wire width 1 output 41 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" + wire width 64 \bpermd_rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" + wire width 64 \bpermd_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" + wire width 64 \bpermd_ra + cell \bpermd \bpermd + connect \rs \bpermd_rs + connect \rb \bpermd_rb + connect \ra \bpermd_ra end - cell \n$3 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" + wire width 64 \popcount_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" + wire width 64 \popcount_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" + wire width 64 \popcount_o + cell \popcount \popcount + connect \a \popcount_a + connect \data_len \popcount_data_len + connect \o \popcount_o end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \input_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$22 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute 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\enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_alu_op__insn_type$23 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_alu_op__fn_unit$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__imm$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__imm_data__imm_ok$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__rc__rc$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__rc__rc_ok$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__oe__oe$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__oe__oe_ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__invert_a$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__zero_a$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__invert_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__write_cr0$34 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_alu_op__input_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__output_carry$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__is_32bit$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_alu_op__is_signed$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_alu_op__insn$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \input_xer_so$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$44 - cell \input \input - connect \muxid \input_muxid - connect \alu_op__insn_type \input_alu_op__insn_type - connect \alu_op__fn_unit \input_alu_op__fn_unit - connect \alu_op__imm_data__imm \input_alu_op__imm_data__imm - connect \alu_op__imm_data__imm_ok \input_alu_op__imm_data__imm_ok - connect \alu_op__rc__rc \input_alu_op__rc__rc - connect \alu_op__rc__rc_ok \input_alu_op__rc__rc_ok - connect \alu_op__oe__oe \input_alu_op__oe__oe - connect \alu_op__oe__oe_ok \input_alu_op__oe__oe_ok - connect \alu_op__invert_a \input_alu_op__invert_a - connect \alu_op__zero_a \input_alu_op__zero_a - connect \alu_op__invert_out \input_alu_op__invert_out - connect \alu_op__write_cr0 \input_alu_op__write_cr0 - connect \alu_op__input_carry \input_alu_op__input_carry - connect \alu_op__output_carry \input_alu_op__output_carry - connect \alu_op__is_32bit \input_alu_op__is_32bit - connect \alu_op__is_signed \input_alu_op__is_signed - connect \alu_op__data_len \input_alu_op__data_len - connect \alu_op__insn \input_alu_op__insn - connect \ra \input_ra - connect \rb \input_rb - connect \xer_so \input_xer_so - connect \xer_ca \input_xer_ca - connect \muxid$1 \input_muxid$22 - connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 - connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 - connect \alu_op__imm_data__imm$4 \input_alu_op__imm_data__imm$25 - connect \alu_op__imm_data__imm_ok$5 \input_alu_op__imm_data__imm_ok$26 - connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 - connect \alu_op__rc__rc_ok$7 \input_alu_op__rc__rc_ok$28 - connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 - connect \alu_op__oe__oe_ok$9 \input_alu_op__oe__oe_ok$30 - connect \alu_op__invert_a$10 \input_alu_op__invert_a$31 - connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 - connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 - connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 - connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 - connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 - connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 - connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 - connect \alu_op__data_len$18 \input_alu_op__data_len$39 - connect \alu_op__insn$19 \input_alu_op__insn$40 - connect \ra$20 \input_ra$41 - connect \rb$21 \input_rb$42 - connect \xer_so$22 \input_xer_so$43 - connect \xer_ca$23 \input_xer_ca$44 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \main_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$45 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 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wire width 1 \output_alu_op__output_carry$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__is_32bit$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__is_signed$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_alu_op__insn$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so_ok - cell \output \output - connect \muxid \output_muxid - connect \alu_op__insn_type \output_alu_op__insn_type - connect \alu_op__fn_unit \output_alu_op__fn_unit - connect \alu_op__imm_data__imm \output_alu_op__imm_data__imm - connect \alu_op__imm_data__imm_ok \output_alu_op__imm_data__imm_ok - connect \alu_op__rc__rc \output_alu_op__rc__rc - connect \alu_op__rc__rc_ok \output_alu_op__rc__rc_ok - connect \alu_op__oe__oe \output_alu_op__oe__oe - connect \alu_op__oe__oe_ok \output_alu_op__oe__oe_ok - connect \alu_op__invert_a \output_alu_op__invert_a - connect \alu_op__zero_a \output_alu_op__zero_a - connect \alu_op__invert_out \output_alu_op__invert_out - connect \alu_op__write_cr0 \output_alu_op__write_cr0 - connect \alu_op__input_carry \output_alu_op__input_carry - connect \alu_op__output_carry \output_alu_op__output_carry - connect \alu_op__is_32bit \output_alu_op__is_32bit - connect \alu_op__is_signed \output_alu_op__is_signed - connect \alu_op__data_len \output_alu_op__data_len - connect \alu_op__insn \output_alu_op__insn - connect \o \output_o - connect \o_ok \output_o_ok - connect \cr_a \output_cr_a - connect \xer_ca \output_xer_ca - connect \xer_ov \output_xer_ov - connect \xer_so \output_xer_so - connect \muxid$1 \output_muxid$66 - connect \alu_op__insn_type$2 \output_alu_op__insn_type$67 - connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$68 - connect \alu_op__imm_data__imm$4 \output_alu_op__imm_data__imm$69 - connect \alu_op__imm_data__imm_ok$5 \output_alu_op__imm_data__imm_ok$70 - connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$71 - connect \alu_op__rc__rc_ok$7 \output_alu_op__rc__rc_ok$72 - connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$73 - connect \alu_op__oe__oe_ok$9 \output_alu_op__oe__oe_ok$74 - connect \alu_op__invert_a$10 \output_alu_op__invert_a$75 - connect \alu_op__zero_a$11 \output_alu_op__zero_a$76 - connect \alu_op__invert_out$12 \output_alu_op__invert_out$77 - connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$78 - connect \alu_op__input_carry$14 \output_alu_op__input_carry$79 - connect \alu_op__output_carry$15 \output_alu_op__output_carry$80 - connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$81 - connect \alu_op__is_signed$17 \output_alu_op__is_signed$82 - connect \alu_op__data_len$18 \output_alu_op__data_len$83 - connect \alu_op__insn$19 \output_alu_op__insn$84 - connect \o$20 \output_o$85 - connect \o_ok$21 \output_o_ok$86 - connect \cr_a$22 \output_cr_a$87 - connect \cr_a_ok \output_cr_a_ok - connect \xer_ca$23 \output_xer_ca$88 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_ov$24 \output_xer_ov$89 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so$25 \output_xer_so$90 - connect \xer_so_ok \output_xer_so_ok - end - process $group_0 - assign \input_muxid 2'00 - assign \input_muxid \muxid - sync init - end - process $group_1 - assign \input_alu_op__insn_type 7'0000000 - assign \input_alu_op__fn_unit 11'00000000000 - assign \input_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_alu_op__imm_data__imm_ok 1'0 - assign \input_alu_op__rc__rc 1'0 - assign \input_alu_op__rc__rc_ok 1'0 - assign \input_alu_op__oe__oe 1'0 - assign \input_alu_op__oe__oe_ok 1'0 - assign \input_alu_op__invert_a 1'0 - assign \input_alu_op__zero_a 1'0 - assign \input_alu_op__invert_out 1'0 - assign \input_alu_op__write_cr0 1'0 - assign \input_alu_op__input_carry 2'00 - assign \input_alu_op__output_carry 1'0 - assign \input_alu_op__is_32bit 1'0 - assign \input_alu_op__is_signed 1'0 - assign \input_alu_op__data_len 4'0000 - assign \input_alu_op__insn 32'00000000000000000000000000000000 - assign { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_a { \input_alu_op__oe__oe_ok \input_alu_op__oe__oe } { \input_alu_op__rc__rc_ok \input_alu_op__rc__rc } { \input_alu_op__imm_data__imm_ok \input_alu_op__imm_data__imm } \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } - sync init - end - process $group_19 - assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_ra \ra - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" + wire width 64 \clz_sig_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + wire width 7 \clz_lz + cell \clz \clz + connect \sig_in \clz_sig_in + connect \lz \clz_lz end - process $group_20 - assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_rb \rb - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" + wire width 64 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" + cell $and $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $20 end - process $group_21 - assign \input_xer_so 1'0 - assign \input_xer_so \xer_so - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" + wire width 64 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" + cell $or $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $22 end - process $group_22 - assign \input_xer_ca 2'00 - assign \input_xer_ca \xer_ca - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" + wire width 64 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" + cell $xor $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $24 end - process $group_23 - assign \main_muxid 2'00 - assign \main_muxid \input_muxid$22 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $26 end - process $group_24 - assign \main_alu_op__insn_type 7'0000000 - assign \main_alu_op__fn_unit 11'00000000000 - assign \main_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_alu_op__imm_data__imm_ok 1'0 - assign \main_alu_op__rc__rc 1'0 - assign \main_alu_op__rc__rc_ok 1'0 - assign \main_alu_op__oe__oe 1'0 - assign \main_alu_op__oe__oe_ok 1'0 - assign \main_alu_op__invert_a 1'0 - assign \main_alu_op__zero_a 1'0 - assign \main_alu_op__invert_out 1'0 - assign \main_alu_op__write_cr0 1'0 - assign \main_alu_op__input_carry 2'00 - assign \main_alu_op__output_carry 1'0 - assign \main_alu_op__is_32bit 1'0 - assign \main_alu_op__is_signed 1'0 - assign \main_alu_op__data_len 4'0000 - assign \main_alu_op__insn 32'00000000000000000000000000000000 - assign { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_a { \main_alu_op__oe__oe_ok \main_alu_op__oe__oe } { \main_alu_op__rc__rc_ok \main_alu_op__rc__rc } { \main_alu_op__imm_data__imm_ok \main_alu_op__imm_data__imm } \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_a$31 { \input_alu_op__oe__oe_ok$30 \input_alu_op__oe__oe$29 } { \input_alu_op__rc__rc_ok$28 \input_alu_op__rc__rc$27 } { \input_alu_op__imm_data__imm_ok$26 \input_alu_op__imm_data__imm$25 } \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $28 end - process $group_42 - assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \input_ra$41 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $30 end - process $group_43 - assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \input_rb$42 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $32 end - process $group_44 - assign \main_xer_so 1'0 - assign \main_xer_so \input_xer_so$43 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $34 end - process $group_45 - assign \main_xer_ca 2'00 - assign \main_xer_ca \input_xer_ca$44 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $36 end - process $group_46 - assign \output_muxid 2'00 - assign \output_muxid \main_muxid$45 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $38 end - process $group_47 - assign \output_alu_op__insn_type 7'0000000 - assign \output_alu_op__fn_unit 11'00000000000 - assign \output_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_alu_op__imm_data__imm_ok 1'0 - assign \output_alu_op__rc__rc 1'0 - assign \output_alu_op__rc__rc_ok 1'0 - assign \output_alu_op__oe__oe 1'0 - assign \output_alu_op__oe__oe_ok 1'0 - assign \output_alu_op__invert_a 1'0 - assign \output_alu_op__zero_a 1'0 - assign \output_alu_op__invert_out 1'0 - assign \output_alu_op__write_cr0 1'0 - assign \output_alu_op__input_carry 2'00 - assign \output_alu_op__output_carry 1'0 - assign \output_alu_op__is_32bit 1'0 - assign \output_alu_op__is_signed 1'0 - assign \output_alu_op__data_len 4'0000 - assign \output_alu_op__insn 32'00000000000000000000000000000000 - assign { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_a { \output_alu_op__oe__oe_ok \output_alu_op__oe__oe } { \output_alu_op__rc__rc_ok \output_alu_op__rc__rc } { \output_alu_op__imm_data__imm_ok \output_alu_op__imm_data__imm } \output_alu_op__fn_unit \output_alu_op__insn_type } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_a$54 { \main_alu_op__oe__oe_ok$53 \main_alu_op__oe__oe$52 } { \main_alu_op__rc__rc_ok$51 \main_alu_op__rc__rc$50 } { \main_alu_op__imm_data__imm_ok$49 \main_alu_op__imm_data__imm$48 } \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $40 end - process $group_65 - assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_o_ok 1'0 - assign { \output_o_ok \output_o } { \main_o_ok \main_o } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $42 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$91 - process $group_67 - assign \output_cr_a 4'0000 - assign \cr_a_ok$91 1'0 - assign { \cr_a_ok$91 \output_cr_a } { \main_cr_a_ok \main_cr_a } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $44 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$92 - process $group_69 - assign \output_xer_ca 2'00 - assign \xer_ca_ok$92 1'0 - assign { \xer_ca_ok$92 \output_xer_ca } { \main_xer_ca_ok \main_xer_ca$64 } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $46 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$93 - process $group_71 - assign \output_xer_ov 2'00 - assign \xer_ov_ok$93 1'0 - assign { \xer_ov_ok$93 \output_xer_ov } { \main_xer_ov_ok \main_xer_ov } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $48 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$95 - process $group_73 - assign \output_xer_so 1'0 - assign \xer_so_ok$94 1'0 - assign { \xer_so_ok$94 \output_xer_so } { \xer_so_ok$95 \main_xer_so$65 } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $50 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$96 - process $group_75 - assign \p_valid_i$96 1'0 - assign \p_valid_i$96 \p_valid_i - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $52 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_76 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $54 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $57 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 8 parameter \Y_WIDTH 1 - connect \A \p_valid_i$96 - connect \B \p_ready_o - connect \Y $97 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $56 end - process $group_77 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $97 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $58 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$99 - process $group_78 - assign \muxid$99 2'00 - assign \muxid$99 \output_muxid$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $60 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $62 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $65 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $64 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $66 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $68 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $70 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $74 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $76 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $78 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $81 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $80 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $83 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $82 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $84 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $86 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $88 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $90 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $92 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $94 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $96 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $98 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $100 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $102 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $104 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $106 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $108 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $110 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $112 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $114 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $116 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $118 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $120 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $122 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $124 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $126 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $128 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $130 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $132 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $134 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $136 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $138 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $140 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $142 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $144 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $146 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $148 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $150 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + wire width 1 $152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $152 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + wire width 1 $154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + cell $eq $155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__data_len [3] + connect \B 1'1 + connect \Y $154 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + wire width 64 $156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" + wire width 1 \par0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" + wire width 1 \par1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + wire width 1 $157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $xor $158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \par0 + connect \B \par1 + connect \Y $157 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 64 + connect \A $157 + connect \Y $156 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + wire width 64 $160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + wire width 8 $161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $sub $162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \B 6'100000 + connect \Y $161 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + wire width 8 $163 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + cell $pos $164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \Y $163 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + wire width 8 $165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $mux $166 + parameter \WIDTH 8 + connect \A $163 + connect \B $161 + connect \S \logical_op__is_32bit + connect \Y $165 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A $165 + connect \Y $160 + end + process $group_1 + assign \o_ok 1'0 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + assign \o $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + assign \o $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + assign \o $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + assign \o { { $138 $140 $142 $144 $146 $148 $150 $152 } { $122 $124 $126 $128 $130 $132 $134 $136 } { $106 $108 $110 $112 $114 $116 $118 $120 } { $90 $92 $94 $96 $98 $100 $102 $104 } { $74 $76 $78 $80 $82 $84 $86 $88 } { $58 $60 $62 $64 $66 $68 $70 $72 } { $42 $44 $46 $48 $50 $52 $54 $56 } { $26 $28 $30 $32 $34 $36 $38 $40 } } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + assign \o \popcount_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + switch { $154 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + case 1'1 + assign \o $156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:90" + case + assign { \o_ok \o } [0] \par0 + assign { \o_ok \o } [32] \par1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + assign \o $160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + assign \o \bpermd_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + assign \o_ok 1'0 + end + sync init + end + process $group_2 + assign \popcount_a 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + assign \popcount_a \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28" + wire width 64 \b + process $group_3 + assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + assign \b \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 $168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 64 + connect \A \logical_op__data_len + connect \Y $168 + end + process $group_4 + assign \popcount_data_len 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + assign \popcount_data_len $168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" + wire width 1 $170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" + cell $reduce_xor $171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } + connect \Y $170 + end + process $group_5 + assign \par0 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + assign \par0 $170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" + wire width 1 $172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" + cell $reduce_xor $173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } + connect \Y $172 + end + process $group_6 + assign \par1 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + assign \par1 $172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" + wire width 1 \count_right + process $group_7 + assign \count_right 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + assign \count_right { \logical_op__insn [10] \logical_op__insn [9] \logical_op__insn [8] \logical_op__insn [7] \logical_op__insn [6] \logical_op__insn [5] \logical_op__insn [4] \logical_op__insn [3] \logical_op__insn [2] \logical_op__insn [1] } [9] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:103" + wire width 32 \a32 + process $group_8 + assign \a32 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + assign \a32 \ra [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" + wire width 64 \cntz_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + wire width 64 $174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + wire width 32 $175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $mux $176 + parameter \WIDTH 32 + connect \A \a32 + connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } + connect \S \count_right + connect \Y $175 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A $175 + connect \Y $174 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" + wire width 64 $178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" + cell $mux $179 + parameter \WIDTH 64 + connect \A \ra + connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } + connect \S \count_right + connect \Y $178 + end + process $group_9 + assign \cntz_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" + switch { \logical_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" + case 1'1 + assign \cntz_i $174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:108" + case + assign \cntz_i $178 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + process $group_10 + assign \clz_sig_in 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + assign \clz_sig_in \cntz_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + process $group_11 + assign \bpermd_rs 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + assign \bpermd_rs \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + process $group_12 + assign \bpermd_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" + attribute \nmigen.decoding "OP_AND/4" + case 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" + attribute \nmigen.decoding "OP_OR/53" + case 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" + attribute \nmigen.decoding "OP_XOR/67" + case 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" + attribute \nmigen.decoding "OP_CMPB/11" + case 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" + attribute \nmigen.decoding "OP_POPCNT/54" + case 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" + attribute \nmigen.decoding "OP_PRTY/55" + case 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" + attribute \nmigen.decoding "OP_CNTZ/14" + case 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" + attribute \nmigen.decoding "OP_BPERM/9" + case 7'0001001 + assign \bpermd_rb \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" + attribute \nmigen.decoding "" + case + end + sync init + end + process $group_13 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_14 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1" +module \logical_pipe1 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -47349,7 +33924,9 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$100 + wire width 7 output 5 \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -47363,396 +33940,107 @@ module \pipe attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_op__fn_unit$101 + wire width 11 output 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__imm$102 + wire width 11 \logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__imm_ok$103 + wire width 64 output 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc$104 + wire width 64 \logical_op__imm_data__imm$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc_ok$105 + wire width 1 output 8 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe$106 + wire width 1 \logical_op__imm_data__imm_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe_ok$107 + wire width 1 output 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_a$108 + wire width 1 \logical_op__rc__rc$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__zero_a$109 + wire width 1 output 10 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_out$110 + wire width 1 \logical_op__rc__rc_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__write_cr0$111 - attribute \enum_base_type "CryIn" + wire width 1 output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$next + attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$112 + wire width 2 output 15 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__output_carry$113 + wire width 2 \logical_op__input_carry$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_32bit$114 + wire width 1 output 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_signed$115 + wire width 1 \logical_op__invert_out$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$116 + wire width 1 output 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$117 - process $group_79 - assign \alu_op__insn_type$100 7'0000000 - assign \alu_op__fn_unit$101 11'00000000000 - assign \alu_op__imm_data__imm$102 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$103 1'0 - assign \alu_op__rc__rc$104 1'0 - assign \alu_op__rc__rc_ok$105 1'0 - assign \alu_op__oe__oe$106 1'0 - assign \alu_op__oe__oe_ok$107 1'0 - assign \alu_op__invert_a$108 1'0 - assign \alu_op__zero_a$109 1'0 - assign \alu_op__invert_out$110 1'0 - assign \alu_op__write_cr0$111 1'0 - assign \alu_op__input_carry$112 2'00 - assign \alu_op__output_carry$113 1'0 - assign \alu_op__is_32bit$114 1'0 - assign \alu_op__is_signed$115 1'0 - assign \alu_op__data_len$116 4'0000 - assign \alu_op__insn$117 32'00000000000000000000000000000000 - assign { \alu_op__insn$117 \alu_op__data_len$116 \alu_op__is_signed$115 \alu_op__is_32bit$114 \alu_op__output_carry$113 \alu_op__input_carry$112 \alu_op__write_cr0$111 \alu_op__invert_out$110 \alu_op__zero_a$109 \alu_op__invert_a$108 { \alu_op__oe__oe_ok$107 \alu_op__oe__oe$106 } { \alu_op__rc__rc_ok$105 \alu_op__rc__rc$104 } { \alu_op__imm_data__imm_ok$103 \alu_op__imm_data__imm$102 } \alu_op__fn_unit$101 \alu_op__insn_type$100 } { \output_alu_op__insn$84 \output_alu_op__data_len$83 \output_alu_op__is_signed$82 \output_alu_op__is_32bit$81 \output_alu_op__output_carry$80 \output_alu_op__input_carry$79 \output_alu_op__write_cr0$78 \output_alu_op__invert_out$77 \output_alu_op__zero_a$76 \output_alu_op__invert_a$75 { \output_alu_op__oe__oe_ok$74 \output_alu_op__oe__oe$73 } { \output_alu_op__rc__rc_ok$72 \output_alu_op__rc__rc$71 } { \output_alu_op__imm_data__imm_ok$70 \output_alu_op__imm_data__imm$69 } \output_alu_op__fn_unit$68 \output_alu_op__insn_type$67 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$119 - process $group_97 - assign \o$118 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$119 1'0 - assign { \o_ok$119 \o$118 } { \output_o_ok$86 \output_o$85 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$121 - process $group_99 - assign \cr_a$120 4'0000 - assign \cr_a_ok$121 1'0 - assign { \cr_a_ok$121 \cr_a$120 } { \output_cr_a_ok \output_cr_a$87 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$123 - process $group_101 - assign \xer_ca$122 2'00 - assign \xer_ca_ok$123 1'0 - assign { \xer_ca_ok$123 \xer_ca$122 } { \output_xer_ca_ok \output_xer_ca$88 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$125 - process $group_103 - assign \xer_ov$124 2'00 - assign \xer_ov_ok$125 1'0 - assign { \xer_ov_ok$125 \xer_ov$124 } { \output_xer_ov_ok \output_xer_ov$89 } - sync init - end + wire width 1 \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$126 + wire width 64 output 23 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$127 - process $group_105 - assign \xer_so$126 1'0 - assign \xer_so_ok$127 1'0 - assign { \xer_so_ok$127 \xer_so$126 } { \output_xer_so_ok \output_xer_so$90 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_107 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_108 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$99 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$99 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_109 - assign \alu_op__insn_type$2$next \alu_op__insn_type$2 - assign \alu_op__fn_unit$3$next \alu_op__fn_unit$3 - assign \alu_op__imm_data__imm$4$next \alu_op__imm_data__imm$4 - assign \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm_ok$5 - assign \alu_op__rc__rc$6$next \alu_op__rc__rc$6 - assign \alu_op__rc__rc_ok$7$next \alu_op__rc__rc_ok$7 - assign \alu_op__oe__oe$8$next \alu_op__oe__oe$8 - assign \alu_op__oe__oe_ok$9$next \alu_op__oe__oe_ok$9 - assign \alu_op__invert_a$10$next \alu_op__invert_a$10 - assign \alu_op__zero_a$11$next \alu_op__zero_a$11 - assign \alu_op__invert_out$12$next \alu_op__invert_out$12 - assign \alu_op__write_cr0$13$next \alu_op__write_cr0$13 - assign \alu_op__input_carry$14$next \alu_op__input_carry$14 - assign \alu_op__output_carry$15$next \alu_op__output_carry$15 - assign \alu_op__is_32bit$16$next \alu_op__is_32bit$16 - assign \alu_op__is_signed$17$next \alu_op__is_signed$17 - assign \alu_op__data_len$18$next \alu_op__data_len$18 - assign \alu_op__insn$19$next \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_a$10$next { \alu_op__oe__oe_ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__rc_ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$117 \alu_op__data_len$116 \alu_op__is_signed$115 \alu_op__is_32bit$114 \alu_op__output_carry$113 \alu_op__input_carry$112 \alu_op__write_cr0$111 \alu_op__invert_out$110 \alu_op__zero_a$109 \alu_op__invert_a$108 { \alu_op__oe__oe_ok$107 \alu_op__oe__oe$106 } { \alu_op__rc__rc_ok$105 \alu_op__rc__rc$104 } { \alu_op__imm_data__imm_ok$103 \alu_op__imm_data__imm$102 } \alu_op__fn_unit$101 \alu_op__insn_type$100 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_a$10$next { \alu_op__oe__oe_ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__rc_ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$117 \alu_op__data_len$116 \alu_op__is_signed$115 \alu_op__is_32bit$114 \alu_op__output_carry$113 \alu_op__input_carry$112 \alu_op__write_cr0$111 \alu_op__invert_out$110 \alu_op__zero_a$109 \alu_op__invert_a$108 { \alu_op__oe__oe_ok$107 \alu_op__oe__oe$106 } { \alu_op__rc__rc_ok$105 \alu_op__rc__rc$104 } { \alu_op__imm_data__imm_ok$103 \alu_op__imm_data__imm$102 } \alu_op__fn_unit$101 \alu_op__insn_type$100 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$5$next 1'0 - assign \alu_op__rc__rc$6$next 1'0 - assign \alu_op__rc__rc_ok$7$next 1'0 - assign \alu_op__oe__oe$8$next 1'0 - assign \alu_op__oe__oe_ok$9$next 1'0 - end - sync init - update \alu_op__insn_type$2 7'0000000 - update \alu_op__fn_unit$3 11'00000000000 - update \alu_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_op__imm_data__imm_ok$5 1'0 - update \alu_op__rc__rc$6 1'0 - update \alu_op__rc__rc_ok$7 1'0 - update \alu_op__oe__oe$8 1'0 - update \alu_op__oe__oe_ok$9 1'0 - update \alu_op__invert_a$10 1'0 - update \alu_op__zero_a$11 1'0 - update \alu_op__invert_out$12 1'0 - update \alu_op__write_cr0$13 1'0 - update \alu_op__input_carry$14 2'00 - update \alu_op__output_carry$15 1'0 - update \alu_op__is_32bit$16 1'0 - update \alu_op__is_signed$17 1'0 - update \alu_op__data_len$18 4'0000 - update \alu_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \alu_op__insn_type$2 \alu_op__insn_type$2$next - update \alu_op__fn_unit$3 \alu_op__fn_unit$3$next - update \alu_op__imm_data__imm$4 \alu_op__imm_data__imm$4$next - update \alu_op__imm_data__imm_ok$5 \alu_op__imm_data__imm_ok$5$next - update \alu_op__rc__rc$6 \alu_op__rc__rc$6$next - update \alu_op__rc__rc_ok$7 \alu_op__rc__rc_ok$7$next - update \alu_op__oe__oe$8 \alu_op__oe__oe$8$next - update \alu_op__oe__oe_ok$9 \alu_op__oe__oe_ok$9$next - update \alu_op__invert_a$10 \alu_op__invert_a$10$next - update \alu_op__zero_a$11 \alu_op__zero_a$11$next - update \alu_op__invert_out$12 \alu_op__invert_out$12$next - update \alu_op__write_cr0$13 \alu_op__write_cr0$13$next - update \alu_op__input_carry$14 \alu_op__input_carry$14$next - update \alu_op__output_carry$15 \alu_op__output_carry$15$next - update \alu_op__is_32bit$16 \alu_op__is_32bit$16$next - update \alu_op__is_signed$17 \alu_op__is_signed$17$next - update \alu_op__data_len$18 \alu_op__data_len$18$next - update \alu_op__insn$19 \alu_op__insn$19$next - end - process $group_127 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$119 \o$118 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$119 \o$118 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_129 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$121 \cr_a$120 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$121 \cr_a$120 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next - end - process $group_131 - assign \xer_ca$20$next \xer_ca$20 - assign \xer_ca_ok$next \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ca_ok$next \xer_ca$20$next } { \xer_ca_ok$123 \xer_ca$122 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ca_ok$next \xer_ca$20$next } { \xer_ca_ok$123 \xer_ca$122 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ca_ok$next 1'0 - end - sync init - update \xer_ca$20 2'00 - update \xer_ca_ok 1'0 - sync posedge \coresync_clk - update \xer_ca$20 \xer_ca$20$next - update \xer_ca_ok \xer_ca_ok$next - end - process $group_133 - assign \xer_ov$next \xer_ov - assign \xer_ov_ok$next \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$125 \xer_ov$124 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$125 \xer_ov$124 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ov_ok$next 1'0 - end - sync init - update \xer_ov 2'00 - update \xer_ov_ok 1'0 - sync posedge \coresync_clk - update \xer_ov \xer_ov$next - update \xer_ov_ok \xer_ov_ok$next - end - process $group_135 - assign \xer_so$21$next \xer_so$21 - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$21$next } { \xer_so_ok$127 \xer_so$126 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$21$next } { \xer_so_ok$127 \xer_so$126 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so$21 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so$21 \xer_so$21$next - update \xer_so_ok \xer_so_ok$next - end - process $group_137 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_138 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \xer_so_ok$95 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0" -module \alu_alu0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk + wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok + wire width 1 output 24 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_a_ok + wire width 1 \o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ca_ok + wire width 4 output 25 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \xer_ov_ok + wire width 4 \cr_a$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \xer_so_ok - attribute \src "simple/issuer.py:89" - wire width 1 input 6 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 8 \n_ready_i + wire width 1 output 26 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 9 \o + wire width 1 \cr_a_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 10 \cr_a + wire width 2 output 27 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 11 \xer_ca + wire width 2 \xer_ca$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 12 \xer_ov + wire width 1 output 28 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 13 \xer_so + wire width 1 \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 31 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -47827,7 +34115,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 14 \alu_op__insn_type + wire width 7 input 32 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -47841,69 +34129,57 @@ module \alu_alu0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 15 \alu_op__fn_unit + wire width 11 input 33 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 16 \alu_op__imm_data__imm + wire width 64 input 34 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \alu_op__imm_data__imm_ok + wire width 1 input 35 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \alu_op__rc__rc + wire width 1 input 36 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \alu_op__rc__rc_ok + wire width 1 input 37 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \alu_op__oe__oe + wire width 1 input 38 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 21 \alu_op__oe__oe_ok + wire width 1 input 39 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 22 \alu_op__invert_a + wire width 1 input 40 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 23 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 24 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 25 \alu_op__write_cr0 + wire width 1 input 41 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 26 \alu_op__input_carry + wire width 2 input 42 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 27 \alu_op__output_carry + wire width 1 input 43 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 28 \alu_op__is_32bit + wire width 1 input 44 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 29 \alu_op__is_signed + wire width 1 input 45 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 30 \alu_op__data_len + wire width 1 input 46 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 31 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 32 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 33 \rb + wire width 1 input 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 34 \xer_so$1 + wire width 64 input 50 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 35 \xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 36 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 37 \p_ready_o - cell \p \p + wire width 64 input 51 \rb + cell \p$45 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n \n + cell \n$46 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid + wire width 2 \input_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -47978,7 +34254,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_alu_op__insn_type + wire width 7 \input_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -47992,57 +34268,224 @@ module \alu_alu0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_alu_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__imm_data__imm_ok + wire width 11 \input_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__rc__rc + wire width 64 \input_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__rc__rc_ok + wire width 1 \input_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__oe__oe + wire width 1 \input_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__oe__oe_ok + wire width 1 \input_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__invert_a + wire width 1 \input_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__zero_a + wire width 1 \input_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__invert_out + wire width 1 \input_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__write_cr0 + wire width 1 \input_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_alu_op__input_carry + wire width 2 \input_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__output_carry + wire width 1 \input_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__is_32bit + wire width 1 \input_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__is_signed + wire width 1 \input_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_alu_op__data_len + wire width 4 \input_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_alu_op__insn + wire width 32 \input_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra + wire width 64 \input_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$21 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \input_logical_op__fn_unit$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__imm$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__imm_data__imm_ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__rc__rc$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__rc__rc_ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__oe__oe$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__oe__oe_ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__invert_in$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__zero_a$30 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__invert_out$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__write_cr0$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__output_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__is_32bit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__is_signed$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_xer_so + wire width 64 \input_ra$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_n_ready_i + wire width 64 \input_rb$40 + cell \input$47 \input + connect \muxid \input_muxid + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__imm_data__imm \input_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc_ok \input_logical_op__rc__rc_ok + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe_ok \input_logical_op__oe__oe_ok + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__insn \input_logical_op__insn + connect \ra \input_ra + connect \rb \input_rb + connect \muxid$1 \input_muxid$20 + connect \logical_op__insn_type$2 \input_logical_op__insn_type$21 + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$22 + connect \logical_op__imm_data__imm$4 \input_logical_op__imm_data__imm$23 + connect \logical_op__imm_data__imm_ok$5 \input_logical_op__imm_data__imm_ok$24 + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$25 + connect \logical_op__rc__rc_ok$7 \input_logical_op__rc__rc_ok$26 + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$27 + connect \logical_op__oe__oe_ok$9 \input_logical_op__oe__oe_ok$28 + connect \logical_op__invert_in$10 \input_logical_op__invert_in$29 + connect \logical_op__zero_a$11 \input_logical_op__zero_a$30 + connect \logical_op__input_carry$12 \input_logical_op__input_carry$31 + connect \logical_op__invert_out$13 \input_logical_op__invert_out$32 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$33 + connect \logical_op__output_carry$15 \input_logical_op__output_carry$34 + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$35 + connect \logical_op__is_signed$17 \input_logical_op__is_signed$36 + connect \logical_op__data_len$18 \input_logical_op__data_len$37 + connect \logical_op__insn$19 \input_logical_op__insn$38 + connect \ra$20 \input_ra$39 + connect \rb$21 \input_rb$40 + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 + wire width 2 \main_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -48117,7 +34560,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_alu_op__insn_type$4 + wire width 7 \main_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -48131,197 +34574,335 @@ module \alu_alu0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_alu_op__fn_unit$5 + wire width 11 \main_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$41 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_alu_op__imm_data__imm$6 + wire width 7 \main_logical_op__insn_type$42 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__imm_data__imm_ok$7 + wire width 11 \main_logical_op__fn_unit$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__rc__rc$8 + wire width 64 \main_logical_op__imm_data__imm$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__rc__rc_ok$9 + wire width 1 \main_logical_op__imm_data__imm_ok$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__oe__oe$10 + wire width 1 \main_logical_op__rc__rc$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__oe__oe_ok$11 + wire width 1 \main_logical_op__rc__rc_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__invert_a$12 + wire width 1 \main_logical_op__oe__oe$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__zero_a$13 + wire width 1 \main_logical_op__oe__oe_ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__invert_out$14 + wire width 1 \main_logical_op__invert_in$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__write_cr0$15 + wire width 1 \main_logical_op__zero_a$51 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_alu_op__input_carry$16 + wire width 2 \main_logical_op__input_carry$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__output_carry$17 + wire width 1 \main_logical_op__invert_out$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__is_32bit$18 + wire width 1 \main_logical_op__write_cr0$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_alu_op__is_signed$19 + wire width 1 \main_logical_op__output_carry$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_alu_op__data_len$20 + wire width 1 \main_logical_op__is_32bit$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_alu_op__insn$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_xer_ca$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_ov_ok + wire width 1 \main_logical_op__is_signed$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_so$23 + wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_so_ok - cell \pipe \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_p_valid_i - connect \p_ready_o \pipe_p_ready_o - connect \muxid \pipe_muxid - connect \alu_op__insn_type \pipe_alu_op__insn_type - connect \alu_op__fn_unit \pipe_alu_op__fn_unit - connect \alu_op__imm_data__imm \pipe_alu_op__imm_data__imm - connect \alu_op__imm_data__imm_ok \pipe_alu_op__imm_data__imm_ok - connect \alu_op__rc__rc \pipe_alu_op__rc__rc - connect \alu_op__rc__rc_ok \pipe_alu_op__rc__rc_ok - connect \alu_op__oe__oe \pipe_alu_op__oe__oe - connect \alu_op__oe__oe_ok \pipe_alu_op__oe__oe_ok - connect \alu_op__invert_a \pipe_alu_op__invert_a - connect \alu_op__zero_a \pipe_alu_op__zero_a - connect \alu_op__invert_out \pipe_alu_op__invert_out - connect \alu_op__write_cr0 \pipe_alu_op__write_cr0 - connect \alu_op__input_carry \pipe_alu_op__input_carry - connect \alu_op__output_carry \pipe_alu_op__output_carry - connect \alu_op__is_32bit \pipe_alu_op__is_32bit - connect \alu_op__is_signed \pipe_alu_op__is_signed - connect \alu_op__data_len \pipe_alu_op__data_len - connect \alu_op__insn \pipe_alu_op__insn - connect \ra \pipe_ra - connect \rb \pipe_rb - connect \xer_so \pipe_xer_so - connect \xer_ca \pipe_xer_ca - connect \n_valid_o \pipe_n_valid_o - connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$3 - connect \alu_op__insn_type$2 \pipe_alu_op__insn_type$4 - connect \alu_op__fn_unit$3 \pipe_alu_op__fn_unit$5 - connect \alu_op__imm_data__imm$4 \pipe_alu_op__imm_data__imm$6 - connect \alu_op__imm_data__imm_ok$5 \pipe_alu_op__imm_data__imm_ok$7 - connect \alu_op__rc__rc$6 \pipe_alu_op__rc__rc$8 - connect \alu_op__rc__rc_ok$7 \pipe_alu_op__rc__rc_ok$9 - connect \alu_op__oe__oe$8 \pipe_alu_op__oe__oe$10 - connect \alu_op__oe__oe_ok$9 \pipe_alu_op__oe__oe_ok$11 - connect \alu_op__invert_a$10 \pipe_alu_op__invert_a$12 - connect \alu_op__zero_a$11 \pipe_alu_op__zero_a$13 - connect \alu_op__invert_out$12 \pipe_alu_op__invert_out$14 - connect \alu_op__write_cr0$13 \pipe_alu_op__write_cr0$15 - connect \alu_op__input_carry$14 \pipe_alu_op__input_carry$16 - connect \alu_op__output_carry$15 \pipe_alu_op__output_carry$17 - connect \alu_op__is_32bit$16 \pipe_alu_op__is_32bit$18 - connect \alu_op__is_signed$17 \pipe_alu_op__is_signed$19 - connect \alu_op__data_len$18 \pipe_alu_op__data_len$20 - connect \alu_op__insn$19 \pipe_alu_op__insn$21 - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \cr_a \pipe_cr_a - connect \cr_a_ok \pipe_cr_a_ok - connect \xer_ca$20 \pipe_xer_ca$22 - connect \xer_ca_ok \pipe_xer_ca_ok - connect \xer_ov \pipe_xer_ov - connect \xer_ov_ok \pipe_xer_ov_ok - connect \xer_so$21 \pipe_xer_so$23 - connect \xer_so_ok \pipe_xer_so_ok + wire width 1 \main_o_ok + cell \main$48 \main + connect \muxid \main_muxid + connect \logical_op__insn_type \main_logical_op__insn_type + connect \logical_op__fn_unit \main_logical_op__fn_unit + connect \logical_op__imm_data__imm \main_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \main_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \main_logical_op__rc__rc + connect \logical_op__rc__rc_ok \main_logical_op__rc__rc_ok + connect \logical_op__oe__oe \main_logical_op__oe__oe + connect \logical_op__oe__oe_ok \main_logical_op__oe__oe_ok + connect \logical_op__invert_in \main_logical_op__invert_in + connect \logical_op__zero_a \main_logical_op__zero_a + connect \logical_op__input_carry \main_logical_op__input_carry + connect \logical_op__invert_out \main_logical_op__invert_out + connect \logical_op__write_cr0 \main_logical_op__write_cr0 + connect \logical_op__output_carry \main_logical_op__output_carry + connect \logical_op__is_32bit \main_logical_op__is_32bit + connect \logical_op__is_signed \main_logical_op__is_signed + connect \logical_op__data_len \main_logical_op__data_len + connect \logical_op__insn \main_logical_op__insn + connect \ra \main_ra + connect \rb \main_rb + connect \muxid$1 \main_muxid$41 + connect \logical_op__insn_type$2 \main_logical_op__insn_type$42 + connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$43 + connect \logical_op__imm_data__imm$4 \main_logical_op__imm_data__imm$44 + connect \logical_op__imm_data__imm_ok$5 \main_logical_op__imm_data__imm_ok$45 + connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$46 + connect \logical_op__rc__rc_ok$7 \main_logical_op__rc__rc_ok$47 + connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$48 + connect \logical_op__oe__oe_ok$9 \main_logical_op__oe__oe_ok$49 + connect \logical_op__invert_in$10 \main_logical_op__invert_in$50 + connect \logical_op__zero_a$11 \main_logical_op__zero_a$51 + connect \logical_op__input_carry$12 \main_logical_op__input_carry$52 + connect \logical_op__invert_out$13 \main_logical_op__invert_out$53 + connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$54 + connect \logical_op__output_carry$15 \main_logical_op__output_carry$55 + connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$56 + connect \logical_op__is_signed$17 \main_logical_op__is_signed$57 + connect \logical_op__data_len$18 \main_logical_op__data_len$58 + connect \logical_op__insn$19 \main_logical_op__insn$59 + connect \o \main_o + connect \o_ok \main_o_ok end process $group_0 - assign \pipe_p_valid_i 1'0 - assign \pipe_p_valid_i \p_valid_i + assign \input_muxid 2'00 + assign \input_muxid \muxid$1 sync init end process $group_1 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_p_ready_o + assign \input_logical_op__insn_type 7'0000000 + assign \input_logical_op__fn_unit 11'00000000000 + assign \input_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_logical_op__imm_data__imm_ok 1'0 + assign \input_logical_op__rc__rc 1'0 + assign \input_logical_op__rc__rc_ok 1'0 + assign \input_logical_op__oe__oe 1'0 + assign \input_logical_op__oe__oe_ok 1'0 + assign \input_logical_op__invert_in 1'0 + assign \input_logical_op__zero_a 1'0 + assign \input_logical_op__input_carry 2'00 + assign \input_logical_op__invert_out 1'0 + assign \input_logical_op__write_cr0 1'0 + assign \input_logical_op__output_carry 1'0 + assign \input_logical_op__is_32bit 1'0 + assign \input_logical_op__is_signed 1'0 + assign \input_logical_op__data_len 4'0000 + assign \input_logical_op__insn 32'00000000000000000000000000000000 + assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in { \input_logical_op__oe__oe_ok \input_logical_op__oe__oe } { \input_logical_op__rc__rc_ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_2 - assign \pipe_muxid 2'00 - assign \pipe_muxid \muxid + process $group_19 + assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_ra \ra sync init end - process $group_3 - assign \pipe_alu_op__insn_type 7'0000000 - assign \pipe_alu_op__fn_unit 11'00000000000 - assign \pipe_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_alu_op__imm_data__imm_ok 1'0 - assign \pipe_alu_op__rc__rc 1'0 - assign \pipe_alu_op__rc__rc_ok 1'0 - assign \pipe_alu_op__oe__oe 1'0 - assign \pipe_alu_op__oe__oe_ok 1'0 - assign \pipe_alu_op__invert_a 1'0 - assign \pipe_alu_op__zero_a 1'0 - assign \pipe_alu_op__invert_out 1'0 - assign \pipe_alu_op__write_cr0 1'0 - assign \pipe_alu_op__input_carry 2'00 - assign \pipe_alu_op__output_carry 1'0 - assign \pipe_alu_op__is_32bit 1'0 - assign \pipe_alu_op__is_signed 1'0 - assign \pipe_alu_op__data_len 4'0000 - assign \pipe_alu_op__insn 32'00000000000000000000000000000000 - assign { \pipe_alu_op__insn \pipe_alu_op__data_len \pipe_alu_op__is_signed \pipe_alu_op__is_32bit \pipe_alu_op__output_carry \pipe_alu_op__input_carry \pipe_alu_op__write_cr0 \pipe_alu_op__invert_out \pipe_alu_op__zero_a \pipe_alu_op__invert_a { \pipe_alu_op__oe__oe_ok \pipe_alu_op__oe__oe } { \pipe_alu_op__rc__rc_ok \pipe_alu_op__rc__rc } { \pipe_alu_op__imm_data__imm_ok \pipe_alu_op__imm_data__imm } \pipe_alu_op__fn_unit \pipe_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } + process $group_20 + assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_rb \rb sync init end process $group_21 - assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_ra \ra + assign \main_muxid 2'00 + assign \main_muxid \input_muxid$20 sync init end process $group_22 - assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_rb \rb + assign \main_logical_op__insn_type 7'0000000 + assign \main_logical_op__fn_unit 11'00000000000 + assign \main_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_logical_op__imm_data__imm_ok 1'0 + assign \main_logical_op__rc__rc 1'0 + assign \main_logical_op__rc__rc_ok 1'0 + assign \main_logical_op__oe__oe 1'0 + assign \main_logical_op__oe__oe_ok 1'0 + assign \main_logical_op__invert_in 1'0 + assign \main_logical_op__zero_a 1'0 + assign \main_logical_op__input_carry 2'00 + assign \main_logical_op__invert_out 1'0 + assign \main_logical_op__write_cr0 1'0 + assign \main_logical_op__output_carry 1'0 + assign \main_logical_op__is_32bit 1'0 + assign \main_logical_op__is_signed 1'0 + assign \main_logical_op__data_len 4'0000 + assign \main_logical_op__insn 32'00000000000000000000000000000000 + assign { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in { \main_logical_op__oe__oe_ok \main_logical_op__oe__oe } { \main_logical_op__rc__rc_ok \main_logical_op__rc__rc } { \main_logical_op__imm_data__imm_ok \main_logical_op__imm_data__imm } \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$38 \input_logical_op__data_len$37 \input_logical_op__is_signed$36 \input_logical_op__is_32bit$35 \input_logical_op__output_carry$34 \input_logical_op__write_cr0$33 \input_logical_op__invert_out$32 \input_logical_op__input_carry$31 \input_logical_op__zero_a$30 \input_logical_op__invert_in$29 { \input_logical_op__oe__oe_ok$28 \input_logical_op__oe__oe$27 } { \input_logical_op__rc__rc_ok$26 \input_logical_op__rc__rc$25 } { \input_logical_op__imm_data__imm_ok$24 \input_logical_op__imm_data__imm$23 } \input_logical_op__fn_unit$22 \input_logical_op__insn_type$21 } sync init end - process $group_23 - assign \pipe_xer_so 1'0 - assign \pipe_xer_so \xer_so$1 + process $group_40 + assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_ra \input_ra$39 sync init end - process $group_24 - assign \pipe_xer_ca 2'00 - assign \pipe_xer_ca \xer_ca$2 + process $group_41 + assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_rb \input_rb$40 sync init end - process $group_25 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$60 + process $group_42 + assign \p_valid_i$60 1'0 + assign \p_valid_i$60 \p_valid_i sync init end - process $group_26 - assign \pipe_n_ready_i 1'0 - assign \pipe_n_ready_i \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_43 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$60 + connect \B \p_ready_o + connect \Y $61 + end + process $group_44 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $61 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$24 - process $group_27 - assign \muxid$24 2'00 - assign \muxid$24 \pipe_muxid$3 + wire width 2 \muxid$63 + process $group_45 + assign \muxid$63 2'00 + assign \muxid$63 \main_muxid$41 sync init end attribute \enum_base_type "MicrOp" @@ -48398,7 +34979,7 @@ module \alu_alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$25 + wire width 7 \logical_op__insn_type$64 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -48412,1117 +34993,369 @@ module \alu_alu0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__imm$27 + wire width 11 \logical_op__fn_unit$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__imm_ok$28 + wire width 64 \logical_op__imm_data__imm$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc$29 + wire width 1 \logical_op__imm_data__imm_ok$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc_ok$30 + wire width 1 \logical_op__rc__rc$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe$31 + wire width 1 \logical_op__rc__rc_ok$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe_ok$32 + wire width 1 \logical_op__oe__oe$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_a$33 + wire width 1 \logical_op__oe__oe_ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__zero_a$34 + wire width 1 \logical_op__invert_in$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_out$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__write_cr0$36 + wire width 1 \logical_op__zero_a$73 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$37 + wire width 2 \logical_op__input_carry$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__output_carry$38 + wire width 1 \logical_op__invert_out$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_32bit$39 + wire width 1 \logical_op__write_cr0$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_signed$40 + wire width 1 \logical_op__output_carry$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$41 + wire width 1 \logical_op__is_32bit$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$42 - process $group_28 - assign \alu_op__insn_type$25 7'0000000 - assign \alu_op__fn_unit$26 11'00000000000 - assign \alu_op__imm_data__imm$27 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__imm_ok$28 1'0 - assign \alu_op__rc__rc$29 1'0 - assign \alu_op__rc__rc_ok$30 1'0 - assign \alu_op__oe__oe$31 1'0 - assign \alu_op__oe__oe_ok$32 1'0 - assign \alu_op__invert_a$33 1'0 - assign \alu_op__zero_a$34 1'0 - assign \alu_op__invert_out$35 1'0 - assign \alu_op__write_cr0$36 1'0 - assign \alu_op__input_carry$37 2'00 - assign \alu_op__output_carry$38 1'0 - assign \alu_op__is_32bit$39 1'0 - assign \alu_op__is_signed$40 1'0 - assign \alu_op__data_len$41 4'0000 - assign \alu_op__insn$42 32'00000000000000000000000000000000 - assign { \alu_op__insn$42 \alu_op__data_len$41 \alu_op__is_signed$40 \alu_op__is_32bit$39 \alu_op__output_carry$38 \alu_op__input_carry$37 \alu_op__write_cr0$36 \alu_op__invert_out$35 \alu_op__zero_a$34 \alu_op__invert_a$33 { \alu_op__oe__oe_ok$32 \alu_op__oe__oe$31 } { \alu_op__rc__rc_ok$30 \alu_op__rc__rc$29 } { \alu_op__imm_data__imm_ok$28 \alu_op__imm_data__imm$27 } \alu_op__fn_unit$26 \alu_op__insn_type$25 } { \pipe_alu_op__insn$21 \pipe_alu_op__data_len$20 \pipe_alu_op__is_signed$19 \pipe_alu_op__is_32bit$18 \pipe_alu_op__output_carry$17 \pipe_alu_op__input_carry$16 \pipe_alu_op__write_cr0$15 \pipe_alu_op__invert_out$14 \pipe_alu_op__zero_a$13 \pipe_alu_op__invert_a$12 { \pipe_alu_op__oe__oe_ok$11 \pipe_alu_op__oe__oe$10 } { \pipe_alu_op__rc__rc_ok$9 \pipe_alu_op__rc__rc$8 } { \pipe_alu_op__imm_data__imm_ok$7 \pipe_alu_op__imm_data__imm$6 } \pipe_alu_op__fn_unit$5 \pipe_alu_op__insn_type$4 } - sync init - end + wire width 1 \logical_op__is_signed$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$81 process $group_46 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_o_ok \pipe_o } - sync init - end - process $group_48 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a } + assign \logical_op__insn_type$64 7'0000000 + assign \logical_op__fn_unit$65 11'00000000000 + assign \logical_op__imm_data__imm$66 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$67 1'0 + assign \logical_op__rc__rc$68 1'0 + assign \logical_op__rc__rc_ok$69 1'0 + assign \logical_op__oe__oe$70 1'0 + assign \logical_op__oe__oe_ok$71 1'0 + assign \logical_op__invert_in$72 1'0 + assign \logical_op__zero_a$73 1'0 + assign \logical_op__input_carry$74 2'00 + assign \logical_op__invert_out$75 1'0 + assign \logical_op__write_cr0$76 1'0 + assign \logical_op__output_carry$77 1'0 + assign \logical_op__is_32bit$78 1'0 + assign \logical_op__is_signed$79 1'0 + assign \logical_op__data_len$80 4'0000 + assign \logical_op__insn$81 32'00000000000000000000000000000000 + assign { \logical_op__insn$81 \logical_op__data_len$80 \logical_op__is_signed$79 \logical_op__is_32bit$78 \logical_op__output_carry$77 \logical_op__write_cr0$76 \logical_op__invert_out$75 \logical_op__input_carry$74 \logical_op__zero_a$73 \logical_op__invert_in$72 { \logical_op__oe__oe_ok$71 \logical_op__oe__oe$70 } { \logical_op__rc__rc_ok$69 \logical_op__rc__rc$68 } { \logical_op__imm_data__imm_ok$67 \logical_op__imm_data__imm$66 } \logical_op__fn_unit$65 \logical_op__insn_type$64 } { \main_logical_op__insn$59 \main_logical_op__data_len$58 \main_logical_op__is_signed$57 \main_logical_op__is_32bit$56 \main_logical_op__output_carry$55 \main_logical_op__write_cr0$54 \main_logical_op__invert_out$53 \main_logical_op__input_carry$52 \main_logical_op__zero_a$51 \main_logical_op__invert_in$50 { \main_logical_op__oe__oe_ok$49 \main_logical_op__oe__oe$48 } { \main_logical_op__rc__rc_ok$47 \main_logical_op__rc__rc$46 } { \main_logical_op__imm_data__imm_ok$45 \main_logical_op__imm_data__imm$44 } \main_logical_op__fn_unit$43 \main_logical_op__insn_type$42 } sync init end - process $group_50 - assign \xer_ca 2'00 - assign \xer_ca_ok 1'0 - assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$22 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$83 + process $group_64 + assign \o$82 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$83 1'0 + assign { \o_ok$83 \o$82 } { \main_o_ok \main_o } sync init end - process $group_52 - assign \xer_ov 2'00 - assign \xer_ov_ok 1'0 - assign { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$87 + process $group_66 + assign \cr_a$84 4'0000 + assign \cr_a_ok$85 1'0 + assign { \cr_a_ok$85 \cr_a$84 } { \cr_a_ok$87 \cr_a$86 } sync init end - process $group_54 - assign \xer_so 1'0 - assign \xer_so_ok 1'0 - assign { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$23 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$91 + process $group_68 + assign \xer_ca$88 2'00 + assign \xer_ca_ok$89 1'0 + assign { \xer_ca_ok$89 \xer_ca$88 } { \xer_ca_ok$91 \xer_ca$90 } sync init end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l" -module \src_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_70 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 4'0000 + assign \r_busy$next 1'0 end sync init - update \q_int 4'0000 + update \r_busy 1'0 sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $7 + update \r_busy \r_busy$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_71 + assign \muxid$next \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$next \muxid$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$next \muxid$63 + end + sync init + update \muxid 2'00 + sync posedge \coresync_clk + update \muxid \muxid$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 4'0000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 4'0000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 4'0000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l" -module \opc_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 + process $group_72 + assign \logical_op__insn_type$next \logical_op__insn_type + assign \logical_op__fn_unit$next \logical_op__fn_unit + assign \logical_op__imm_data__imm$next \logical_op__imm_data__imm + assign \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm_ok + assign \logical_op__rc__rc$next \logical_op__rc__rc + assign \logical_op__rc__rc_ok$next \logical_op__rc__rc_ok + assign \logical_op__oe__oe$next \logical_op__oe__oe + assign \logical_op__oe__oe_ok$next \logical_op__oe__oe_ok + assign \logical_op__invert_in$next \logical_op__invert_in + assign \logical_op__zero_a$next \logical_op__zero_a + assign \logical_op__input_carry$next \logical_op__input_carry + assign \logical_op__invert_out$next \logical_op__invert_out + assign \logical_op__write_cr0$next \logical_op__write_cr0 + assign \logical_op__output_carry$next \logical_op__output_carry + assign \logical_op__is_32bit$next \logical_op__is_32bit + assign \logical_op__is_signed$next \logical_op__is_signed + assign \logical_op__data_len$next \logical_op__data_len + assign \logical_op__insn$next \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$81 \logical_op__data_len$80 \logical_op__is_signed$79 \logical_op__is_32bit$78 \logical_op__output_carry$77 \logical_op__write_cr0$76 \logical_op__invert_out$75 \logical_op__input_carry$74 \logical_op__zero_a$73 \logical_op__invert_in$72 { \logical_op__oe__oe_ok$71 \logical_op__oe__oe$70 } { \logical_op__rc__rc_ok$69 \logical_op__rc__rc$68 } { \logical_op__imm_data__imm_ok$67 \logical_op__imm_data__imm$66 } \logical_op__fn_unit$65 \logical_op__insn_type$64 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$81 \logical_op__data_len$80 \logical_op__is_signed$79 \logical_op__is_32bit$78 \logical_op__output_carry$77 \logical_op__write_cr0$76 \logical_op__invert_out$75 \logical_op__input_carry$74 \logical_op__zero_a$73 \logical_op__invert_in$72 { \logical_op__oe__oe_ok$71 \logical_op__oe__oe$70 } { \logical_op__rc__rc_ok$69 \logical_op__rc__rc$68 } { \logical_op__imm_data__imm_ok$67 \logical_op__imm_data__imm$66 } \logical_op__fn_unit$65 \logical_op__insn_type$64 } + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 1'0 + assign \logical_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$next 1'0 + assign \logical_op__rc__rc$next 1'0 + assign \logical_op__rc__rc_ok$next 1'0 + assign \logical_op__oe__oe$next 1'0 + assign \logical_op__oe__oe_ok$next 1'0 end sync init - update \q_int 1'0 + update \logical_op__insn_type 7'0000000 + update \logical_op__fn_unit 11'00000000000 + update \logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok 1'0 + update \logical_op__rc__rc 1'0 + update \logical_op__rc__rc_ok 1'0 + update \logical_op__oe__oe 1'0 + update \logical_op__oe__oe_ok 1'0 + update \logical_op__invert_in 1'0 + update \logical_op__zero_a 1'0 + update \logical_op__input_carry 2'00 + update \logical_op__invert_out 1'0 + update \logical_op__write_cr0 1'0 + update \logical_op__output_carry 1'0 + update \logical_op__is_32bit 1'0 + update \logical_op__is_signed 1'0 + update \logical_op__data_len 4'0000 + update \logical_op__insn 32'00000000000000000000000000000000 sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l" -module \req_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $3 - connect \B \s_req - connect \Y $5 + update \logical_op__insn_type \logical_op__insn_type$next + update \logical_op__fn_unit \logical_op__fn_unit$next + update \logical_op__imm_data__imm \logical_op__imm_data__imm$next + update \logical_op__imm_data__imm_ok \logical_op__imm_data__imm_ok$next + update \logical_op__rc__rc \logical_op__rc__rc$next + update \logical_op__rc__rc_ok \logical_op__rc__rc_ok$next + update \logical_op__oe__oe \logical_op__oe__oe$next + update \logical_op__oe__oe_ok \logical_op__oe__oe_ok$next + update \logical_op__invert_in \logical_op__invert_in$next + update \logical_op__zero_a \logical_op__zero_a$next + update \logical_op__input_carry \logical_op__input_carry$next + update \logical_op__invert_out \logical_op__invert_out$next + update \logical_op__write_cr0 \logical_op__write_cr0$next + update \logical_op__output_carry \logical_op__output_carry$next + update \logical_op__is_32bit \logical_op__is_32bit$next + update \logical_op__is_signed \logical_op__is_signed$next + update \logical_op__data_len \logical_op__data_len$next + update \logical_op__insn \logical_op__insn$next end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 + process $group_90 + assign \o$next \o + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$next } { \o_ok$83 \o$82 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$next } { \o_ok$83 \o$82 } + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 5'00000 + assign \o_ok$next 1'0 end sync init - update \q_int 5'00000 + update \o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 5'00000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 5'00000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 5'00000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l" -module \rst_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 + update \o \o$next + update \o_ok \o_ok$next end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 + process $group_92 + assign \cr_a$next \cr_a + assign \cr_a_ok$next \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$85 \cr_a$84 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$85 \cr_a$84 } + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 1'0 + assign \cr_a_ok$next 1'0 end sync init - update \q_int 1'0 + update \cr_a 4'0000 + update \cr_a_ok 1'0 sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l" -module \rok_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 + update \cr_a \cr_a$next + update \cr_a_ok \cr_a_ok$next end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 + process $group_94 + assign \xer_ca$next \xer_ca + assign \xer_ca_ok$next \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$89 \xer_ca$88 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$89 \xer_ca$88 } + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 1'0 + assign \xer_ca_ok$next 1'0 end sync init - update \q_int 1'0 + update \xer_ca 2'00 + update \xer_ca_ok 1'0 sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 + update \xer_ca \xer_ca$next + update \xer_ca_ok \xer_ca_ok$next end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 + process $group_96 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 + process $group_97 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data sync init end + connect \cr_a$86 4'0000 + connect \cr_a_ok$87 1'0 + connect \xer_ca$90 2'00 + connect \xer_ca_ok$91 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l" -module \alui_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.p" +module \p$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 - end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 - end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 + assign \trigger 1'0 + assign \trigger $1 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_l" -module \alu_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.n" +module \n$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 - end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 - end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 + assign \trigger 1'0 + assign \trigger $1 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0" -module \alu0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.output" +module \output$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -49597,7 +35430,7 @@ module \alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_alu0__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -49611,101 +35444,53 @@ module \alu0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_alu0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_alu0__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_alu0__imm_data__imm_ok + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \oper_i_alu_alu0__rc__rc + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_alu0__rc__rc_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \oper_i_alu_alu0__oe__oe + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_alu0__oe__oe_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \oper_i_alu_alu0__invert_a + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \oper_i_alu_alu0__zero_a + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \oper_i_alu_alu0__invert_out + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_alu_alu0__write_cr0 + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \oper_i_alu_alu0__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_alu_alu0__output_carry + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \oper_i_alu_alu0__is_32bit + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \oper_i_alu_alu0__is_signed + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \oper_i_alu_alu0__data_len + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \oper_i_alu_alu0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 19 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 20 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 4 input 21 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 22 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 23 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 24 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 25 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 1 input 26 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 2 input 27 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 28 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 29 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 input 30 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 31 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 32 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 33 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 34 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 35 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 36 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 37 \dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 38 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 output 39 \dest5_o - attribute \src "simple/issuer.py:89" - wire width 1 input 40 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_alu0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_alu0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_alu0_o + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_alu0_cr_a + wire width 64 input 19 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_alu0_xer_ca + wire width 1 input 20 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_alu0_xer_ov + wire width 4 input 21 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \alu_alu0_xer_so + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -49780,7 +35565,7 @@ module \alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_alu0_alu_op__insn_type + wire width 7 output 24 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -49794,844 +35579,343 @@ module \alu0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_alu0_alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_alu0_alu_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__imm_data__imm_ok + wire width 11 output 25 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__rc__rc + wire width 64 output 26 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__rc__rc_ok + wire width 1 output 27 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__oe__oe + wire width 1 output 28 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__oe__oe_ok + wire width 1 output 29 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__invert_a + wire width 1 output 30 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__zero_a + wire width 1 output 31 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__invert_out + wire width 1 output 32 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__write_cr0 + wire width 1 output 33 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_alu0_alu_op__input_carry + wire width 2 output 34 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__output_carry + wire width 1 output 35 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__is_32bit + wire width 1 output 36 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__is_signed + wire width 1 output 37 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_alu0_alu_op__data_len + wire width 1 output 38 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_alu0_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_alu0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_alu0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \alu_alu0_xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_alu0_xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_alu0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_alu0_p_ready_o - cell \alu_alu0 \alu_alu0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \cr_a_ok \cr_a_ok - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_alu0_n_valid_o - connect \n_ready_i \alu_alu0_n_ready_i - connect \o \alu_alu0_o - connect \cr_a \alu_alu0_cr_a - connect \xer_ca \alu_alu0_xer_ca - connect \xer_ov \alu_alu0_xer_ov - connect \xer_so \alu_alu0_xer_so - connect \alu_op__insn_type \alu_alu0_alu_op__insn_type - connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit - connect \alu_op__imm_data__imm \alu_alu0_alu_op__imm_data__imm - connect \alu_op__imm_data__imm_ok \alu_alu0_alu_op__imm_data__imm_ok - connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc - connect \alu_op__rc__rc_ok \alu_alu0_alu_op__rc__rc_ok - connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe - connect \alu_op__oe__oe_ok \alu_alu0_alu_op__oe__oe_ok - connect \alu_op__invert_a \alu_alu0_alu_op__invert_a - connect \alu_op__zero_a \alu_alu0_alu_op__zero_a - connect \alu_op__invert_out \alu_alu0_alu_op__invert_out - connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 - connect \alu_op__input_carry \alu_alu0_alu_op__input_carry - connect \alu_op__output_carry \alu_alu0_alu_op__output_carry - connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit - connect \alu_op__is_signed \alu_alu0_alu_op__is_signed - connect \alu_op__data_len \alu_alu0_alu_op__data_len - connect \alu_op__insn \alu_alu0_alu_op__insn - connect \ra \alu_alu0_ra - connect \rb \alu_alu0_rb - connect \xer_so$1 \alu_alu0_xer_so$1 - connect \xer_ca$2 \alu_alu0_xer_ca$2 - connect \p_valid_i \alu_alu0_p_valid_i - connect \p_ready_o \alu_alu0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \src_l_q_src - cell \src_l \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req$next - cell \req_l \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - cell \rst_l \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 4 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $not $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__rel_o - connect \Y $6 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 4 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $or $9 + wire width 1 output 39 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 42 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 43 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 44 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 45 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 46 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 47 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" + wire width 65 \o$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + wire width 65 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + wire width 64 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + cell $not $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $6 - connect \B \cu_rd__go_i - connect \Y $8 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $reduce_and $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + cell $pos $28 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $5 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A $26 + connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $30 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 - connect \Y $11 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $29 end process $group_0 - assign \all_rd 1'0 - assign \all_rd $11 + assign \o$24 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + switch { \logical_op__invert_out } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + case 1'1 + assign \o$24 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + case + assign \o$24 $29 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + wire width 64 \target process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd + assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \target \o$24 [63:0] sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $and $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $13 - connect \Y $15 end process $group_2 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse $15 + assign \xer_ca$23 2'00 + assign \xer_ca$23 \xer_ca sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_done process $group_3 - assign \alu_done 1'0 - assign \alu_done \alu_alu0_n_valid_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly$next - process $group_4 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done - sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $17 - connect \Y $19 - end - process $group_5 - assign \alu_pulse 1'0 - assign \alu_pulse $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" - wire width 5 \alu_pulsem - process $group_6 - assign \alu_pulsem 5'00000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 5 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 5 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 5 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $21 - end - process $group_7 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $21 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 5'00000 - end + assign \xer_ca_ok 1'0 + assign \xer_ca_ok \logical_op__output_carry sync init - update \prev_wr_go 5'00000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 5 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wrmask_o - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 5 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__rel_o - connect \B $25 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + wire width 1 \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + cell $eq $32 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $23 + connect \A \logical_op__insn_type + connect \B 7'0001010 connect \Y $31 end - process $group_8 - assign \cu_done_o 1'0 - assign \cu_done_o $31 + process $group_4 + assign \is_cmp 1'0 + assign \is_cmp $31 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + wire width 1 \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + cell $eq $34 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i + connect \A \logical_op__insn_type + connect \B 7'0001100 connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" + process $group_5 + assign \is_cmpeqb 1'0 + assign \is_cmpeqb $33 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + wire width 1 \msb_test + process $group_6 + assign \msb_test 1'0 + assign \msb_test \target [63] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 1 \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" cell $reduce_bool $36 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 64 parameter \Y_WIDTH 1 - connect \A \prev_wr_go + connect \A \target connect \Y $35 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" + process $group_7 + assign \is_nzero 1'0 + assign \is_nzero $35 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + wire width 1 \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $or $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $33 - connect \B $35 + connect \A \msb_test connect \Y $37 end - process $group_9 - assign \wr_any 1'0 - assign \wr_any $37 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $not $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $and $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_alu0_n_ready_i + connect \A \is_nzero + connect \B $37 connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" + process $group_8 + assign \is_positive 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_positive \msb_test + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_positive $39 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" + wire width 1 \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $and $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $not $42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $39 + connect \A \msb_test connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 5 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" cell $and $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $eq $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $43 - connect \B 1'0 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $41 - connect \B $45 - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $eq $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $49 - connect \B \alu_alu0_n_ready_i - connect \Y $51 + connect \A \is_nzero + connect \B $41 + connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $51 - connect \B \alu_alu0_n_valid_o - connect \Y $53 + process $group_9 + assign \is_negative 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_negative $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_negative \msb_test + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + cell $not $46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $53 - connect \B \cu_busy_o - connect \Y $55 + connect \A \is_nzero + connect \Y $45 end process $group_10 - assign \req_done 1'0 - assign \req_done $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + assign \cr0 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + switch { \is_cmpeqb } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" case 1'1 - assign \req_done 1'1 + assign \cr0 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + case + assign \cr0 { \is_negative \is_positive $45 1'0 } end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $57 - end process $group_11 - assign \reset 1'0 - assign \reset $57 + assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o$20 \o$24 [63:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - cell $or $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $59 - end process $group_12 - assign \rst_r 1'0 - assign \rst_r $59 + assign \o_ok$21 1'0 + assign \o_ok$21 \o_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - wire width 5 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - cell $or $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $61 - end process $group_13 - assign \reset_w 5'00000 - assign \reset_w $61 + assign \cr_a$22 4'0000 + assign \cr_a$22 \cr0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - wire width 4 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - cell $or $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $63 - end process $group_14 - assign \reset_r 4'0000 - assign \reset_r $63 + assign \cr_a_ok 1'0 + assign \cr_a_ok \logical_op__write_cr0 sync init end process $group_15 - assign \rok_l_s_rdok 1'0 - assign \rok_l_s_rdok \cu_issue_i + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - cell $and $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_n_valid_o - connect \B \cu_busy_o - connect \Y $65 - end process $group_16 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $65 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_17 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \all_rd - sync init - end - process $group_18 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \rst_r - sync init - end - process $group_19 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_20 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_21 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 4'0000 - end - sync init - update \src_l_s_src 4'0000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_22 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 4'1111 - end - sync init - update \src_l_r_src 4'1111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - wire width 5 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - cell $and $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $67 - end - process $group_23 - assign \req_l_s_req 5'00000 - assign \req_l_s_req $67 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - wire width 5 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - cell $or $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $69 - end - process $group_24 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $69 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 5'11111 - end + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init - update \req_l_r_req 5'11111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2" +module \logical_pipe2 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -50706,7 +35990,7 @@ module \alu0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -50720,1338 +36004,63 @@ module \alu0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__imm_ok + wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc + wire width 64 input 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc_ok + wire width 1 input 8 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe + wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe_ok + wire width 1 input 10 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__invert_a + wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__zero_a + wire width 1 input 12 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__invert_out + wire width 1 input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__write_cr0 + wire width 1 input 14 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__input_carry + wire width 2 input 15 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__output_carry + wire width 1 input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit + wire width 1 input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_signed + wire width 1 input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len + wire width 1 input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_out - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_out$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__input_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__input_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__data_len$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 132 $71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $72 - parameter \WIDTH 132 - connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry \oper_l__input_carry \oper_l__write_cr0 \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } - connect \B { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_a { \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe } { \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc } { \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm } \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } - connect \S \cu_issue_i - connect \Y $71 - end - process $group_25 - assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 11'00000000000 - assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__imm_data__imm_ok 1'0 - assign \oper_r__rc__rc 1'0 - assign \oper_r__rc__rc_ok 1'0 - assign \oper_r__oe__oe 1'0 - assign \oper_r__oe__oe_ok 1'0 - assign \oper_r__invert_a 1'0 - assign \oper_r__zero_a 1'0 - assign \oper_r__invert_out 1'0 - assign \oper_r__write_cr0 1'0 - assign \oper_r__input_carry 2'00 - assign \oper_r__output_carry 1'0 - assign \oper_r__is_32bit 1'0 - assign \oper_r__is_signed 1'0 - assign \oper_r__data_len 4'0000 - assign \oper_r__insn 32'00000000000000000000000000000000 - assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__input_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $71 - sync init - end - process $group_43 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__rc__rc$next \oper_l__rc__rc - assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok - assign \oper_l__oe__oe$next \oper_l__oe__oe - assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok - assign \oper_l__invert_a$next \oper_l__invert_a - assign \oper_l__zero_a$next \oper_l__zero_a - assign \oper_l__invert_out$next \oper_l__invert_out - assign \oper_l__write_cr0$next \oper_l__write_cr0 - assign \oper_l__input_carry$next \oper_l__input_carry - assign \oper_l__output_carry$next \oper_l__output_carry - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__data_len$next \oper_l__data_len - assign \oper_l__insn$next \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__input_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_a { \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe } { \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc } { \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm } \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - assign \oper_l__rc__rc$next 1'0 - assign \oper_l__rc__rc_ok$next 1'0 - assign \oper_l__oe__oe$next 1'0 - assign \oper_l__oe__oe_ok$next 1'0 - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 11'00000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__rc__rc 1'0 - update \oper_l__rc__rc_ok 1'0 - update \oper_l__oe__oe 1'0 - update \oper_l__oe__oe_ok 1'0 - update \oper_l__invert_a 1'0 - update \oper_l__zero_a 1'0 - update \oper_l__invert_out 1'0 - update \oper_l__write_cr0 1'0 - update \oper_l__input_carry 2'00 - update \oper_l__output_carry 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__data_len 4'0000 - update \oper_l__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__rc__rc \oper_l__rc__rc$next - update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next - update \oper_l__oe__oe \oper_l__oe__oe$next - update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next - update \oper_l__invert_a \oper_l__invert_a$next - update \oper_l__zero_a \oper_l__zero_a$next - update \oper_l__invert_out \oper_l__invert_out$next - update \oper_l__write_cr0 \oper_l__write_cr0$next - update \oper_l__input_carry \oper_l__input_carry$next - update \oper_l__output_carry \oper_l__output_carry$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__data_len \oper_l__data_len$next - update \oper_l__insn \oper_l__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $73 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $74 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $74 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $76 - parameter \WIDTH 65 - connect \A { \data_r0_l__o_ok \data_r0_l__o } - connect \B { \o_ok \alu_alu0_o } - connect \S $74 - connect \Y $73 - end - process $group_61 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - assign { \data_r0__o_ok \data_r0__o } $73 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $77 - end - process $group_63 - assign \data_r0_l__o$next \data_r0_l__o - assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_alu0_o } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0_l__o_ok$next 1'0 - end - sync init - update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0_l__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0_l__o \data_r0_l__o$next - update \data_r0_l__o_ok \data_r0_l__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 5 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $80 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $80 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $82 - parameter \WIDTH 5 - connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a } - connect \B { \cr_a_ok \alu_alu0_cr_a } - connect \S $80 - connect \Y $79 - end - process $group_65 - assign \data_r1__cr_a 4'0000 - assign \data_r1__cr_a_ok 1'0 - assign { \data_r1__cr_a_ok \data_r1__cr_a } $79 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $83 - end - process $group_67 - assign \data_r1_l__cr_a$next \data_r1_l__cr_a - assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $83 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_alu0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1_l__cr_a_ok$next 1'0 - end - sync init - update \data_r1_l__cr_a 4'0000 - update \data_r1_l__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r1_l__cr_a \data_r1_l__cr_a$next - update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 3 $85 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $86 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $88 - parameter \WIDTH 3 - connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } - connect \B { \xer_ca_ok \alu_alu0_xer_ca } - connect \S $86 - connect \Y $85 - end - process $group_69 - assign \data_r2__xer_ca 2'00 - assign \data_r2__xer_ca_ok 1'0 - assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $85 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $89 - end - process $group_71 - assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca - assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $89 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \alu_alu0_xer_ca } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2_l__xer_ca_ok$next 1'0 - end - sync init - update \data_r2_l__xer_ca 2'00 - update \data_r2_l__xer_ca_ok 1'0 - sync posedge \coresync_clk - update \data_r2_l__xer_ca \data_r2_l__xer_ca$next - update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 2 \data_r3__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r3__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r3_l__xer_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r3_l__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 3 $91 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $92 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $92 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $94 - parameter \WIDTH 3 - connect \A { \data_r3_l__xer_ov_ok \data_r3_l__xer_ov } - connect \B { \xer_ov_ok \alu_alu0_xer_ov } - connect \S $92 - connect \Y $91 - end - process $group_73 - assign \data_r3__xer_ov 2'00 - assign \data_r3__xer_ov_ok 1'0 - assign { \data_r3__xer_ov_ok \data_r3__xer_ov } $91 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $95 - end - process $group_75 - assign \data_r3_l__xer_ov$next \data_r3_l__xer_ov - assign \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $95 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov$next } { \xer_ov_ok \alu_alu0_xer_ov } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r3_l__xer_ov_ok$next 1'0 - end - sync init - update \data_r3_l__xer_ov 2'00 - update \data_r3_l__xer_ov_ok 1'0 - sync posedge \coresync_clk - update \data_r3_l__xer_ov \data_r3_l__xer_ov$next - update \data_r3_l__xer_ov_ok \data_r3_l__xer_ov_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r4__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r4__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r4_l__xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r4_l__xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r4_l__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r4_l__xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $97 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $98 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $98 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $100 - parameter \WIDTH 2 - connect \A { \data_r4_l__xer_so_ok \data_r4_l__xer_so } - connect \B { \xer_so_ok \alu_alu0_xer_so } - connect \S $98 - connect \Y $97 - end - process $group_77 - assign \data_r4__xer_so 1'0 - assign \data_r4__xer_so_ok 1'0 - assign { \data_r4__xer_so_ok \data_r4__xer_so } $97 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $101 - end - process $group_79 - assign \data_r4_l__xer_so$next \data_r4_l__xer_so - assign \data_r4_l__xer_so_ok$next \data_r4_l__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $101 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r4_l__xer_so_ok$next \data_r4_l__xer_so$next } { \xer_so_ok \alu_alu0_xer_so } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r4_l__xer_so_ok$next 1'0 - end - sync init - update \data_r4_l__xer_so 1'0 - update \data_r4_l__xer_so_ok 1'0 - sync posedge \coresync_clk - update \data_r4_l__xer_so \data_r4_l__xer_so$next - update \data_r4_l__xer_so_ok \data_r4_l__xer_so_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r0__o_ok - connect \B \cu_busy_o - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r1__cr_a_ok - connect \B \cu_busy_o - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r2__xer_ca_ok - connect \B \cu_busy_o - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r3__xer_ov_ok - connect \B \cu_busy_o - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r4__xer_so_ok - connect \B \cu_busy_o - connect \Y $111 - end - process $group_81 - assign \cu_wrmask_o 5'00000 - assign \cu_wrmask_o { $111 $109 $107 $105 $103 } - sync init - end - process $group_82 - assign \alu_alu0_alu_op__insn_type 7'0000000 - assign \alu_alu0_alu_op__fn_unit 11'00000000000 - assign \alu_alu0_alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_alu0_alu_op__imm_data__imm_ok 1'0 - assign \alu_alu0_alu_op__rc__rc 1'0 - assign \alu_alu0_alu_op__rc__rc_ok 1'0 - assign \alu_alu0_alu_op__oe__oe 1'0 - assign \alu_alu0_alu_op__oe__oe_ok 1'0 - assign \alu_alu0_alu_op__invert_a 1'0 - assign \alu_alu0_alu_op__zero_a 1'0 - assign \alu_alu0_alu_op__invert_out 1'0 - assign \alu_alu0_alu_op__write_cr0 1'0 - assign \alu_alu0_alu_op__input_carry 2'00 - assign \alu_alu0_alu_op__output_carry 1'0 - assign \alu_alu0_alu_op__is_32bit 1'0 - assign \alu_alu0_alu_op__is_signed 1'0 - assign \alu_alu0_alu_op__data_len 4'0000 - assign \alu_alu0_alu_op__insn 32'00000000000000000000000000000000 - assign { \alu_alu0_alu_op__insn \alu_alu0_alu_op__data_len \alu_alu0_alu_op__is_signed \alu_alu0_alu_op__is_32bit \alu_alu0_alu_op__output_carry \alu_alu0_alu_op__input_carry \alu_alu0_alu_op__write_cr0 \alu_alu0_alu_op__invert_out \alu_alu0_alu_op__zero_a \alu_alu0_alu_op__invert_a { \alu_alu0_alu_op__oe__oe_ok \alu_alu0_alu_op__oe__oe } { \alu_alu0_alu_op__rc__rc_ok \alu_alu0_alu_op__rc__rc } { \alu_alu0_alu_op__imm_data__imm_ok \alu_alu0_alu_op__imm_data__imm } \alu_alu0_alu_op__fn_unit \alu_alu0_alu_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__input_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - cell $mux $114 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \oper_r__zero_a - connect \Y $113 - end - process $group_100 - assign \src_sel 1'0 - assign \src_sel $113 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 64 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $116 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \oper_r__zero_a - connect \Y $115 - end - process $group_101 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $115 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 1 \src_sel$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - cell $mux $119 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \oper_r__imm_data__imm_ok - connect \Y $118 - end - process $group_102 - assign \src_sel$117 1'0 - assign \src_sel$117 $118 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165" - wire width 64 \src_or_imm$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 64 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $122 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \oper_r__imm_data__imm - connect \S \oper_r__imm_data__imm_ok - connect \Y $121 - end - process $group_103 - assign \src_or_imm$120 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$120 $121 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $124 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $123 - end - process $group_104 - assign \alu_alu0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_alu0_ra $123 - sync init - end - process $group_105 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src_or_imm - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $126 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$120 - connect \S \src_sel$117 - connect \Y $125 - end - process $group_106 - assign \alu_alu0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_alu0_rb $125 - sync init - end - process $group_107 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel$117 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src_or_imm$120 - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $128 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $127 - end - process $group_108 - assign \alu_alu0_xer_so$1 1'0 - assign \alu_alu0_xer_so$1 $127 - sync init - end - process $group_109 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 1'0 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $129 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $130 - parameter \WIDTH 2 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $129 - end - process $group_110 - assign \alu_alu0_xer_ca$2 2'00 - assign \alu_alu0_xer_ca$2 $129 - sync init - end - process $group_111 - assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r3$next \src4_i - end - sync init - update \src_r3 2'00 - sync posedge \coresync_clk - update \src_r3 \src_r3$next - end - process $group_112 - assign \alu_alu0_p_valid_i 1'0 - assign \alu_alu0_p_valid_i \alui_l_q_alui - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - wire width 1 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - cell $and $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $131 - end - process $group_113 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $131 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end - sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next - end - process $group_114 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init - end - process $group_115 - assign \alu_alu0_n_ready_i 1'0 - assign \alu_alu0_n_ready_i \alu_l_q_alu - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - wire width 1 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - cell $and $134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $133 - end - process $group_116 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $133 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_117 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_118 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $135 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - wire width 1 $137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - cell $not $138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \oper_r__zero_a - connect \Y $137 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - wire width 1 $139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - cell $not $140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \oper_r__imm_data__imm_ok - connect \Y $139 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $135 - connect \B { 1'1 1'1 $139 $137 } - connect \Y $141 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $not $144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rdmaskn_i - connect \Y $143 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $141 - connect \B $143 - connect \Y $145 - end - process $group_119 - assign \cu_rd__rel_o 4'0000 - assign \cu_rd__rel_o $145 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $147 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $149 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $151 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $153 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $155 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 5 $157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B { $147 $149 $151 $153 $155 } - connect \Y $157 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 5 $159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $157 - connect \B \cu_wrmask_o - connect \Y $159 - end - process $group_120 - assign \cu_wr__rel_o 5'00000 - assign \cu_wr__rel_o $159 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $161 - end - process $group_121 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $161 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $163 - end - process $group_122 - assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $163 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $165 - end - process $group_123 - assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $165 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $167 - end - process $group_124 - assign \dest4_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $167 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest4_o { \data_r3__xer_ov_ok \data_r3__xer_ov } [1:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [4] - connect \B \cu_busy_o - connect \Y $169 - end - process $group_125 - assign \dest5_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $169 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest5_o { \data_r4__xer_so_ok \data_r4__xer_so } [0] - end - sync init - end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.p" -module \p$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.n" -module \n$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.p" -module \p$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.n" -module \n$8 + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 28 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o + wire width 1 output 29 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.main" -module \main$9 + wire width 1 input 30 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid + wire width 2 output 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -52126,7 +36135,9 @@ module \main$9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \cr_op__insn_type + wire width 7 output 32 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -52140,27 +36151,111 @@ module \main$9 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \cr_op__fn_unit + wire width 11 output 33 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \cr_op__insn + wire width 11 \logical_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \cr_op__read_cr_whole + wire width 64 output 34 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \cr_op__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 6 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 7 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 8 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 9 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 10 \cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 11 \cr_c + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 42 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 50 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 51 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 52 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 53 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 54 \xer_ca$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 55 \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$25$next + cell \p$49 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$50 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 12 \muxid$1 + wire width 2 \output_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -52235,7 +36330,7 @@ module \main$9 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 13 \cr_op__insn_type$2 + wire width 7 \output_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -52249,685 +36344,53 @@ module \main$9 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 14 \cr_op__fn_unit$3 + wire width 11 \output_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 15 \cr_op__insn$4 + wire width 64 \output_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 16 \cr_op__read_cr_whole$5 + wire width 1 \output_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 17 \cr_op__write_cr_whole$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 18 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 19 \o_ok + wire width 1 \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 output 20 \full_cr$7 + wire width 64 \output_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 21 \full_cr_ok + wire width 1 \output_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 22 \cr_a$8 + wire width 4 \output_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:47" - wire width 32 \mask - process $group_0 - assign \mask 32'00000000000000000000000000000000 - assign \mask { { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [7] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [6] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [5] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [4] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [3] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [2] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [1] } { { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] { \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] } [0] } } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 5 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A \cr_a - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - wire width 1 \bit_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:84" - wire width 2 \bt - process $group_1 - assign \cr_a$8 4'0000 - assign \cr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - assign { \cr_a_ok \cr_a$8 } $9 - assign \cr_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \cr_a$8 \cr_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:108" - switch \bt - case 2'00 - assign { \cr_a_ok \cr_a$8 } [0] \bit_o - case 2'01 - assign { \cr_a_ok \cr_a$8 } [1] \bit_o - case 2'10 - assign { \cr_a_ok \cr_a$8 } [2] \bit_o - case 2'-- - assign { \cr_a_ok \cr_a$8 } [3] \bit_o - end - switch { } - case - assign \cr_a_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:73" - wire width 4 \lut - process $group_3 - assign \lut 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \lut \cr_op__insn [9:6] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:89" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:89" - wire width 3 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:89" - cell $sub $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B { \cr_op__insn [25] \cr_op__insn [24] \cr_op__insn [23] \cr_op__insn [22] \cr_op__insn [21] } [1:0] - connect \Y $12 - end - connect $11 $12 - process $group_4 - assign \bt 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \bt $11 [1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:85" - wire width 2 \ba - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:90" - wire width 3 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:90" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:90" - cell $sub $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B { \cr_op__insn [20] \cr_op__insn [19] \cr_op__insn [18] \cr_op__insn [17] \cr_op__insn [16] } [1:0] - connect \Y $15 - end - connect $14 $15 - process $group_5 - assign \ba 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \ba $14 [1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - wire width 2 \bb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" - wire width 3 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" - wire width 3 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" - cell $sub $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B { \cr_op__insn [15] \cr_op__insn [14] \cr_op__insn [13] \cr_op__insn [12] \cr_op__insn [11] } [1:0] - connect \Y $18 - end - connect $17 $18 - process $group_6 - assign \bb 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \bb $17 [1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" - wire width 1 \bit_a - process $group_7 - assign \bit_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:96" - switch \ba - case 2'00 - assign \bit_a \cr_a [0] - case 2'01 - assign \bit_a \cr_a [1] - case 2'10 - assign \bit_a \cr_a [2] - case 2'-- - assign \bit_a \cr_a [3] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:95" - wire width 1 \bit_b - process $group_8 - assign \bit_b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97" - switch \bb - case 2'00 - assign \bit_b \cr_b [0] - case 2'01 - assign \bit_b \cr_b [1] - case 2'10 - assign \bit_b \cr_b [2] - case 2'-- - assign \bit_b \cr_b [3] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:102" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:102" - cell $mux $21 - parameter \WIDTH 1 - connect \A \lut [1] - connect \B \lut [3] - connect \S \bit_a - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:103" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:103" - cell $mux $23 - parameter \WIDTH 1 - connect \A \lut [0] - connect \B \lut [2] - connect \S \bit_a - connect \Y $22 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:103" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:103" - cell $mux $25 - parameter \WIDTH 1 - connect \A $22 - connect \B $20 - connect \S \bit_b - connect \Y $24 - end - process $group_9 - assign \bit_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \bit_o $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" - wire width 32 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \ra [31:0] - connect \B \mask - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" - wire width 32 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" - cell $not $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \mask - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" - wire width 32 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" - cell $and $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \full_cr - connect \B $28 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" - wire width 32 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:116" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $26 - connect \B $30 - connect \Y $32 - end - process $group_10 - assign \full_cr$7 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - assign \full_cr$7 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - process $group_11 - assign \full_cr_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - assign \full_cr_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:124" - wire width 1 \move_one - process $group_12 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - assign \move_one \cr_op__insn [20] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:130" - wire width 64 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:130" - wire width 32 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:130" - cell $and $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \full_cr - connect \B \mask - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:130" - cell $pos $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A $35 - connect \Y $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \full_cr - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:150" - wire width 65 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:150" - wire width 64 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:146" - wire width 1 \cr_bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:150" - cell $mux $42 - parameter \WIDTH 64 - connect \A \rb - connect \B \ra - connect \S \cr_bit - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:150" - cell $pos $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A $41 - connect \Y $40 - end - process $group_13 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:128" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:128" - case 1'1 - assign \o $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:132" - case - assign \o $38 - end - switch { } - case - assign \o_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - assign { \o_ok \o } $40 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154" - switch { \cr_a [2] \cr_a [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:154" - case 2'-1 - assign \o 64'1111111111111111111111111111111111111111111111111111111111111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:156" - case 2'1- - assign \o 64'0000000000000000000000000000000000000000000000000000000000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:158" - case - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - end - switch { } - case - assign \o_ok 1'1 - end - end - sync init - end - process $group_15 - assign \cr_bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:55" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:57" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:66" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:112" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:120" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:138" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:147" - switch { \cr_op__insn [10] \cr_op__insn [9] \cr_op__insn [8] \cr_op__insn [7] \cr_op__insn [6] } [1:0] - case 2'00 - assign \cr_bit \cr_a [3] - case 2'01 - assign \cr_bit \cr_a [2] - case 2'10 - assign \cr_bit \cr_a [1] - case 2'-- - assign \cr_bit \cr_a [0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:153" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - process $group_16 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_17 - assign \cr_op__insn_type$2 7'0000000 - assign \cr_op__fn_unit$3 11'00000000000 - assign \cr_op__insn$4 32'00000000000000000000000000000000 - assign \cr_op__read_cr_whole$5 1'0 - assign \cr_op__write_cr_whole$6 1'0 - assign { \cr_op__write_cr_whole$6 \cr_op__read_cr_whole$5 \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe" -module \pipe$6 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o + wire width 2 \output_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid + wire width 2 \output_muxid$26 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -53002,7 +36465,7 @@ module \pipe$6 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \cr_op__insn_type + wire width 7 \output_logical_op__insn_type$27 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -53016,33 +36479,195 @@ module \pipe$6 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \cr_op__fn_unit + wire width 11 \output_logical_op__fn_unit$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \cr_op__insn + wire width 64 \output_logical_op__imm_data__imm$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \cr_op__read_cr_whole + wire width 1 \output_logical_op__imm_data__imm_ok$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \cr_op__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 12 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 13 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 14 \cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 15 \cr_c - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 16 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 17 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 18 \muxid$1 + wire width 1 \output_logical_op__rc__rc$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__rc__rc_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__oe__oe$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__oe__oe_ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__invert_in$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__zero_a$36 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__invert_out$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__write_cr0$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__output_carry$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__is_32bit$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__is_signed$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_o_ok$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_ca_ok + cell \output$51 \output + connect \muxid \output_muxid + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__imm_data__imm \output_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc_ok \output_logical_op__rc__rc_ok + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe_ok \output_logical_op__oe__oe_ok + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__insn \output_logical_op__insn + connect \o \output_o + connect \o_ok \output_o_ok + connect \cr_a \output_cr_a + connect \xer_ca \output_xer_ca + connect \muxid$1 \output_muxid$26 + connect \logical_op__insn_type$2 \output_logical_op__insn_type$27 + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$28 + connect \logical_op__imm_data__imm$4 \output_logical_op__imm_data__imm$29 + connect \logical_op__imm_data__imm_ok$5 \output_logical_op__imm_data__imm_ok$30 + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$31 + connect \logical_op__rc__rc_ok$7 \output_logical_op__rc__rc_ok$32 + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$33 + connect \logical_op__oe__oe_ok$9 \output_logical_op__oe__oe_ok$34 + connect \logical_op__invert_in$10 \output_logical_op__invert_in$35 + connect \logical_op__zero_a$11 \output_logical_op__zero_a$36 + connect \logical_op__input_carry$12 \output_logical_op__input_carry$37 + connect \logical_op__invert_out$13 \output_logical_op__invert_out$38 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$39 + connect \logical_op__output_carry$15 \output_logical_op__output_carry$40 + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$41 + connect \logical_op__is_signed$17 \output_logical_op__is_signed$42 + connect \logical_op__data_len$18 \output_logical_op__data_len$43 + connect \logical_op__insn$19 \output_logical_op__insn$44 + connect \o$20 \output_o$45 + connect \o_ok$21 \output_o_ok$46 + connect \cr_a$22 \output_cr_a$47 + connect \cr_a_ok \output_cr_a_ok + connect \xer_ca$23 \output_xer_ca$48 + connect \xer_ca_ok \output_xer_ca_ok + end + process $group_0 + assign \output_muxid 2'00 + assign \output_muxid \muxid + sync init + end + process $group_1 + assign \output_logical_op__insn_type 7'0000000 + assign \output_logical_op__fn_unit 11'00000000000 + assign \output_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_logical_op__imm_data__imm_ok 1'0 + assign \output_logical_op__rc__rc 1'0 + assign \output_logical_op__rc__rc_ok 1'0 + assign \output_logical_op__oe__oe 1'0 + assign \output_logical_op__oe__oe_ok 1'0 + assign \output_logical_op__invert_in 1'0 + assign \output_logical_op__zero_a 1'0 + assign \output_logical_op__input_carry 2'00 + assign \output_logical_op__invert_out 1'0 + assign \output_logical_op__write_cr0 1'0 + assign \output_logical_op__output_carry 1'0 + assign \output_logical_op__is_32bit 1'0 + assign \output_logical_op__is_signed 1'0 + assign \output_logical_op__data_len 4'0000 + assign \output_logical_op__insn 32'00000000000000000000000000000000 + assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in { \output_logical_op__oe__oe_ok \output_logical_op__oe__oe } { \output_logical_op__rc__rc_ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm } \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_o_ok 1'0 + assign { \output_o_ok \output_o } { \o_ok \o } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$49 + process $group_21 + assign \output_cr_a 4'0000 + assign \cr_a_ok$49 1'0 + assign { \cr_a_ok$49 \output_cr_a } { \cr_a_ok \cr_a } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$50 + process $group_23 + assign \output_xer_ca 2'00 + assign \xer_ca_ok$50 1'0 + assign { \xer_ca_ok$50 \output_xer_ca } { \xer_ca_ok \xer_ca } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$51 + process $group_25 + assign \p_valid_i$51 1'0 + assign \p_valid_i$51 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_26 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$51 + connect \B \p_ready_o + connect \Y $52 + end + process $group_27 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $52 + sync init + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next + wire width 2 \muxid$54 + process $group_28 + assign \muxid$54 2'00 + assign \muxid$54 \output_muxid$26 + sync init + end attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -53117,9 +36742,7 @@ module \pipe$6 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 19 \cr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$2$next + wire width 7 \logical_op__insn_type$55 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -53133,55 +36756,313 @@ module \pipe$6 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 20 \cr_op__fn_unit$3 + wire width 11 \logical_op__fn_unit$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \cr_op__fn_unit$3$next + wire width 64 \logical_op__imm_data__imm$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 21 \cr_op__insn$4 + wire width 1 \logical_op__imm_data__imm_ok$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$4$next + wire width 1 \logical_op__rc__rc$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 22 \cr_op__read_cr_whole$5 + wire width 1 \logical_op__rc__rc_ok$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__read_cr_whole$5$next + wire width 1 \logical_op__oe__oe$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 23 \cr_op__write_cr_whole$6 + wire width 1 \logical_op__oe__oe_ok$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__write_cr_whole$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 25 \o_ok + wire width 1 \logical_op__invert_in$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$64 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$72 + process $group_29 + assign \logical_op__insn_type$55 7'0000000 + assign \logical_op__fn_unit$56 11'00000000000 + assign \logical_op__imm_data__imm$57 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$58 1'0 + assign \logical_op__rc__rc$59 1'0 + assign \logical_op__rc__rc_ok$60 1'0 + assign \logical_op__oe__oe$61 1'0 + assign \logical_op__oe__oe_ok$62 1'0 + assign \logical_op__invert_in$63 1'0 + assign \logical_op__zero_a$64 1'0 + assign \logical_op__input_carry$65 2'00 + assign \logical_op__invert_out$66 1'0 + assign \logical_op__write_cr0$67 1'0 + assign \logical_op__output_carry$68 1'0 + assign \logical_op__is_32bit$69 1'0 + assign \logical_op__is_signed$70 1'0 + assign \logical_op__data_len$71 4'0000 + assign \logical_op__insn$72 32'00000000000000000000000000000000 + assign { \logical_op__insn$72 \logical_op__data_len$71 \logical_op__is_signed$70 \logical_op__is_32bit$69 \logical_op__output_carry$68 \logical_op__write_cr0$67 \logical_op__invert_out$66 \logical_op__input_carry$65 \logical_op__zero_a$64 \logical_op__invert_in$63 { \logical_op__oe__oe_ok$62 \logical_op__oe__oe$61 } { \logical_op__rc__rc_ok$60 \logical_op__rc__rc$59 } { \logical_op__imm_data__imm_ok$58 \logical_op__imm_data__imm$57 } \logical_op__fn_unit$56 \logical_op__insn_type$55 } { \output_logical_op__insn$44 \output_logical_op__data_len$43 \output_logical_op__is_signed$42 \output_logical_op__is_32bit$41 \output_logical_op__output_carry$40 \output_logical_op__write_cr0$39 \output_logical_op__invert_out$38 \output_logical_op__input_carry$37 \output_logical_op__zero_a$36 \output_logical_op__invert_in$35 { \output_logical_op__oe__oe_ok$34 \output_logical_op__oe__oe$33 } { \output_logical_op__rc__rc_ok$32 \output_logical_op__rc__rc$31 } { \output_logical_op__imm_data__imm_ok$30 \output_logical_op__imm_data__imm$29 } \output_logical_op__fn_unit$28 \output_logical_op__insn_type$27 } + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$next + wire width 64 \o$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 output 26 \full_cr$7 + wire width 1 \o_ok$74 + process $group_47 + assign \o$73 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$74 1'0 + assign { \o_ok$74 \o$73 } { \output_o_ok$46 \output_o$45 } + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \full_cr$7$next + wire width 4 \cr_a$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 27 \full_cr_ok + wire width 1 \cr_a_ok$76 + process $group_49 + assign \cr_a$75 4'0000 + assign \cr_a_ok$76 1'0 + assign { \cr_a_ok$76 \cr_a$75 } { \output_cr_a_ok \output_cr_a$47 } + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \full_cr_ok$next + wire width 2 \xer_ca$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 28 \cr_a$8 + wire width 1 \xer_ca_ok$78 + process $group_51 + assign \xer_ca$77 2'00 + assign \xer_ca_ok$78 1'0 + assign { \xer_ca_ok$78 \xer_ca$77 } { \output_xer_ca_ok \output_xer_ca$48 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_53 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_54 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$54 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_55 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$72 \logical_op__data_len$71 \logical_op__is_signed$70 \logical_op__is_32bit$69 \logical_op__output_carry$68 \logical_op__write_cr0$67 \logical_op__invert_out$66 \logical_op__input_carry$65 \logical_op__zero_a$64 \logical_op__invert_in$63 { \logical_op__oe__oe_ok$62 \logical_op__oe__oe$61 } { \logical_op__rc__rc_ok$60 \logical_op__rc__rc$59 } { \logical_op__imm_data__imm_ok$58 \logical_op__imm_data__imm$57 } \logical_op__fn_unit$56 \logical_op__insn_type$55 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$72 \logical_op__data_len$71 \logical_op__is_signed$70 \logical_op__is_32bit$69 \logical_op__output_carry$68 \logical_op__write_cr0$67 \logical_op__invert_out$66 \logical_op__input_carry$65 \logical_op__zero_a$64 \logical_op__invert_in$63 { \logical_op__oe__oe_ok$62 \logical_op__oe__oe$61 } { \logical_op__rc__rc_ok$60 \logical_op__rc__rc$59 } { \logical_op__imm_data__imm_ok$58 \logical_op__imm_data__imm$57 } \logical_op__fn_unit$56 \logical_op__insn_type$55 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_73 + assign \o$20$next \o$20 + assign \o_ok$21$next \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$21$next \o$20$next } { \o_ok$74 \o$73 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$21$next \o$20$next } { \o_ok$74 \o$73 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \o_ok$21$next 1'0 + end + sync init + update \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok$21 1'0 + sync posedge \coresync_clk + update \o$20 \o$20$next + update \o_ok$21 \o_ok$21$next + end + process $group_75 + assign \cr_a$22$next \cr_a$22 + assign \cr_a_ok$23$next \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$76 \cr_a$75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$76 \cr_a$75 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cr_a_ok$23$next 1'0 + end + sync init + update \cr_a$22 4'0000 + update \cr_a_ok$23 1'0 + sync posedge \coresync_clk + update \cr_a$22 \cr_a$22$next + update \cr_a_ok$23 \cr_a_ok$23$next + end + process $group_77 + assign \xer_ca$24$next \xer_ca$24 + assign \xer_ca_ok$25$next \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ca_ok$25$next \xer_ca$24$next } { \xer_ca_ok$78 \xer_ca$77 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ca_ok$25$next \xer_ca$24$next } { \xer_ca_ok$78 \xer_ca$77 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ca_ok$25$next 1'0 + end + sync init + update \xer_ca$24 2'00 + update \xer_ca_ok$25 1'0 + sync posedge \coresync_clk + update \xer_ca$24 \xer_ca$24$next + update \xer_ca_ok$25 \xer_ca_ok$25$next + end + process $group_79 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_80 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0" +module \alu_logical0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$8$next + wire width 1 output 1 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 29 \cr_a_ok + wire width 1 output 2 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$next - cell \p$7 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$8 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid + wire width 1 output 3 \xer_ca_ok + attribute \src "simple/issuer.py:102" + wire width 1 input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 6 \n_ready_i attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -53256,7 +37137,7 @@ module \pipe$6 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type + wire width 7 input 7 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -53270,27 +37151,71 @@ module \pipe$6 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_cr_op__fn_unit + wire width 11 input 8 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn + wire width 64 input 9 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_cr_op__read_cr_whole + wire width 1 input 10 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_cr_op__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \main_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_a + wire width 1 input 11 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 21 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 22 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 23 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 24 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 25 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 26 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 27 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_b + wire width 64 input 28 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_c + wire width 64 input 29 \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 30 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 31 \p_ready_o + cell \p$43 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$44 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \logical_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \logical_pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$9 + wire width 2 \logical_pipe1_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -53365,7 +37290,7 @@ module \pipe$6 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type$10 + wire width 7 \logical_pipe1_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -53379,136 +37304,61 @@ module \pipe$6 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_cr_op__fn_unit$11 + wire width 11 \logical_pipe1_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn$12 + wire width 64 \logical_pipe1_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_cr_op__read_cr_whole$13 + wire width 1 \logical_pipe1_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_cr_op__write_cr_whole$14 + wire width 1 \logical_pipe1_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o + wire width 64 \logical_pipe1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_o_ok + wire width 1 \logical_pipe1_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \main_full_cr$15 + wire width 4 \logical_pipe1_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_full_cr_ok + wire width 1 \logical_pipe1_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \main_cr_a$16 + wire width 2 \logical_pipe1_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_cr_a_ok - cell \main$9 \main - connect \muxid \main_muxid - connect \cr_op__insn_type \main_cr_op__insn_type - connect \cr_op__fn_unit \main_cr_op__fn_unit - connect \cr_op__insn \main_cr_op__insn - connect \cr_op__read_cr_whole \main_cr_op__read_cr_whole - connect \cr_op__write_cr_whole \main_cr_op__write_cr_whole - connect \ra \main_ra - connect \rb \main_rb - connect \full_cr \main_full_cr - connect \cr_a \main_cr_a - connect \cr_b \main_cr_b - connect \cr_c \main_cr_c - connect \muxid$1 \main_muxid$9 - connect \cr_op__insn_type$2 \main_cr_op__insn_type$10 - connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$11 - connect \cr_op__insn$4 \main_cr_op__insn$12 - connect \cr_op__read_cr_whole$5 \main_cr_op__read_cr_whole$13 - connect \cr_op__write_cr_whole$6 \main_cr_op__write_cr_whole$14 - connect \o \main_o - connect \o_ok \main_o_ok - connect \full_cr$7 \main_full_cr$15 - connect \full_cr_ok \main_full_cr_ok - connect \cr_a$8 \main_cr_a$16 - connect \cr_a_ok \main_cr_a_ok - end - process $group_0 - assign \main_muxid 2'00 - assign \main_muxid \muxid - sync init - end - process $group_1 - assign \main_cr_op__insn_type 7'0000000 - assign \main_cr_op__fn_unit 11'00000000000 - assign \main_cr_op__insn 32'00000000000000000000000000000000 - assign \main_cr_op__read_cr_whole 1'0 - assign \main_cr_op__write_cr_whole 1'0 - assign { \main_cr_op__write_cr_whole \main_cr_op__read_cr_whole \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - sync init - end - process $group_6 - assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \ra - sync init - end - process $group_7 - assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \rb - sync init - end - process $group_8 - assign \main_full_cr 32'00000000000000000000000000000000 - assign \main_full_cr \full_cr - sync init - end - process $group_9 - assign \main_cr_a 4'0000 - assign \main_cr_a \cr_a - sync init - end - process $group_10 - assign \main_cr_b 4'0000 - assign \main_cr_b \cr_b - sync init - end - process $group_11 - assign \main_cr_c 4'0000 - assign \main_cr_c \cr_c - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$17 - process $group_12 - assign \p_valid_i$17 1'0 - assign \p_valid_i$17 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_13 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$17 - connect \B \p_ready_o - connect \Y $18 - end - process $group_14 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $18 - sync init - end + wire width 1 \logical_pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \logical_pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \logical_pipe1_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$20 - process $group_15 - assign \muxid$20 2'00 - assign \muxid$20 \main_muxid$9 - sync init - end + wire width 2 \logical_pipe1_muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -53583,7 +37433,7 @@ module \pipe$6 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$21 + wire width 7 \logical_pipe1_logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -53597,352 +37447,107 @@ module \pipe$6 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \cr_op__fn_unit$22 + wire width 11 \logical_pipe1_logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$23 + wire width 64 \logical_pipe1_logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__read_cr_whole$24 + wire width 1 \logical_pipe1_logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__write_cr_whole$25 - process $group_16 - assign \cr_op__insn_type$21 7'0000000 - assign \cr_op__fn_unit$22 11'00000000000 - assign \cr_op__insn$23 32'00000000000000000000000000000000 - assign \cr_op__read_cr_whole$24 1'0 - assign \cr_op__write_cr_whole$25 1'0 - assign { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 } { \main_cr_op__write_cr_whole$14 \main_cr_op__read_cr_whole$13 \main_cr_op__insn$12 \main_cr_op__fn_unit$11 \main_cr_op__insn_type$10 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$27 - process $group_21 - assign \o$26 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$27 1'0 - assign { \o_ok$27 \o$26 } { \main_o_ok \main_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \full_cr$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \full_cr_ok$29 - process $group_23 - assign \full_cr$28 32'00000000000000000000000000000000 - assign \full_cr_ok$29 1'0 - assign { \full_cr_ok$29 \full_cr$28 } { \main_full_cr_ok \main_full_cr$15 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$31 - process $group_25 - assign \cr_a$30 4'0000 - assign \cr_a_ok$31 1'0 - assign { \cr_a_ok$31 \cr_a$30 } { \main_cr_a_ok \main_cr_a$16 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_27 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_28 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$20 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_29 - assign \cr_op__insn_type$2$next \cr_op__insn_type$2 - assign \cr_op__fn_unit$3$next \cr_op__fn_unit$3 - assign \cr_op__insn$4$next \cr_op__insn$4 - assign \cr_op__read_cr_whole$5$next \cr_op__read_cr_whole$5 - assign \cr_op__write_cr_whole$6$next \cr_op__write_cr_whole$6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_op__write_cr_whole$6$next \cr_op__read_cr_whole$5$next \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_op__write_cr_whole$6$next \cr_op__read_cr_whole$5$next \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__write_cr_whole$25 \cr_op__read_cr_whole$24 \cr_op__insn$23 \cr_op__fn_unit$22 \cr_op__insn_type$21 } - end - sync init - update \cr_op__insn_type$2 7'0000000 - update \cr_op__fn_unit$3 11'00000000000 - update \cr_op__insn$4 32'00000000000000000000000000000000 - update \cr_op__read_cr_whole$5 1'0 - update \cr_op__write_cr_whole$6 1'0 - sync posedge \coresync_clk - update \cr_op__insn_type$2 \cr_op__insn_type$2$next - update \cr_op__fn_unit$3 \cr_op__fn_unit$3$next - update \cr_op__insn$4 \cr_op__insn$4$next - update \cr_op__read_cr_whole$5 \cr_op__read_cr_whole$5$next - update \cr_op__write_cr_whole$6 \cr_op__write_cr_whole$6$next - end - process $group_34 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$27 \o$26 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$27 \o$26 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_36 - assign \full_cr$7$next \full_cr$7 - assign \full_cr_ok$next \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \full_cr_ok$next \full_cr$7$next } { \full_cr_ok$29 \full_cr$28 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \full_cr_ok$next \full_cr$7$next } { \full_cr_ok$29 \full_cr$28 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \full_cr_ok$next 1'0 - end - sync init - update \full_cr$7 32'00000000000000000000000000000000 - update \full_cr_ok 1'0 - sync posedge \coresync_clk - update \full_cr$7 \full_cr$7$next - update \full_cr_ok \full_cr_ok$next - end - process $group_38 - assign \cr_a$8$next \cr_a$8 - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$8$next } { \cr_a_ok$31 \cr_a$30 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$8$next } { \cr_a_ok$31 \cr_a$30 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a$8 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a$8 \cr_a$8$next - update \cr_a_ok \cr_a_ok$next - end - process $group_40 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_41 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0" -module \alu_cr0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \cr_a_ok - attribute \src "simple/issuer.py:89" - wire width 1 input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 7 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 output 8 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 9 \cr_a - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" + wire width 1 \logical_pipe1_logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 10 \cr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" + wire width 1 \logical_pipe1_logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 11 \cr_op__fn_unit + wire width 1 \logical_pipe1_logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \cr_op__insn + wire width 1 \logical_pipe1_logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \cr_op__read_cr_whole + wire width 1 \logical_pipe1_logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \cr_op__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 15 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 16 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 17 \full_cr$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 18 \cr_a$2 + wire width 1 \logical_pipe1_logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe1_logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 19 \cr_b + wire width 64 \logical_pipe1_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 20 \cr_c - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 21 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 22 \p_ready_o - cell \p$4 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$5 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + wire width 64 \logical_pipe1_rb + cell \logical_pipe1 \logical_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \n_valid_o \logical_pipe1_n_valid_o + connect \n_ready_i \logical_pipe1_n_ready_i + connect \muxid \logical_pipe1_muxid + connect \logical_op__insn_type \logical_pipe1_logical_op__insn_type + connect \logical_op__fn_unit \logical_pipe1_logical_op__fn_unit + connect \logical_op__imm_data__imm \logical_pipe1_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \logical_pipe1_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \logical_pipe1_logical_op__rc__rc + connect \logical_op__rc__rc_ok \logical_pipe1_logical_op__rc__rc_ok + connect \logical_op__oe__oe \logical_pipe1_logical_op__oe__oe + connect \logical_op__oe__oe_ok \logical_pipe1_logical_op__oe__oe_ok + connect \logical_op__invert_in \logical_pipe1_logical_op__invert_in + connect \logical_op__zero_a \logical_pipe1_logical_op__zero_a + connect \logical_op__input_carry \logical_pipe1_logical_op__input_carry + connect \logical_op__invert_out \logical_pipe1_logical_op__invert_out + connect \logical_op__write_cr0 \logical_pipe1_logical_op__write_cr0 + connect \logical_op__output_carry \logical_pipe1_logical_op__output_carry + connect \logical_op__is_32bit \logical_pipe1_logical_op__is_32bit + connect \logical_op__is_signed \logical_pipe1_logical_op__is_signed + connect \logical_op__data_len \logical_pipe1_logical_op__data_len + connect \logical_op__insn \logical_pipe1_logical_op__insn + connect \o \logical_pipe1_o + connect \o_ok \logical_pipe1_o_ok + connect \cr_a \logical_pipe1_cr_a + connect \cr_a_ok \logical_pipe1_cr_a_ok + connect \xer_ca \logical_pipe1_xer_ca + connect \xer_ca_ok \logical_pipe1_xer_ca_ok + connect \p_valid_i \logical_pipe1_p_valid_i + connect \p_ready_o \logical_pipe1_p_ready_o + connect \muxid$1 \logical_pipe1_muxid$1 + connect \logical_op__insn_type$2 \logical_pipe1_logical_op__insn_type$2 + connect \logical_op__fn_unit$3 \logical_pipe1_logical_op__fn_unit$3 + connect \logical_op__imm_data__imm$4 \logical_pipe1_logical_op__imm_data__imm$4 + connect \logical_op__imm_data__imm_ok$5 \logical_pipe1_logical_op__imm_data__imm_ok$5 + connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 + connect \logical_op__rc__rc_ok$7 \logical_pipe1_logical_op__rc__rc_ok$7 + connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 + connect \logical_op__oe__oe_ok$9 \logical_pipe1_logical_op__oe__oe_ok$9 + connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 + connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 + connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 + connect \logical_op__invert_out$13 \logical_pipe1_logical_op__invert_out$13 + connect \logical_op__write_cr0$14 \logical_pipe1_logical_op__write_cr0$14 + connect \logical_op__output_carry$15 \logical_pipe1_logical_op__output_carry$15 + connect \logical_op__is_32bit$16 \logical_pipe1_logical_op__is_32bit$16 + connect \logical_op__is_signed$17 \logical_pipe1_logical_op__is_signed$17 + connect \logical_op__data_len$18 \logical_pipe1_logical_op__data_len$18 + connect \logical_op__insn$19 \logical_pipe1_logical_op__insn$19 + connect \ra \logical_pipe1_ra + connect \rb \logical_pipe1_rb end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_p_valid_i + wire width 1 \logical_pipe2_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_p_ready_o + wire width 1 \logical_pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid + wire width 2 \logical_pipe2_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -54017,7 +37622,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_cr_op__insn_type + wire width 7 \logical_pipe2_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -54031,31 +37636,61 @@ module \alu_cr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_cr_op__fn_unit + wire width 11 \logical_pipe2_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_cr_op__insn + wire width 64 \logical_pipe2_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_cr_op__read_cr_whole + wire width 1 \logical_pipe2_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_cr_op__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \pipe_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_c + wire width 1 \logical_pipe2_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe2_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \logical_pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \logical_pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \logical_pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \logical_pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \logical_pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \logical_pipe2_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_n_valid_o + wire width 1 \logical_pipe2_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_n_ready_i + wire width 1 \logical_pipe2_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 + wire width 2 \logical_pipe2_muxid$20 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -54130,7 +37765,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_cr_op__insn_type$4 + wire width 7 \logical_pipe2_logical_op__insn_type$21 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -54144,128 +37779,232 @@ module \alu_cr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_cr_op__fn_unit$5 + wire width 11 \logical_pipe2_logical_op__fn_unit$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_cr_op__insn$6 + wire width 64 \logical_pipe2_logical_op__imm_data__imm$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_cr_op__read_cr_whole$7 + wire width 1 \logical_pipe2_logical_op__imm_data__imm_ok$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_cr_op__write_cr_whole$8 + wire width 1 \logical_pipe2_logical_op__rc__rc$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__rc__rc_ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__oe__oe$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__oe__oe_ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__invert_in$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__zero_a$30 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__invert_out$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__write_cr0$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__output_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__is_32bit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_pipe2_logical_op__is_signed$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe2_logical_op__data_len$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o + wire width 64 \logical_pipe2_o$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_o_ok + wire width 1 \logical_pipe2_o_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \pipe_full_cr$9 + wire width 4 \logical_pipe2_cr_a$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_full_cr_ok + wire width 1 \logical_pipe2_cr_a_ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe_cr_a$10 + wire width 2 \logical_pipe2_xer_ca$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_cr_a_ok - cell \pipe$6 \pipe + wire width 1 \logical_pipe2_xer_ca_ok$44 + cell \logical_pipe2 \logical_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_p_valid_i - connect \p_ready_o \pipe_p_ready_o - connect \muxid \pipe_muxid - connect \cr_op__insn_type \pipe_cr_op__insn_type - connect \cr_op__fn_unit \pipe_cr_op__fn_unit - connect \cr_op__insn \pipe_cr_op__insn - connect \cr_op__read_cr_whole \pipe_cr_op__read_cr_whole - connect \cr_op__write_cr_whole \pipe_cr_op__write_cr_whole - connect \ra \pipe_ra - connect \rb \pipe_rb - connect \full_cr \pipe_full_cr - connect \cr_a \pipe_cr_a - connect \cr_b \pipe_cr_b - connect \cr_c \pipe_cr_c - connect \n_valid_o \pipe_n_valid_o - connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$3 - connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 - connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 - connect \cr_op__insn$4 \pipe_cr_op__insn$6 - connect \cr_op__read_cr_whole$5 \pipe_cr_op__read_cr_whole$7 - connect \cr_op__write_cr_whole$6 \pipe_cr_op__write_cr_whole$8 - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \full_cr$7 \pipe_full_cr$9 - connect \full_cr_ok \pipe_full_cr_ok - connect \cr_a$8 \pipe_cr_a$10 - connect \cr_a_ok \pipe_cr_a_ok + connect \p_valid_i \logical_pipe2_p_valid_i + connect \p_ready_o \logical_pipe2_p_ready_o + connect \muxid \logical_pipe2_muxid + connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type + connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit + connect \logical_op__imm_data__imm \logical_pipe2_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \logical_pipe2_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc + connect \logical_op__rc__rc_ok \logical_pipe2_logical_op__rc__rc_ok + connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe + connect \logical_op__oe__oe_ok \logical_pipe2_logical_op__oe__oe_ok + connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in + connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a + connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry + connect \logical_op__invert_out \logical_pipe2_logical_op__invert_out + connect \logical_op__write_cr0 \logical_pipe2_logical_op__write_cr0 + connect \logical_op__output_carry \logical_pipe2_logical_op__output_carry + connect \logical_op__is_32bit \logical_pipe2_logical_op__is_32bit + connect \logical_op__is_signed \logical_pipe2_logical_op__is_signed + connect \logical_op__data_len \logical_pipe2_logical_op__data_len + connect \logical_op__insn \logical_pipe2_logical_op__insn + connect \o \logical_pipe2_o + connect \o_ok \logical_pipe2_o_ok + connect \cr_a \logical_pipe2_cr_a + connect \cr_a_ok \logical_pipe2_cr_a_ok + connect \xer_ca \logical_pipe2_xer_ca + connect \xer_ca_ok \logical_pipe2_xer_ca_ok + connect \n_valid_o \logical_pipe2_n_valid_o + connect \n_ready_i \logical_pipe2_n_ready_i + connect \muxid$1 \logical_pipe2_muxid$20 + connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$21 + connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$22 + connect \logical_op__imm_data__imm$4 \logical_pipe2_logical_op__imm_data__imm$23 + connect \logical_op__imm_data__imm_ok$5 \logical_pipe2_logical_op__imm_data__imm_ok$24 + connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$25 + connect \logical_op__rc__rc_ok$7 \logical_pipe2_logical_op__rc__rc_ok$26 + connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$27 + connect \logical_op__oe__oe_ok$9 \logical_pipe2_logical_op__oe__oe_ok$28 + connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$29 + connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$30 + connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$31 + connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$32 + connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$33 + connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$34 + connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$35 + connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$36 + connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$37 + connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$38 + connect \o$20 \logical_pipe2_o$39 + connect \o_ok$21 \logical_pipe2_o_ok$40 + connect \cr_a$22 \logical_pipe2_cr_a$41 + connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$42 + connect \xer_ca$24 \logical_pipe2_xer_ca$43 + connect \xer_ca_ok$25 \logical_pipe2_xer_ca_ok$44 end process $group_0 - assign \pipe_p_valid_i 1'0 - assign \pipe_p_valid_i \p_valid_i + assign \logical_pipe2_p_valid_i 1'0 + assign \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o sync init end process $group_1 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_p_ready_o + assign \logical_pipe1_n_ready_i 1'0 + assign \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid process $group_2 - assign \pipe_muxid 2'00 - assign \pipe_muxid \muxid + assign \logical_pipe2_muxid 2'00 + assign \logical_pipe2_muxid \logical_pipe1_muxid sync init end process $group_3 - assign \pipe_cr_op__insn_type 7'0000000 - assign \pipe_cr_op__fn_unit 11'00000000000 - assign \pipe_cr_op__insn 32'00000000000000000000000000000000 - assign \pipe_cr_op__read_cr_whole 1'0 - assign \pipe_cr_op__write_cr_whole 1'0 - assign { \pipe_cr_op__write_cr_whole \pipe_cr_op__read_cr_whole \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__write_cr_whole \cr_op__read_cr_whole \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + assign \logical_pipe2_logical_op__insn_type 7'0000000 + assign \logical_pipe2_logical_op__fn_unit 11'00000000000 + assign \logical_pipe2_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_pipe2_logical_op__imm_data__imm_ok 1'0 + assign \logical_pipe2_logical_op__rc__rc 1'0 + assign \logical_pipe2_logical_op__rc__rc_ok 1'0 + assign \logical_pipe2_logical_op__oe__oe 1'0 + assign \logical_pipe2_logical_op__oe__oe_ok 1'0 + assign \logical_pipe2_logical_op__invert_in 1'0 + assign \logical_pipe2_logical_op__zero_a 1'0 + assign \logical_pipe2_logical_op__input_carry 2'00 + assign \logical_pipe2_logical_op__invert_out 1'0 + assign \logical_pipe2_logical_op__write_cr0 1'0 + assign \logical_pipe2_logical_op__output_carry 1'0 + assign \logical_pipe2_logical_op__is_32bit 1'0 + assign \logical_pipe2_logical_op__is_signed 1'0 + assign \logical_pipe2_logical_op__data_len 4'0000 + assign \logical_pipe2_logical_op__insn 32'00000000000000000000000000000000 + assign { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in { \logical_pipe2_logical_op__oe__oe_ok \logical_pipe2_logical_op__oe__oe } { \logical_pipe2_logical_op__rc__rc_ok \logical_pipe2_logical_op__rc__rc } { \logical_pipe2_logical_op__imm_data__imm_ok \logical_pipe2_logical_op__imm_data__imm } \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in { \logical_pipe1_logical_op__oe__oe_ok \logical_pipe1_logical_op__oe__oe } { \logical_pipe1_logical_op__rc__rc_ok \logical_pipe1_logical_op__rc__rc } { \logical_pipe1_logical_op__imm_data__imm_ok \logical_pipe1_logical_op__imm_data__imm } \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } sync init end - process $group_8 - assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_ra \ra + process $group_21 + assign \logical_pipe2_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_pipe2_o_ok 1'0 + assign { \logical_pipe2_o_ok \logical_pipe2_o } { \logical_pipe1_o_ok \logical_pipe1_o } sync init end - process $group_9 - assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_rb \rb + process $group_23 + assign \logical_pipe2_cr_a 4'0000 + assign \logical_pipe2_cr_a_ok 1'0 + assign { \logical_pipe2_cr_a_ok \logical_pipe2_cr_a } { \logical_pipe1_cr_a_ok \logical_pipe1_cr_a } sync init end - process $group_10 - assign \pipe_full_cr 32'00000000000000000000000000000000 - assign \pipe_full_cr \full_cr$1 + process $group_25 + assign \logical_pipe2_xer_ca 2'00 + assign \logical_pipe2_xer_ca_ok 1'0 + assign { \logical_pipe2_xer_ca_ok \logical_pipe2_xer_ca } { \logical_pipe1_xer_ca_ok \logical_pipe1_xer_ca } sync init end - process $group_11 - assign \pipe_cr_a 4'0000 - assign \pipe_cr_a \cr_a$2 + process $group_27 + assign \logical_pipe1_p_valid_i 1'0 + assign \logical_pipe1_p_valid_i \p_valid_i sync init end - process $group_12 - assign \pipe_cr_b 4'0000 - assign \pipe_cr_b \cr_b + process $group_28 + assign \p_ready_o 1'0 + assign \p_ready_o \logical_pipe1_p_ready_o sync init end - process $group_13 - assign \pipe_cr_c 4'0000 - assign \pipe_cr_c \cr_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + process $group_29 + assign \logical_pipe1_muxid$1 2'00 + assign \logical_pipe1_muxid$1 \muxid sync init end - process $group_14 + process $group_30 + assign \logical_pipe1_logical_op__insn_type$2 7'0000000 + assign \logical_pipe1_logical_op__fn_unit$3 11'00000000000 + assign \logical_pipe1_logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_pipe1_logical_op__imm_data__imm_ok$5 1'0 + assign \logical_pipe1_logical_op__rc__rc$6 1'0 + assign \logical_pipe1_logical_op__rc__rc_ok$7 1'0 + assign \logical_pipe1_logical_op__oe__oe$8 1'0 + assign \logical_pipe1_logical_op__oe__oe_ok$9 1'0 + assign \logical_pipe1_logical_op__invert_in$10 1'0 + assign \logical_pipe1_logical_op__zero_a$11 1'0 + assign \logical_pipe1_logical_op__input_carry$12 2'00 + assign \logical_pipe1_logical_op__invert_out$13 1'0 + assign \logical_pipe1_logical_op__write_cr0$14 1'0 + assign \logical_pipe1_logical_op__output_carry$15 1'0 + assign \logical_pipe1_logical_op__is_32bit$16 1'0 + assign \logical_pipe1_logical_op__is_signed$17 1'0 + assign \logical_pipe1_logical_op__data_len$18 4'0000 + assign \logical_pipe1_logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 { \logical_pipe1_logical_op__oe__oe_ok$9 \logical_pipe1_logical_op__oe__oe$8 } { \logical_pipe1_logical_op__rc__rc_ok$7 \logical_pipe1_logical_op__rc__rc$6 } { \logical_pipe1_logical_op__imm_data__imm_ok$5 \logical_pipe1_logical_op__imm_data__imm$4 } \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_48 + assign \logical_pipe1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_pipe1_ra \ra + sync init + end + process $group_49 + assign \logical_pipe1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_pipe1_rb \rb + sync init + end + process $group_50 assign \n_valid_o 1'0 - assign \n_valid_o \pipe_n_valid_o + assign \n_valid_o \logical_pipe2_n_valid_o sync init end - process $group_15 - assign \pipe_n_ready_i 1'0 - assign \pipe_n_ready_i \n_ready_i + process $group_51 + assign \logical_pipe2_n_ready_i 1'0 + assign \logical_pipe2_n_ready_i \n_ready_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$11 - process $group_16 - assign \muxid$11 2'00 - assign \muxid$11 \pipe_muxid$3 + wire width 2 \muxid$45 + process $group_52 + assign \muxid$45 2'00 + assign \muxid$45 \logical_pipe2_muxid$20 sync init end attribute \enum_base_type "MicrOp" @@ -54342,7 +38081,7 @@ module \alu_cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$12 + wire width 7 \logical_op__insn_type$46 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -54356,91 +38095,134 @@ module \alu_cr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \cr_op__fn_unit$13 + wire width 11 \logical_op__fn_unit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$14 + wire width 64 \logical_op__imm_data__imm$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__read_cr_whole$15 + wire width 1 \logical_op__imm_data__imm_ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \cr_op__write_cr_whole$16 - process $group_17 - assign \cr_op__insn_type$12 7'0000000 - assign \cr_op__fn_unit$13 11'00000000000 - assign \cr_op__insn$14 32'00000000000000000000000000000000 - assign \cr_op__read_cr_whole$15 1'0 - assign \cr_op__write_cr_whole$16 1'0 - assign { \cr_op__write_cr_whole$16 \cr_op__read_cr_whole$15 \cr_op__insn$14 \cr_op__fn_unit$13 \cr_op__insn_type$12 } { \pipe_cr_op__write_cr_whole$8 \pipe_cr_op__read_cr_whole$7 \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } + wire width 1 \logical_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$63 + process $group_53 + assign \logical_op__insn_type$46 7'0000000 + assign \logical_op__fn_unit$47 11'00000000000 + assign \logical_op__imm_data__imm$48 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$49 1'0 + assign \logical_op__rc__rc$50 1'0 + assign \logical_op__rc__rc_ok$51 1'0 + assign \logical_op__oe__oe$52 1'0 + assign \logical_op__oe__oe_ok$53 1'0 + assign \logical_op__invert_in$54 1'0 + assign \logical_op__zero_a$55 1'0 + assign \logical_op__input_carry$56 2'00 + assign \logical_op__invert_out$57 1'0 + assign \logical_op__write_cr0$58 1'0 + assign \logical_op__output_carry$59 1'0 + assign \logical_op__is_32bit$60 1'0 + assign \logical_op__is_signed$61 1'0 + assign \logical_op__data_len$62 4'0000 + assign \logical_op__insn$63 32'00000000000000000000000000000000 + assign { \logical_op__insn$63 \logical_op__data_len$62 \logical_op__is_signed$61 \logical_op__is_32bit$60 \logical_op__output_carry$59 \logical_op__write_cr0$58 \logical_op__invert_out$57 \logical_op__input_carry$56 \logical_op__zero_a$55 \logical_op__invert_in$54 { \logical_op__oe__oe_ok$53 \logical_op__oe__oe$52 } { \logical_op__rc__rc_ok$51 \logical_op__rc__rc$50 } { \logical_op__imm_data__imm_ok$49 \logical_op__imm_data__imm$48 } \logical_op__fn_unit$47 \logical_op__insn_type$46 } { \logical_pipe2_logical_op__insn$38 \logical_pipe2_logical_op__data_len$37 \logical_pipe2_logical_op__is_signed$36 \logical_pipe2_logical_op__is_32bit$35 \logical_pipe2_logical_op__output_carry$34 \logical_pipe2_logical_op__write_cr0$33 \logical_pipe2_logical_op__invert_out$32 \logical_pipe2_logical_op__input_carry$31 \logical_pipe2_logical_op__zero_a$30 \logical_pipe2_logical_op__invert_in$29 { \logical_pipe2_logical_op__oe__oe_ok$28 \logical_pipe2_logical_op__oe__oe$27 } { \logical_pipe2_logical_op__rc__rc_ok$26 \logical_pipe2_logical_op__rc__rc$25 } { \logical_pipe2_logical_op__imm_data__imm_ok$24 \logical_pipe2_logical_op__imm_data__imm$23 } \logical_pipe2_logical_op__fn_unit$22 \logical_pipe2_logical_op__insn_type$21 } sync init end - process $group_22 + process $group_71 assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_o_ok \pipe_o } - sync init - end - process $group_24 - assign \full_cr 32'00000000000000000000000000000000 - assign \full_cr_ok 1'0 - assign { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$9 } + assign { \o_ok \o } { \logical_pipe2_o_ok$40 \logical_pipe2_o$39 } sync init end - process $group_26 + process $group_73 assign \cr_a 4'0000 assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$10 } + assign { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$42 \logical_pipe2_cr_a$41 } + sync init + end + process $group_75 + assign \xer_ca 2'00 + assign \xer_ca_ok 1'0 + assign { \xer_ca_ok \xer_ca } { \logical_pipe2_xer_ca_ok$44 \logical_pipe2_xer_ca$43 } sync init end connect \muxid 2'00 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l" -module \src_l$10 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" +module \src_l$52 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 2 \s_src + wire width 2 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 3 \r_src + wire width 2 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 4 \q_src + wire width 2 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int + wire width 2 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next + wire width 2 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $1 + wire width 2 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \r_src connect \Y $1 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $3 + wire width 2 $3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \q_int connect \B $1 connect \Y $3 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $5 + wire width 2 $5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A $3 connect \B \s_src connect \Y $5 @@ -54451,98 +38233,98 @@ module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 6'000000 + assign \q_int$next 2'00 end sync init - update \q_int 6'000000 + update \q_int 2'00 sync posedge \coresync_clk update \q_int \q_int$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $7 + wire width 2 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \r_src connect \Y $7 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $9 + wire width 2 $9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \q_int connect \B $7 connect \Y $9 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $11 + wire width 2 $11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A $9 connect \B \s_src connect \Y $11 end process $group_1 - assign \q_src 6'000000 + assign \q_src 2'00 assign \q_src $11 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_src + wire width 2 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 $13 + wire width 2 $13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \q_src connect \Y $13 end process $group_2 - assign \qn_src 6'000000 + assign \qn_src 2'00 assign \qn_src $13 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_src + wire width 2 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 $15 + wire width 2 $15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \q_src connect \B \q_int connect \Y $15 end process $group_3 - assign \qlq_src 6'000000 + assign \qlq_src 2'00 assign \qlq_src $15 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l" -module \opc_l$11 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" +module \opc_l$53 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -54683,11 +38465,11 @@ module \opc_l$11 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l" -module \req_l$12 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" +module \req_l$54 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 output 2 \q_req @@ -54828,11 +38610,11 @@ module \req_l$12 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l" -module \rst_l$13 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" +module \rst_l$55 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -54973,11 +38755,11 @@ module \rst_l$13 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l" -module \rok_l$14 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" +module \rok_l$56 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -55118,11 +38900,11 @@ module \rok_l$14 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l" -module \alui_l$15 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" +module \alui_l$57 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -55263,11 +39045,11 @@ module \alui_l$15 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l" -module \alu_l$16 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" +module \alu_l$58 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -55408,9 +39190,9 @@ module \alu_l$16 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0" -module \cr0 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0" +module \logical0 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -55486,7 +39268,7 @@ module \cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_cr0__insn_type + wire width 7 input 1 \oper_i_alu_logical0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -55500,63 +39282,79 @@ module \cr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_cr0__fn_unit + wire width 11 input 2 \oper_i_alu_logical0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \oper_i_alu_cr0__insn + wire width 64 input 3 \oper_i_alu_logical0__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_cr0__read_cr_whole + wire width 1 input 4 \oper_i_alu_logical0__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \oper_i_alu_cr0__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 6 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 7 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 6 input 8 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 9 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 input 10 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 11 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 12 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 32 input 13 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 4 input 14 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 4 input 15 \src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 4 input 16 \src6_i + wire width 1 input 5 \oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \oper_i_alu_logical0__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \oper_i_alu_logical0__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \oper_i_alu_logical0__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_alu_logical0__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_logical0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 2 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 24 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 17 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 18 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 19 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 20 \dest1_o + wire width 1 output 26 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 27 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 28 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 29 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 21 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 32 output 22 \dest2_o + wire width 1 output 30 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 31 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 24 \dest3_o - attribute \src "simple/issuer.py:89" - wire width 1 input 25 \coresync_rst + wire width 1 output 32 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 33 \dest3_o + attribute \src "simple/issuer.py:102" + wire width 1 input 34 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_cr0_n_valid_o + wire width 1 \alu_logical0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_cr0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_cr0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \alu_cr0_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_cr0_cr_a + wire width 1 \alu_logical0_n_ready_i attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -55631,7 +39429,9 @@ module \cr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_cr0_cr_op__insn_type + wire width 7 \alu_logical0_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_logical0_logical_op__insn_type$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -55645,65 +39445,136 @@ module \cr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_cr0_cr_op__fn_unit + wire width 11 \alu_logical0_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_cr0_cr_op__insn + wire width 11 \alu_logical0_logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_cr0_cr_op__read_cr_whole + wire width 64 \alu_logical0_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_cr0_cr_op__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_cr0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_cr0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \alu_cr0_full_cr$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \alu_cr0_cr_a$2 + wire width 64 \alu_logical0_logical_op__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__zero_a$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_logical0_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_logical0_logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_logical0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_logical0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_logical0_logical_op__data_len$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_logical0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_logical0_logical_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_logical0_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_logical0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_logical0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \alu_cr0_cr_b + wire width 64 \alu_logical0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \alu_cr0_cr_c + wire width 64 \alu_logical0_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_cr0_p_valid_i + wire width 1 \alu_logical0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_cr0_p_ready_o - cell \alu_cr0 \alu_cr0 + wire width 1 \alu_logical0_p_ready_o + cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \o_ok \o_ok - connect \full_cr_ok \full_cr_ok connect \cr_a_ok \cr_a_ok + connect \xer_ca_ok \xer_ca_ok connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_cr0_n_valid_o - connect \n_ready_i \alu_cr0_n_ready_i - connect \o \alu_cr0_o - connect \full_cr \alu_cr0_full_cr - connect \cr_a \alu_cr0_cr_a - connect \cr_op__insn_type \alu_cr0_cr_op__insn_type - connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit - connect \cr_op__insn \alu_cr0_cr_op__insn - connect \cr_op__read_cr_whole \alu_cr0_cr_op__read_cr_whole - connect \cr_op__write_cr_whole \alu_cr0_cr_op__write_cr_whole - connect \ra \alu_cr0_ra - connect \rb \alu_cr0_rb - connect \full_cr$1 \alu_cr0_full_cr$1 - connect \cr_a$2 \alu_cr0_cr_a$2 - connect \cr_b \alu_cr0_cr_b - connect \cr_c \alu_cr0_cr_c - connect \p_valid_i \alu_cr0_p_valid_i - connect \p_ready_o \alu_cr0_p_ready_o + connect \n_valid_o \alu_logical0_n_valid_o + connect \n_ready_i \alu_logical0_n_ready_i + connect \logical_op__insn_type \alu_logical0_logical_op__insn_type + connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit + connect \logical_op__imm_data__imm \alu_logical0_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \alu_logical0_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc + connect \logical_op__rc__rc_ok \alu_logical0_logical_op__rc__rc_ok + connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe + connect \logical_op__oe__oe_ok \alu_logical0_logical_op__oe__oe_ok + connect \logical_op__invert_in \alu_logical0_logical_op__invert_in + connect \logical_op__zero_a \alu_logical0_logical_op__zero_a + connect \logical_op__input_carry \alu_logical0_logical_op__input_carry + connect \logical_op__invert_out \alu_logical0_logical_op__invert_out + connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 + connect \logical_op__output_carry \alu_logical0_logical_op__output_carry + connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit + connect \logical_op__is_signed \alu_logical0_logical_op__is_signed + connect \logical_op__data_len \alu_logical0_logical_op__data_len + connect \logical_op__insn \alu_logical0_logical_op__insn + connect \o \alu_logical0_o + connect \cr_a \alu_logical0_cr_a + connect \xer_ca \alu_logical0_xer_ca + connect \ra \alu_logical0_ra + connect \rb \alu_logical0_rb + connect \p_valid_i \alu_logical0_p_valid_i + connect \p_ready_o \alu_logical0_p_ready_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \src_l_s_src + wire width 2 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \src_l_s_src$next + wire width 2 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \src_l_r_src + wire width 2 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \src_l_r_src$next + wire width 2 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 \src_l_q_src - cell \src_l$10 \src_l + wire width 2 \src_l_q_src + cell \src_l$52 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_src \src_l_s_src @@ -55720,7 +39591,7 @@ module \cr0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$11 \opc_l + cell \opc_l$53 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_opc \opc_l_s_opc @@ -55731,11 +39602,13 @@ module \cr0 wire width 3 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \req_l_r_req$next - cell \req_l$12 \req_l + cell \req_l$54 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -55744,9 +39617,13 @@ module \cr0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$13 \rst_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst$next + cell \rst_l$55 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_rst \rst_l_s_rst @@ -55756,11 +39633,13 @@ module \cr0 wire width 1 \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$14 \rok_l + cell \rok_l$56 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -55775,7 +39654,7 @@ module \cr0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$15 \alui_l + cell \alui_l$57 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -55790,19 +39669,19 @@ module \cr0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$16 \alu_l + cell \alu_l$58 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" - wire width 1 \all_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - cell $and $4 + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -55810,62 +39689,62 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $3 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 6 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $not $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 2 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $5 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \cu_rd__rel_o - connect \Y $6 + connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 6 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $or $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 2 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $7 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $6 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $4 connect \B \cu_rd__go_i - connect \Y $8 + connect \Y $6 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $reduce_and $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $5 + connect \A $6 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 - connect \Y $11 + connect \A $1 + connect \B $3 + connect \Y $9 end process $group_0 assign \all_rd 1'0 - assign \all_rd $11 + assign \all_rd $9 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \all_rd_dly$next process $group_1 assign \all_rd_dly$next \all_rd_dly @@ -55875,48 +39754,55 @@ module \cr0 sync posedge \coresync_clk update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $not $14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $12 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $13 + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $and $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $14 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd - connect \B $13 - connect \Y $15 + connect \B $11 + connect \Y $13 end process $group_2 + assign \all_rd_rise 1'0 + assign \all_rd_rise $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire width 1 \all_rd_pulse + process $group_3 assign \all_rd_pulse 1'0 - assign \all_rd_pulse $15 + assign \all_rd_pulse \all_rd_rise sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire width 1 \alu_done - process $group_3 + process $group_4 assign \alu_done 1'0 - assign \alu_done \alu_cr0_n_valid_o + assign \alu_done \alu_logical0_n_valid_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \alu_done_dly$next - process $group_4 + process $group_5 assign \alu_done_dly$next \alu_done_dly assign \alu_done_dly$next \alu_done sync init @@ -55924,51 +39810,58 @@ module \cr0 sync posedge \coresync_clk update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $not $18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $17 + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $and $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done - connect \B $17 - connect \Y $19 + connect \B $15 + connect \Y $17 end - process $group_5 + process $group_6 + assign \alu_done_rise 1'0 + assign \alu_done_rise $17 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire width 1 \alu_pulse + process $group_7 assign \alu_pulse 1'0 - assign \alu_pulse $19 + assign \alu_pulse \alu_done_rise sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" wire width 3 \alu_pulsem - process $group_6 + process $group_8 assign \alu_pulsem 3'000 assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 3 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - cell $and $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 3 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -55976,11 +39869,11 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $21 + connect \Y $19 end - process $group_7 + process $group_9 assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $21 + assign \prev_wr_go$next $19 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -55991,140 +39884,140 @@ module \cr0 sync posedge \coresync_clk update \prev_wr_go \prev_wr_go$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" wire width 3 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $24 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $25 + connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $26 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o - connect \B $25 - connect \Y $27 + connect \B $23 + connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $reduce_bool $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_bool $27 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $24 + connect \A $25 + connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 + connect \A $22 + connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o - connect \B $23 - connect \Y $31 + connect \B $21 + connect \Y $29 end - process $group_8 + process $group_10 assign \cu_done_o 1'0 - assign \cu_done_o $31 + assign \cu_done_o $29 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $32 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $33 + connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $34 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $35 + connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $or $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $33 - connect \B $35 - connect \Y $37 + connect \A $31 + connect \B $33 + connect \Y $35 end - process $group_9 + process $group_11 assign \wr_any 1'0 - assign \wr_any $37 + assign \wr_any $35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $not $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_cr0_n_ready_i - connect \Y $39 + connect \A \alu_logical0_n_ready_i + connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $and $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any - connect \B $39 - connect \Y $41 + connect \B $37 + connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 3 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 3 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $42 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -56132,38 +40025,38 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $43 + connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $eq $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $44 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $43 + connect \A $41 connect \B 1'0 - connect \Y $45 + connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $41 - connect \B $45 - connect \Y $47 + connect \A $39 + connect \B $43 + connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $eq $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $48 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -56171,11 +40064,24 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $47 + connect \B \alu_logical0_n_ready_i connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -56183,12 +40089,12 @@ module \cr0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $49 - connect \B \alu_cr0_n_ready_i + connect \B \alu_logical0_n_valid_o connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" cell $and $54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -56196,41 +40102,28 @@ module \cr0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $51 - connect \B \alu_cr0_n_valid_o - connect \Y $53 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $53 connect \B \cu_busy_o - connect \Y $55 + connect \Y $53 end - process $group_10 + process $group_12 assign \req_done 1'0 - assign \req_done $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + assign \req_done $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch { $53 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" case 1'1 assign \req_done 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -56238,19 +40131,19 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $57 + connect \Y $55 end - process $group_11 + process $group_13 assign \reset 1'0 - assign \reset $57 + assign \reset $55 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - cell $or $60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -56258,19 +40151,19 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $59 + connect \Y $57 end - process $group_12 + process $group_14 assign \rst_r 1'0 - assign \rst_r $59 + assign \rst_r $57 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - wire width 3 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - cell $or $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 3 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $60 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -56278,54 +40171,62 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $61 + connect \Y $59 end - process $group_13 + process $group_15 assign \reset_w 3'000 - assign \reset_w $61 + assign \reset_w $59 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 6 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - wire width 6 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - cell $or $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 2 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 2 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $62 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $63 + connect \B { \cu_go_die_i \cu_go_die_i } + connect \Y $61 end - process $group_14 - assign \reset_r 6'000000 - assign \reset_r $63 + process $group_16 + assign \reset_r 2'00 + assign \reset_r $61 sync init end - process $group_15 - assign \rok_l_s_rdok 1'0 - assign \rok_l_s_rdok \cu_issue_i + process $group_17 + assign \rok_l_s_rdok$next \rok_l_s_rdok + assign \rok_l_s_rdok$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_s_rdok$next 1'0 + end sync init + update \rok_l_s_rdok 1'0 + sync posedge \coresync_clk + update \rok_l_s_rdok \rok_l_s_rdok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - cell $and $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_cr0_n_valid_o + connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o - connect \Y $65 + connect \Y $63 end - process $group_16 + process $group_18 assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $65 + assign \rok_l_r_rdok$next $63 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -56336,17 +40237,33 @@ module \cr0 sync posedge \coresync_clk update \rok_l_r_rdok \rok_l_r_rdok$next end - process $group_17 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \all_rd + process $group_19 + assign \rst_l_s_rst$next \rst_l_s_rst + assign \rst_l_s_rst$next \all_rd + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_s_rst$next 1'0 + end sync init + update \rst_l_s_rst 1'0 + sync posedge \coresync_clk + update \rst_l_s_rst \rst_l_s_rst$next end - process $group_18 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \rst_r + process $group_20 + assign \rst_l_r_rst$next \rst_l_r_rst + assign \rst_l_r_rst$next \rst_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_r_rst$next 1'1 + end sync init + update \rst_l_r_rst 1'1 + sync posedge \coresync_clk + update \rst_l_r_rst \rst_l_r_rst$next end - process $group_19 + process $group_21 assign \opc_l_s_opc$next \opc_l_s_opc assign \opc_l_s_opc$next \cu_issue_i attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -56359,7 +40276,7 @@ module \cr0 sync posedge \coresync_clk update \opc_l_s_opc \opc_l_s_opc$next end - process $group_20 + process $group_22 assign \opc_l_r_opc$next \opc_l_r_opc assign \opc_l_r_opc$next \req_done attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -56372,36 +40289,36 @@ module \cr0 sync posedge \coresync_clk update \opc_l_r_opc \opc_l_r_opc$next end - process $group_21 + process $group_23 assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \src_l_s_src$next 6'000000 + assign \src_l_s_src$next 2'00 end sync init - update \src_l_s_src 6'000000 + update \src_l_s_src 2'00 sync posedge \coresync_clk update \src_l_s_src \src_l_s_src$next end - process $group_22 + process $group_24 assign \src_l_r_src$next \src_l_r_src assign \src_l_r_src$next \reset_r attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \src_l_r_src$next 6'111111 + assign \src_l_r_src$next 2'11 end sync init - update \src_l_r_src 6'111111 + update \src_l_r_src 2'11 sync posedge \coresync_clk update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - cell $and $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 3 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $66 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -56409,17 +40326,25 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $67 + connect \Y $65 end - process $group_23 - assign \req_l_s_req 3'000 - assign \req_l_s_req $67 + process $group_25 + assign \req_l_s_req$next \req_l_s_req + assign \req_l_s_req$next $65 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_s_req$next 3'000 + end sync init + update \req_l_s_req 3'000 + sync posedge \coresync_clk + update \req_l_s_req \req_l_s_req$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - wire width 3 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - cell $or $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 3 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $68 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -56427,11 +40352,11 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $69 + connect \Y $67 end - process $group_24 + process $group_26 assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $69 + assign \req_l_r_req$next $67 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -56442,423 +40367,295 @@ module \cr0 sync posedge \coresync_clk update \req_l_r_req \req_l_r_req$next end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__read_cr_whole$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr_whole$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 52 $71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $72 - parameter \WIDTH 52 - connect \A { \oper_l__write_cr_whole \oper_l__read_cr_whole \oper_l__insn \oper_l__fn_unit \oper_l__insn_type } - connect \B { \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } - connect \S \cu_issue_i - connect \Y $71 - end - process $group_25 - assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 11'00000000000 - assign \oper_r__insn 32'00000000000000000000000000000000 - assign \oper_r__read_cr_whole 1'0 - assign \oper_r__write_cr_whole 1'0 - assign { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $71 - sync init - end - process $group_30 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__insn$next \oper_l__insn - assign \oper_l__read_cr_whole$next \oper_l__read_cr_whole - assign \oper_l__write_cr_whole$next \oper_l__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + process $group_27 + assign \alu_logical0_logical_op__insn_type$next \alu_logical0_logical_op__insn_type + assign \alu_logical0_logical_op__fn_unit$next \alu_logical0_logical_op__fn_unit + assign \alu_logical0_logical_op__imm_data__imm$next \alu_logical0_logical_op__imm_data__imm + assign \alu_logical0_logical_op__imm_data__imm_ok$next \alu_logical0_logical_op__imm_data__imm_ok + assign \alu_logical0_logical_op__rc__rc$next \alu_logical0_logical_op__rc__rc + assign \alu_logical0_logical_op__rc__rc_ok$next \alu_logical0_logical_op__rc__rc_ok + assign \alu_logical0_logical_op__oe__oe$next \alu_logical0_logical_op__oe__oe + assign \alu_logical0_logical_op__oe__oe_ok$next \alu_logical0_logical_op__oe__oe_ok + assign \alu_logical0_logical_op__invert_in$next \alu_logical0_logical_op__invert_in + assign \alu_logical0_logical_op__zero_a$next \alu_logical0_logical_op__zero_a + assign \alu_logical0_logical_op__input_carry$next \alu_logical0_logical_op__input_carry + assign \alu_logical0_logical_op__invert_out$next \alu_logical0_logical_op__invert_out + assign \alu_logical0_logical_op__write_cr0$next \alu_logical0_logical_op__write_cr0 + assign \alu_logical0_logical_op__output_carry$next \alu_logical0_logical_op__output_carry + assign \alu_logical0_logical_op__is_32bit$next \alu_logical0_logical_op__is_32bit + assign \alu_logical0_logical_op__is_signed$next \alu_logical0_logical_op__is_signed + assign \alu_logical0_logical_op__data_len$next \alu_logical0_logical_op__data_len + assign \alu_logical0_logical_op__insn$next \alu_logical0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" case 1'1 - assign { \oper_l__write_cr_whole$next \oper_l__read_cr_whole$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + assign { \alu_logical0_logical_op__insn$next \alu_logical0_logical_op__data_len$next \alu_logical0_logical_op__is_signed$next \alu_logical0_logical_op__is_32bit$next \alu_logical0_logical_op__output_carry$next \alu_logical0_logical_op__write_cr0$next \alu_logical0_logical_op__invert_out$next \alu_logical0_logical_op__input_carry$next \alu_logical0_logical_op__zero_a$next \alu_logical0_logical_op__invert_in$next { \alu_logical0_logical_op__oe__oe_ok$next \alu_logical0_logical_op__oe__oe$next } { \alu_logical0_logical_op__rc__rc_ok$next \alu_logical0_logical_op__rc__rc$next } { \alu_logical0_logical_op__imm_data__imm_ok$next \alu_logical0_logical_op__imm_data__imm$next } \alu_logical0_logical_op__fn_unit$next \alu_logical0_logical_op__insn_type$next } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in { \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe } { \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc } { \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm } \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 11'00000000000 - update \oper_l__insn 32'00000000000000000000000000000000 - update \oper_l__read_cr_whole 1'0 - update \oper_l__write_cr_whole 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_logical0_logical_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_logical0_logical_op__imm_data__imm_ok$next 1'0 + assign \alu_logical0_logical_op__rc__rc$next 1'0 + assign \alu_logical0_logical_op__rc__rc_ok$next 1'0 + assign \alu_logical0_logical_op__oe__oe$next 1'0 + assign \alu_logical0_logical_op__oe__oe_ok$next 1'0 + end + sync init + update \alu_logical0_logical_op__insn_type 7'0000000 + update \alu_logical0_logical_op__fn_unit 11'00000000000 + update \alu_logical0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_logical0_logical_op__imm_data__imm_ok 1'0 + update \alu_logical0_logical_op__rc__rc 1'0 + update \alu_logical0_logical_op__rc__rc_ok 1'0 + update \alu_logical0_logical_op__oe__oe 1'0 + update \alu_logical0_logical_op__oe__oe_ok 1'0 + update \alu_logical0_logical_op__invert_in 1'0 + update \alu_logical0_logical_op__zero_a 1'0 + update \alu_logical0_logical_op__input_carry 2'00 + update \alu_logical0_logical_op__invert_out 1'0 + update \alu_logical0_logical_op__write_cr0 1'0 + update \alu_logical0_logical_op__output_carry 1'0 + update \alu_logical0_logical_op__is_32bit 1'0 + update \alu_logical0_logical_op__is_signed 1'0 + update \alu_logical0_logical_op__data_len 4'0000 + update \alu_logical0_logical_op__insn 32'00000000000000000000000000000000 sync posedge \coresync_clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__insn \oper_l__insn$next - update \oper_l__read_cr_whole \oper_l__read_cr_whole$next - update \oper_l__write_cr_whole \oper_l__write_cr_whole$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" + update \alu_logical0_logical_op__insn_type \alu_logical0_logical_op__insn_type$next + update \alu_logical0_logical_op__fn_unit \alu_logical0_logical_op__fn_unit$next + update \alu_logical0_logical_op__imm_data__imm \alu_logical0_logical_op__imm_data__imm$next + update \alu_logical0_logical_op__imm_data__imm_ok \alu_logical0_logical_op__imm_data__imm_ok$next + update \alu_logical0_logical_op__rc__rc \alu_logical0_logical_op__rc__rc$next + update \alu_logical0_logical_op__rc__rc_ok \alu_logical0_logical_op__rc__rc_ok$next + update \alu_logical0_logical_op__oe__oe \alu_logical0_logical_op__oe__oe$next + update \alu_logical0_logical_op__oe__oe_ok \alu_logical0_logical_op__oe__oe_ok$next + update \alu_logical0_logical_op__invert_in \alu_logical0_logical_op__invert_in$next + update \alu_logical0_logical_op__zero_a \alu_logical0_logical_op__zero_a$next + update \alu_logical0_logical_op__input_carry \alu_logical0_logical_op__input_carry$next + update \alu_logical0_logical_op__invert_out \alu_logical0_logical_op__invert_out$next + update \alu_logical0_logical_op__write_cr0 \alu_logical0_logical_op__write_cr0$next + update \alu_logical0_logical_op__output_carry \alu_logical0_logical_op__output_carry$next + update \alu_logical0_logical_op__is_32bit \alu_logical0_logical_op__is_32bit$next + update \alu_logical0_logical_op__is_signed \alu_logical0_logical_op__is_signed$next + update \alu_logical0_logical_op__data_len \alu_logical0_logical_op__data_len$next + update \alu_logical0_logical_op__insn \alu_logical0_logical_op__insn$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $73 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $74 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $74 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $76 - parameter \WIDTH 65 - connect \A { \data_r0_l__o_ok \data_r0_l__o } - connect \B { \o_ok \alu_cr0_o } - connect \S $74 - connect \Y $73 - end - process $group_35 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - assign { \data_r0__o_ok \data_r0__o } $73 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $77 - end - process $group_37 - assign \data_r0_l__o$next \data_r0_l__o - assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok$next + process $group_45 + assign \data_r0__o$next \data_r0__o + assign \data_r0__o_ok$next \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_logical0_o } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" case 1'1 - assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_cr0_o } + assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \data_r0_l__o_ok$next 1'0 + assign \data_r0__o_ok$next 1'0 end sync init - update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0_l__o_ok 1'0 + update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0__o_ok 1'0 sync posedge \coresync_clk - update \data_r0_l__o \data_r0_l__o$next - update \data_r0_l__o_ok \data_r0_l__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 32 \data_r1__full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r1__full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \data_r1_l__full_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \data_r1_l__full_cr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__full_cr_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 33 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $80 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $80 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $82 - parameter \WIDTH 33 - connect \A { \data_r1_l__full_cr_ok \data_r1_l__full_cr } - connect \B { \full_cr_ok \alu_cr0_full_cr } - connect \S $80 - connect \Y $79 - end - process $group_39 - assign \data_r1__full_cr 32'00000000000000000000000000000000 - assign \data_r1__full_cr_ok 1'0 - assign { \data_r1__full_cr_ok \data_r1__full_cr } $79 - sync init + update \data_r0__o \data_r0__o$next + update \data_r0__o_ok \data_r0__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $83 - end - process $group_41 - assign \data_r1_l__full_cr$next \data_r1_l__full_cr - assign \data_r1_l__full_cr_ok$next \data_r1_l__full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $83 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__cr_a_ok$next + process $group_47 + assign \data_r1__cr_a$next \data_r1__cr_a + assign \data_r1__cr_a_ok$next \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" case 1'1 - assign { \data_r1_l__full_cr_ok$next \data_r1_l__full_cr$next } { \full_cr_ok \alu_cr0_full_cr } + assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } { \cr_a_ok \alu_logical0_cr_a } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } 5'00000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \data_r1_l__full_cr_ok$next 1'0 + assign \data_r1__cr_a_ok$next 1'0 end sync init - update \data_r1_l__full_cr 32'00000000000000000000000000000000 - update \data_r1_l__full_cr_ok 1'0 + update \data_r1__cr_a 4'0000 + update \data_r1__cr_a_ok 1'0 sync posedge \coresync_clk - update \data_r1_l__full_cr \data_r1_l__full_cr$next - update \data_r1_l__full_cr_ok \data_r1_l__full_cr_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 4 \data_r2__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r2__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r2_l__cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r2_l__cr_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 5 $85 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $86 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $88 - parameter \WIDTH 5 - connect \A { \data_r2_l__cr_a_ok \data_r2_l__cr_a } - connect \B { \cr_a_ok \alu_cr0_cr_a } - connect \S $86 - connect \Y $85 - end - process $group_43 - assign \data_r2__cr_a 4'0000 - assign \data_r2__cr_a_ok 1'0 - assign { \data_r2__cr_a_ok \data_r2__cr_a } $85 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $89 + update \data_r1__cr_a \data_r1__cr_a$next + update \data_r1__cr_a_ok \data_r1__cr_a_ok$next end - process $group_45 - assign \data_r2_l__cr_a$next \data_r2_l__cr_a - assign \data_r2_l__cr_a_ok$next \data_r2_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $89 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__xer_ca_ok$next + process $group_49 + assign \data_r2__xer_ca$next \data_r2__xer_ca + assign \data_r2__xer_ca_ok$next \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } { \xer_ca_ok \alu_logical0_xer_ca } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" case 1'1 - assign { \data_r2_l__cr_a_ok$next \data_r2_l__cr_a$next } { \cr_a_ok \alu_cr0_cr_a } + assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } 3'000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \data_r2_l__cr_a_ok$next 1'0 + assign \data_r2__xer_ca_ok$next 1'0 end sync init - update \data_r2_l__cr_a 4'0000 - update \data_r2_l__cr_a_ok 1'0 + update \data_r2__xer_ca 2'00 + update \data_r2__xer_ca_ok 1'0 sync posedge \coresync_clk - update \data_r2_l__cr_a \data_r2_l__cr_a$next - update \data_r2_l__cr_a_ok \data_r2_l__cr_a_ok$next + update \data_r2__xer_ca \data_r2__xer_ca$next + update \data_r2__xer_ca_ok \data_r2__xer_ca_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r0__o_ok + connect \A \o_ok connect \B \cu_busy_o - connect \Y $91 + connect \Y $69 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r1__full_cr_ok + connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $93 + connect \Y $71 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r2__cr_a_ok + connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $95 + connect \Y $73 end - process $group_47 + process $group_51 assign \cu_wrmask_o 3'000 - assign \cu_wrmask_o { $95 $93 $91 } + assign \cu_wrmask_o { $73 $71 $69 } sync init end - process $group_48 - assign \alu_cr0_cr_op__insn_type 7'0000000 - assign \alu_cr0_cr_op__fn_unit 11'00000000000 - assign \alu_cr0_cr_op__insn 32'00000000000000000000000000000000 - assign \alu_cr0_cr_op__read_cr_whole 1'0 - assign \alu_cr0_cr_op__write_cr_whole 1'0 - assign { \alu_cr0_cr_op__write_cr_whole \alu_cr0_cr_op__read_cr_whole \alu_cr0_cr_op__insn \alu_cr0_cr_op__fn_unit \alu_cr0_cr_op__insn_type } { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $76 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__zero_a + connect \Y $75 + end + process $group_52 + assign \src_sel 1'0 + assign \src_sel $75 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $78 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_logical0_logical_op__zero_a + connect \Y $77 + end + process $group_53 + assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm $77 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire width 1 \src_sel$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire width 1 $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $81 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__imm_data__imm_ok + connect \Y $80 + end + process $group_54 + assign \src_sel$79 1'0 + assign \src_sel$79 $80 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $84 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_logical0_logical_op__imm_data__imm + connect \S \alu_logical0_logical_op__imm_data__imm_ok + connect \Y $83 + end + process $group_55 + assign \src_or_imm$82 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm$82 $83 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" @@ -56866,27 +40663,27 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $97 + wire width 64 $85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $98 + cell $mux $86 parameter \WIDTH 64 connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $97 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $85 end - process $group_53 - assign \alu_cr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_cr0_ra $97 + process $group_56 + assign \alu_logical0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_logical0_ra $85 sync init end - process $group_54 + process $group_57 assign \src_r0$next \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } + switch { \src_sel } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign \src_r0$next \src1_i + assign \src_r0$next \src_or_imm end sync init update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -56898,182 +40695,54 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $99 + wire width 64 $87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $100 + cell $mux $88 parameter \WIDTH 64 connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $99 + connect \B \src_or_imm$82 + connect \S \src_sel$79 + connect \Y $87 end - process $group_55 - assign \alu_cr0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_cr0_rb $99 + process $group_58 + assign \alu_logical0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_logical0_rb $87 sync init end - process $group_56 + process $group_59 assign \src_r1$next \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [1] } + switch { \src_sel$79 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign \src_r1$next \src2_i + assign \src_r1$next \src_or_imm$82 end sync init update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk update \src_r1 \src_r1$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 32 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 32 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 32 $101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $102 - parameter \WIDTH 32 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $101 - end - process $group_57 - assign \alu_cr0_full_cr$1 32'00000000000000000000000000000000 - assign \alu_cr0_full_cr$1 $101 - sync init - end - process $group_58 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 4 $103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $104 - parameter \WIDTH 4 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $103 - end - process $group_59 - assign \alu_cr0_cr_a$2 4'0000 - assign \alu_cr0_cr_a$2 $103 - sync init - end process $group_60 - assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r3$next \src4_i - end - sync init - update \src_r3 4'0000 - sync posedge \coresync_clk - update \src_r3 \src_r3$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r4$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 4 $105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $106 - parameter \WIDTH 4 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $105 - end - process $group_61 - assign \alu_cr0_cr_b 4'0000 - assign \alu_cr0_cr_b $105 - sync init - end - process $group_62 - assign \src_r4$next \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [4] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r4$next \src5_i - end - sync init - update \src_r4 4'0000 - sync posedge \coresync_clk - update \src_r4 \src_r4$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r5$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 4 $107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $108 - parameter \WIDTH 4 - connect \A \src_r5 - connect \B \src6_i - connect \S \src_l_q_src [5] - connect \Y $107 - end - process $group_63 - assign \alu_cr0_cr_c 4'0000 - assign \alu_cr0_cr_c $107 - sync init - end - process $group_64 - assign \src_r5$next \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [5] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r5$next \src6_i - end - sync init - update \src_r5 4'0000 - sync posedge \coresync_clk - update \src_r5 \src_r5$next - end - process $group_65 - assign \alu_cr0_p_valid_i 1'0 - assign \alu_cr0_p_valid_i \alui_l_q_alui + assign \alu_logical0_p_valid_i 1'0 + assign \alu_logical0_p_valid_i \alui_l_q_alui sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - cell $and $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_cr0_p_ready_o + connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $109 + connect \Y $89 end - process $group_66 + process $group_61 assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $109 + assign \alui_l_r_alui$next $89 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -57084,32 +40753,32 @@ module \cr0 sync posedge \coresync_clk update \alui_l_r_alui \alui_l_r_alui$next end - process $group_67 + process $group_62 assign \alui_l_s_alui 1'0 assign \alui_l_s_alui \all_rd_pulse sync init end - process $group_68 - assign \alu_cr0_n_ready_i 1'0 - assign \alu_cr0_n_ready_i \alu_l_q_alu + process $group_63 + assign \alu_logical0_n_ready_i 1'0 + assign \alu_logical0_n_ready_i \alu_l_q_alu sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - cell $and $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_cr0_n_valid_o + connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $111 + connect \Y $91 end - process $group_69 + process $group_64 assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $111 + assign \alu_l_r_alu$next $91 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -57120,76 +40789,96 @@ module \cr0 sync posedge \coresync_clk update \alu_l_r_alu \alu_l_r_alu$next end - process $group_70 + process $group_65 assign \alu_l_s_alu 1'0 assign \alu_l_s_alu \all_rd_pulse sync init end - process $group_71 + process $group_66 assign \cu_busy_o 1'0 assign \cu_busy_o \opc_l_q_opc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 6 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 2 $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $94 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $113 + connect \B { \cu_busy_o \cu_busy_o } + connect \Y $93 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 6 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire width 1 $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $96 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_logical_op__zero_a + connect \Y $95 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire width 1 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_logical_op__imm_data__imm_ok + connect \Y $97 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 2 $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $113 - connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 } - connect \Y $115 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $93 + connect \B { $97 $95 } + connect \Y $99 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 6 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $not $118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 2 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $102 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \cu_rdmaskn_i - connect \Y $117 + connect \Y $101 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 6 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 2 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $104 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $115 - connect \B $117 - connect \Y $119 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $99 + connect \B $101 + connect \Y $103 end - process $group_72 - assign \cu_rd__rel_o 6'000000 - assign \cu_rd__rel_o $119 + process $group_67 + assign \cu_rd__rel_o 2'00 + assign \cu_rd__rel_o $103 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -57197,12 +40886,12 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $121 + connect \Y $105 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -57210,12 +40899,12 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $123 + connect \Y $107 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -57223,43 +40912,43 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $125 + connect \Y $109 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 3 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $112 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 connect \A \req_l_q_req - connect \B { $121 $123 $125 } - connect \Y $127 + connect \B { $105 $107 $109 } + connect \Y $111 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 3 $129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $114 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $127 + connect \A $111 connect \B \cu_wrmask_o - connect \Y $129 + connect \Y $113 end - process $group_73 + process $group_68 assign \cu_wr__rel_o 3'000 - assign \cu_wr__rel_o $129 + assign \cu_wr__rel_o $113 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -57267,22 +40956,22 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $131 + connect \Y $115 end - process $group_74 + process $group_69 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $131 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $115 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -57290,22 +40979,22 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $133 + connect \Y $117 end - process $group_75 - assign \dest2_o 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $133 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + process $group_70 + assign \dest2_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $117 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 - assign \dest2_o { \data_r1__full_cr_ok \data_r1__full_cr } [31:0] + assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -57313,15 +41002,15 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $135 + connect \Y $119 end - process $group_76 - assign \dest3_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $135 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + process $group_71 + assign \dest3_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $119 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 - assign \dest3_o { \data_r2__cr_a_ok \data_r2__cr_a } [3:0] + assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] end sync init end @@ -57329,8 +41018,8 @@ module \cr0 connect \cu_shadown_i 1'1 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.p" -module \p$17 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.p" +module \p$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -57357,8 +41046,8 @@ module \p$17 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.n" -module \n$18 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.n" +module \n$60 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -57385,8 +41074,8 @@ module \n$18 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.p" -module \p$20 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.p" +module \p$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -57413,8 +41102,8 @@ module \p$20 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.n" -module \n$21 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.n" +module \n$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -57441,12 +41130,10 @@ module \n$21 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.main" -module \main$22 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.spr_main" +module \spr_main attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 1 \br_op__cia attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -57521,7 +41208,7 @@ module \main$22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \br_op__insn_type + wire width 7 input 1 \spr_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -57535,27 +41222,23 @@ module \main$22 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 3 \br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 4 \br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \br_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \br_op__imm_data__imm_ok + wire width 11 input 2 \spr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \br_op__lk + wire width 32 input 3 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \br_op__is_32bit + wire width 1 input 4 \spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \fast1 + wire width 64 input 5 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \fast2 + wire width 64 input 6 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 11 \cr_a + wire width 1 input 7 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 8 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 9 \xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 12 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 13 \br_op__cia$2 + wire width 2 output 10 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -57630,7 +41313,7 @@ module \main$22 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 14 \br_op__insn_type$3 + wire width 7 output 11 \spr_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -57644,524 +41327,256 @@ module \main$22 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 15 \br_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 16 \br_op__insn$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 17 \br_op__imm_data__imm$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 18 \br_op__imm_data__imm_ok$7 + wire width 11 output 12 \spr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 19 \br_op__lk$8 + wire width 32 output 13 \spr_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 20 \br_op__is_32bit$9 + wire width 1 output 14 \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 21 \fast1$10 + wire width 64 output 15 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 22 \fast1_ok + wire width 1 output 16 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 23 \fast2$11 + wire width 64 output 17 \fast1$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 24 \fast2_ok + wire width 1 output 18 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 25 \nia + wire width 1 output 19 \xer_so$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 26 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:84" - wire width 64 \br_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" - cell $eq $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \br_op__insn_type - connect \B 7'0001000 - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" - cell $or $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \br_op__insn [1] } - connect \B $12 - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:83" - wire width 64 \br_imm_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:91" - wire width 65 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:91" - wire width 65 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:91" - cell $add $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \br_imm_addr - connect \B \br_op__cia - connect \Y $17 - end - connect $16 $17 + wire width 1 output 20 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 21 \xer_ov$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 22 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 23 \xer_ca$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 24 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" + wire width 10 \spr process $group_0 - assign \br_addr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" - case 1'1 - assign \br_addr \br_imm_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:90" - case - assign \br_addr $16 [63:0] - end + assign \spr 10'0000000000 + assign \spr { { \spr_op__insn [15] \spr_op__insn [14] \spr_op__insn [13] \spr_op__insn [12] \spr_op__insn [11] } { \spr_op__insn [20] \spr_op__insn [19] \spr_op__insn [18] \spr_op__insn [17] \spr_op__insn [16] } } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:101" - wire width 2 \bi process $group_1 - assign \bi 2'00 - assign \bi { \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] } [1:0] + assign \fast1$6 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + assign \fast1$6 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:102" - wire width 1 \cr_bit process $group_2 - assign \cr_bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:104" - switch \bi - case 2'00 - assign \cr_bit \cr_a [3] - case 2'01 - assign \cr_bit \cr_a [2] - case 2'10 - assign \cr_bit \cr_a [1] - case 2'-- - assign \cr_bit \cr_a [0] + assign \fast1_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + assign \fast1_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:107" - wire width 1 \ctr_write process $group_3 - assign \ctr_write 1'0 - assign \ctr_write 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114" - case - assign \ctr_write 1'1 + assign \xer_so$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_so$7 \ra [31] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:111" - wire width 1 \bc_taken - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_bit - connect \B { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [3] - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113" - cell $or $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $19 - connect \B { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4] - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" - cell $eq $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4:3] - connect \B 1'0 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:131" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:131" - cell $eq $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4:3] - connect \B 1'1 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" - cell $eq $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [4] - connect \B 1'1 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:127" - wire width 1 \ctr_zero_bo1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_bit - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" - cell $and $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ctr_zero_bo1 - connect \B $29 - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" - cell $and $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ctr_zero_bo1 - connect \B \cr_bit - connect \Y $33 - end process $group_4 - assign \bc_taken 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - case 1'1 - assign \bc_taken $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" - switch { $27 $25 $23 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" - case 3'--1 - assign \bc_taken $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:131" - case 3'-1- - assign \bc_taken $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133" - case 3'1-- - assign \bc_taken \ctr_zero_bo1 + assign \xer_so_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_so_ok 1'1 end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116" - wire width 64 \ctr_n - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" - wire width 65 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" - wire width 65 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117" - cell $sub $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \fast1 - connect \B 1'1 - connect \Y $36 - end - connect $35 $36 process $group_5 - assign \ctr_n 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114" - case - assign \ctr_n $35 [63:0] + assign \xer_ov$8 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_ov$8 [0] \ra [30] + assign \xer_ov$8 [1] \ra [19] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 end sync init end process $group_6 - assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114" - case - assign \fast1$10 \ctr_n + assign \xer_ov_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_ov_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - wire width 64 \ctr_m - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 64 $38 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \fast1 [31:0] - connect \Y $38 - end process $group_7 - assign \ctr_m 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" - switch { \br_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" - case 1'1 - assign \ctr_m $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" - case - assign \ctr_m \fast1 + assign \xer_ca$9 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_ca$9 [0] \ra [29] + assign \xer_ca$9 [1] \ra [18] end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:128" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:128" - cell $reduce_or $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \ctr_m - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:128" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:128" - cell $xor $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [1] - connect \B $40 - connect \Y $42 - end process $group_8 - assign \ctr_zero_bo1 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - switch { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114" - case - assign \ctr_zero_bo1 $42 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" - cell $not $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] \br_op__insn [1] } [5] - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" - cell $and $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] \br_op__insn [1] } [9] - connect \B $44 - connect \Y $46 - end - process $group_9 - assign \br_imm_addr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - switch \br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - attribute \nmigen.decoding "OP_B/6" - case 7'0000110 - assign \br_imm_addr { { { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] } { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } } 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:144" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - assign \br_imm_addr { { { { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] } { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } } 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:150" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" - switch { $46 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" - case 1'1 - assign \br_imm_addr { \fast1 [63:2] 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:154" - case - assign \br_imm_addr { \fast2 [63:2] 2'00 } + assign \xer_ca_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_ca_ok 1'1 end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:85" - wire width 1 \br_taken process $group_10 - assign \br_taken 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - switch \br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - attribute \nmigen.decoding "OP_B/6" - case 7'0000110 - assign \br_taken 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:144" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - assign \br_taken \bc_taken - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:150" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - assign \br_taken \bc_taken + assign \o_ok 1'0 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:72" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:74" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + assign \o \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" + case 10'0000000001 + assign { \o_ok \o } [31] \xer_so + assign { \o_ok \o } [30] \xer_ov [0] + assign { \o_ok \o } [19] \xer_ov [1] + assign { \o_ok \o } [29] \xer_ca [0] + assign { \o_ok \o } [18] \xer_ca [1] + end end sync init end process $group_11 - assign \fast1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - switch \br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - attribute \nmigen.decoding "OP_B/6" - case 7'0000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:144" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - assign \fast1_ok \ctr_write - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:150" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - assign \fast1_ok \ctr_write - end - sync init - end - process $group_12 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia \br_addr - sync init - end - process $group_13 - assign \nia_ok 1'0 - assign \nia_ok \br_taken - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:167" - wire width 65 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:167" - wire width 65 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:167" - cell $add $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \br_op__cia - connect \B 3'100 - connect \Y $49 - end - connect $48 $49 - process $group_14 - assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164" - switch { \br_op__lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164" - case 1'1 - assign \fast2$11 $48 [63:0] - end - sync init - end - process $group_15 - assign \fast2_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164" - switch { \br_op__lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164" - case 1'1 - assign \fast2_ok 1'1 - end - sync init - end - process $group_16 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_17 - assign \br_op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__insn_type$3 7'0000000 - assign \br_op__fn_unit$4 11'00000000000 - assign \br_op__insn$5 32'00000000000000000000000000000000 - assign \br_op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__imm_ok$7 1'0 - assign \br_op__lk$8 1'0 - assign \br_op__is_32bit$9 1'0 - assign { \br_op__is_32bit$9 \br_op__lk$8 { \br_op__imm_data__imm_ok$7 \br_op__imm_data__imm$6 } \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + process $group_12 + assign \spr_op__insn_type$2 7'0000000 + assign \spr_op__fn_unit$3 11'00000000000 + assign \spr_op__insn$4 32'00000000000000000000000000000000 + assign \spr_op__is_32bit$5 1'0 + assign { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe" -module \pipe$19 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe" +module \pipe$61 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -58169,8 +41584,6 @@ module \pipe$19 wire width 1 output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \br_op__cia attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -58245,7 +41658,7 @@ module \pipe$19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 6 \br_op__insn_type + wire width 7 input 5 \spr_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -58259,35 +41672,31 @@ module \pipe$19 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 7 \br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 8 \br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \br_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \br_op__imm_data__imm_ok + wire width 11 input 6 \spr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \br_op__lk + wire width 32 input 7 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \br_op__is_32bit + wire width 1 input 8 \spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \fast1 + wire width 64 input 9 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \fast2 + wire width 64 input 10 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 15 \cr_a + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 12 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 13 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 14 \xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 16 \n_valid_o + wire width 1 output 15 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 17 \n_ready_i + wire width 1 input 16 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 18 \muxid$1 + wire width 2 output 17 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \br_op__cia$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__cia$2$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -58362,9 +41771,9 @@ module \pipe$19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 20 \br_op__insn_type$3 + wire width 7 output 18 \spr_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \br_op__insn_type$3$next + wire width 7 \spr_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -58378,65 +41787,75 @@ module \pipe$19 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 21 \br_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \br_op__fn_unit$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \br_op__insn$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \br_op__insn$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 23 \br_op__imm_data__imm$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__imm$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \br_op__imm_data__imm_ok$7 + wire width 11 output 19 \spr_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__imm_data__imm_ok$7$next + wire width 11 \spr_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \br_op__lk$8 + wire width 32 output 20 \spr_op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__lk$8$next + wire width 32 \spr_op__insn$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \br_op__is_32bit$9 + wire width 1 output 21 \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__is_32bit$9$next + wire width 1 \spr_op__is_32bit$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 27 \fast1$10 + wire width 64 output 22 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$10$next + wire width 64 \o$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 28 \fast1_ok + wire width 1 output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr1$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 25 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 26 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 27 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 29 \fast2$11 + wire width 1 output 28 \xer_so$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$11$next + wire width 1 \xer_so$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 30 \fast2_ok + wire width 1 output 29 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast2_ok$next + wire width 1 \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 31 \nia + wire width 2 output 30 \xer_ov$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \nia$next + wire width 2 \xer_ov$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 32 \nia_ok + wire width 1 output 31 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \nia_ok$next - cell \p$20 \p + wire width 1 \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 32 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 33 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$next + cell \p$62 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$21 \n + cell \n$63 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__cia + wire width 2 \spr_main_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -58511,7 +41930,7 @@ module \pipe$19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_br_op__insn_type + wire width 7 \spr_main_spr_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -58525,27 +41944,23 @@ module \pipe$19 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_br_op__imm_data__imm_ok + wire width 11 \spr_main_spr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_br_op__lk + wire width 32 \spr_main_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_br_op__is_32bit + wire width 1 \spr_main_spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast1 + wire width 64 \spr_main_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast2 + wire width 64 \spr_main_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_a + wire width 1 \spr_main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \spr_main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \spr_main_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__cia$13 + wire width 2 \spr_main_muxid$11 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -58620,7 +42035,7 @@ module \pipe$19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_br_op__insn_type$14 + wire width 7 \spr_main_spr_op__insn_type$12 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -58634,100 +42049,113 @@ module \pipe$19 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_br_op__fn_unit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_br_op__insn$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_br_op__imm_data__imm$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_br_op__imm_data__imm_ok$18 + wire width 11 \spr_main_spr_op__fn_unit$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_br_op__lk$19 + wire width 32 \spr_main_spr_op__insn$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_br_op__is_32bit$20 + wire width 1 \spr_main_spr_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast1$21 + wire width 64 \spr_main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_fast1_ok + wire width 1 \spr_main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast2$22 + wire width 64 \spr_main_fast1$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_fast2_ok + wire width 1 \spr_main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_nia + wire width 1 \spr_main_xer_so$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_nia_ok - cell \main$22 \main - connect \muxid \main_muxid - connect \br_op__cia \main_br_op__cia - connect \br_op__insn_type \main_br_op__insn_type - connect \br_op__fn_unit \main_br_op__fn_unit - connect \br_op__insn \main_br_op__insn - connect \br_op__imm_data__imm \main_br_op__imm_data__imm - connect \br_op__imm_data__imm_ok \main_br_op__imm_data__imm_ok - connect \br_op__lk \main_br_op__lk - connect \br_op__is_32bit \main_br_op__is_32bit - connect \fast1 \main_fast1 - connect \fast2 \main_fast2 - connect \cr_a \main_cr_a - connect \muxid$1 \main_muxid$12 - connect \br_op__cia$2 \main_br_op__cia$13 - connect \br_op__insn_type$3 \main_br_op__insn_type$14 - connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 - connect \br_op__insn$5 \main_br_op__insn$16 - connect \br_op__imm_data__imm$6 \main_br_op__imm_data__imm$17 - connect \br_op__imm_data__imm_ok$7 \main_br_op__imm_data__imm_ok$18 - connect \br_op__lk$8 \main_br_op__lk$19 - connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 - connect \fast1$10 \main_fast1$21 - connect \fast1_ok \main_fast1_ok - connect \fast2$11 \main_fast2$22 - connect \fast2_ok \main_fast2_ok - connect \nia \main_nia - connect \nia_ok \main_nia_ok + wire width 1 \spr_main_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \spr_main_xer_ov$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \spr_main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \spr_main_xer_ca$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \spr_main_xer_ca_ok + cell \spr_main \spr_main + connect \muxid \spr_main_muxid + connect \spr_op__insn_type \spr_main_spr_op__insn_type + connect \spr_op__fn_unit \spr_main_spr_op__fn_unit + connect \spr_op__insn \spr_main_spr_op__insn + connect \spr_op__is_32bit \spr_main_spr_op__is_32bit + connect \ra \spr_main_ra + connect \fast1 \spr_main_fast1 + connect \xer_so \spr_main_xer_so + connect \xer_ov \spr_main_xer_ov + connect \xer_ca \spr_main_xer_ca + connect \muxid$1 \spr_main_muxid$11 + connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 + connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 + connect \spr_op__insn$4 \spr_main_spr_op__insn$14 + connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 + connect \o \spr_main_o + connect \o_ok \spr_main_o_ok + connect \fast1$6 \spr_main_fast1$16 + connect \fast1_ok \spr_main_fast1_ok + connect \xer_so$7 \spr_main_xer_so$17 + connect \xer_so_ok \spr_main_xer_so_ok + connect \xer_ov$8 \spr_main_xer_ov$18 + connect \xer_ov_ok \spr_main_xer_ov_ok + connect \xer_ca$9 \spr_main_xer_ca$19 + connect \xer_ca_ok \spr_main_xer_ca_ok end process $group_0 - assign \main_muxid 2'00 - assign \main_muxid \muxid + assign \spr_main_muxid 2'00 + assign \spr_main_muxid \muxid sync init end process $group_1 - assign \main_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_br_op__insn_type 7'0000000 - assign \main_br_op__fn_unit 11'00000000000 - assign \main_br_op__insn 32'00000000000000000000000000000000 - assign \main_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_br_op__imm_data__imm_ok 1'0 - assign \main_br_op__lk 1'0 - assign \main_br_op__is_32bit 1'0 - assign { \main_br_op__is_32bit \main_br_op__lk { \main_br_op__imm_data__imm_ok \main_br_op__imm_data__imm } \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + assign \spr_main_spr_op__insn_type 7'0000000 + assign \spr_main_spr_op__fn_unit 11'00000000000 + assign \spr_main_spr_op__insn 32'00000000000000000000000000000000 + assign \spr_main_spr_op__is_32bit 1'0 + assign { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } sync init end - process $group_9 - assign \main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_fast1 \fast1 + process $group_5 + assign \spr_main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr_main_ra \ra sync init end - process $group_10 - assign \main_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_fast2 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr1$20 + process $group_6 + assign \spr1$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr1$20 \spr1 sync init end - process $group_11 - assign \main_cr_a 4'0000 - assign \main_cr_a \cr_a + process $group_7 + assign \spr_main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr_main_fast1 \fast1 + sync init + end + process $group_8 + assign \spr_main_xer_so 1'0 + assign \spr_main_xer_so \xer_so + sync init + end + process $group_9 + assign \spr_main_xer_ov 2'00 + assign \spr_main_xer_ov \xer_ov + sync init + end + process $group_10 + assign \spr_main_xer_ca 2'00 + assign \spr_main_xer_ca \xer_ca sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$23 - process $group_12 - assign \p_valid_i$23 1'0 - assign \p_valid_i$23 \p_valid_i + wire width 1 \p_valid_i$21 + process $group_11 + assign \p_valid_i$21 1'0 + assign \p_valid_i$21 \p_valid_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" wire width 1 \n_i_rdy_data - process $group_13 + process $group_12 assign \n_i_rdy_data 1'0 assign \n_i_rdy_data \n_ready_i sync init @@ -58735,32 +42163,30 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire width 1 \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $24 + wire width 1 $22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $25 + cell $and $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$23 + connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $24 + connect \Y $22 end - process $group_14 + process $group_13 assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $24 + assign \p_valid_i_p_ready_o $22 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$26 - process $group_15 - assign \muxid$26 2'00 - assign \muxid$26 \main_muxid$12 + wire width 2 \muxid$24 + process $group_14 + assign \muxid$24 2'00 + assign \muxid$24 \spr_main_muxid$11 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__cia$27 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -58835,7 +42261,7 @@ module \pipe$19 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \br_op__insn_type$28 + wire width 7 \spr_op__insn_type$25 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -58849,64 +42275,88 @@ module \pipe$19 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \br_op__fn_unit$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \br_op__insn$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__imm$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__imm_data__imm_ok$32 + wire width 11 \spr_op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__lk$33 + wire width 32 \spr_op__insn$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__is_32bit$34 - process $group_16 - assign \br_op__cia$27 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__insn_type$28 7'0000000 - assign \br_op__fn_unit$29 11'00000000000 - assign \br_op__insn$30 32'00000000000000000000000000000000 - assign \br_op__imm_data__imm$31 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__imm_ok$32 1'0 - assign \br_op__lk$33 1'0 - assign \br_op__is_32bit$34 1'0 - assign { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 { \main_br_op__imm_data__imm_ok$18 \main_br_op__imm_data__imm$17 } \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } + wire width 1 \spr_op__is_32bit$28 + process $group_15 + assign \spr_op__insn_type$25 7'0000000 + assign \spr_op__fn_unit$26 11'00000000000 + assign \spr_op__insn$27 32'00000000000000000000000000000000 + assign \spr_op__is_32bit$28 1'0 + assign { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$30 + process $group_19 + assign \o$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$30 1'0 + assign { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr1$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \spr1_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr1$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \spr1_ok$34 + process $group_21 + assign \spr1$31 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr1_ok$32 1'0 + assign { \spr1_ok$32 \spr1$31 } { \spr1_ok$34 \spr1$33 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 64 \fast1$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \fast1_ok$36 - process $group_24 + process $group_23 assign \fast1$35 64'0000000000000000000000000000000000000000000000000000000000000000 assign \fast1_ok$36 1'0 - assign { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } + assign { \fast1_ok$36 \fast1$35 } { \spr_main_fast1_ok \spr_main_fast1$16 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$37 + wire width 1 \xer_so$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast2_ok$38 - process $group_26 - assign \fast2$37 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2_ok$38 1'0 - assign { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } + wire width 1 \xer_so_ok$38 + process $group_25 + assign \xer_so$37 1'0 + assign \xer_so_ok$38 1'0 + assign { \xer_so_ok$38 \xer_so$37 } { \spr_main_xer_so_ok \spr_main_xer_so$17 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \nia$39 + wire width 2 \xer_ov$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \nia_ok$40 - process $group_28 - assign \nia$39 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia_ok$40 1'0 - assign { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } + wire width 1 \xer_ov_ok$40 + process $group_27 + assign \xer_ov$39 2'00 + assign \xer_ov_ok$40 1'0 + assign { \xer_ov_ok$40 \xer_ov$39 } { \spr_main_xer_ov_ok \spr_main_xer_ov$18 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$42 + process $group_29 + assign \xer_ca$41 2'00 + assign \xer_ca_ok$42 1'0 + assign { \xer_ca_ok$42 \xer_ca$41 } { \spr_main_xer_ca_ok \spr_main_xer_ca$19 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy$next - process $group_30 + process $group_31 assign \r_busy$next \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } @@ -58927,76 +42377,106 @@ module \pipe$19 sync posedge \coresync_clk update \r_busy \r_busy$next end - process $group_31 + process $group_32 assign \muxid$1$next \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$1$next \muxid$26 + assign \muxid$1$next \muxid$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$1$next \muxid$26 + assign \muxid$1$next \muxid$24 end sync init update \muxid$1 2'00 sync posedge \coresync_clk update \muxid$1 \muxid$1$next end - process $group_32 - assign \br_op__cia$2$next \br_op__cia$2 - assign \br_op__insn_type$3$next \br_op__insn_type$3 - assign \br_op__fn_unit$4$next \br_op__fn_unit$4 - assign \br_op__insn$5$next \br_op__insn$5 - assign \br_op__imm_data__imm$6$next \br_op__imm_data__imm$6 - assign \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm_ok$7 - assign \br_op__lk$8$next \br_op__lk$8 - assign \br_op__is_32bit$9$next \br_op__is_32bit$9 + process $group_33 + assign \spr_op__insn_type$2$next \spr_op__insn_type$2 + assign \spr_op__fn_unit$3$next \spr_op__fn_unit$3 + assign \spr_op__insn$4$next \spr_op__insn$4 + assign \spr_op__is_32bit$5$next \spr_op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { \spr_op__is_32bit$5$next \spr_op__insn$4$next \spr_op__fn_unit$3$next \spr_op__insn_type$2$next } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { \spr_op__is_32bit$5$next \spr_op__insn$4$next \spr_op__fn_unit$3$next \spr_op__insn_type$2$next } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + end + sync init + update \spr_op__insn_type$2 7'0000000 + update \spr_op__fn_unit$3 11'00000000000 + update \spr_op__insn$4 32'00000000000000000000000000000000 + update \spr_op__is_32bit$5 1'0 + sync posedge \coresync_clk + update \spr_op__insn_type$2 \spr_op__insn_type$2$next + update \spr_op__fn_unit$3 \spr_op__fn_unit$3$next + update \spr_op__insn$4 \spr_op__insn$4$next + update \spr_op__is_32bit$5 \spr_op__is_32bit$5$next + end + process $group_37 + assign \o$next \o + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$next } { \o_ok$30 \o$29 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$next } { \o_ok$30 \o$29 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \br_op__imm_data__imm$6$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__imm_ok$7$next 1'0 + assign \o_ok$next 1'0 end sync init - update \br_op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000 - update \br_op__insn_type$3 7'0000000 - update \br_op__fn_unit$4 11'00000000000 - update \br_op__insn$5 32'00000000000000000000000000000000 - update \br_op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000 - update \br_op__imm_data__imm_ok$7 1'0 - update \br_op__lk$8 1'0 - update \br_op__is_32bit$9 1'0 + update \o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 sync posedge \coresync_clk - update \br_op__cia$2 \br_op__cia$2$next - update \br_op__insn_type$3 \br_op__insn_type$3$next - update \br_op__fn_unit$4 \br_op__fn_unit$4$next - update \br_op__insn$5 \br_op__insn$5$next - update \br_op__imm_data__imm$6 \br_op__imm_data__imm$6$next - update \br_op__imm_data__imm_ok$7 \br_op__imm_data__imm_ok$7$next - update \br_op__lk$8 \br_op__lk$8$next - update \br_op__is_32bit$9 \br_op__is_32bit$9$next + update \o \o$next + update \o_ok \o_ok$next end - process $group_40 - assign \fast1$10$next \fast1$10 + process $group_39 + assign \spr1$6$next \spr1$6 + assign \spr1_ok$next \spr1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \spr1_ok$next \spr1$6$next } { \spr1_ok$32 \spr1$31 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \spr1_ok$next \spr1$6$next } { \spr1_ok$32 \spr1$31 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \spr1_ok$next 1'0 + end + sync init + update \spr1$6 64'0000000000000000000000000000000000000000000000000000000000000000 + update \spr1_ok 1'0 + sync posedge \coresync_clk + update \spr1$6 \spr1$6$next + update \spr1_ok \spr1_ok$next + end + process $group_41 + assign \fast1$7$next \fast1$7 assign \fast1_ok$next \fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$36 \fast1$35 } + assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$36 \fast1$35 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$36 \fast1$35 } + assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$36 \fast1$35 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -59004,96 +42484,120 @@ module \pipe$19 assign \fast1_ok$next 1'0 end sync init - update \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast1$7 64'0000000000000000000000000000000000000000000000000000000000000000 update \fast1_ok 1'0 sync posedge \coresync_clk - update \fast1$10 \fast1$10$next + update \fast1$7 \fast1$7$next update \fast1_ok \fast1_ok$next end - process $group_42 - assign \fast2$11$next \fast2$11 - assign \fast2_ok$next \fast2_ok + process $group_43 + assign \xer_so$8$next \xer_so$8 + assign \xer_so_ok$next \xer_so_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$38 \fast2$37 } + assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$38 \xer_so$37 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$38 \fast2$37 } + assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$38 \xer_so$37 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \fast2_ok$next 1'0 + assign \xer_so_ok$next 1'0 end sync init - update \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - update \fast2_ok 1'0 + update \xer_so$8 1'0 + update \xer_so_ok 1'0 sync posedge \coresync_clk - update \fast2$11 \fast2$11$next - update \fast2_ok \fast2_ok$next + update \xer_so$8 \xer_so$8$next + update \xer_so_ok \xer_so_ok$next end - process $group_44 - assign \nia$next \nia - assign \nia_ok$next \nia_ok + process $group_45 + assign \xer_ov$9$next \xer_ov$9 + assign \xer_ov_ok$next \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \nia_ok$next \nia$next } { \nia_ok$40 \nia$39 } + assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$40 \xer_ov$39 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \nia_ok$next \nia$next } { \nia_ok$40 \nia$39 } + assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$40 \xer_ov$39 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \nia_ok$next 1'0 + assign \xer_ov_ok$next 1'0 end sync init - update \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \nia_ok 1'0 + update \xer_ov$9 2'00 + update \xer_ov_ok 1'0 sync posedge \coresync_clk - update \nia \nia$next - update \nia_ok \nia_ok$next + update \xer_ov$9 \xer_ov$9$next + update \xer_ov_ok \xer_ov_ok$next end - process $group_46 + process $group_47 + assign \xer_ca$10$next \xer_ca$10 + assign \xer_ca_ok$next \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$42 \xer_ca$41 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$42 \xer_ca$41 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ca_ok$next 1'0 + end + sync init + update \xer_ca$10 2'00 + update \xer_ca_ok 1'0 + sync posedge \coresync_clk + update \xer_ca$10 \xer_ca$10$next + update \xer_ca_ok \xer_ca_ok$next + end + process $group_49 assign \n_valid_o 1'0 assign \n_valid_o \r_busy sync init end - process $group_47 + process $group_50 assign \p_ready_o 1'0 assign \p_ready_o \n_i_rdy_data sync init end + connect \spr1$33 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \spr1_ok$34 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0" -module \alu_branch0 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0" +module \alu_spr0 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \fast1_ok + wire width 1 output 1 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \fast2_ok + wire width 1 output 2 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \nia_ok - attribute \src "simple/issuer.py:89" - wire width 1 input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 6 \n_ready_i + wire width 1 output 3 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 7 \fast1 + wire width 1 output 4 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 8 \fast2 + wire width 1 output 5 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 9 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 10 \br_op__cia + wire width 1 output 6 \spr1_ok + attribute \src "simple/issuer.py:102" + wire width 1 input 7 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 8 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 9 \n_ready_i attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -59168,7 +42672,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 11 \br_op__insn_type + wire width 7 input 10 \spr_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -59182,32 +42686,44 @@ module \alu_branch0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 12 \br_op__fn_unit + wire width 11 input 11 \spr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 13 \br_op__insn + wire width 32 input 12 \spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 14 \br_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \br_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \br_op__is_32bit + wire width 1 input 13 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 14 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 15 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 18 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 19 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \fast1$1 + wire width 64 input 20 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \fast2$2 + wire width 64 input 21 \spr1$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 20 \cr_a + wire width 64 input 22 \fast1$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 23 \xer_so$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 24 \xer_ov$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 25 \xer_ca$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 21 \p_valid_i + wire width 1 input 26 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 22 \p_ready_o - cell \p$17 \p + wire width 1 output 27 \p_ready_o + cell \p$59 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$18 \n + cell \n$60 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -59217,8 +42733,6 @@ module \alu_branch0 wire width 1 \pipe_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__cia attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -59293,7 +42807,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_br_op__insn_type + wire width 7 \pipe_spr_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -59307,31 +42821,29 @@ module \alu_branch0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__imm_data__imm_ok + wire width 11 \pipe_spr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__lk + wire width 32 \pipe_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__is_32bit + wire width 1 \pipe_spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \pipe_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast2 + wire width 1 \pipe_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_a + wire width 2 \pipe_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 \pipe_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" wire width 1 \pipe_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__cia$4 + wire width 2 \pipe_muxid$6 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -59406,7 +42918,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_br_op__insn_type$5 + wire width 7 \pipe_spr_op__insn_type$7 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -59420,63 +42932,70 @@ module \alu_branch0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_br_op__fn_unit$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_br_op__insn$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__imm_data__imm$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__imm_data__imm_ok$9 + wire width 11 \pipe_spr_op__fn_unit$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__lk$10 + wire width 32 \pipe_spr_op__insn$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__is_32bit$11 + wire width 1 \pipe_spr_op__is_32bit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_spr1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 64 \pipe_fast1$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" wire width 1 \pipe_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast2$13 + wire width 1 \pipe_xer_so$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_fast2_ok + wire width 1 \pipe_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_nia + wire width 2 \pipe_xer_ov$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_nia_ok - cell \pipe$19 \pipe + wire width 1 \pipe_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe_xer_ca$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_xer_ca_ok + cell \pipe$61 \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \p_valid_i \pipe_p_valid_i connect \p_ready_o \pipe_p_ready_o connect \muxid \pipe_muxid - connect \br_op__cia \pipe_br_op__cia - connect \br_op__insn_type \pipe_br_op__insn_type - connect \br_op__fn_unit \pipe_br_op__fn_unit - connect \br_op__insn \pipe_br_op__insn - connect \br_op__imm_data__imm \pipe_br_op__imm_data__imm - connect \br_op__imm_data__imm_ok \pipe_br_op__imm_data__imm_ok - connect \br_op__lk \pipe_br_op__lk - connect \br_op__is_32bit \pipe_br_op__is_32bit + connect \spr_op__insn_type \pipe_spr_op__insn_type + connect \spr_op__fn_unit \pipe_spr_op__fn_unit + connect \spr_op__insn \pipe_spr_op__insn + connect \spr_op__is_32bit \pipe_spr_op__is_32bit + connect \ra \pipe_ra + connect \spr1 \pipe_spr1 connect \fast1 \pipe_fast1 - connect \fast2 \pipe_fast2 - connect \cr_a \pipe_cr_a + connect \xer_so \pipe_xer_so + connect \xer_ov \pipe_xer_ov + connect \xer_ca \pipe_xer_ca connect \n_valid_o \pipe_n_valid_o connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$3 - connect \br_op__cia$2 \pipe_br_op__cia$4 - connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 - connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 - connect \br_op__insn$5 \pipe_br_op__insn$7 - connect \br_op__imm_data__imm$6 \pipe_br_op__imm_data__imm$8 - connect \br_op__imm_data__imm_ok$7 \pipe_br_op__imm_data__imm_ok$9 - connect \br_op__lk$8 \pipe_br_op__lk$10 - connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 - connect \fast1$10 \pipe_fast1$12 + connect \muxid$1 \pipe_muxid$6 + connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 + connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 + connect \spr_op__insn$4 \pipe_spr_op__insn$9 + connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \spr1$6 \pipe_spr1$11 + connect \spr1_ok \pipe_spr1_ok + connect \fast1$7 \pipe_fast1$12 connect \fast1_ok \pipe_fast1_ok - connect \fast2$11 \pipe_fast2$13 - connect \fast2_ok \pipe_fast2_ok - connect \nia \pipe_nia - connect \nia_ok \pipe_nia_ok + connect \xer_so$8 \pipe_xer_so$13 + connect \xer_so_ok \pipe_xer_so_ok + connect \xer_ov$9 \pipe_xer_ov$14 + connect \xer_ov_ok \pipe_xer_ov_ok + connect \xer_ca$10 \pipe_xer_ca$15 + connect \xer_ca_ok \pipe_xer_ca_ok end process $group_0 assign \pipe_p_valid_i 1'0 @@ -59496,51 +43015,60 @@ module \alu_branch0 sync init end process $group_3 - assign \pipe_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_br_op__insn_type 7'0000000 - assign \pipe_br_op__fn_unit 11'00000000000 - assign \pipe_br_op__insn 32'00000000000000000000000000000000 - assign \pipe_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_br_op__imm_data__imm_ok 1'0 - assign \pipe_br_op__lk 1'0 - assign \pipe_br_op__is_32bit 1'0 - assign { \pipe_br_op__is_32bit \pipe_br_op__lk { \pipe_br_op__imm_data__imm_ok \pipe_br_op__imm_data__imm } \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__imm_ok \br_op__imm_data__imm } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + assign \pipe_spr_op__insn_type 7'0000000 + assign \pipe_spr_op__fn_unit 11'00000000000 + assign \pipe_spr_op__insn 32'00000000000000000000000000000000 + assign \pipe_spr_op__is_32bit 1'0 + assign { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } sync init end - process $group_11 + process $group_7 + assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_ra \ra + sync init + end + process $group_8 + assign \pipe_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_spr1 \spr1$1 + sync init + end + process $group_9 assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_fast1 \fast1$1 + assign \pipe_fast1 \fast1$2 sync init end - process $group_12 - assign \pipe_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_fast2 \fast2$2 + process $group_10 + assign \pipe_xer_so 1'0 + assign \pipe_xer_so \xer_so$3 sync init end - process $group_13 - assign \pipe_cr_a 4'0000 - assign \pipe_cr_a \cr_a + process $group_11 + assign \pipe_xer_ov 2'00 + assign \pipe_xer_ov \xer_ov$4 sync init end - process $group_14 + process $group_12 + assign \pipe_xer_ca 2'00 + assign \pipe_xer_ca \xer_ca$5 + sync init + end + process $group_13 assign \n_valid_o 1'0 assign \n_valid_o \pipe_n_valid_o sync init end - process $group_15 + process $group_14 assign \pipe_n_ready_i 1'0 assign \pipe_n_ready_i \n_ready_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$14 - process $group_16 - assign \muxid$14 2'00 - assign \muxid$14 \pipe_muxid$3 + wire width 2 \muxid$16 + process $group_15 + assign \muxid$16 2'00 + assign \muxid$16 \pipe_muxid$6 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__cia$15 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -59615,7 +43143,7 @@ module \alu_branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \br_op__insn_type$16 + wire width 7 \spr_op__insn_type$17 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -59629,98 +43157,106 @@ module \alu_branch0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \br_op__fn_unit$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \br_op__insn$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__imm$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__imm_data__imm_ok$20 + wire width 11 \spr_op__fn_unit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__lk$21 + wire width 32 \spr_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__is_32bit$22 - process $group_17 - assign \br_op__cia$15 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__insn_type$16 7'0000000 - assign \br_op__fn_unit$17 11'00000000000 - assign \br_op__insn$18 32'00000000000000000000000000000000 - assign \br_op__imm_data__imm$19 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__imm_ok$20 1'0 - assign \br_op__lk$21 1'0 - assign \br_op__is_32bit$22 1'0 - assign { \br_op__is_32bit$22 \br_op__lk$21 { \br_op__imm_data__imm_ok$20 \br_op__imm_data__imm$19 } \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 { \pipe_br_op__imm_data__imm_ok$9 \pipe_br_op__imm_data__imm$8 } \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } + wire width 1 \spr_op__is_32bit$20 + process $group_16 + assign \spr_op__insn_type$17 7'0000000 + assign \spr_op__fn_unit$18 11'00000000000 + assign \spr_op__insn$19 32'00000000000000000000000000000000 + assign \spr_op__is_32bit$20 1'0 + assign { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } sync init end - process $group_25 + process $group_20 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'0 + assign { \o_ok \o } { \pipe_o_ok \pipe_o } + sync init + end + process $group_22 + assign \spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr1_ok 1'0 + assign { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } + sync init + end + process $group_24 assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000 assign \fast1_ok 1'0 assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } sync init end - process $group_27 - assign \fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2_ok 1'0 - assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } + process $group_26 + assign \xer_so 1'0 + assign \xer_so_ok 1'0 + assign { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } sync init end - process $group_29 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia_ok 1'0 - assign { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } + process $group_28 + assign \xer_ov 2'00 + assign \xer_ov_ok 1'0 + assign { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } + sync init + end + process $group_30 + assign \xer_ca 2'00 + assign \xer_ca_ok 1'0 + assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } sync init end connect \muxid 2'00 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l" -module \src_l$23 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l" +module \src_l$64 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src + wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src + wire width 6 input 3 \r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src + wire width 6 output 4 \q_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int + wire width 6 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next + wire width 6 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 + wire width 6 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \r_src connect \Y $1 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 + wire width 6 $3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_int connect \B $1 connect \Y $3 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 + wire width 6 $5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A $3 connect \B \s_src connect \Y $5 @@ -59731,98 +43267,98 @@ module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 3'000 + assign \q_int$next 6'000000 end sync init - update \q_int 3'000 + update \q_int 6'000000 sync posedge \coresync_clk update \q_int \q_int$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 + wire width 6 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \r_src connect \Y $7 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 + wire width 6 $9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_int connect \B $7 connect \Y $9 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 + wire width 6 $11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A $9 connect \B \s_src connect \Y $11 end process $group_1 - assign \q_src 3'000 + assign \q_src 6'000000 assign \q_src $11 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src + wire width 6 \qn_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 + wire width 6 $13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_src connect \Y $13 end process $group_2 - assign \qn_src 3'000 + assign \qn_src 6'000000 assign \qn_src $13 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src + wire width 6 \qlq_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 + wire width 6 $15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int connect \Y $15 end process $group_3 - assign \qlq_src 3'000 + assign \qlq_src 6'000000 assign \qlq_src $15 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l" -module \opc_l$24 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l" +module \opc_l$65 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_opc @@ -59963,54 +43499,54 @@ module \opc_l$24 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l" -module \req_l$25 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l" +module \req_l$66 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req + wire width 6 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req + wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req + wire width 6 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int + wire width 6 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next + wire width 6 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 + wire width 6 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \r_req connect \Y $1 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 + wire width 6 $3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_int connect \B $1 connect \Y $3 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 + wire width 6 $5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A $3 connect \B \s_req connect \Y $5 @@ -60021,98 +43557,98 @@ module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 3'000 + assign \q_int$next 6'000000 end sync init - update \q_int 3'000 + update \q_int 6'000000 sync posedge \coresync_clk update \q_int \q_int$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 + wire width 6 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \r_req connect \Y $7 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 + wire width 6 $9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_int connect \B $7 connect \Y $9 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 + wire width 6 $11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A $9 connect \B \s_req connect \Y $11 end process $group_1 - assign \q_req 3'000 + assign \q_req 6'000000 assign \q_req $11 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req + wire width 6 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 + wire width 6 $13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_req connect \Y $13 end process $group_2 - assign \qn_req 3'000 + assign \qn_req 6'000000 assign \qn_req $13 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req + wire width 6 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 + wire width 6 $15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int connect \Y $15 end process $group_3 - assign \qlq_req 3'000 + assign \qlq_req 6'000000 assign \qlq_req $15 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l" -module \rst_l$26 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l" +module \rst_l$67 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 input 2 \s_rst @@ -60253,11 +43789,11 @@ module \rst_l$26 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l" -module \rok_l$27 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l" +module \rok_l$68 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_rdok @@ -60398,11 +43934,11 @@ module \rok_l$27 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l" -module \alui_l$28 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l" +module \alui_l$69 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alui @@ -60543,11 +44079,11 @@ module \alui_l$28 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l" -module \alu_l$29 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l" +module \alu_l$70 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 output 2 \q_alu @@ -60688,12 +44224,10 @@ module \alu_l$29 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0" -module \branch0 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0" +module \spr0 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 1 \oper_i_alu_branch0__cia attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -60768,7 +44302,7 @@ module \branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \oper_i_alu_branch0__insn_type + wire width 7 input 1 \oper_i_alu_spr0__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -60782,63 +44316,67 @@ module \branch0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 3 \oper_i_alu_branch0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 4 \oper_i_alu_branch0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \oper_i_alu_branch0__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_branch0__imm_data__imm_ok + wire width 11 input 2 \oper_i_alu_spr0__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \oper_i_alu_branch0__lk + wire width 32 input 3 \oper_i_alu_spr0__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_branch0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 9 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 10 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 input 11 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 12 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 13 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 4 input 14 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 15 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 16 \src2_i + wire width 1 input 4 \oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 input 5 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 output 6 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 7 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 8 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 9 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 10 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 input 11 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 12 \src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 13 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 14 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 15 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 17 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 18 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 19 \cu_wr__go_i + wire width 1 output 16 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 17 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 18 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 19 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 20 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 21 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 22 \dest2_o + wire width 1 output 20 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 21 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 24 \dest3_o - attribute \src "simple/issuer.py:89" - wire width 1 input 25 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_branch0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_branch0_n_ready_i + wire width 1 output 22 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 23 \dest5_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_branch0_fast1 + wire width 1 output 24 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 output 25 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_branch0_fast2 + wire width 1 output 26 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 27 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_branch0_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__cia + wire width 1 output 28 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 29 \dest2_o + attribute \src "simple/issuer.py:102" + wire width 1 input 30 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \alu_spr0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \alu_spr0_n_ready_i attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -60913,7 +44451,9 @@ module \branch0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_branch0_br_op__insn_type + wire width 7 \alu_spr0_spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_spr0_spr_op__insn_type$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -60927,63 +44467,86 @@ module \branch0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_branch0_br_op__fn_unit + wire width 11 \alu_spr0_spr_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_branch0_br_op__insn + wire width 11 \alu_spr0_spr_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__imm_data__imm + wire width 32 \alu_spr0_spr_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__imm_data__imm_ok + wire width 32 \alu_spr0_spr_op__insn$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__lk + wire width 1 \alu_spr0_spr_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__is_32bit + wire width 1 \alu_spr0_spr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_spr0_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_spr0_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_spr0_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \alu_spr0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_spr0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_spr0_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_branch0_fast1$1 + wire width 64 \alu_spr0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_branch0_fast2$2 + wire width 64 \alu_spr0_spr1$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \alu_branch0_cr_a + wire width 64 \alu_spr0_fast1$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \alu_spr0_xer_so$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_spr0_xer_ov$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_spr0_xer_ca$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_branch0_p_valid_i + wire width 1 \alu_spr0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_branch0_p_ready_o - cell \alu_branch0 \alu_branch0 + wire width 1 \alu_spr0_p_ready_o + cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk + connect \o_ok \o_ok + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov_ok \xer_ov_ok + connect \xer_so_ok \xer_so_ok connect \fast1_ok \fast1_ok - connect \fast2_ok \fast2_ok - connect \nia_ok \nia_ok + connect \spr1_ok \spr1_ok connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_branch0_n_valid_o - connect \n_ready_i \alu_branch0_n_ready_i - connect \fast1 \alu_branch0_fast1 - connect \fast2 \alu_branch0_fast2 - connect \nia \alu_branch0_nia - connect \br_op__cia \alu_branch0_br_op__cia - connect \br_op__insn_type \alu_branch0_br_op__insn_type - connect \br_op__fn_unit \alu_branch0_br_op__fn_unit - connect \br_op__insn \alu_branch0_br_op__insn - connect \br_op__imm_data__imm \alu_branch0_br_op__imm_data__imm - connect \br_op__imm_data__imm_ok \alu_branch0_br_op__imm_data__imm_ok - connect \br_op__lk \alu_branch0_br_op__lk - connect \br_op__is_32bit \alu_branch0_br_op__is_32bit - connect \fast1$1 \alu_branch0_fast1$1 - connect \fast2$2 \alu_branch0_fast2$2 - connect \cr_a \alu_branch0_cr_a - connect \p_valid_i \alu_branch0_p_valid_i - connect \p_ready_o \alu_branch0_p_ready_o + connect \n_valid_o \alu_spr0_n_valid_o + connect \n_ready_i \alu_spr0_n_ready_i + connect \spr_op__insn_type \alu_spr0_spr_op__insn_type + connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit + connect \spr_op__insn \alu_spr0_spr_op__insn + connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit + connect \o \alu_spr0_o + connect \spr1 \alu_spr0_spr1 + connect \fast1 \alu_spr0_fast1 + connect \xer_so \alu_spr0_xer_so + connect \xer_ov \alu_spr0_xer_ov + connect \xer_ca \alu_spr0_xer_ca + connect \ra \alu_spr0_ra + connect \spr1$1 \alu_spr0_spr1$1 + connect \fast1$2 \alu_spr0_fast1$2 + connect \xer_so$3 \alu_spr0_xer_so$3 + connect \xer_ov$4 \alu_spr0_xer_ov$4 + connect \xer_ca$5 \alu_spr0_xer_ca$5 + connect \p_valid_i \alu_spr0_p_valid_i + connect \p_ready_o \alu_spr0_p_ready_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src + wire width 6 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next + wire width 6 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src + wire width 6 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next + wire width 6 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - cell \src_l$23 \src_l + wire width 6 \src_l_q_src + cell \src_l$64 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_src \src_l_s_src @@ -61000,7 +44563,7 @@ module \branch0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$24 \opc_l + cell \opc_l$65 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_opc \opc_l_s_opc @@ -61008,14 +44571,16 @@ module \branch0 connect \q_opc \opc_l_q_opc end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req + wire width 6 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req + wire width 6 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 \req_l_s_req$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req + wire width 6 \req_l_r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req$next - cell \req_l$25 \req_l + wire width 6 \req_l_r_req$next + cell \req_l$66 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_req \req_l_q_req @@ -61024,9 +44589,13 @@ module \branch0 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$26 \rst_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst$next + cell \rst_l$67 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \s_rst \rst_l_s_rst @@ -61036,11 +44605,13 @@ module \branch0 wire width 1 \rok_l_q_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$27 \rok_l + cell \rok_l$68 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_rdok \rok_l_q_rdok @@ -61055,7 +44626,7 @@ module \branch0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$28 \alui_l + cell \alui_l$69 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alui \alui_l_q_alui @@ -61070,19 +44641,19 @@ module \branch0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$29 \alu_l + cell \alu_l$70 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst connect \q_alu \alu_l_q_alu connect \r_alu \alu_l_r_alu connect \s_alu \alu_l_s_alu end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 $3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - cell $and $4 + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $7 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -61090,62 +44661,62 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $3 + connect \Y $6 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 3 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $not $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 6 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $10 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $6 + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 3 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $or $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 6 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $6 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $9 connect \B \cu_rd__go_i - connect \Y $8 + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $reduce_and $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $5 + connect \A $11 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 - connect \Y $11 + connect \A $6 + connect \B $8 + connect \Y $14 end process $group_0 assign \all_rd 1'0 - assign \all_rd $11 + assign \all_rd $14 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \all_rd_dly$next process $group_1 assign \all_rd_dly$next \all_rd_dly @@ -61155,48 +44726,55 @@ module \branch0 sync posedge \coresync_clk update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $not $14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $17 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $13 + connect \Y $16 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $and $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $19 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd - connect \B $13 - connect \Y $15 + connect \B $16 + connect \Y $18 end process $group_2 + assign \all_rd_rise 1'0 + assign \all_rd_rise $18 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire width 1 \all_rd_pulse + process $group_3 assign \all_rd_pulse 1'0 - assign \all_rd_pulse $15 + assign \all_rd_pulse \all_rd_rise sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" wire width 1 \alu_done - process $group_3 + process $group_4 assign \alu_done 1'0 - assign \alu_done \alu_branch0_n_valid_o + assign \alu_done \alu_spr0_n_valid_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \alu_done_dly$next - process $group_4 + process $group_5 assign \alu_done_dly$next \alu_done_dly assign \alu_done_dly$next \alu_done sync init @@ -61204,313 +44782,320 @@ module \branch0 sync posedge \coresync_clk update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $not $18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $21 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $17 + connect \Y $20 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $and $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done - connect \B $17 - connect \Y $19 + connect \B $20 + connect \Y $22 end - process $group_5 + process $group_6 + assign \alu_done_rise 1'0 + assign \alu_done_rise $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire width 1 \alu_pulse + process $group_7 assign \alu_pulse 1'0 - assign \alu_pulse $19 + assign \alu_pulse \alu_done_rise sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" - wire width 3 \alu_pulsem - process $group_6 - assign \alu_pulsem 3'000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 6 \alu_pulsem + process $group_8 + assign \alu_pulsem 6'000000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 3 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - cell $and $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 6 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 6 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 6 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $21 + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $24 end - process $group_7 + process $group_9 assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $21 + assign \prev_wr_go$next $24 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \prev_wr_go$next 3'000 + assign \prev_wr_go$next 6'000000 end sync init - update \prev_wr_go 3'000 + update \prev_wr_go 6'000000 sync posedge \coresync_clk update \prev_wr_go \prev_wr_go$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 6 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 6 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $25 + connect \Y $28 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 6 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o - connect \B $25 - connect \Y $27 + connect \B $28 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $reduce_bool $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_bool $32 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $24 + connect \A $30 + connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $33 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 + connect \A $27 + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $35 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_busy_o - connect \B $23 - connect \Y $31 + connect \B $26 + connect \Y $34 end - process $group_8 + process $group_10 assign \cu_done_o 1'0 - assign \cu_done_o $31 + assign \cu_done_o $34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $37 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $33 + connect \Y $36 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $39 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $35 + connect \Y $38 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $or $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $41 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $33 - connect \B $35 - connect \Y $37 + connect \A $36 + connect \B $38 + connect \Y $40 end - process $group_9 + process $group_11 assign \wr_any 1'0 - assign \wr_any $37 + assign \wr_any $40 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $not $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $43 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_ready_i - connect \Y $39 + connect \A \alu_spr0_n_ready_i + connect \Y $42 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $and $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_any - connect \B $39 - connect \Y $41 + connect \B $42 + connect \Y $44 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 3 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 6 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $47 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $43 + connect \Y $46 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $eq $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $49 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $43 + connect \A $46 connect \B 1'0 - connect \Y $45 + connect \Y $48 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $51 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $41 - connect \B $45 - connect \Y $47 + connect \A $44 + connect \B $48 + connect \Y $50 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $eq $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $53 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $49 + connect \Y $52 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $55 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $49 - connect \B \alu_branch0_n_ready_i - connect \Y $51 + connect \A $52 + connect \B \alu_spr0_n_ready_i + connect \Y $54 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $57 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $51 - connect \B \alu_branch0_n_valid_o - connect \Y $53 + connect \A $54 + connect \B \alu_spr0_n_valid_o + connect \Y $56 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $59 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $53 + connect \A $56 connect \B \cu_busy_o - connect \Y $55 + connect \Y $58 end - process $group_10 + process $group_12 assign \req_done 1'0 - assign \req_done $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + assign \req_done $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch { $58 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" case 1'1 assign \req_done 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire width 1 $60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $61 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -61518,19 +45103,19 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $57 + connect \Y $60 end - process $group_11 + process $group_13 assign \reset 1'0 - assign \reset $57 + assign \reset $60 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - cell $or $60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire width 1 $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $63 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -61538,74 +45123,82 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $59 + connect \Y $62 end - process $group_12 + process $group_14 assign \rst_r 1'0 - assign \rst_r $59 + assign \rst_r $62 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - wire width 3 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - cell $or $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 6 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 6 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $65 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $61 + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $64 end - process $group_13 - assign \reset_w 3'000 - assign \reset_w $61 + process $group_15 + assign \reset_w 6'000000 + assign \reset_w $64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - wire width 3 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - cell $or $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 6 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 6 $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $67 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $63 + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $66 end - process $group_14 - assign \reset_r 3'000 - assign \reset_r $63 + process $group_16 + assign \reset_r 6'000000 + assign \reset_r $66 sync init end - process $group_15 - assign \rok_l_s_rdok 1'0 - assign \rok_l_s_rdok \cu_issue_i + process $group_17 + assign \rok_l_s_rdok$next \rok_l_s_rdok + assign \rok_l_s_rdok$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_s_rdok$next 1'0 + end sync init + update \rok_l_s_rdok 1'0 + sync posedge \coresync_clk + update \rok_l_s_rdok \rok_l_s_rdok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - cell $and $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire width 1 $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_valid_o + connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $65 + connect \Y $68 end - process $group_16 + process $group_18 assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $65 + assign \rok_l_r_rdok$next $68 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -61616,17 +45209,33 @@ module \branch0 sync posedge \coresync_clk update \rok_l_r_rdok \rok_l_r_rdok$next end - process $group_17 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \all_rd + process $group_19 + assign \rst_l_s_rst$next \rst_l_s_rst + assign \rst_l_s_rst$next \all_rd + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_s_rst$next 1'0 + end sync init + update \rst_l_s_rst 1'0 + sync posedge \coresync_clk + update \rst_l_s_rst \rst_l_s_rst$next end - process $group_18 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \rst_r + process $group_20 + assign \rst_l_r_rst$next \rst_l_r_rst + assign \rst_l_r_rst$next \rst_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_r_rst$next 1'1 + end sync init + update \rst_l_r_rst 1'1 + sync posedge \coresync_clk + update \rst_l_r_rst \rst_l_r_rst$next end - process $group_19 + process $group_21 assign \opc_l_s_opc$next \opc_l_s_opc assign \opc_l_s_opc$next \cu_issue_i attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -61639,7 +45248,7 @@ module \branch0 sync posedge \coresync_clk update \opc_l_s_opc \opc_l_s_opc$next end - process $group_20 + process $group_22 assign \opc_l_r_opc$next \opc_l_r_opc assign \opc_l_r_opc$next \req_done attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -61652,566 +45261,397 @@ module \branch0 sync posedge \coresync_clk update \opc_l_r_opc \opc_l_r_opc$next end - process $group_21 + process $group_23 assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \src_l_s_src$next 3'000 + assign \src_l_s_src$next 6'000000 end sync init - update \src_l_s_src 3'000 + update \src_l_s_src 6'000000 sync posedge \coresync_clk update \src_l_s_src \src_l_s_src$next end - process $group_22 + process $group_24 assign \src_l_r_src$next \src_l_r_src assign \src_l_r_src$next \reset_r attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \src_l_r_src$next 3'111 + assign \src_l_r_src$next 6'111111 end sync init - update \src_l_r_src 3'111 + update \src_l_r_src 6'111111 sync posedge \coresync_clk update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - cell $and $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 6 $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $71 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $67 + connect \Y $70 end - process $group_23 - assign \req_l_s_req 3'000 - assign \req_l_s_req $67 + process $group_25 + assign \req_l_s_req$next \req_l_s_req + assign \req_l_s_req$next $70 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_s_req$next 6'000000 + end sync init + update \req_l_s_req 6'000000 + sync posedge \coresync_clk + update \req_l_s_req \req_l_s_req$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - wire width 3 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - cell $or $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 6 $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $73 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $69 + connect \Y $72 end - process $group_24 + process $group_26 assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $69 + assign \req_l_r_req$next $72 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \req_l_r_req$next 3'111 + assign \req_l_r_req$next 6'111111 end sync init - update \req_l_r_req 3'111 + update \req_l_r_req 6'111111 sync posedge \coresync_clk update \req_l_r_req \req_l_r_req$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__cia - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__cia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__cia$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__lk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__lk$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 181 $71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $72 - parameter \WIDTH 181 - connect \A { \oper_l__is_32bit \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn \oper_l__fn_unit \oper_l__insn_type \oper_l__cia } - connect \B { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk { \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm } \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } - connect \S \cu_issue_i - connect \Y $71 - end - process $group_25 - assign \oper_r__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 11'00000000000 - assign \oper_r__insn 32'00000000000000000000000000000000 - assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__imm_data__imm_ok 1'0 - assign \oper_r__lk 1'0 - assign \oper_r__is_32bit 1'0 - assign { \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn \oper_r__fn_unit \oper_r__insn_type \oper_r__cia } $71 + process $group_27 + assign \alu_spr0_spr_op__insn_type$next \alu_spr0_spr_op__insn_type + assign \alu_spr0_spr_op__fn_unit$next \alu_spr0_spr_op__fn_unit + assign \alu_spr0_spr_op__insn$next \alu_spr0_spr_op__insn + assign \alu_spr0_spr_op__is_32bit$next \alu_spr0_spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + case 1'1 + assign { \alu_spr0_spr_op__is_32bit$next \alu_spr0_spr_op__insn$next \alu_spr0_spr_op__fn_unit$next \alu_spr0_spr_op__insn_type$next } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + end sync init + update \alu_spr0_spr_op__insn_type 7'0000000 + update \alu_spr0_spr_op__fn_unit 11'00000000000 + update \alu_spr0_spr_op__insn 32'00000000000000000000000000000000 + update \alu_spr0_spr_op__is_32bit 1'0 + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn_type \alu_spr0_spr_op__insn_type$next + update \alu_spr0_spr_op__fn_unit \alu_spr0_spr_op__fn_unit$next + update \alu_spr0_spr_op__insn \alu_spr0_spr_op__insn$next + update \alu_spr0_spr_op__is_32bit \alu_spr0_spr_op__is_32bit$next end - process $group_33 - assign \oper_l__cia$next \oper_l__cia - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__insn$next \oper_l__insn - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__lk$next \oper_l__lk - assign \oper_l__is_32bit$next \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok$next + process $group_31 + assign \data_r0__o$next \data_r0__o + assign \data_r0__o_ok$next \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_spr0_o } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" case 1'1 - assign { \oper_l__is_32bit$next \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next \oper_l__cia$next } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk { \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm } \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 + assign \data_r0__o_ok$next 1'0 end sync init - update \oper_l__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 11'00000000000 - update \oper_l__insn 32'00000000000000000000000000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__lk 1'0 - update \oper_l__is_32bit 1'0 + update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0__o_ok 1'0 sync posedge \coresync_clk - update \oper_l__cia \oper_l__cia$next - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__insn \oper_l__insn$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__lk \oper_l__lk$next - update \oper_l__is_32bit \oper_l__is_32bit$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r0__fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r0__fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__fast1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__fast1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $73 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $74 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $74 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $76 - parameter \WIDTH 65 - connect \A { \data_r0_l__fast1_ok \data_r0_l__fast1 } - connect \B { \fast1_ok \alu_branch0_fast1 } - connect \S $74 - connect \Y $73 - end - process $group_41 - assign \data_r0__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__fast1_ok 1'0 - assign { \data_r0__fast1_ok \data_r0__fast1 } $73 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $77 + update \data_r0__o \data_r0__o$next + update \data_r0__o_ok \data_r0__o_ok$next end - process $group_43 - assign \data_r0_l__fast1$next \data_r0_l__fast1 - assign \data_r0_l__fast1_ok$next \data_r0_l__fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__spr1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__spr1_ok$next + process $group_33 + assign \data_r1__spr1$next \data_r1__spr1 + assign \data_r1__spr1_ok$next \data_r1__spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r1__spr1_ok$next \data_r1__spr1$next } { \spr1_ok \alu_spr0_spr1 } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" case 1'1 - assign { \data_r0_l__fast1_ok$next \data_r0_l__fast1$next } { \fast1_ok \alu_branch0_fast1 } + assign { \data_r1__spr1_ok$next \data_r1__spr1$next } 65'00000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \data_r0_l__fast1_ok$next 1'0 + assign \data_r1__spr1_ok$next 1'0 end sync init - update \data_r0_l__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0_l__fast1_ok 1'0 + update \data_r1__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r1__spr1_ok 1'0 sync posedge \coresync_clk - update \data_r0_l__fast1 \data_r0_l__fast1$next - update \data_r0_l__fast1_ok \data_r0_l__fast1_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r1__fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r1__fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r1_l__fast2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r1_l__fast2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__fast2_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $80 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $80 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $82 - parameter \WIDTH 65 - connect \A { \data_r1_l__fast2_ok \data_r1_l__fast2 } - connect \B { \fast2_ok \alu_branch0_fast2 } - connect \S $80 - connect \Y $79 + update \data_r1__spr1 \data_r1__spr1$next + update \data_r1__spr1_ok \data_r1__spr1_ok$next end - process $group_45 - assign \data_r1__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r1__fast2_ok 1'0 - assign { \data_r1__fast2_ok \data_r1__fast2 } $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__fast1_ok$next + process $group_35 + assign \data_r2__fast1$next \data_r2__fast1 + assign \data_r2__fast1_ok$next \data_r2__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r2__fast1_ok$next \data_r2__fast1$next } { \fast1_ok \alu_spr0_fast1 } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r2__fast1_ok$next \data_r2__fast1$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r2__fast1_ok$next 1'0 + end sync init + update \data_r2__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r2__fast1_ok 1'0 + sync posedge \coresync_clk + update \data_r2__fast1 \data_r2__fast1$next + update \data_r2__fast1_ok \data_r2__fast1_ok$next end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $83 - end - process $group_47 - assign \data_r1_l__fast2$next \data_r1_l__fast2 - assign \data_r1_l__fast2_ok$next \data_r1_l__fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $83 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so_ok$next + process $group_37 + assign \data_r3__xer_so$next \data_r3__xer_so + assign \data_r3__xer_so_ok$next \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" case 1'1 - assign { \data_r1_l__fast2_ok$next \data_r1_l__fast2$next } { \fast2_ok \alu_branch0_fast2 } + assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } { \xer_so_ok \alu_spr0_xer_so } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \data_r1_l__fast2_ok$next 1'0 + assign \data_r3__xer_so_ok$next 1'0 end sync init - update \data_r1_l__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r1_l__fast2_ok 1'0 + update \data_r3__xer_so 1'0 + update \data_r3__xer_so_ok 1'0 sync posedge \coresync_clk - update \data_r1_l__fast2 \data_r1_l__fast2$next - update \data_r1_l__fast2_ok \data_r1_l__fast2_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r2__nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r2__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r2_l__nia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r2_l__nia$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__nia_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $85 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $86 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $88 - parameter \WIDTH 65 - connect \A { \data_r2_l__nia_ok \data_r2_l__nia } - connect \B { \nia_ok \alu_branch0_nia } - connect \S $86 - connect \Y $85 + update \data_r3__xer_so \data_r3__xer_so$next + update \data_r3__xer_so_ok \data_r3__xer_so_ok$next end - process $group_49 - assign \data_r2__nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r2__nia_ok 1'0 - assign { \data_r2__nia_ok \data_r2__nia } $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r4__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r4__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r4__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r4__xer_ov_ok$next + process $group_39 + assign \data_r4__xer_ov$next \data_r4__xer_ov + assign \data_r4__xer_ov_ok$next \data_r4__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r4__xer_ov_ok$next \data_r4__xer_ov$next } { \xer_ov_ok \alu_spr0_xer_ov } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r4__xer_ov_ok$next \data_r4__xer_ov$next } 3'000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r4__xer_ov_ok$next 1'0 + end sync init + update \data_r4__xer_ov 2'00 + update \data_r4__xer_ov_ok 1'0 + sync posedge \coresync_clk + update \data_r4__xer_ov \data_r4__xer_ov$next + update \data_r4__xer_ov_ok \data_r4__xer_ov_ok$next end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $89 - end - process $group_51 - assign \data_r2_l__nia$next \data_r2_l__nia - assign \data_r2_l__nia_ok$next \data_r2_l__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $89 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r5__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r5__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r5__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r5__xer_ca_ok$next + process $group_41 + assign \data_r5__xer_ca$next \data_r5__xer_ca + assign \data_r5__xer_ca_ok$next \data_r5__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" case 1'1 - assign { \data_r2_l__nia_ok$next \data_r2_l__nia$next } { \nia_ok \alu_branch0_nia } + assign { \data_r5__xer_ca_ok$next \data_r5__xer_ca$next } { \xer_ca_ok \alu_spr0_xer_ca } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r5__xer_ca_ok$next \data_r5__xer_ca$next } 3'000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \data_r2_l__nia_ok$next 1'0 + assign \data_r5__xer_ca_ok$next 1'0 end sync init - update \data_r2_l__nia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r2_l__nia_ok 1'0 + update \data_r5__xer_ca 2'00 + update \data_r5__xer_ca_ok 1'0 sync posedge \coresync_clk - update \data_r2_l__nia \data_r2_l__nia$next - update \data_r2_l__nia_ok \data_r2_l__nia_ok$next + update \data_r5__xer_ca \data_r5__xer_ca$next + update \data_r5__xer_ca_ok \data_r5__xer_ca_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r0__fast1_ok + connect \A \o_ok connect \B \cu_busy_o - connect \Y $91 + connect \Y $74 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r1__fast2_ok + connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $93 + connect \Y $76 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r2__nia_ok + connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $95 + connect \Y $78 end - process $group_53 - assign \cu_wrmask_o 3'000 - assign \cu_wrmask_o { $95 $93 $91 } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $81 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $80 end - process $group_54 - assign \alu_branch0_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_branch0_br_op__insn_type 7'0000000 - assign \alu_branch0_br_op__fn_unit 11'00000000000 - assign \alu_branch0_br_op__insn 32'00000000000000000000000000000000 - assign \alu_branch0_br_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_branch0_br_op__imm_data__imm_ok 1'0 - assign \alu_branch0_br_op__lk 1'0 - assign \alu_branch0_br_op__is_32bit 1'0 - assign { \alu_branch0_br_op__is_32bit \alu_branch0_br_op__lk { \alu_branch0_br_op__imm_data__imm_ok \alu_branch0_br_op__imm_data__imm } \alu_branch0_br_op__insn \alu_branch0_br_op__fn_unit \alu_branch0_br_op__insn_type \alu_branch0_br_op__cia } { \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn \oper_r__fn_unit \oper_r__insn_type \oper_r__cia } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - cell $mux $98 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \oper_r__imm_data__imm_ok - connect \Y $97 - end - process $group_62 - assign \src_sel 1'0 - assign \src_sel $97 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $83 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $82 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 64 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $100 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \oper_r__imm_data__imm - connect \S \oper_r__imm_data__imm_ok - connect \Y $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ca_ok + connect \B \cu_busy_o + connect \Y $84 end - process $group_63 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $99 + process $group_43 + assign \cu_wrmask_o 6'000000 + assign \cu_wrmask_o { $84 $82 $80 $78 $76 $74 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" @@ -62219,21 +45659,21 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $101 + wire width 64 $86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $102 + cell $mux $87 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $101 + connect \Y $86 end - process $group_64 - assign \alu_branch0_fast1$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_branch0_fast1$1 $101 + process $group_44 + assign \alu_spr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_spr0_ra $86 sync init end - process $group_65 + process $group_45 assign \src_r0$next \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [0] } @@ -62251,27 +45691,27 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $103 + wire width 64 $88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $104 + cell $mux $89 parameter \WIDTH 64 connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $103 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $88 end - process $group_66 - assign \alu_branch0_fast2$2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_branch0_fast2$2 $103 + process $group_46 + assign \alu_spr0_spr1$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_spr0_spr1$1 $88 sync init end - process $group_67 + process $group_47 assign \src_r1$next \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } + switch { \src_l_q_src [1] } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign \src_r1$next \src_or_imm + assign \src_r1$next \src2_i end sync init update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -62279,25 +45719,25 @@ module \branch0 update \src_r1 \src_r1$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r2 + wire width 64 \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r2$next + wire width 64 \src_r2$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 4 $105 + wire width 64 $90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $106 - parameter \WIDTH 4 + cell $mux $91 + parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $105 + connect \Y $90 end - process $group_68 - assign \alu_branch0_cr_a 4'0000 - assign \alu_branch0_cr_a $105 + process $group_48 + assign \alu_spr0_fast1$2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_spr0_fast1$2 $90 sync init end - process $group_69 + process $group_49 assign \src_r2$next \src_r2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \src_l_q_src [2] } @@ -62306,31 +45746,127 @@ module \branch0 assign \src_r2$next \src3_i end sync init - update \src_r2 4'0000 + update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk update \src_r2 \src_r2$next end - process $group_70 - assign \alu_branch0_p_valid_i 1'0 - assign \alu_branch0_p_valid_i \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $92 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $93 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $92 + end + process $group_50 + assign \alu_spr0_xer_so$3 1'0 + assign \alu_spr0_xer_so$3 $92 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - cell $and $108 + process $group_51 + assign \src_r3$next \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [3] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r3$next \src4_i + end + sync init + update \src_r3 1'0 + sync posedge \coresync_clk + update \src_r3 \src_r3$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r4$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $94 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $95 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $94 + end + process $group_52 + assign \alu_spr0_xer_ov$4 2'00 + assign \alu_spr0_xer_ov$4 $94 + sync init + end + process $group_53 + assign \src_r4$next \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [4] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r4$next \src5_i + end + sync init + update \src_r4 2'00 + sync posedge \coresync_clk + update \src_r4 \src_r4$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r5$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $96 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $97 + parameter \WIDTH 2 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $96 + end + process $group_54 + assign \alu_spr0_xer_ca$5 2'00 + assign \alu_spr0_xer_ca$5 $96 + sync init + end + process $group_55 + assign \src_r5$next \src_r5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [5] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r5$next \src6_i + end + sync init + update \src_r5 2'00 + sync posedge \coresync_clk + update \src_r5 \src_r5$next + end + process $group_56 + assign \alu_spr0_p_valid_i 1'0 + assign \alu_spr0_p_valid_i \alui_l_q_alui + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_branch0_p_ready_o + connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $107 + connect \Y $98 end - process $group_71 + process $group_57 assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $107 + assign \alui_l_r_alui$next $98 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -62341,32 +45877,32 @@ module \branch0 sync posedge \coresync_clk update \alui_l_r_alui \alui_l_r_alui$next end - process $group_72 + process $group_58 assign \alui_l_s_alui 1'0 assign \alui_l_s_alui \all_rd_pulse sync init end - process $group_73 - assign \alu_branch0_n_ready_i 1'0 - assign \alu_branch0_n_ready_i \alu_l_q_alu + process $group_59 + assign \alu_spr0_n_ready_i 1'0 + assign \alu_spr0_n_ready_i \alu_l_q_alu sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - cell $and $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire width 1 $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_valid_o + connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $109 + connect \Y $100 end - process $group_74 + process $group_60 assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $109 + assign \alu_l_r_alu$next $100 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 @@ -62377,86 +45913,76 @@ module \branch0 sync posedge \coresync_clk update \alu_l_r_alu \alu_l_r_alu$next end - process $group_75 + process $group_61 assign \alu_l_s_alu 1'0 assign \alu_l_s_alu \all_rd_pulse sync init end - process $group_76 + process $group_62 assign \cu_busy_o 1'0 assign \cu_busy_o \opc_l_q_opc sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $103 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $111 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - cell $not $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \oper_r__imm_data__imm_ok - connect \Y $113 + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $102 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $105 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $111 - connect \B { 1'1 $113 1'1 } - connect \Y $115 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $102 + connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 } + connect \Y $104 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $not $118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $107 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $117 + connect \Y $106 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 6 $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $109 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $115 - connect \B $117 - connect \Y $119 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $104 + connect \B $106 + connect \Y $108 end - process $group_77 - assign \cu_rd__rel_o 3'000 - assign \cu_rd__rel_o $119 + process $group_63 + assign \cu_rd__rel_o 6'000000 + assign \cu_rd__rel_o $108 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -62464,12 +45990,12 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $121 + connect \Y $110 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -62477,12 +46003,12 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $123 + connect \Y $112 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -62490,43 +46016,82 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $125 + connect \Y $114 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 3 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $117 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $116 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $118 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $120 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 6 $122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \req_l_q_req - connect \B { $121 $123 $125 } - connect \Y $127 + connect \B { $110 $112 $114 $116 $118 $120 } + connect \Y $122 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 3 $129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 6 $124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $125 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $127 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $122 connect \B \cu_wrmask_o - connect \Y $129 + connect \Y $124 end - process $group_78 - assign \cu_wr__rel_o 3'000 - assign \cu_wr__rel_o $129 + process $group_64 + assign \cu_wr__rel_o 6'000000 + assign \cu_wr__rel_o $124 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -62534,22 +46099,22 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $131 + connect \Y $126 end - process $group_79 + process $group_65 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $131 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $126 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 - assign \dest1_o { \data_r0__fast1_ok \data_r0__fast1 } [63:0] + assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -62557,22 +46122,22 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $133 + connect \Y $128 end - process $group_80 + process $group_66 assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $133 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $128 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 - assign \dest2_o { \data_r1__fast2_ok \data_r1__fast2 } [63:0] + assign \dest2_o { \data_r1__spr1_ok \data_r1__spr1 } [63:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -62580,15 +46145,84 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $135 + connect \Y $130 end - process $group_81 + process $group_67 assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $135 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $130 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" case 1'1 - assign \dest3_o { \data_r2__nia_ok \data_r2__nia } [63:0] + assign \dest3_o { \data_r2__fast1_ok \data_r2__fast1 } [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $132 + end + process $group_68 + assign \dest4_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $132 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [4] + connect \B \cu_busy_o + connect \Y $134 + end + process $group_69 + assign \dest5_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $134 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest5_o { \data_r4__xer_ov_ok \data_r4__xer_ov } [1:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [5] + connect \B \cu_busy_o + connect \Y $136 + end + process $group_70 + assign \dest6_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $136 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest6_o { \data_r5__xer_ca_ok \data_r5__xer_ca } [1:0] end sync init end @@ -62596,8 +46230,8 @@ module \branch0 connect \cu_shadown_i 1'1 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.p" -module \p$30 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.p" +module \p$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -62624,8 +46258,8 @@ module \p$30 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.n" -module \n$31 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.n" +module \n$72 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -62652,8 +46286,8 @@ module \n$31 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.p" -module \p$33 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.p" +module \p$73 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -62680,8 +46314,8 @@ module \p$33 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.n" -module \n$34 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.n" +module \n$74 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -62708,8 +46342,8 @@ module \n$34 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.main" -module \main$35 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.input" +module \input$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -62786,7 +46420,7 @@ module \main$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \trap_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -62800,29 +46434,51 @@ module \main$35 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \trap_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \trap_op__insn + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \trap_op__msr + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \trap_op__cia + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \trap_op__is_32bit + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 input 7 \trap_op__traptype + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 8 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \ra + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \rb + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \fast1 + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 12 \fast2 + wire width 1 input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 13 \muxid$1 + wire width 2 output 22 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -62897,7 +46553,7 @@ module \main$35 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 14 \trap_op__insn_type$2 + wire width 7 output 23 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -62911,984 +46567,898 @@ module \main$35 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 15 \trap_op__fn_unit$3 + wire width 11 output 24 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 16 \trap_op__insn$4 + wire width 64 output 25 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 17 \trap_op__msr$5 + wire width 1 output 26 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 18 \trap_op__cia$6 + wire width 1 output 27 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 19 \trap_op__is_32bit$7 + wire width 1 output 28 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 output 20 \trap_op__traptype$8 + wire width 1 output 29 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 21 \trap_op__trapaddr$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 25 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 26 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 27 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 28 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 29 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 30 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 31 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133" - wire width 5 \to - process $group_0 - assign \to 5'00000 - assign \to { \trap_op__insn [25] \trap_op__insn [24] \trap_op__insn [23] \trap_op__insn [22] \trap_op__insn [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137" - wire width 64 \a_s - process $group_1 - assign \a_s 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch { \trap_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - case 1'1 - assign \a_s { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" - case - assign \a_s \ra - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" - wire width 64 \b_s - process $group_2 - assign \b_s 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch { \trap_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - case 1'1 - assign \b_s { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" - case - assign \b_s \rb - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:140" + wire width 1 output 30 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 64 $12 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $24 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \ra [31:0] - connect \Y $12 + connect \A \ra + connect \Y $23 end - process $group_3 + process $group_0 assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch { \trap_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch { \logical_op__invert_in } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" case 1'1 - assign \a $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" + assign \a $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:29" case assign \a \ra end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" + process $group_1 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \a + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 64 $14 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \rb [31:0] - connect \Y $14 + process $group_2 + assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \b \rb + sync init + end + process $group_3 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \b + assign \rb$21 \rb + sync init end process $group_4 - assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch { \trap_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + assign \xer_so$22 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" + switch { \logical_op__oe__oe_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" case 1'1 - assign \b $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" - case - assign \b \rb + assign \xer_so$22 \xer_so end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156" - wire width 1 \lt_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" - cell $lt $17 - parameter \A_SIGNED 1 - parameter \A_WIDTH 64 - parameter \B_SIGNED 1 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a_s - connect \B \b_s - connect \Y $16 - end process $group_5 - assign \lt_s 1'0 - assign \lt_s $16 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" - wire width 1 \gt_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $gt $19 - parameter \A_SIGNED 1 - parameter \A_WIDTH 64 - parameter \B_SIGNED 1 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a_s - connect \B \b_s - connect \Y $18 - end process $group_6 - assign \gt_s 1'0 - assign \gt_s $18 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" - wire width 1 \lt_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $lt $21 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.setup_stage" +module \setup_stage + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 26 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 41 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 42 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 43 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 44 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 45 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 46 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" + wire width 128 output 47 \dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" + wire width 64 output 48 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" + wire width 2 output 49 \operation + wire width 1 $verilog_initial_trigger + process $group_0 + assign \operation 2'00 + assign \operation 2'01 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $mux $22 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \logical_op__is_32bit + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $and $24 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 64 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $20 + connect \A $21 + connect \B \logical_op__is_signed + connect \Y $23 end - process $group_7 - assign \lt_u 1'0 - assign \lt_u $20 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" - wire width 1 \gt_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $gt $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $22 - end - process $group_8 - assign \gt_u 1'0 - assign \gt_u $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" - wire width 1 \equal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $eq $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $24 - end - process $group_9 - assign \equal 1'0 - assign \equal $24 + process $group_1 + assign \dividend_neg 1'0 + assign \dividend_neg $23 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:170" - wire width 5 \trap_bits - process $group_10 - assign \trap_bits 5'00000 - assign \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $mux $26 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \logical_op__is_32bit + connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" - wire width 1 \should_trap - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - wire width 5 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \trap_bits - connect \B \to - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $reduce_or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $reduce_or $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \trap_op__traptype - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $or $33 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $26 - connect \B $30 - connect \Y $32 + connect \A $25 + connect \B \logical_op__is_signed + connect \Y $27 end - process $group_11 - assign \should_trap 1'0 - assign \should_trap $32 + process $group_2 + assign \divisor_neg 1'0 + assign \divisor_neg $27 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - wire width 64 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - wire width 20 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - cell $sshl $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" + wire width 64 \abs_dor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + wire width 65 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + wire width 65 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $neg $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 20 - connect \A \trap_op__trapaddr - connect \B 3'100 - connect \Y $35 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - cell $pos $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 65 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \Y_WIDTH 64 - connect \A $35 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + wire width 65 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $mux $35 + parameter \WIDTH 65 + connect \A $32 + connect \B $30 + connect \S \divisor_neg connect \Y $34 end - process $group_12 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \nia $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \nia { { { } \fast1 [63:2] } 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \nia 64'0000000000000000000000000000000000000000000000000000110000000000 - end + connect $29 $34 + process $group_3 + assign \abs_dor 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \abs_dor $29 [63:0] sync init end - process $group_13 - assign \nia_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \nia_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \nia_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \nia_ok 1'1 - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" + wire width 64 \abs_dend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + wire width 65 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + wire width 65 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $neg $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:301" - wire width 65 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:301" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 65 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:301" - cell $add $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $40 parameter \A_SIGNED 0 parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 parameter \Y_WIDTH 65 - connect \A \trap_op__cia - connect \B 3'100 + connect \A \ra connect \Y $39 end - connect $38 $39 - process $group_14 - assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \fast1$10 \trap_op__cia - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \fast1$10 $38 [63:0] - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + wire width 65 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $mux $42 + parameter \WIDTH 65 + connect \A $39 + connect \B $37 + connect \S \dividend_neg + connect \Y $41 end - process $group_15 - assign \fast1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \fast1_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \fast1_ok 1'1 - end + connect $36 $41 + process $group_4 + assign \abs_dend 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \abs_dend $36 [63:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $eq $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + cell $ge $44 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 64 parameter \Y_WIDTH 1 - connect \A \trap_op__traptype - connect \B 1'0 - connect \Y $41 + connect \A \abs_dend + connect \B \abs_dor + connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - wire width 5 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - cell $and $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $eq $46 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 5 - connect \A \trap_op__traptype - connect \B 2'10 - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A $44 - connect \Y $43 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - wire width 5 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - cell $and $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $and $48 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \trap_op__traptype - connect \B 1'1 - connect \Y $48 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 parameter \Y_WIDTH 1 - connect \A $48 + connect \A $43 + connect \B $45 connect \Y $47 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - wire width 5 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - cell $and $53 + process $group_5 + assign \dive_abs_ov64 1'0 + assign \dive_abs_ov64 $47 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" + cell $ge $50 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A \trap_op__traptype - connect \B 4'1000 - connect \Y $52 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \abs_dend [31:0] + connect \B \abs_dor [31:0] + connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $eq $52 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A $52 + connect \A \logical_op__insn_type + connect \B 7'0011110 connect \Y $51 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" - wire width 5 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" - cell $and $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $and $54 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \trap_op__traptype - connect \B 5'10000 - connect \Y $56 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $56 - connect \Y $55 + connect \A $49 + connect \B $51 + connect \Y $53 end - process $group_16 - assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2$11 [15:0] \trap_op__msr [15:0] - assign \fast2$11 [26:22] \trap_op__msr [26:22] - assign \fast2$11 [63:31] \trap_op__msr [63:31] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - switch { $41 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - case 1'1 - assign \fast2$11 [17] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - switch { $43 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - case 1'1 - assign \fast2$11 [18] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - switch { $47 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - case 1'1 - assign \fast2$11 [20] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - switch { $51 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - case 1'1 - assign \fast2$11 [16] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:198" - case 1'1 - assign \fast2$11 [19] 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2$11 [15:0] \trap_op__msr [15:0] - assign \fast2$11 [26:22] \trap_op__msr [26:22] - assign \fast2$11 [63:31] \trap_op__msr [63:31] - end + process $group_6 + assign \dive_abs_ov32 1'0 + assign \dive_abs_ov32 $53 sync init end - process $group_17 - assign \fast2_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \fast2_ok 1'1 - assign \fast2_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \fast2_ok 1'1 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + wire width 32 $55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $56 + parameter \WIDTH 32 + connect \A \abs_dor [63:32] + connect \B 32'00000000000000000000000000000000 + connect \S \logical_op__is_32bit + connect \Y $55 + end + process $group_7 + assign \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand [31:0] \abs_dor [31:0] + assign \divisor_radicand [63:32] $55 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 65 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" + cell $eq $58 parameter \A_SIGNED 0 parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \trap_op__msr + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $57 + end + process $group_8 + assign \div_by_zero 1'0 + assign \div_by_zero $57 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + wire width 32 $59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $60 + parameter \WIDTH 32 + connect \A \abs_dend [63:32] + connect \B 32'00000000000000000000000000000000 + connect \S \logical_op__is_32bit connect \Y $59 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + wire width 128 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + wire width 95 $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $sshl $63 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \trap_op__insn [22] \trap_op__insn [21] } + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 95 + connect \A \abs_dend [31:0] + connect \B 6'100000 + connect \Y $62 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 95 + parameter \Y_WIDTH 128 + connect \A $62 connect \Y $61 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" - cell $eq $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + wire width 191 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + wire width 191 $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + cell $sshl $67 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \trap_op__insn_type - connect \B 7'1001000 - connect \Y $63 + parameter \Y_WIDTH 191 + connect \A \abs_dend + connect \B 7'1000000 + connect \Y $66 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - cell $eq $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [34:32] - connect \B 3'010 - connect \Y $65 + connect $65 $66 + process $group_9 + assign \dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:74" + attribute \nmigen.decoding "OP_DIV/29|OP_MOD/47" + case 7'0011101, 7'0101111 + assign \dividend [31:0] \abs_dend [31:0] + assign \dividend [63:32] $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:77" + attribute \nmigen.decoding "OP_DIVE/30" + case 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" + switch { \logical_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" + case 1'1 + assign \dividend $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:80" + case + assign \dividend $65 [127:0] + end + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - cell $eq $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ra [34:32] - connect \B 3'000 - connect \Y $67 + process $group_10 + assign \xer_so$20 1'0 + assign \xer_so$20 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - cell $and $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $65 - connect \B $67 - connect \Y $69 + process $group_11 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $not $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [60] - connect \Y $71 + process $group_12 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:281" - cell $eq $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [34:32] - connect \B 3'010 - connect \Y $73 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.core_setup_stage.core" +module \core$76 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" + wire width 128 input 0 \dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" + wire width 64 input 1 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 3 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 4 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 5 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 6 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 7 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 8 \compare_rhs + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $eq $76 + wire width 1 $verilog_initial_trigger + process $group_1 + assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_2 + assign \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:265" + wire width 192 \lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 255 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 255 $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + cell $sshl $5 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 128 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \fast2 [34:32] - connect \B 3'000 - connect \Y $75 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 255 + connect \A \dividend + connect \B 7'1000000 + connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $and $78 + connect $3 $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:272" + wire width 319 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:272" + wire width 319 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:272" + cell $sshl $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $73 - connect \B $75 - connect \Y $77 - end - process $group_18 - assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \msr_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \msr \trap_op__msr - assign \msr [63] 1'1 - assign \msr [15] 1'0 - assign \msr [14] 1'0 - assign \msr [5] 1'0 - assign \msr [4] 1'0 - assign \msr [1] 1'0 - assign \msr [0] 1'1 - assign \msr [11] 1'0 - assign \msr [8] 1'0 - assign \msr [23] 1'0 - assign \msr [32] 1'0 - assign \msr [25] 1'0 - assign \msr [13] 1'0 - assign \msr [3] 1'0 - assign \msr [10] 1'0 - assign \msr [9] 1'0 - assign \msr [58] 1'0 - assign \msr_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - assign { \msr_ok \msr } $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:212" - switch { $61 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:212" - case 1'1 - assign \msr [1] \ra [1] - assign \msr [15] \ra [15] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:216" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" - switch { $63 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:219" - case 1'1 - assign \msr [11:1] \ra [11:1] - assign \msr [59:13] \ra [59:13] - assign \msr [63:61] \ra [63:61] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:226" - case 1'1 - assign \msr [34:32] \trap_op__msr [34:32] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:229" - case - assign \msr [11:1] \ra [11:1] - assign \msr [31:13] \ra [31:13] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" - switch { \msr [14] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" - case 1'1 - assign \msr [15] 1'1 - assign \msr [5] 1'1 - assign \msr [4] 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - case 1'1 - assign \msr [60] \trap_op__msr [60] - assign \msr [12] \trap_op__msr [12] - end - switch { } - case - assign \msr_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \msr [15:0] \fast2 [15:0] - assign \msr [26:22] \fast2 [26:22] - assign \msr [63:31] \fast2 [63:31] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:269" - switch { \trap_op__msr [60] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:269" - case 1'1 - assign { \msr_ok \msr } [12] \fast2 [12] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:271" - case - assign { \msr_ok \msr } [12] \trap_op__msr [12] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" - switch { \msr [14] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" - case 1'1 - assign \msr [15] 1'1 - assign \msr [5] 1'1 - assign \msr [4] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - case 1'1 - assign \msr [34:32] \trap_op__msr [34:32] - end - switch { } - case - assign \msr_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \msr \trap_op__msr - assign \msr [63] 1'1 - assign \msr [15] 1'0 - assign \msr [14] 1'0 - assign \msr [5] 1'0 - assign \msr [4] 1'0 - assign \msr [1] 1'0 - assign \msr [0] 1'1 - assign \msr [11] 1'0 - assign \msr [8] 1'0 - assign \msr [23] 1'0 - assign \msr [32] 1'0 - assign \msr [25] 1'0 - assign \msr [13] 1'0 - assign \msr [3] 1'0 - assign \msr [10] 1'0 - assign \msr [9] 1'0 - assign \msr [58] 1'0 - assign \msr_ok 1'1 - end - sync init + parameter \B_WIDTH 8 + parameter \Y_WIDTH 319 + connect \A \divisor_radicand + connect \B 8'10000000 + connect \Y $7 end - process $group_20 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - assign \o \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 + connect $6 $7 + process $group_3 + assign \lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \lhs $3 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \lhs $6 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:273" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end sync init end - process $group_21 - assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:208" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:250" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:258" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:290" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - end + process $group_4 + assign \compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs \lhs sync init end - process $group_22 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + process $group_5 + assign \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $verilog_initial_trigger $verilog_initial_trigger sync init end - process $group_23 - assign \trap_op__insn_type$2 7'0000000 - assign \trap_op__fn_unit$3 11'00000000000 - assign \trap_op__insn$4 32'00000000000000000000000000000000 - assign \trap_op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__is_32bit$7 1'0 - assign \trap_op__traptype$8 5'00000 - assign \trap_op__trapaddr$9 13'0000000000000 - assign { \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + process $group_6 + assign \operation$2 2'00 + assign \operation$2 \operation sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe" -module \pipe$32 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.core_setup_stage" +module \core_setup_stage attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -63963,7 +47533,7 @@ module \pipe$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \trap_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -63977,41 +47547,73 @@ module \pipe$32 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \trap_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \trap_op__insn + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \trap_op__msr + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \trap_op__cia + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \trap_op__is_32bit + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 input 11 \trap_op__traptype + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 12 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 15 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 16 \fast2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 17 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 18 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 19 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" + wire width 128 input 27 \dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" + wire width 64 input 28 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" + wire width 2 input 29 \operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 30 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" attribute \enum_value_0000101 "OP_ATTN" attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" @@ -64080,9 +47682,7 @@ module \pipe$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 20 \trap_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$2$next + wire width 7 output 31 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -64096,83 +47696,228 @@ module \pipe$32 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 21 \trap_op__fn_unit$3 + wire width 11 output 32 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \trap_op__fn_unit$3$next + wire width 64 output 33 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \trap_op__insn$4 + wire width 1 output 34 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$4$next + wire width 1 output 35 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 23 \trap_op__msr$5 + wire width 1 output 36 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$5$next + wire width 1 output 37 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \trap_op__cia$6 + wire width 1 output 38 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$6$next + wire width 1 output 39 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \trap_op__is_32bit$7 + wire width 1 output 40 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \trap_op__is_32bit$7$next + wire width 2 output 41 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 output 26 \trap_op__traptype$8 + wire width 1 output 42 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \trap_op__traptype$8$next + wire width 1 output 43 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 27 \trap_op__trapaddr$9 + wire width 1 output 44 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 28 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 29 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 30 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 31 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 32 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 33 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 34 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 35 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \nia_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 36 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 37 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \msr_ok$next - cell \p$33 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o + wire width 1 output 45 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 47 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 48 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 49 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 50 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 51 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 52 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 53 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 54 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 55 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 56 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 57 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 58 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 59 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 60 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 61 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 62 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" + wire width 128 \core_dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + cell \core$76 \core + connect \dividend \core_dividend + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \divisor_radicand$1 \core_divisor_radicand$30 + connect \operation$2 \core_operation$31 + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs end - cell \n$34 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_dividend \dividend + sync init + end + process $group_28 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_29 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_30 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$30 + sync init + end + process $group_31 + assign \operation$29 2'00 + assign \operation$29 \core_operation$31 + sync init end + process $group_32 + assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root \core_quotient_root + sync init + end + process $group_33 + assign \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand \core_root_times_radicand + sync init + end + process $group_34 + assign \compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs \core_compare_lhs + sync init + end + process $group_35 + assign \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs \core_compare_rhs + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start" +module \pipe_start + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 3 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -64247,7 +47992,9 @@ module \pipe$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__insn_type + wire width 7 output 5 \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -64261,29 +48008,139 @@ module \pipe$32 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_trap_op__fn_unit + wire width 11 output 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn + wire width 11 \logical_op__fn_unit$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__msr + wire width 64 output 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia + wire width 64 \logical_op__imm_data__imm$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_trap_op__is_32bit + wire width 1 output 8 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \main_trap_op__traptype + wire width 1 \logical_op__imm_data__imm_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__trapaddr + wire width 1 output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra + wire width 64 output 23 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb + wire width 64 \ra$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast1 + wire width 64 output 24 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_fast2 + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 37 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 38 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$12 + wire width 2 input 39 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -64358,7 +48215,7 @@ module \pipe$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__insn_type$13 + wire width 7 input 40 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -64372,151 +48229,59 @@ module \pipe$32 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_trap_op__fn_unit$14 + wire width 11 input 41 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn$15 + wire width 64 input 42 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__msr$16 + wire width 1 input 43 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia$17 + wire width 1 input 44 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_trap_op__is_32bit$18 + wire width 1 input 45 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \main_trap_op__traptype$19 + wire width 1 input 46 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__trapaddr$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast1$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast2$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_msr_ok - cell \main$35 \main - connect \muxid \main_muxid - connect \trap_op__insn_type \main_trap_op__insn_type - connect \trap_op__fn_unit \main_trap_op__fn_unit - connect \trap_op__insn \main_trap_op__insn - connect \trap_op__msr \main_trap_op__msr - connect \trap_op__cia \main_trap_op__cia - connect \trap_op__is_32bit \main_trap_op__is_32bit - connect \trap_op__traptype \main_trap_op__traptype - connect \trap_op__trapaddr \main_trap_op__trapaddr - connect \ra \main_ra - connect \rb \main_rb - connect \fast1 \main_fast1 - connect \fast2 \main_fast2 - connect \muxid$1 \main_muxid$12 - connect \trap_op__insn_type$2 \main_trap_op__insn_type$13 - connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$14 - connect \trap_op__insn$4 \main_trap_op__insn$15 - connect \trap_op__msr$5 \main_trap_op__msr$16 - connect \trap_op__cia$6 \main_trap_op__cia$17 - connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$18 - connect \trap_op__traptype$8 \main_trap_op__traptype$19 - connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$20 - connect \o \main_o - connect \o_ok \main_o_ok - connect \fast1$10 \main_fast1$21 - connect \fast1_ok \main_fast1_ok - connect \fast2$11 \main_fast2$22 - connect \fast2_ok \main_fast2_ok - connect \nia \main_nia - connect \nia_ok \main_nia_ok - connect \msr \main_msr - connect \msr_ok \main_msr_ok - end - process $group_0 - assign \main_muxid 2'00 - assign \main_muxid \muxid - sync init - end - process $group_1 - assign \main_trap_op__insn_type 7'0000000 - assign \main_trap_op__fn_unit 11'00000000000 - assign \main_trap_op__insn 32'00000000000000000000000000000000 - assign \main_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_trap_op__is_32bit 1'0 - assign \main_trap_op__traptype 5'00000 - assign \main_trap_op__trapaddr 13'0000000000000 - assign { \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - sync init - end - process $group_9 - assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \ra - sync init - end - process $group_10 - assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \rb - sync init - end - process $group_11 - assign \main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_fast1 \fast1 - sync init - end - process $group_12 - assign \main_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_fast2 \fast2 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$23 - process $group_13 - assign \p_valid_i$23 1'0 - assign \p_valid_i$23 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_14 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$23 - connect \B \p_ready_o - connect \Y $24 + wire width 1 input 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 49 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 60 \xer_so$22 + cell \p$73 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_15 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $24 - sync init + cell \n$74 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$26 - process $group_16 - assign \muxid$26 2'00 - assign \muxid$26 \main_muxid$12 - sync init - end + wire width 2 \input_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -64591,7 +48356,7 @@ module \pipe$32 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$27 + wire width 7 \input_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -64605,321 +48370,51 @@ module \pipe$32 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \trap_op__fn_unit$28 + wire width 11 \input_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$29 + wire width 64 \input_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$30 + wire width 1 \input_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$31 + wire width 1 \input_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \trap_op__is_32bit$32 + wire width 1 \input_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \trap_op__traptype$33 + wire width 1 \input_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$34 - process $group_17 - assign \trap_op__insn_type$27 7'0000000 - assign \trap_op__fn_unit$28 11'00000000000 - assign \trap_op__insn$29 32'00000000000000000000000000000000 - assign \trap_op__msr$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__cia$31 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__is_32bit$32 1'0 - assign \trap_op__traptype$33 5'00000 - assign \trap_op__trapaddr$34 13'0000000000000 - assign { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } { \main_trap_op__trapaddr$20 \main_trap_op__traptype$19 \main_trap_op__is_32bit$18 \main_trap_op__cia$17 \main_trap_op__msr$16 \main_trap_op__insn$15 \main_trap_op__fn_unit$14 \main_trap_op__insn_type$13 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$36 - process $group_25 - assign \o$35 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$36 1'0 - assign { \o_ok$36 \o$35 } { \main_o_ok \main_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast1_ok$38 - process $group_27 - assign \fast1$37 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok$38 1'0 - assign { \fast1_ok$38 \fast1$37 } { \main_fast1_ok \main_fast1$21 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast2_ok$40 - process $group_29 - assign \fast2$39 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2_ok$40 1'0 - assign { \fast2_ok$40 \fast2$39 } { \main_fast2_ok \main_fast2$22 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \nia$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \nia_ok$42 - process $group_31 - assign \nia$41 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia_ok$42 1'0 - assign { \nia_ok$42 \nia$41 } { \main_nia_ok \main_nia } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \msr$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \msr_ok$44 - process $group_33 - assign \msr$43 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \msr_ok$44 1'0 - assign { \msr_ok$44 \msr$43 } { \main_msr_ok \main_msr } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_35 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_36 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$26 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_37 - assign \trap_op__insn_type$2$next \trap_op__insn_type$2 - assign \trap_op__fn_unit$3$next \trap_op__fn_unit$3 - assign \trap_op__insn$4$next \trap_op__insn$4 - assign \trap_op__msr$5$next \trap_op__msr$5 - assign \trap_op__cia$6$next \trap_op__cia$6 - assign \trap_op__is_32bit$7$next \trap_op__is_32bit$7 - assign \trap_op__traptype$8$next \trap_op__traptype$8 - assign \trap_op__trapaddr$9$next \trap_op__trapaddr$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \trap_op__trapaddr$9$next \trap_op__traptype$8$next \trap_op__is_32bit$7$next \trap_op__cia$6$next \trap_op__msr$5$next \trap_op__insn$4$next \trap_op__fn_unit$3$next \trap_op__insn_type$2$next } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \trap_op__trapaddr$9$next \trap_op__traptype$8$next \trap_op__is_32bit$7$next \trap_op__cia$6$next \trap_op__msr$5$next \trap_op__insn$4$next \trap_op__fn_unit$3$next \trap_op__insn_type$2$next } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } - end - sync init - update \trap_op__insn_type$2 7'0000000 - update \trap_op__fn_unit$3 11'00000000000 - update \trap_op__insn$4 32'00000000000000000000000000000000 - update \trap_op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000 - update \trap_op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000 - update \trap_op__is_32bit$7 1'0 - update \trap_op__traptype$8 5'00000 - update \trap_op__trapaddr$9 13'0000000000000 - sync posedge \coresync_clk - update \trap_op__insn_type$2 \trap_op__insn_type$2$next - update \trap_op__fn_unit$3 \trap_op__fn_unit$3$next - update \trap_op__insn$4 \trap_op__insn$4$next - update \trap_op__msr$5 \trap_op__msr$5$next - update \trap_op__cia$6 \trap_op__cia$6$next - update \trap_op__is_32bit$7 \trap_op__is_32bit$7$next - update \trap_op__traptype$8 \trap_op__traptype$8$next - update \trap_op__trapaddr$9 \trap_op__trapaddr$9$next - end - process $group_45 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$36 \o$35 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$36 \o$35 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_47 - assign \fast1$10$next \fast1$10 - assign \fast1_ok$next \fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$38 \fast1$37 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$38 \fast1$37 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \fast1_ok$next 1'0 - end - sync init - update \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 - update \fast1_ok 1'0 - sync posedge \coresync_clk - update \fast1$10 \fast1$10$next - update \fast1_ok \fast1_ok$next - end - process $group_49 - assign \fast2$11$next \fast2$11 - assign \fast2_ok$next \fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$40 \fast2$39 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$40 \fast2$39 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \fast2_ok$next 1'0 - end - sync init - update \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - update \fast2_ok 1'0 - sync posedge \coresync_clk - update \fast2$11 \fast2$11$next - update \fast2_ok \fast2_ok$next - end - process $group_51 - assign \nia$next \nia - assign \nia_ok$next \nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \nia_ok$next \nia$next } { \nia_ok$42 \nia$41 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \nia_ok$next \nia$next } { \nia_ok$42 \nia$41 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \nia_ok$next 1'0 - end - sync init - update \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \nia_ok 1'0 - sync posedge \coresync_clk - update \nia \nia$next - update \nia_ok \nia_ok$next - end - process $group_53 - assign \msr$next \msr - assign \msr_ok$next \msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \msr_ok$next \msr$next } { \msr_ok$44 \msr$43 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \msr_ok$next \msr$next } { \msr_ok$44 \msr$43 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \msr_ok$next 1'0 - end - sync init - update \msr 64'0000000000000000000000000000000000000000000000000000000000000000 - update \msr_ok 1'0 - sync posedge \coresync_clk - update \msr \msr$next - update \msr_ok \msr_ok$next - end - process $group_55 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_56 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0" -module \alu_trap0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \msr_ok - attribute \src "simple/issuer.py:89" - wire width 1 input 6 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 8 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 9 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 10 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 11 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 12 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 13 \msr + wire width 1 \input_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \input_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$23 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -64994,7 +48489,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 14 \trap_op__insn_type + wire width 7 \input_logical_op__insn_type$24 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -65008,45 +48503,97 @@ module \alu_trap0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 15 \trap_op__fn_unit + wire width 11 \input_logical_op__fn_unit$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \trap_op__insn + wire width 64 \input_logical_op__imm_data__imm$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 17 \trap_op__msr + wire width 1 \input_logical_op__imm_data__imm_ok$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 18 \trap_op__cia + wire width 1 \input_logical_op__rc__rc$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \trap_op__is_32bit + wire width 1 \input_logical_op__rc__rc_ok$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 input 20 \trap_op__traptype + wire width 1 \input_logical_op__oe__oe$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 21 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 22 \ra + wire width 1 \input_logical_op__oe__oe_ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__zero_a$33 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_logical_op__is_signed$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \rb + wire width 64 \input_ra$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \fast1$1 + wire width 64 \input_rb$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 25 \fast2$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 26 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 27 \p_ready_o - cell \p$30 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$31 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + wire width 1 \input_xer_so$44 + cell \input$75 \input + connect \muxid \input_muxid + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__imm_data__imm \input_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc_ok \input_logical_op__rc__rc_ok + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe_ok \input_logical_op__oe__oe_ok + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__insn \input_logical_op__insn + connect \ra \input_ra + connect \rb \input_rb + connect \xer_so \input_xer_so + connect \muxid$1 \input_muxid$23 + connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 + connect \logical_op__imm_data__imm$4 \input_logical_op__imm_data__imm$26 + connect \logical_op__imm_data__imm_ok$5 \input_logical_op__imm_data__imm_ok$27 + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 + connect \logical_op__rc__rc_ok$7 \input_logical_op__rc__rc_ok$29 + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 + connect \logical_op__oe__oe_ok$9 \input_logical_op__oe__oe_ok$31 + connect \logical_op__invert_in$10 \input_logical_op__invert_in$32 + connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 + connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 + connect \logical_op__invert_out$13 \input_logical_op__invert_out$35 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 + connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38 + connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 + connect \logical_op__data_len$18 \input_logical_op__data_len$40 + connect \logical_op__insn$19 \input_logical_op__insn$41 + connect \ra$20 \input_ra$42 + connect \rb$21 \input_rb$43 + connect \xer_so$22 \input_xer_so$44 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid + wire width 2 \setup_stage_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -65121,7 +48668,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__insn_type + wire width 7 \setup_stage_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -65135,33 +48682,51 @@ module \alu_trap0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_trap_op__fn_unit + wire width 11 \setup_stage_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_trap_op__insn + wire width 64 \setup_stage_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__msr + wire width 1 \setup_stage_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__cia + wire width 1 \setup_stage_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_trap_op__is_32bit + wire width 1 \setup_stage_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \pipe_trap_op__traptype + wire width 1 \setup_stage_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra + wire width 1 \setup_stage_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \setup_stage_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \setup_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \setup_stage_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb + wire width 64 \setup_stage_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast1 + wire width 64 \setup_stage_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_n_ready_i + wire width 1 \setup_stage_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 + wire width 2 \setup_stage_muxid$45 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -65236,7 +48801,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__insn_type$4 + wire width 7 \setup_stage_logical_op__insn_type$46 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -65250,145 +48815,264 @@ module \alu_trap0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_trap_op__fn_unit$5 + wire width 11 \setup_stage_logical_op__fn_unit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_trap_op__insn$6 + wire width 64 \setup_stage_logical_op__imm_data__imm$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__msr$7 + wire width 1 \setup_stage_logical_op__imm_data__imm_ok$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__cia$8 + wire width 1 \setup_stage_logical_op__rc__rc$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_trap_op__is_32bit$9 + wire width 1 \setup_stage_logical_op__rc__rc_ok$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \pipe_trap_op__traptype$10 + wire width 1 \setup_stage_logical_op__oe__oe$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_trap_op__trapaddr$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast2$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_msr_ok - cell \pipe$32 \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_p_valid_i - connect \p_ready_o \pipe_p_ready_o - connect \muxid \pipe_muxid - connect \trap_op__insn_type \pipe_trap_op__insn_type - connect \trap_op__fn_unit \pipe_trap_op__fn_unit - connect \trap_op__insn \pipe_trap_op__insn - connect \trap_op__msr \pipe_trap_op__msr - connect \trap_op__cia \pipe_trap_op__cia - connect \trap_op__is_32bit \pipe_trap_op__is_32bit - connect \trap_op__traptype \pipe_trap_op__traptype - connect \trap_op__trapaddr \pipe_trap_op__trapaddr - connect \ra \pipe_ra - connect \rb \pipe_rb - connect \fast1 \pipe_fast1 - connect \fast2 \pipe_fast2 - connect \n_valid_o \pipe_n_valid_o - connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$3 - connect \trap_op__insn_type$2 \pipe_trap_op__insn_type$4 - connect \trap_op__fn_unit$3 \pipe_trap_op__fn_unit$5 - connect \trap_op__insn$4 \pipe_trap_op__insn$6 - connect \trap_op__msr$5 \pipe_trap_op__msr$7 - connect \trap_op__cia$6 \pipe_trap_op__cia$8 - connect \trap_op__is_32bit$7 \pipe_trap_op__is_32bit$9 - connect \trap_op__traptype$8 \pipe_trap_op__traptype$10 - connect \trap_op__trapaddr$9 \pipe_trap_op__trapaddr$11 - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \fast1$10 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \fast2$11 \pipe_fast2$13 - connect \fast2_ok \pipe_fast2_ok - connect \nia \pipe_nia - connect \nia_ok \pipe_nia_ok - connect \msr \pipe_msr - connect \msr_ok \pipe_msr_ok - end - process $group_0 - assign \pipe_p_valid_i 1'0 - assign \pipe_p_valid_i \p_valid_i - sync init - end - process $group_1 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_p_ready_o - sync init + wire width 1 \setup_stage_logical_op__oe__oe_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__zero_a$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \setup_stage_logical_op__input_carry$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__invert_out$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__write_cr0$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \setup_stage_logical_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \setup_stage_logical_op__data_len$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \setup_stage_logical_op__insn$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \setup_stage_xer_so$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \setup_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \setup_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \setup_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \setup_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \setup_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" + wire width 128 \setup_stage_dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" + wire width 64 \setup_stage_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" + wire width 2 \setup_stage_operation + cell \setup_stage \setup_stage + connect \muxid \setup_stage_muxid + connect \logical_op__insn_type \setup_stage_logical_op__insn_type + connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit + connect \logical_op__imm_data__imm \setup_stage_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \setup_stage_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc + connect \logical_op__rc__rc_ok \setup_stage_logical_op__rc__rc_ok + connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe + connect \logical_op__oe__oe_ok \setup_stage_logical_op__oe__oe_ok + connect \logical_op__invert_in \setup_stage_logical_op__invert_in + connect \logical_op__zero_a \setup_stage_logical_op__zero_a + connect \logical_op__input_carry \setup_stage_logical_op__input_carry + connect \logical_op__invert_out \setup_stage_logical_op__invert_out + connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 + connect \logical_op__output_carry \setup_stage_logical_op__output_carry + connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit + connect \logical_op__is_signed \setup_stage_logical_op__is_signed + connect \logical_op__data_len \setup_stage_logical_op__data_len + connect \logical_op__insn \setup_stage_logical_op__insn + connect \ra \setup_stage_ra + connect \rb \setup_stage_rb + connect \xer_so \setup_stage_xer_so + connect \muxid$1 \setup_stage_muxid$45 + connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 + connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 + connect \logical_op__imm_data__imm$4 \setup_stage_logical_op__imm_data__imm$48 + connect \logical_op__imm_data__imm_ok$5 \setup_stage_logical_op__imm_data__imm_ok$49 + connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 + connect \logical_op__rc__rc_ok$7 \setup_stage_logical_op__rc__rc_ok$51 + connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 + connect \logical_op__oe__oe_ok$9 \setup_stage_logical_op__oe__oe_ok$53 + connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 + connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 + connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 + connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 + connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 + connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 + connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 + connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 + connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 + connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 + connect \xer_so$20 \setup_stage_xer_so$64 + connect \divisor_neg \setup_stage_divisor_neg + connect \dividend_neg \setup_stage_dividend_neg + connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 + connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 + connect \div_by_zero \setup_stage_div_by_zero + connect \dividend \setup_stage_dividend + connect \divisor_radicand \setup_stage_divisor_radicand + connect \operation \setup_stage_operation end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_2 - assign \pipe_muxid 2'00 - assign \pipe_muxid \muxid - sync init - end - process $group_3 - assign \pipe_trap_op__insn_type 7'0000000 - assign \pipe_trap_op__fn_unit 11'00000000000 - assign \pipe_trap_op__insn 32'00000000000000000000000000000000 - assign \pipe_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_trap_op__is_32bit 1'0 - assign \pipe_trap_op__traptype 5'00000 - assign \pipe_trap_op__trapaddr 13'0000000000000 - assign { \pipe_trap_op__trapaddr \pipe_trap_op__traptype \pipe_trap_op__is_32bit \pipe_trap_op__cia \pipe_trap_op__msr \pipe_trap_op__insn \pipe_trap_op__fn_unit \pipe_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - sync init - end - process $group_11 - assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_ra \ra - sync init - end - process $group_12 - assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_rb \rb - sync init - end - process $group_13 - assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_fast1 \fast1$1 - sync init - end - process $group_14 - assign \pipe_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_fast2 \fast2$2 - sync init - end - process $group_15 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_n_valid_o - sync init - end - process $group_16 - assign \pipe_n_ready_i 1'0 - assign \pipe_n_ready_i \n_ready_i - sync init - end + wire width 2 \core_setup_stage_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_setup_stage_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_setup_stage_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_setup_stage_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_setup_stage_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_setup_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_setup_stage_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_setup_stage_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_setup_stage_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_setup_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_setup_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_setup_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_setup_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_setup_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_setup_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:109" + wire width 128 \core_setup_stage_dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:110" + wire width 64 \core_setup_stage_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:111" + wire width 2 \core_setup_stage_operation attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$14 - process $group_17 - assign \muxid$14 2'00 - assign \muxid$14 \pipe_muxid$3 - sync init - end + wire width 2 \core_setup_stage_muxid$65 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -65463,7 +49147,7 @@ module \alu_trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$15 + wire width 7 \core_setup_stage_logical_op__insn_type$66 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -65477,1083 +49161,1602 @@ module \alu_trap0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \trap_op__fn_unit$16 + wire width 11 \core_setup_stage_logical_op__fn_unit$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$17 + wire width 64 \core_setup_stage_logical_op__imm_data__imm$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$18 + wire width 1 \core_setup_stage_logical_op__imm_data__imm_ok$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$19 + wire width 1 \core_setup_stage_logical_op__rc__rc$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \trap_op__is_32bit$20 + wire width 1 \core_setup_stage_logical_op__rc__rc_ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \trap_op__traptype$21 + wire width 1 \core_setup_stage_logical_op__oe__oe$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$22 - process $group_18 - assign \trap_op__insn_type$15 7'0000000 - assign \trap_op__fn_unit$16 11'00000000000 - assign \trap_op__insn$17 32'00000000000000000000000000000000 - assign \trap_op__msr$18 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__cia$19 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__is_32bit$20 1'0 - assign \trap_op__traptype$21 5'00000 - assign \trap_op__trapaddr$22 13'0000000000000 - assign { \trap_op__trapaddr$22 \trap_op__traptype$21 \trap_op__is_32bit$20 \trap_op__cia$19 \trap_op__msr$18 \trap_op__insn$17 \trap_op__fn_unit$16 \trap_op__insn_type$15 } { \pipe_trap_op__trapaddr$11 \pipe_trap_op__traptype$10 \pipe_trap_op__is_32bit$9 \pipe_trap_op__cia$8 \pipe_trap_op__msr$7 \pipe_trap_op__insn$6 \pipe_trap_op__fn_unit$5 \pipe_trap_op__insn_type$4 } + wire width 1 \core_setup_stage_logical_op__oe__oe_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__invert_in$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__zero_a$75 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_setup_stage_logical_op__input_carry$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__invert_out$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__write_cr0$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__output_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__is_32bit$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_setup_stage_logical_op__is_signed$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_setup_stage_logical_op__data_len$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_setup_stage_logical_op__insn$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_setup_stage_ra$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_setup_stage_rb$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_setup_stage_xer_so$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_setup_stage_divisor_neg$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_setup_stage_dividend_neg$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_setup_stage_dive_abs_ov32$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_setup_stage_dive_abs_ov64$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_setup_stage_div_by_zero$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_setup_stage_divisor_radicand$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_setup_stage_operation$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_setup_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_setup_stage_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_setup_stage_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_setup_stage_compare_rhs + cell \core_setup_stage \core_setup_stage + connect \muxid \core_setup_stage_muxid + connect \logical_op__insn_type \core_setup_stage_logical_op__insn_type + connect \logical_op__fn_unit \core_setup_stage_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_setup_stage_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_setup_stage_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_setup_stage_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_setup_stage_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_setup_stage_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_setup_stage_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_setup_stage_logical_op__invert_in + connect \logical_op__zero_a \core_setup_stage_logical_op__zero_a + connect \logical_op__input_carry \core_setup_stage_logical_op__input_carry + connect \logical_op__invert_out \core_setup_stage_logical_op__invert_out + connect \logical_op__write_cr0 \core_setup_stage_logical_op__write_cr0 + connect \logical_op__output_carry \core_setup_stage_logical_op__output_carry + connect \logical_op__is_32bit \core_setup_stage_logical_op__is_32bit + connect \logical_op__is_signed \core_setup_stage_logical_op__is_signed + connect \logical_op__data_len \core_setup_stage_logical_op__data_len + connect \logical_op__insn \core_setup_stage_logical_op__insn + connect \ra \core_setup_stage_ra + connect \rb \core_setup_stage_rb + connect \xer_so \core_setup_stage_xer_so + connect \divisor_neg \core_setup_stage_divisor_neg + connect \dividend_neg \core_setup_stage_dividend_neg + connect \dive_abs_ov32 \core_setup_stage_dive_abs_ov32 + connect \dive_abs_ov64 \core_setup_stage_dive_abs_ov64 + connect \div_by_zero \core_setup_stage_div_by_zero + connect \dividend \core_setup_stage_dividend + connect \divisor_radicand \core_setup_stage_divisor_radicand + connect \operation \core_setup_stage_operation + connect \muxid$1 \core_setup_stage_muxid$65 + connect \logical_op__insn_type$2 \core_setup_stage_logical_op__insn_type$66 + connect \logical_op__fn_unit$3 \core_setup_stage_logical_op__fn_unit$67 + connect \logical_op__imm_data__imm$4 \core_setup_stage_logical_op__imm_data__imm$68 + connect \logical_op__imm_data__imm_ok$5 \core_setup_stage_logical_op__imm_data__imm_ok$69 + connect \logical_op__rc__rc$6 \core_setup_stage_logical_op__rc__rc$70 + connect \logical_op__rc__rc_ok$7 \core_setup_stage_logical_op__rc__rc_ok$71 + connect \logical_op__oe__oe$8 \core_setup_stage_logical_op__oe__oe$72 + connect \logical_op__oe__oe_ok$9 \core_setup_stage_logical_op__oe__oe_ok$73 + connect \logical_op__invert_in$10 \core_setup_stage_logical_op__invert_in$74 + connect \logical_op__zero_a$11 \core_setup_stage_logical_op__zero_a$75 + connect \logical_op__input_carry$12 \core_setup_stage_logical_op__input_carry$76 + connect \logical_op__invert_out$13 \core_setup_stage_logical_op__invert_out$77 + connect \logical_op__write_cr0$14 \core_setup_stage_logical_op__write_cr0$78 + connect \logical_op__output_carry$15 \core_setup_stage_logical_op__output_carry$79 + connect \logical_op__is_32bit$16 \core_setup_stage_logical_op__is_32bit$80 + connect \logical_op__is_signed$17 \core_setup_stage_logical_op__is_signed$81 + connect \logical_op__data_len$18 \core_setup_stage_logical_op__data_len$82 + connect \logical_op__insn$19 \core_setup_stage_logical_op__insn$83 + connect \ra$20 \core_setup_stage_ra$84 + connect \rb$21 \core_setup_stage_rb$85 + connect \xer_so$22 \core_setup_stage_xer_so$86 + connect \divisor_neg$23 \core_setup_stage_divisor_neg$87 + connect \dividend_neg$24 \core_setup_stage_dividend_neg$88 + connect \dive_abs_ov32$25 \core_setup_stage_dive_abs_ov32$89 + connect \dive_abs_ov64$26 \core_setup_stage_dive_abs_ov64$90 + connect \div_by_zero$27 \core_setup_stage_div_by_zero$91 + connect \divisor_radicand$28 \core_setup_stage_divisor_radicand$92 + connect \operation$29 \core_setup_stage_operation$93 + connect \quotient_root \core_setup_stage_quotient_root + connect \root_times_radicand \core_setup_stage_root_times_radicand + connect \compare_lhs \core_setup_stage_compare_lhs + connect \compare_rhs \core_setup_stage_compare_rhs + end + process $group_0 + assign \input_muxid 2'00 + assign \input_muxid \muxid$1 sync init end - process $group_26 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_o_ok \pipe_o } + process $group_1 + assign \input_logical_op__insn_type 7'0000000 + assign \input_logical_op__fn_unit 11'00000000000 + assign \input_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_logical_op__imm_data__imm_ok 1'0 + assign \input_logical_op__rc__rc 1'0 + assign \input_logical_op__rc__rc_ok 1'0 + assign \input_logical_op__oe__oe 1'0 + assign \input_logical_op__oe__oe_ok 1'0 + assign \input_logical_op__invert_in 1'0 + assign \input_logical_op__zero_a 1'0 + assign \input_logical_op__input_carry 2'00 + assign \input_logical_op__invert_out 1'0 + assign \input_logical_op__write_cr0 1'0 + assign \input_logical_op__output_carry 1'0 + assign \input_logical_op__is_32bit 1'0 + assign \input_logical_op__is_signed 1'0 + assign \input_logical_op__data_len 4'0000 + assign \input_logical_op__insn 32'00000000000000000000000000000000 + assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in { \input_logical_op__oe__oe_ok \input_logical_op__oe__oe } { \input_logical_op__rc__rc_ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } sync init end - process $group_28 - assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok 1'0 - assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + process $group_19 + assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_ra \ra$20 sync init end - process $group_30 - assign \fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2_ok 1'0 - assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } + process $group_20 + assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_rb \rb$21 sync init end - process $group_32 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia_ok 1'0 - assign { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } + process $group_21 + assign \input_xer_so 1'0 + assign \input_xer_so \xer_so$22 sync init end - process $group_34 - assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \msr_ok 1'0 - assign { \msr_ok \msr } { \pipe_msr_ok \pipe_msr } + process $group_22 + assign \setup_stage_muxid 2'00 + assign \setup_stage_muxid \input_muxid$23 sync init end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l" -module \src_l$36 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $1 + process $group_23 + assign \setup_stage_logical_op__insn_type 7'0000000 + assign \setup_stage_logical_op__fn_unit 11'00000000000 + assign \setup_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \setup_stage_logical_op__imm_data__imm_ok 1'0 + assign \setup_stage_logical_op__rc__rc 1'0 + assign \setup_stage_logical_op__rc__rc_ok 1'0 + assign \setup_stage_logical_op__oe__oe 1'0 + assign \setup_stage_logical_op__oe__oe_ok 1'0 + assign \setup_stage_logical_op__invert_in 1'0 + assign \setup_stage_logical_op__zero_a 1'0 + assign \setup_stage_logical_op__input_carry 2'00 + assign \setup_stage_logical_op__invert_out 1'0 + assign \setup_stage_logical_op__write_cr0 1'0 + assign \setup_stage_logical_op__output_carry 1'0 + assign \setup_stage_logical_op__is_32bit 1'0 + assign \setup_stage_logical_op__is_signed 1'0 + assign \setup_stage_logical_op__data_len 4'0000 + assign \setup_stage_logical_op__insn 32'00000000000000000000000000000000 + assign { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in { \setup_stage_logical_op__oe__oe_ok \setup_stage_logical_op__oe__oe } { \setup_stage_logical_op__rc__rc_ok \setup_stage_logical_op__rc__rc } { \setup_stage_logical_op__imm_data__imm_ok \setup_stage_logical_op__imm_data__imm } \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 { \input_logical_op__oe__oe_ok$31 \input_logical_op__oe__oe$30 } { \input_logical_op__rc__rc_ok$29 \input_logical_op__rc__rc$28 } { \input_logical_op__imm_data__imm_ok$27 \input_logical_op__imm_data__imm$26 } \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $1 - connect \Y $3 + process $group_41 + assign \setup_stage_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \setup_stage_ra \input_ra$42 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $3 - connect \B \s_src - connect \Y $5 + process $group_42 + assign \setup_stage_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \setup_stage_rb \input_rb$43 + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 4'0000 - end + process $group_43 + assign \setup_stage_xer_so 1'0 + assign \setup_stage_xer_so \input_xer_so$44 sync init - update \q_int 4'0000 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $7 + process $group_44 + assign \core_setup_stage_muxid 2'00 + assign \core_setup_stage_muxid \setup_stage_muxid$45 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_45 + assign \core_setup_stage_logical_op__insn_type 7'0000000 + assign \core_setup_stage_logical_op__fn_unit 11'00000000000 + assign \core_setup_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_setup_stage_logical_op__imm_data__imm_ok 1'0 + assign \core_setup_stage_logical_op__rc__rc 1'0 + assign \core_setup_stage_logical_op__rc__rc_ok 1'0 + assign \core_setup_stage_logical_op__oe__oe 1'0 + assign \core_setup_stage_logical_op__oe__oe_ok 1'0 + assign \core_setup_stage_logical_op__invert_in 1'0 + assign \core_setup_stage_logical_op__zero_a 1'0 + assign \core_setup_stage_logical_op__input_carry 2'00 + assign \core_setup_stage_logical_op__invert_out 1'0 + assign \core_setup_stage_logical_op__write_cr0 1'0 + assign \core_setup_stage_logical_op__output_carry 1'0 + assign \core_setup_stage_logical_op__is_32bit 1'0 + assign \core_setup_stage_logical_op__is_signed 1'0 + assign \core_setup_stage_logical_op__data_len 4'0000 + assign \core_setup_stage_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_setup_stage_logical_op__insn \core_setup_stage_logical_op__data_len \core_setup_stage_logical_op__is_signed \core_setup_stage_logical_op__is_32bit \core_setup_stage_logical_op__output_carry \core_setup_stage_logical_op__write_cr0 \core_setup_stage_logical_op__invert_out \core_setup_stage_logical_op__input_carry \core_setup_stage_logical_op__zero_a \core_setup_stage_logical_op__invert_in { \core_setup_stage_logical_op__oe__oe_ok \core_setup_stage_logical_op__oe__oe } { \core_setup_stage_logical_op__rc__rc_ok \core_setup_stage_logical_op__rc__rc } { \core_setup_stage_logical_op__imm_data__imm_ok \core_setup_stage_logical_op__imm_data__imm } \core_setup_stage_logical_op__fn_unit \core_setup_stage_logical_op__insn_type } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 { \setup_stage_logical_op__oe__oe_ok$53 \setup_stage_logical_op__oe__oe$52 } { \setup_stage_logical_op__rc__rc_ok$51 \setup_stage_logical_op__rc__rc$50 } { \setup_stage_logical_op__imm_data__imm_ok$49 \setup_stage_logical_op__imm_data__imm$48 } \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $9 - connect \B \s_src - connect \Y $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$94 + process $group_63 + assign \core_setup_stage_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_setup_stage_ra \ra$94 + sync init end - process $group_1 - assign \q_src 4'0000 - assign \q_src $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$95 + process $group_64 + assign \core_setup_stage_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_setup_stage_rb \rb$95 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \Y $13 + process $group_65 + assign \core_setup_stage_xer_so 1'0 + assign \core_setup_stage_xer_so \setup_stage_xer_so$64 + sync init end - process $group_2 - assign \qn_src 4'0000 - assign \qn_src $13 + process $group_66 + assign \core_setup_stage_divisor_neg 1'0 + assign \core_setup_stage_divisor_neg \setup_stage_divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \B \q_int - connect \Y $15 + process $group_67 + assign \core_setup_stage_dividend_neg 1'0 + assign \core_setup_stage_dividend_neg \setup_stage_dividend_neg + sync init end - process $group_3 - assign \qlq_src 4'0000 - assign \qlq_src $15 + process $group_68 + assign \core_setup_stage_dive_abs_ov32 1'0 + assign \core_setup_stage_dive_abs_ov32 \setup_stage_dive_abs_ov32 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l" -module \opc_l$37 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 + process $group_69 + assign \core_setup_stage_dive_abs_ov64 1'0 + assign \core_setup_stage_dive_abs_ov64 \setup_stage_dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + process $group_70 + assign \core_setup_stage_div_by_zero 1'0 + assign \core_setup_stage_div_by_zero \setup_stage_div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 + process $group_71 + assign \core_setup_stage_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_setup_stage_dividend \setup_stage_dividend + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_72 + assign \core_setup_stage_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_setup_stage_divisor_radicand \setup_stage_divisor_radicand sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 + process $group_73 + assign \core_setup_stage_operation 2'00 + assign \core_setup_stage_operation \setup_stage_operation + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$96 + process $group_74 + assign \p_valid_i$96 1'0 + assign \p_valid_i$96 \p_valid_i + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_75 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $98 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 + connect \A \p_valid_i$96 + connect \B \p_ready_o + connect \Y $97 end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 + process $group_76 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $97 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$99 + process $group_77 + assign \muxid$99 2'00 + assign \muxid$99 \core_setup_stage_muxid$65 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$100 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$109 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$117 + process $group_78 + assign \logical_op__insn_type$100 7'0000000 + assign \logical_op__fn_unit$101 11'00000000000 + assign \logical_op__imm_data__imm$102 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$103 1'0 + assign \logical_op__rc__rc$104 1'0 + assign \logical_op__rc__rc_ok$105 1'0 + assign \logical_op__oe__oe$106 1'0 + assign \logical_op__oe__oe_ok$107 1'0 + assign \logical_op__invert_in$108 1'0 + assign \logical_op__zero_a$109 1'0 + assign \logical_op__input_carry$110 2'00 + assign \logical_op__invert_out$111 1'0 + assign \logical_op__write_cr0$112 1'0 + assign \logical_op__output_carry$113 1'0 + assign \logical_op__is_32bit$114 1'0 + assign \logical_op__is_signed$115 1'0 + assign \logical_op__data_len$116 4'0000 + assign \logical_op__insn$117 32'00000000000000000000000000000000 + assign { \logical_op__insn$117 \logical_op__data_len$116 \logical_op__is_signed$115 \logical_op__is_32bit$114 \logical_op__output_carry$113 \logical_op__write_cr0$112 \logical_op__invert_out$111 \logical_op__input_carry$110 \logical_op__zero_a$109 \logical_op__invert_in$108 { \logical_op__oe__oe_ok$107 \logical_op__oe__oe$106 } { \logical_op__rc__rc_ok$105 \logical_op__rc__rc$104 } { \logical_op__imm_data__imm_ok$103 \logical_op__imm_data__imm$102 } \logical_op__fn_unit$101 \logical_op__insn_type$100 } { \core_setup_stage_logical_op__insn$83 \core_setup_stage_logical_op__data_len$82 \core_setup_stage_logical_op__is_signed$81 \core_setup_stage_logical_op__is_32bit$80 \core_setup_stage_logical_op__output_carry$79 \core_setup_stage_logical_op__write_cr0$78 \core_setup_stage_logical_op__invert_out$77 \core_setup_stage_logical_op__input_carry$76 \core_setup_stage_logical_op__zero_a$75 \core_setup_stage_logical_op__invert_in$74 { \core_setup_stage_logical_op__oe__oe_ok$73 \core_setup_stage_logical_op__oe__oe$72 } { \core_setup_stage_logical_op__rc__rc_ok$71 \core_setup_stage_logical_op__rc__rc$70 } { \core_setup_stage_logical_op__imm_data__imm_ok$69 \core_setup_stage_logical_op__imm_data__imm$68 } \core_setup_stage_logical_op__fn_unit$67 \core_setup_stage_logical_op__insn_type$66 } + sync init end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$118 + process $group_96 + assign \ra$118 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$118 \core_setup_stage_ra$84 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l" -module \req_l$38 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$119 + process $group_97 + assign \rb$119 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$119 \core_setup_stage_rb$85 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B $1 - connect \Y $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$120 + process $group_98 + assign \xer_so$120 1'0 + assign \xer_so$120 \core_setup_stage_xer_so$86 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $3 - connect \B \s_req - connect \Y $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$121 + process $group_99 + assign \divisor_neg$121 1'0 + assign \divisor_neg$121 \core_setup_stage_divisor_neg$87 + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 5'00000 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$122 + process $group_100 + assign \dividend_neg$122 1'0 + assign \dividend_neg$122 \core_setup_stage_dividend_neg$88 sync init - update \q_int 5'00000 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$123 + process $group_101 + assign \dive_abs_ov32$123 1'0 + assign \dive_abs_ov32$123 \core_setup_stage_dive_abs_ov32$89 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B $7 - connect \Y $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$124 + process $group_102 + assign \dive_abs_ov64$124 1'0 + assign \dive_abs_ov64$124 \core_setup_stage_dive_abs_ov64$90 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $9 - connect \B \s_req - connect \Y $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$125 + process $group_103 + assign \div_by_zero$125 1'0 + assign \div_by_zero$125 \core_setup_stage_div_by_zero$91 + sync init end - process $group_1 - assign \q_req 5'00000 - assign \q_req $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$126 + process $group_104 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_setup_stage_divisor_radicand$92 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \Y $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$127 + process $group_105 + assign \operation$127 2'00 + assign \operation$127 \core_setup_stage_operation$93 + sync init end - process $group_2 - assign \qn_req 5'00000 - assign \qn_req $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$128 + process $group_106 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_setup_stage_quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \B \q_int - connect \Y $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$129 + process $group_107 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_setup_stage_root_times_radicand + sync init end - process $group_3 - assign \qlq_req 5'00000 - assign \qlq_req $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$130 + process $group_108 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_setup_stage_compare_lhs sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l" -module \rst_l$39 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$131 + process $group_109 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_setup_stage_compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_110 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 + process $group_111 + assign \muxid$next \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$next \muxid$99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$next \muxid$99 + end + sync init + update \muxid 2'00 + sync posedge \coresync_clk + update \muxid \muxid$next end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 + process $group_112 + assign \logical_op__insn_type$next \logical_op__insn_type + assign \logical_op__fn_unit$next \logical_op__fn_unit + assign \logical_op__imm_data__imm$next \logical_op__imm_data__imm + assign \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm_ok + assign \logical_op__rc__rc$next \logical_op__rc__rc + assign \logical_op__rc__rc_ok$next \logical_op__rc__rc_ok + assign \logical_op__oe__oe$next \logical_op__oe__oe + assign \logical_op__oe__oe_ok$next \logical_op__oe__oe_ok + assign \logical_op__invert_in$next \logical_op__invert_in + assign \logical_op__zero_a$next \logical_op__zero_a + assign \logical_op__input_carry$next \logical_op__input_carry + assign \logical_op__invert_out$next \logical_op__invert_out + assign \logical_op__write_cr0$next \logical_op__write_cr0 + assign \logical_op__output_carry$next \logical_op__output_carry + assign \logical_op__is_32bit$next \logical_op__is_32bit + assign \logical_op__is_signed$next \logical_op__is_signed + assign \logical_op__data_len$next \logical_op__data_len + assign \logical_op__insn$next \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$117 \logical_op__data_len$116 \logical_op__is_signed$115 \logical_op__is_32bit$114 \logical_op__output_carry$113 \logical_op__write_cr0$112 \logical_op__invert_out$111 \logical_op__input_carry$110 \logical_op__zero_a$109 \logical_op__invert_in$108 { \logical_op__oe__oe_ok$107 \logical_op__oe__oe$106 } { \logical_op__rc__rc_ok$105 \logical_op__rc__rc$104 } { \logical_op__imm_data__imm_ok$103 \logical_op__imm_data__imm$102 } \logical_op__fn_unit$101 \logical_op__insn_type$100 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$117 \logical_op__data_len$116 \logical_op__is_signed$115 \logical_op__is_32bit$114 \logical_op__output_carry$113 \logical_op__write_cr0$112 \logical_op__invert_out$111 \logical_op__input_carry$110 \logical_op__zero_a$109 \logical_op__invert_in$108 { \logical_op__oe__oe_ok$107 \logical_op__oe__oe$106 } { \logical_op__rc__rc_ok$105 \logical_op__rc__rc$104 } { \logical_op__imm_data__imm_ok$103 \logical_op__imm_data__imm$102 } \logical_op__fn_unit$101 \logical_op__insn_type$100 } + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 1'0 + assign \logical_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$next 1'0 + assign \logical_op__rc__rc$next 1'0 + assign \logical_op__rc__rc_ok$next 1'0 + assign \logical_op__oe__oe$next 1'0 + assign \logical_op__oe__oe_ok$next 1'0 end sync init - update \q_int 1'0 + update \logical_op__insn_type 7'0000000 + update \logical_op__fn_unit 11'00000000000 + update \logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok 1'0 + update \logical_op__rc__rc 1'0 + update \logical_op__rc__rc_ok 1'0 + update \logical_op__oe__oe 1'0 + update \logical_op__oe__oe_ok 1'0 + update \logical_op__invert_in 1'0 + update \logical_op__zero_a 1'0 + update \logical_op__input_carry 2'00 + update \logical_op__invert_out 1'0 + update \logical_op__write_cr0 1'0 + update \logical_op__output_carry 1'0 + update \logical_op__is_32bit 1'0 + update \logical_op__is_signed 1'0 + update \logical_op__data_len 4'0000 + update \logical_op__insn 32'00000000000000000000000000000000 sync posedge \coresync_clk - update \q_int \q_int$next + update \logical_op__insn_type \logical_op__insn_type$next + update \logical_op__fn_unit \logical_op__fn_unit$next + update \logical_op__imm_data__imm \logical_op__imm_data__imm$next + update \logical_op__imm_data__imm_ok \logical_op__imm_data__imm_ok$next + update \logical_op__rc__rc \logical_op__rc__rc$next + update \logical_op__rc__rc_ok \logical_op__rc__rc_ok$next + update \logical_op__oe__oe \logical_op__oe__oe$next + update \logical_op__oe__oe_ok \logical_op__oe__oe_ok$next + update \logical_op__invert_in \logical_op__invert_in$next + update \logical_op__zero_a \logical_op__zero_a$next + update \logical_op__input_carry \logical_op__input_carry$next + update \logical_op__invert_out \logical_op__invert_out$next + update \logical_op__write_cr0 \logical_op__write_cr0$next + update \logical_op__output_carry \logical_op__output_carry$next + update \logical_op__is_32bit \logical_op__is_32bit$next + update \logical_op__is_signed \logical_op__is_signed$next + update \logical_op__data_len \logical_op__data_len$next + update \logical_op__insn \logical_op__insn$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 + process $group_130 + assign \ra$next \ra + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$next \ra$118 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$next \ra$118 + end + sync init + update \ra 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra \ra$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_131 + assign \rb$next \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$next \rb$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$next \rb$119 + end + sync init + update \rb 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb \rb$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 + process $group_132 + assign \xer_so$next \xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$next \xer_so$120 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$next \xer_so$120 + end + sync init + update \xer_so 1'0 + sync posedge \coresync_clk + update \xer_so \xer_so$next end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 + process $group_133 + assign \divisor_neg$next \divisor_neg + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$next \divisor_neg$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$next \divisor_neg$121 + end sync init + update \divisor_neg 1'0 + sync posedge \coresync_clk + update \divisor_neg \divisor_neg$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 + process $group_134 + assign \dividend_neg$next \dividend_neg + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$next \dividend_neg$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$next \dividend_neg$122 + end + sync init + update \dividend_neg 1'0 + sync posedge \coresync_clk + update \dividend_neg \dividend_neg$next end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 + process $group_135 + assign \dive_abs_ov32$next \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$next \dive_abs_ov32$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$next \dive_abs_ov32$123 + end sync init + update \dive_abs_ov32 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32 \dive_abs_ov32$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + process $group_136 + assign \dive_abs_ov64$next \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$next \dive_abs_ov64$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$next \dive_abs_ov64$124 + end + sync init + update \dive_abs_ov64 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64 \dive_abs_ov64$next + end + process $group_137 + assign \div_by_zero$next \div_by_zero + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$next \div_by_zero$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$next \div_by_zero$125 + end + sync init + update \div_by_zero 1'0 + sync posedge \coresync_clk + update \div_by_zero \div_by_zero$next + end + process $group_138 + assign \divisor_radicand$next \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$next \divisor_radicand$126 + end + sync init + update \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand \divisor_radicand$next + end + process $group_139 + assign \operation$next \operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$next \operation$127 + end + sync init + update \operation 2'00 + sync posedge \coresync_clk + update \operation \operation$next + end + process $group_140 + assign \quotient_root$next \quotient_root + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$next \quotient_root$128 + end + sync init + update \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root \quotient_root$next + end + process $group_141 + assign \root_times_radicand$next \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$next \root_times_radicand$129 + end + sync init + update \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand \root_times_radicand$next + end + process $group_142 + assign \compare_lhs$next \compare_lhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$next \compare_lhs$130 + end + sync init + update \compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs \compare_lhs$next + end + process $group_143 + assign \compare_rhs$next \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$next \compare_rhs$131 + end + sync init + update \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs \compare_rhs$next + end + process $group_144 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_145 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \ra$94 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \rb$95 64'0000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.p" +module \p$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 + process $group_0 + assign \trigger 1'0 + assign \trigger $1 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l" -module \rok_l$40 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.n" +module \n$78 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r_rdok + connect \A \n_ready_i + connect \B \n_valid_o connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_0.core.trial0" +module \trial0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \q_int$next 1'0 + assign \dr_times_trial_bits $3 end sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111111 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l" -module \alui_l$41 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_0.core.trial1" +module \trial1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r_alui + connect \A \operation + connect \B 1'1 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui + connect \A \operation + connect \B 1'1 connect \Y $5 end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111111 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_0.core.pe" +module \pe + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 + connect \A \i + connect \B 1'0 + connect \Y $1 end process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 + assign \n 1'0 + assign \n $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_0.core" +module \core$79 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init end process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l" -module \alu_l$42 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \q_int$next 1'0 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'111111 + connect \Y $30 end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0" -module \trap0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_0" +module \core_calculate_stage_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -66628,7 +50831,7 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_trap0__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -66642,107 +50845,103 @@ module \trap0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_trap0__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \oper_i_alu_trap0__insn + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \oper_i_alu_trap0__msr + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \oper_i_alu_trap0__cia + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_trap0__is_32bit + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 input 7 \oper_i_alu_trap0__traptype + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 8 \oper_i_alu_trap0__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 9 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 10 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 4 input 11 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 12 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 13 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 14 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 15 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 16 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 17 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 18 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 19 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 input 20 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 21 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 22 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 24 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 25 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 26 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 27 \dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 28 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 29 \dest5_o - attribute \src "simple/issuer.py:89" - wire width 1 input 30 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_trap0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_trap0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_msr - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" attribute \enum_value_0011111 "OP_EXTS" @@ -66787,7 +50986,7 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__insn_type + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -66801,810 +51000,836 @@ module \trap0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_trap0_trap_op__fn_unit + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_trap0_trap_op__insn + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_trap0_trap_op__msr + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_trap0_trap_op__cia + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_trap0_trap_op__is_32bit + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \alu_trap0_trap_op__traptype + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_trap0_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_ra + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_rb + wire width 64 output 52 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_fast1$1 + wire width 64 output 53 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_fast2$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_trap0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_trap0_p_ready_o - cell \alu_trap0 \alu_trap0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \fast1_ok \fast1_ok - connect \fast2_ok \fast2_ok - connect \nia_ok \nia_ok - connect \msr_ok \msr_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_trap0_n_valid_o - connect \n_ready_i \alu_trap0_n_ready_i - connect \o \alu_trap0_o - connect \fast1 \alu_trap0_fast1 - connect \fast2 \alu_trap0_fast2 - connect \nia \alu_trap0_nia - connect \msr \alu_trap0_msr - connect \trap_op__insn_type \alu_trap0_trap_op__insn_type - connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit - connect \trap_op__insn \alu_trap0_trap_op__insn - connect \trap_op__msr \alu_trap0_trap_op__msr - connect \trap_op__cia \alu_trap0_trap_op__cia - connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit - connect \trap_op__traptype \alu_trap0_trap_op__traptype - connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr - connect \ra \alu_trap0_ra - connect \rb \alu_trap0_rb - connect \fast1$1 \alu_trap0_fast1$1 - connect \fast2$2 \alu_trap0_fast2$2 - connect \p_valid_i \alu_trap0_p_valid_i - connect \p_ready_o \alu_trap0_p_ready_o + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$79 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \src_l_q_src - cell \src_l$36 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$37 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req$next - cell \req_l$38 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - cell \rst_l$39 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$40 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$41 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$42 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $3 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 4 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $not $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__rel_o - connect \Y $6 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 4 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $or $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $6 - connect \B \cu_rd__go_i - connect \Y $8 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $reduce_and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $5 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 - connect \Y $11 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $11 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $13 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $and $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $13 - connect \Y $15 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_2 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse $15 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_done - process $group_3 - assign \alu_done 1'0 - assign \alu_done \alu_trap0_n_valid_o + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly$next - process $group_4 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $and $20 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_1.core.trial0" +module \trial0$81 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $17 - connect \Y $19 - end - process $group_5 - assign \alu_pulse 1'0 - assign \alu_pulse $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" - wire width 5 \alu_pulsem - process $group_6 - assign \alu_pulsem 5'00000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - sync init + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 5 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 5 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 5 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - cell $and $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $21 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_7 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $21 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \prev_wr_go$next 5'00000 + assign \dr_times_trial_bits $3 end sync init - update \prev_wr_go 5'00000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 5 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wrmask_o - connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 5 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__rel_o - connect \B $25 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $24 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111110 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $23 - connect \Y $31 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_8 - assign \cu_done_o 1'0 - assign \cu_done_o $31 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $36 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_1.core.trial1" +module \trial1$82 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $35 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $or $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $33 - connect \B $35 - connect \Y $37 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_9 - assign \wr_any 1'0 - assign \wr_any $37 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_ready_i - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $and $42 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $39 - connect \Y $41 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 5 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $44 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $43 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111110 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $eq $46 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $43 - connect \B 1'0 - connect \Y $45 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $41 - connect \B $45 - connect \Y $47 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $eq $50 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_1.core.pe" +module \pe$83 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o + connect \A \i connect \B 1'0 - connect \Y $49 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $52 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_1.core" +module \core$80 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$81 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$82 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$83 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A $49 - connect \B \alu_trap0_n_ready_i - connect \Y $51 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $54 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $51 - connect \B \alu_trap0_n_valid_o - connect \Y $53 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $56 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $53 - connect \B \cu_busy_o - connect \Y $55 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_10 - assign \req_done 1'0 - assign \req_done $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \req_done 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $57 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_11 - assign \reset 1'0 - assign \reset $57 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - cell $or $60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $59 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_12 - assign \rst_r 1'0 - assign \rst_r $59 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - wire width 5 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - cell $or $62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $61 - end - process $group_13 - assign \reset_w 5'00000 - assign \reset_w $61 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - wire width 4 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - cell $or $64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $63 - end - process $group_14 - assign \reset_r 4'0000 - assign \reset_r $63 - sync init - end - process $group_15 - assign \rok_l_s_rdok 1'0 - assign \rok_l_s_rdok \cu_issue_i - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - cell $and $66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_valid_o - connect \B \cu_busy_o - connect \Y $65 - end - process $group_16 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $65 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_17 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \all_rd - sync init - end - process $group_18 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \rst_r - sync init - end - process $group_19 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end process $group_20 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_21 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 4'0000 - end - sync init - update \src_l_s_src 4'0000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next end - process $group_22 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 4'1111 - end - sync init - update \src_l_r_src 4'1111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - wire width 5 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - cell $and $68 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $67 - end - process $group_23 - assign \req_l_s_req 5'00000 - assign \req_l_s_req $67 - sync init + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'111110 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - wire width 5 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - cell $or $70 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $69 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_24 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $69 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 5'11111 - end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init - update \req_l_r_req 5'11111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_1" +module \core_calculate_stage_1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -67679,7 +51904,7 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -67693,1124 +51918,989 @@ module \trap0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__msr + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__cia + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \oper_r__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \oper_r__trapaddr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__msr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__msr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__cia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__cia$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 5 \oper_l__traptype - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 5 \oper_l__traptype$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 13 \oper_l__trapaddr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 13 \oper_l__trapaddr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 197 $71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $72 - parameter \WIDTH 197 - connect \A { \oper_l__trapaddr \oper_l__traptype \oper_l__is_32bit \oper_l__cia \oper_l__msr \oper_l__insn \oper_l__fn_unit \oper_l__insn_type } - connect \B { \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } - connect \S \cu_issue_i - connect \Y $71 - end - process $group_25 - assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 11'00000000000 - assign \oper_r__insn 32'00000000000000000000000000000000 - assign \oper_r__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__is_32bit 1'0 - assign \oper_r__traptype 5'00000 - assign \oper_r__trapaddr 13'0000000000000 - assign { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__cia \oper_r__msr \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $71 - sync init - end - process $group_33 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__insn$next \oper_l__insn - assign \oper_l__msr$next \oper_l__msr - assign \oper_l__cia$next \oper_l__cia - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__traptype$next \oper_l__traptype - assign \oper_l__trapaddr$next \oper_l__trapaddr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \oper_l__trapaddr$next \oper_l__traptype$next \oper_l__is_32bit$next \oper_l__cia$next \oper_l__msr$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 11'00000000000 - update \oper_l__insn 32'00000000000000000000000000000000 - update \oper_l__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__is_32bit 1'0 - update \oper_l__traptype 5'00000 - update \oper_l__trapaddr 13'0000000000000 - sync posedge \coresync_clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__insn \oper_l__insn$next - update \oper_l__msr \oper_l__msr$next - update \oper_l__cia \oper_l__cia$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__traptype \oper_l__traptype$next - update \oper_l__trapaddr \oper_l__trapaddr$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $73 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $74 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $74 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $76 - parameter \WIDTH 65 - connect \A { \data_r0_l__o_ok \data_r0_l__o } - connect \B { \o_ok \alu_trap0_o } - connect \S $74 - connect \Y $73 - end - process $group_41 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - assign { \data_r0__o_ok \data_r0__o } $73 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $77 - end - process $group_43 - assign \data_r0_l__o$next \data_r0_l__o - assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_trap0_o } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0_l__o_ok$next 1'0 - end + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$80 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init - update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0_l__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0_l__o \data_r0_l__o$next - update \data_r0_l__o_ok \data_r0_l__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r1__fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r1__fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r1_l__fast1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r1_l__fast1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $80 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $80 + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $82 - parameter \WIDTH 65 - connect \A { \data_r1_l__fast1_ok \data_r1_l__fast1 } - connect \B { \fast1_ok \alu_trap0_fast1 } - connect \S $80 - connect \Y $79 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - process $group_45 - assign \data_r1__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r1__fast1_ok 1'0 - assign { \data_r1__fast1_ok \data_r1__fast1 } $79 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $83 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - process $group_47 - assign \data_r1_l__fast1$next \data_r1_l__fast1 - assign \data_r1_l__fast1_ok$next \data_r1_l__fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $83 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r1_l__fast1_ok$next \data_r1_l__fast1$next } { \fast1_ok \alu_trap0_fast1 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1_l__fast1_ok$next 1'0 - end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init - update \data_r1_l__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r1_l__fast1_ok 1'0 - sync posedge \coresync_clk - update \data_r1_l__fast1 \data_r1_l__fast1$next - update \data_r1_l__fast1_ok \data_r1_l__fast1_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r2__fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r2__fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r2_l__fast2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r2_l__fast2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__fast2_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $85 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $86 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $88 - parameter \WIDTH 65 - connect \A { \data_r2_l__fast2_ok \data_r2_l__fast2 } - connect \B { \fast2_ok \alu_trap0_fast2 } - connect \S $86 - connect \Y $85 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - process $group_49 - assign \data_r2__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r2__fast2_ok 1'0 - assign { \data_r2__fast2_ok \data_r2__fast2 } $85 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $89 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - process $group_51 - assign \data_r2_l__fast2$next \data_r2_l__fast2 - assign \data_r2_l__fast2_ok$next \data_r2_l__fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $89 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r2_l__fast2_ok$next \data_r2_l__fast2$next } { \fast2_ok \alu_trap0_fast2 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2_l__fast2_ok$next 1'0 - end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init - update \data_r2_l__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r2_l__fast2_ok 1'0 - sync posedge \coresync_clk - update \data_r2_l__fast2 \data_r2_l__fast2$next - update \data_r2_l__fast2_ok \data_r2_l__fast2_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r3__nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r3__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r3_l__nia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r3_l__nia$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__nia_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $91 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $92 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $92 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $94 - parameter \WIDTH 65 - connect \A { \data_r3_l__nia_ok \data_r3_l__nia } - connect \B { \nia_ok \alu_trap0_nia } - connect \S $92 - connect \Y $91 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - process $group_53 - assign \data_r3__nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r3__nia_ok 1'0 - assign { \data_r3__nia_ok \data_r3__nia } $91 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $95 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - process $group_55 - assign \data_r3_l__nia$next \data_r3_l__nia - assign \data_r3_l__nia_ok$next \data_r3_l__nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $95 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r3_l__nia_ok$next \data_r3_l__nia$next } { \nia_ok \alu_trap0_nia } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r3_l__nia_ok$next 1'0 - end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init - update \data_r3_l__nia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r3_l__nia_ok 1'0 - sync posedge \coresync_clk - update \data_r3_l__nia \data_r3_l__nia$next - update \data_r3_l__nia_ok \data_r3_l__nia_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r4__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r4__msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r4_l__msr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r4_l__msr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r4_l__msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r4_l__msr_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $97 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $98 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $98 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $100 - parameter \WIDTH 65 - connect \A { \data_r4_l__msr_ok \data_r4_l__msr } - connect \B { \msr_ok \alu_trap0_msr } - connect \S $98 - connect \Y $97 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - process $group_57 - assign \data_r4__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r4__msr_ok 1'0 - assign { \data_r4__msr_ok \data_r4__msr } $97 + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $101 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - process $group_59 - assign \data_r4_l__msr$next \data_r4_l__msr - assign \data_r4_l__msr_ok$next \data_r4_l__msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $101 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r4_l__msr_ok$next \data_r4_l__msr$next } { \msr_ok \alu_trap0_msr } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r4_l__msr_ok$next 1'0 - end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 sync init - update \data_r4_l__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r4_l__msr_ok 1'0 - sync posedge \coresync_clk - update \data_r4_l__msr \data_r4_l__msr$next - update \data_r4_l__msr_ok \data_r4_l__msr_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $104 + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_2.core.trial0" +module \trial0$85 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r0__o_ok - connect \B \cu_busy_o - connect \Y $103 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $106 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r1__fast1_ok - connect \B \cu_busy_o - connect \Y $105 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $108 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r2__fast2_ok - connect \B \cu_busy_o - connect \Y $107 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $110 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r3__nia_ok - connect \B \cu_busy_o - connect \Y $109 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $112 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r4__msr_ok - connect \B \cu_busy_o - connect \Y $111 - end - process $group_61 - assign \cu_wrmask_o 5'00000 - assign \cu_wrmask_o { $111 $109 $107 $105 $103 } - sync init - end - process $group_62 - assign \alu_trap0_trap_op__insn_type 7'0000000 - assign \alu_trap0_trap_op__fn_unit 11'00000000000 - assign \alu_trap0_trap_op__insn 32'00000000000000000000000000000000 - assign \alu_trap0_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_trap_op__is_32bit 1'0 - assign \alu_trap0_trap_op__traptype 5'00000 - assign \alu_trap0_trap_op__trapaddr 13'0000000000000 - assign { \alu_trap0_trap_op__trapaddr \alu_trap0_trap_op__traptype \alu_trap0_trap_op__is_32bit \alu_trap0_trap_op__cia \alu_trap0_trap_op__msr \alu_trap0_trap_op__insn \alu_trap0_trap_op__fn_unit \alu_trap0_trap_op__insn_type } { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__cia \oper_r__msr \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $114 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $113 - end - process $group_70 - assign \alu_trap0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_ra $113 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_71 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \src_r0$next \src1_i + assign \trial_compare_rhs $7 [191:0] end sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $116 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $115 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_2.core.trial1" +module \trial1$86 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - process $group_72 - assign \alu_trap0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_rb $115 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_73 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \src_r1$next \src2_i + assign \dr_times_trial_bits $3 end sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $118 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $117 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_74 - assign \alu_trap0_fast1$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_fast1$1 $117 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111101 + connect \Y $8 end - process $group_75 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \src_r2$next \src3_i + assign \trial_compare_rhs $7 [191:0] end - sync init - update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $120 - parameter \WIDTH 64 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $119 - end - process $group_76 - assign \alu_trap0_fast2$2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_fast2$2 $119 sync init end - process $group_77 - assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_2.core.pe" +module \pe$87 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \src_r3$next \src4_i + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 end - sync init - update \src_r3 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r3 \src_r3$next - end - process $group_78 - assign \alu_trap0_p_valid_i 1'0 - assign \alu_trap0_p_valid_i \alui_l_q_alui sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - cell $and $122 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_trap0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $121 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_79 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $121 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end + process $group_1 + assign \n 1'0 + assign \n $1 sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next end - process $group_80 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_2.core" +module \core$84 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$85 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$86 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$87 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - process $group_81 - assign \alu_trap0_n_ready_i 1'0 - assign \alu_trap0_n_ready_i \alu_l_q_alu + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - cell $and $124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $123 + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init end - process $group_82 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $123 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next end - process $group_83 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init end - process $group_84 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $125 + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $125 - connect \B { 1'1 1'1 1'1 1'1 } - connect \Y $127 + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $not $130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rdmaskn_i - connect \Y $129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $127 - connect \B $129 - connect \Y $131 + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init end - process $group_85 - assign \cu_rd__rel_o 4'0000 - assign \cu_rd__rel_o $131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $133 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $135 + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $137 + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $140 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $139 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $141 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 5 $143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B { $133 $135 $137 $139 $141 } - connect \Y $143 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 5 $145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $146 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $143 - connect \B \cu_wrmask_o - connect \Y $145 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - process $group_86 - assign \cu_wr__rel_o 5'00000 - assign \cu_wr__rel_o $145 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $148 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $147 - end - process $group_87 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $147 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end - sync init + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $150 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $149 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_88 - assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $149 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \dest2_o { \data_r1__fast1_ok \data_r1__fast1 } [63:0] + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $152 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $151 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_89 - assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $151 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest3_o { \data_r2__fast2_ok \data_r2__fast2 } [63:0] - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $154 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $153 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_90 - assign \dest4_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $153 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest4_o { \data_r3__nia_ok \data_r3__nia } [63:0] - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $156 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [4] - connect \B \cu_busy_o - connect \Y $155 - end - process $group_91 - assign \dest5_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $155 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest5_o { \data_r4__msr_ok \data_r4__msr } [63:0] - end - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.p" -module \p$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.n" -module \n$44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.p" -module \p$46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'111101 + connect \Y $30 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.n" -module \n$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.input" -module \input$48 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_2" +module \core_calculate_stage_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -68915,7 +53005,7 @@ module \input$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" @@ -68942,8 +53032,32 @@ module \input$48 wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -69018,7 +53132,7 @@ module \input$48 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \logical_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -69032,83 +53146,112 @@ module \input$48 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 23 \logical_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \logical_op__imm_data__imm$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \logical_op__imm_data__imm_ok$5 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \logical_op__rc__rc$6 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \logical_op__rc__rc_ok$7 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__oe__oe$8 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__oe__oe_ok$9 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__invert_a$10 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__zero_a$11 + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 32 \logical_op__input_carry$12 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__invert_out$13 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__write_cr0$14 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__output_carry$15 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__is_32bit$16 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__is_signed$17 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 38 \logical_op__data_len$18 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 39 \logical_op__insn$19 + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 40 \ra$20 + wire width 64 output 52 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24" - wire width 64 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24" - cell $not $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $22 + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$84 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23" - switch { \logical_op__invert_a } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23" - case 1'1 - assign \a $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25" - case - assign \a \ra - end - sync init - end - process $group_1 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \a - sync init - end - process $group_2 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_3 + process $group_1 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -69117,7 +53260,7 @@ module \input$48 assign \logical_op__rc__rc_ok$7 1'0 assign \logical_op__oe__oe$8 1'0 assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_a$10 1'0 + assign \logical_op__invert_in$10 1'0 assign \logical_op__zero_a$11 1'0 assign \logical_op__input_carry$12 2'00 assign \logical_op__invert_out$13 1'0 @@ -69127,5996 +53270,6923 @@ module \input$48 assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - process $group_21 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 assign \rb$21 \rb sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main.bpermd" -module \bpermd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" - wire width 64 input 0 \rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" - wire width 64 input 1 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" - wire width 64 output 2 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_0 - process $group_0 - assign \rb64_0 1'0 - assign \rb64_0 \rb [63] + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_1 - process $group_1 - assign \rb64_1 1'0 - assign \rb64_1 \rb [62] + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_2 - process $group_2 - assign \rb64_2 1'0 - assign \rb64_2 \rb [61] + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_3 - process $group_3 - assign \rb64_3 1'0 - assign \rb64_3 \rb [60] + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_4 - process $group_4 - assign \rb64_4 1'0 - assign \rb64_4 \rb [59] + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_5 - process $group_5 - assign \rb64_5 1'0 - assign \rb64_5 \rb [58] + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_6 - process $group_6 - assign \rb64_6 1'0 - assign \rb64_6 \rb [57] + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_7 - process $group_7 - assign \rb64_7 1'0 - assign \rb64_7 \rb [56] + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_8 - process $group_8 - assign \rb64_8 1'0 - assign \rb64_8 \rb [55] + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_9 - process $group_9 - assign \rb64_9 1'0 - assign \rb64_9 \rb [54] + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_10 - process $group_10 - assign \rb64_10 1'0 - assign \rb64_10 \rb [53] + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_11 - process $group_11 - assign \rb64_11 1'0 - assign \rb64_11 \rb [52] + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_12 - process $group_12 - assign \rb64_12 1'0 - assign \rb64_12 \rb [51] + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_13 - process $group_13 - assign \rb64_13 1'0 - assign \rb64_13 \rb [50] + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_14 - process $group_14 - assign \rb64_14 1'0 - assign \rb64_14 \rb [49] + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_15 - process $group_15 - assign \rb64_15 1'0 - assign \rb64_15 \rb [48] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_16 - process $group_16 - assign \rb64_16 1'0 - assign \rb64_16 \rb [47] + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_17 - process $group_17 - assign \rb64_17 1'0 - assign \rb64_17 \rb [46] + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_18 - process $group_18 - assign \rb64_18 1'0 - assign \rb64_18 \rb [45] - sync init + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_3.core.trial0" +module \trial0$89 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_19 - process $group_19 - assign \rb64_19 1'0 - assign \rb64_19 \rb [44] - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_20 - process $group_20 - assign \rb64_20 1'0 - assign \rb64_20 \rb [43] + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_21 - process $group_21 - assign \rb64_21 1'0 - assign \rb64_21 \rb [42] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111100 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_22 - process $group_22 - assign \rb64_22 1'0 - assign \rb64_22 \rb [41] +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_3.core.trial1" +module \trial1$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_23 - process $group_23 - assign \rb64_23 1'0 - assign \rb64_23 \rb [40] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111100 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_24 - process $group_24 - assign \rb64_24 1'0 - assign \rb64_24 \rb [39] +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_3.core.pe" +module \pe$91 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_25 - process $group_25 - assign \rb64_25 1'0 - assign \rb64_25 \rb [38] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_26 - process $group_26 - assign \rb64_26 1'0 - assign \rb64_26 \rb [37] +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_3.core" +module \core$88 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$89 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$90 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$91 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_27 - process $group_27 - assign \rb64_27 1'0 - assign \rb64_27 \rb [36] + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_28 - process $group_28 - assign \rb64_28 1'0 - assign \rb64_28 \rb [35] + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_29 - process $group_29 - assign \rb64_29 1'0 - assign \rb64_29 \rb [34] + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_30 - process $group_30 - assign \rb64_30 1'0 - assign \rb64_30 \rb [33] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_31 - process $group_31 - assign \rb64_31 1'0 - assign \rb64_31 \rb [32] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_32 - process $group_32 - assign \rb64_32 1'0 - assign \rb64_32 \rb [31] + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_33 - process $group_33 - assign \rb64_33 1'0 - assign \rb64_33 \rb [30] + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_34 - process $group_34 - assign \rb64_34 1'0 - assign \rb64_34 \rb [29] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_35 - process $group_35 - assign \rb64_35 1'0 - assign \rb64_35 \rb [28] + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_36 - process $group_36 - assign \rb64_36 1'0 - assign \rb64_36 \rb [27] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_37 - process $group_37 - assign \rb64_37 1'0 - assign \rb64_37 \rb [26] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_38 - process $group_38 - assign \rb64_38 1'0 - assign \rb64_38 \rb [25] + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_39 - process $group_39 - assign \rb64_39 1'0 - assign \rb64_39 \rb [24] + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_40 - process $group_40 - assign \rb64_40 1'0 - assign \rb64_40 \rb [23] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_41 - process $group_41 - assign \rb64_41 1'0 - assign \rb64_41 \rb [22] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_42 - process $group_42 - assign \rb64_42 1'0 - assign \rb64_42 \rb [21] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_43 - process $group_43 - assign \rb64_43 1'0 - assign \rb64_43 \rb [20] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_44 - process $group_44 - assign \rb64_44 1'0 - assign \rb64_44 \rb [19] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_45 - process $group_45 - assign \rb64_45 1'0 - assign \rb64_45 \rb [18] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_46 - process $group_46 - assign \rb64_46 1'0 - assign \rb64_46 \rb [17] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_47 - process $group_47 - assign \rb64_47 1'0 - assign \rb64_47 \rb [16] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'111100 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_48 - process $group_48 - assign \rb64_48 1'0 - assign \rb64_48 \rb [15] +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.core_calculate_stage_3" +module \core_calculate_stage_3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$88 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_49 - process $group_49 - assign \rb64_49 1'0 - assign \rb64_49 \rb [14] + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_50 - process $group_50 - assign \rb64_50 1'0 - assign \rb64_50 \rb [13] + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_51 - process $group_51 - assign \rb64_51 1'0 - assign \rb64_51 \rb [12] + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_52 - process $group_52 - assign \rb64_52 1'0 - assign \rb64_52 \rb [11] + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_53 - process $group_53 - assign \rb64_53 1'0 - assign \rb64_53 \rb [10] + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_54 - process $group_54 - assign \rb64_54 1'0 - assign \rb64_54 \rb [9] + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_55 - process $group_55 - assign \rb64_55 1'0 - assign \rb64_55 \rb [8] + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_56 - process $group_56 - assign \rb64_56 1'0 - assign \rb64_56 \rb [7] + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_57 - process $group_57 - assign \rb64_57 1'0 - assign \rb64_57 \rb [6] + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_58 - process $group_58 - assign \rb64_58 1'0 - assign \rb64_58 \rb [5] + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_59 - process $group_59 - assign \rb64_59 1'0 - assign \rb64_59 \rb [4] + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_60 - process $group_60 - assign \rb64_60 1'0 - assign \rb64_60 \rb [3] + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_61 - process $group_61 - assign \rb64_61 1'0 - assign \rb64_61 \rb [2] + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_62 - process $group_62 - assign \rb64_62 1'0 - assign \rb64_62 \rb [1] + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_63 - process $group_63 - assign \rb64_63 1'0 - assign \rb64_63 \rb [0] + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_0 - process $group_64 - assign \idx_0 8'00000000 - assign \idx_0 \rs [7:0] + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" - wire width 64 \perm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_0 - connect \B 7'1000000 - connect \Y $1 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_1 - connect \B 7'1000000 - connect \Y $3 + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_2 - connect \B 7'1000000 - connect \Y $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_3 - connect \B 7'1000000 - connect \Y $7 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_4 - connect \B 7'1000000 - connect \Y $9 + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_5 - connect \B 7'1000000 - connect \Y $11 + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0" +module \pipe_middle_0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute 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"OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 41 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$77 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_6 - connect \B 7'1000000 - connect \Y $13 + cell \n$78 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_7 - connect \B 7'1000000 - connect \Y $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_0_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_0_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_0_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_0_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_0_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_0_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_0_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_0_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_0_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_0_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_0_muxid$34 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_0_logical_op__insn_type$35 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_0_logical_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_0_logical_op__imm_data__imm$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__imm_data__imm_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__invert_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_0_logical_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__write_cr0$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_0_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_0_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_0_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_0_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_0_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_0_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_0_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_0_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_0_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_0_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_0_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_0_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_0_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_0_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_0_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_0_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_0_compare_rhs$66 + cell \core_calculate_stage_0 \core_calculate_stage_0 + connect \muxid \core_calculate_stage_0_muxid + connect \logical_op__insn_type \core_calculate_stage_0_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_0_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_0_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_0_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_0_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_0_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_0_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_0_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_0_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_0_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_0_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_0_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_0_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_0_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_0_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_0_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_0_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_0_logical_op__insn + connect \ra \core_calculate_stage_0_ra + connect \rb \core_calculate_stage_0_rb + connect \xer_so \core_calculate_stage_0_xer_so + connect \divisor_neg \core_calculate_stage_0_divisor_neg + connect \dividend_neg \core_calculate_stage_0_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_0_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_0_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_0_div_by_zero + connect \divisor_radicand \core_calculate_stage_0_divisor_radicand + connect \operation \core_calculate_stage_0_operation + connect \quotient_root \core_calculate_stage_0_quotient_root + connect \root_times_radicand \core_calculate_stage_0_root_times_radicand + connect \compare_lhs \core_calculate_stage_0_compare_lhs + connect \compare_rhs \core_calculate_stage_0_compare_rhs + connect \muxid$1 \core_calculate_stage_0_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_0_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_0_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_0_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_0_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_0_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_0_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_0_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_0_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_0_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_0_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_0_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_0_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_0_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_0_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_0_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_0_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_0_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_0_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_0_ra$53 + connect \rb$21 \core_calculate_stage_0_rb$54 + connect \xer_so$22 \core_calculate_stage_0_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_0_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_0_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_0_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_0_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_0_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_0_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_0_operation$62 + connect \quotient_root$30 \core_calculate_stage_0_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_0_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_0_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_0_compare_rhs$66 end - process $group_65 - assign \perm 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_0 - case 8'00000000 - assign \perm [0] \rb64_0 - case 8'00000001 - assign \perm [0] \rb64_1 - case 8'00000010 - assign \perm [0] \rb64_2 - case 8'00000011 - assign \perm [0] \rb64_3 - case 8'00000100 - assign \perm [0] \rb64_4 - case 8'00000101 - assign \perm [0] \rb64_5 - case 8'00000110 - assign \perm [0] \rb64_6 - case 8'00000111 - assign \perm [0] \rb64_7 - case 8'00001000 - assign \perm [0] \rb64_8 - case 8'00001001 - assign \perm [0] \rb64_9 - case 8'00001010 - assign \perm [0] \rb64_10 - case 8'00001011 - assign \perm [0] \rb64_11 - case 8'00001100 - assign \perm [0] \rb64_12 - case 8'00001101 - assign \perm [0] \rb64_13 - case 8'00001110 - assign \perm [0] \rb64_14 - case 8'00001111 - assign \perm [0] \rb64_15 - case 8'00010000 - assign \perm [0] \rb64_16 - case 8'00010001 - assign \perm [0] \rb64_17 - case 8'00010010 - assign \perm [0] \rb64_18 - case 8'00010011 - assign \perm [0] \rb64_19 - case 8'00010100 - assign \perm [0] \rb64_20 - case 8'00010101 - assign \perm [0] \rb64_21 - case 8'00010110 - assign \perm [0] \rb64_22 - case 8'00010111 - assign \perm [0] \rb64_23 - case 8'00011000 - assign \perm [0] \rb64_24 - case 8'00011001 - assign \perm [0] \rb64_25 - case 8'00011010 - assign \perm [0] \rb64_26 - case 8'00011011 - assign \perm [0] \rb64_27 - case 8'00011100 - assign \perm [0] \rb64_28 - case 8'00011101 - assign \perm [0] \rb64_29 - case 8'00011110 - assign \perm [0] \rb64_30 - case 8'00011111 - assign \perm [0] \rb64_31 - case 8'00100000 - assign \perm [0] \rb64_32 - case 8'00100001 - assign \perm [0] \rb64_33 - case 8'00100010 - assign \perm [0] \rb64_34 - case 8'00100011 - assign \perm [0] \rb64_35 - case 8'00100100 - assign \perm [0] \rb64_36 - case 8'00100101 - assign \perm [0] \rb64_37 - case 8'00100110 - assign \perm [0] \rb64_38 - case 8'00100111 - assign \perm [0] \rb64_39 - case 8'00101000 - assign \perm [0] \rb64_40 - case 8'00101001 - assign \perm [0] \rb64_41 - case 8'00101010 - assign \perm [0] \rb64_42 - case 8'00101011 - assign \perm [0] \rb64_43 - case 8'00101100 - assign \perm [0] \rb64_44 - case 8'00101101 - assign \perm [0] \rb64_45 - case 8'00101110 - assign \perm [0] \rb64_46 - case 8'00101111 - assign \perm [0] \rb64_47 - case 8'00110000 - assign \perm [0] \rb64_48 - case 8'00110001 - assign \perm [0] \rb64_49 - case 8'00110010 - assign \perm [0] \rb64_50 - case 8'00110011 - assign \perm [0] \rb64_51 - case 8'00110100 - assign \perm [0] \rb64_52 - case 8'00110101 - assign \perm [0] \rb64_53 - case 8'00110110 - assign \perm [0] \rb64_54 - case 8'00110111 - assign \perm [0] \rb64_55 - case 8'00111000 - assign \perm [0] \rb64_56 - case 8'00111001 - assign \perm [0] \rb64_57 - case 8'00111010 - assign \perm [0] \rb64_58 - case 8'00111011 - assign \perm [0] \rb64_59 - case 8'00111100 - assign \perm [0] \rb64_60 - case 8'00111101 - assign \perm [0] \rb64_61 - case 8'00111110 - assign \perm [0] \rb64_62 - case 8'-------- - assign \perm [0] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_1 - case 8'00000000 - assign \perm [1] \rb64_0 - case 8'00000001 - assign \perm [1] \rb64_1 - case 8'00000010 - assign \perm [1] \rb64_2 - case 8'00000011 - assign \perm [1] \rb64_3 - case 8'00000100 - assign \perm [1] \rb64_4 - case 8'00000101 - assign \perm [1] \rb64_5 - case 8'00000110 - assign \perm [1] \rb64_6 - case 8'00000111 - assign \perm [1] \rb64_7 - case 8'00001000 - assign \perm [1] \rb64_8 - case 8'00001001 - assign \perm [1] \rb64_9 - case 8'00001010 - assign \perm [1] \rb64_10 - case 8'00001011 - assign \perm [1] \rb64_11 - case 8'00001100 - assign \perm [1] \rb64_12 - case 8'00001101 - assign \perm [1] \rb64_13 - case 8'00001110 - assign \perm [1] \rb64_14 - case 8'00001111 - assign \perm [1] \rb64_15 - case 8'00010000 - assign \perm [1] \rb64_16 - case 8'00010001 - assign \perm [1] \rb64_17 - case 8'00010010 - assign \perm [1] \rb64_18 - case 8'00010011 - assign \perm [1] \rb64_19 - case 8'00010100 - assign \perm [1] \rb64_20 - case 8'00010101 - assign \perm [1] \rb64_21 - case 8'00010110 - assign \perm [1] \rb64_22 - case 8'00010111 - assign \perm [1] \rb64_23 - case 8'00011000 - assign \perm [1] \rb64_24 - case 8'00011001 - assign \perm [1] \rb64_25 - case 8'00011010 - assign \perm [1] \rb64_26 - case 8'00011011 - assign \perm [1] \rb64_27 - case 8'00011100 - assign \perm [1] \rb64_28 - case 8'00011101 - assign \perm [1] \rb64_29 - case 8'00011110 - assign \perm [1] \rb64_30 - case 8'00011111 - assign \perm [1] \rb64_31 - case 8'00100000 - assign \perm [1] \rb64_32 - case 8'00100001 - assign \perm [1] \rb64_33 - case 8'00100010 - assign \perm [1] \rb64_34 - case 8'00100011 - assign \perm [1] \rb64_35 - case 8'00100100 - assign \perm [1] \rb64_36 - case 8'00100101 - assign \perm [1] \rb64_37 - case 8'00100110 - assign \perm [1] \rb64_38 - case 8'00100111 - assign \perm [1] \rb64_39 - case 8'00101000 - assign \perm [1] \rb64_40 - case 8'00101001 - assign \perm [1] \rb64_41 - case 8'00101010 - assign \perm [1] \rb64_42 - case 8'00101011 - assign \perm [1] \rb64_43 - case 8'00101100 - assign \perm [1] \rb64_44 - case 8'00101101 - assign \perm [1] \rb64_45 - case 8'00101110 - assign \perm [1] \rb64_46 - case 8'00101111 - assign \perm [1] \rb64_47 - case 8'00110000 - assign \perm [1] \rb64_48 - case 8'00110001 - assign \perm [1] \rb64_49 - case 8'00110010 - assign \perm [1] \rb64_50 - case 8'00110011 - assign \perm [1] \rb64_51 - case 8'00110100 - assign \perm [1] \rb64_52 - case 8'00110101 - assign \perm [1] \rb64_53 - case 8'00110110 - assign \perm [1] \rb64_54 - case 8'00110111 - assign \perm [1] \rb64_55 - case 8'00111000 - assign \perm [1] \rb64_56 - case 8'00111001 - assign \perm [1] \rb64_57 - case 8'00111010 - assign \perm [1] \rb64_58 - case 8'00111011 - assign \perm [1] \rb64_59 - case 8'00111100 - assign \perm [1] \rb64_60 - case 8'00111101 - assign \perm [1] \rb64_61 - case 8'00111110 - assign \perm [1] \rb64_62 - case 8'-------- - assign \perm [1] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_2 - case 8'00000000 - assign \perm [2] \rb64_0 - case 8'00000001 - assign \perm [2] \rb64_1 - case 8'00000010 - assign \perm [2] \rb64_2 - case 8'00000011 - assign \perm [2] \rb64_3 - case 8'00000100 - assign \perm [2] \rb64_4 - case 8'00000101 - assign \perm [2] \rb64_5 - case 8'00000110 - assign \perm [2] \rb64_6 - case 8'00000111 - assign \perm [2] \rb64_7 - case 8'00001000 - assign \perm [2] \rb64_8 - case 8'00001001 - assign \perm [2] \rb64_9 - case 8'00001010 - assign \perm [2] \rb64_10 - case 8'00001011 - assign \perm [2] \rb64_11 - case 8'00001100 - assign \perm [2] \rb64_12 - case 8'00001101 - assign \perm [2] \rb64_13 - case 8'00001110 - assign \perm [2] \rb64_14 - case 8'00001111 - assign \perm [2] \rb64_15 - case 8'00010000 - assign \perm [2] \rb64_16 - case 8'00010001 - assign \perm [2] \rb64_17 - case 8'00010010 - assign \perm [2] \rb64_18 - case 8'00010011 - assign \perm [2] \rb64_19 - case 8'00010100 - assign \perm [2] \rb64_20 - case 8'00010101 - assign \perm [2] \rb64_21 - case 8'00010110 - assign \perm [2] \rb64_22 - case 8'00010111 - assign \perm [2] \rb64_23 - case 8'00011000 - assign \perm [2] \rb64_24 - case 8'00011001 - assign \perm [2] \rb64_25 - case 8'00011010 - assign \perm [2] \rb64_26 - case 8'00011011 - assign \perm [2] \rb64_27 - case 8'00011100 - assign \perm [2] \rb64_28 - case 8'00011101 - assign \perm [2] \rb64_29 - case 8'00011110 - assign \perm [2] \rb64_30 - case 8'00011111 - assign \perm [2] \rb64_31 - case 8'00100000 - assign \perm [2] \rb64_32 - case 8'00100001 - assign \perm [2] \rb64_33 - case 8'00100010 - assign \perm [2] \rb64_34 - case 8'00100011 - assign \perm [2] \rb64_35 - case 8'00100100 - assign \perm [2] \rb64_36 - case 8'00100101 - assign \perm [2] \rb64_37 - case 8'00100110 - assign \perm [2] \rb64_38 - case 8'00100111 - assign \perm [2] \rb64_39 - case 8'00101000 - assign \perm [2] \rb64_40 - case 8'00101001 - assign \perm [2] \rb64_41 - case 8'00101010 - assign \perm [2] \rb64_42 - case 8'00101011 - assign \perm [2] \rb64_43 - case 8'00101100 - assign \perm [2] \rb64_44 - case 8'00101101 - assign \perm [2] \rb64_45 - case 8'00101110 - assign \perm [2] \rb64_46 - case 8'00101111 - assign \perm [2] \rb64_47 - case 8'00110000 - assign \perm [2] \rb64_48 - case 8'00110001 - assign \perm [2] \rb64_49 - case 8'00110010 - assign \perm [2] \rb64_50 - case 8'00110011 - assign \perm [2] \rb64_51 - case 8'00110100 - assign \perm [2] \rb64_52 - case 8'00110101 - assign \perm [2] \rb64_53 - case 8'00110110 - assign \perm [2] \rb64_54 - case 8'00110111 - assign \perm [2] \rb64_55 - case 8'00111000 - assign \perm [2] \rb64_56 - case 8'00111001 - assign \perm [2] \rb64_57 - case 8'00111010 - assign \perm [2] \rb64_58 - case 8'00111011 - assign \perm [2] \rb64_59 - case 8'00111100 - assign \perm [2] \rb64_60 - case 8'00111101 - assign \perm [2] \rb64_61 - case 8'00111110 - assign \perm [2] \rb64_62 - case 8'-------- - assign \perm [2] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_3 - case 8'00000000 - assign \perm [3] \rb64_0 - case 8'00000001 - assign \perm [3] \rb64_1 - case 8'00000010 - assign \perm [3] \rb64_2 - case 8'00000011 - assign \perm [3] \rb64_3 - case 8'00000100 - assign \perm [3] \rb64_4 - case 8'00000101 - assign \perm [3] \rb64_5 - case 8'00000110 - assign \perm [3] \rb64_6 - case 8'00000111 - assign \perm [3] \rb64_7 - case 8'00001000 - assign \perm [3] \rb64_8 - case 8'00001001 - assign \perm [3] \rb64_9 - case 8'00001010 - assign \perm [3] \rb64_10 - case 8'00001011 - assign \perm [3] \rb64_11 - case 8'00001100 - assign \perm [3] \rb64_12 - case 8'00001101 - assign \perm [3] \rb64_13 - case 8'00001110 - assign \perm [3] \rb64_14 - case 8'00001111 - assign \perm [3] \rb64_15 - case 8'00010000 - assign \perm [3] \rb64_16 - case 8'00010001 - assign \perm [3] \rb64_17 - case 8'00010010 - assign \perm [3] \rb64_18 - case 8'00010011 - assign \perm [3] \rb64_19 - case 8'00010100 - assign \perm [3] \rb64_20 - case 8'00010101 - assign \perm [3] \rb64_21 - case 8'00010110 - assign \perm [3] \rb64_22 - case 8'00010111 - assign \perm [3] \rb64_23 - case 8'00011000 - assign \perm [3] \rb64_24 - case 8'00011001 - assign \perm [3] \rb64_25 - case 8'00011010 - assign \perm [3] \rb64_26 - case 8'00011011 - assign \perm [3] \rb64_27 - case 8'00011100 - assign \perm [3] \rb64_28 - case 8'00011101 - assign \perm [3] \rb64_29 - case 8'00011110 - assign \perm [3] \rb64_30 - case 8'00011111 - assign \perm [3] \rb64_31 - case 8'00100000 - assign \perm [3] \rb64_32 - case 8'00100001 - assign \perm [3] \rb64_33 - case 8'00100010 - assign \perm [3] \rb64_34 - case 8'00100011 - assign \perm [3] \rb64_35 - case 8'00100100 - assign \perm [3] \rb64_36 - case 8'00100101 - assign \perm [3] \rb64_37 - case 8'00100110 - assign \perm [3] \rb64_38 - case 8'00100111 - assign \perm [3] \rb64_39 - case 8'00101000 - assign \perm [3] \rb64_40 - case 8'00101001 - assign \perm [3] \rb64_41 - case 8'00101010 - assign \perm [3] \rb64_42 - case 8'00101011 - assign \perm [3] \rb64_43 - case 8'00101100 - assign \perm [3] \rb64_44 - case 8'00101101 - assign \perm [3] \rb64_45 - case 8'00101110 - assign \perm [3] \rb64_46 - case 8'00101111 - assign \perm [3] \rb64_47 - case 8'00110000 - assign \perm [3] \rb64_48 - case 8'00110001 - assign \perm [3] \rb64_49 - case 8'00110010 - assign \perm [3] \rb64_50 - case 8'00110011 - assign \perm [3] \rb64_51 - case 8'00110100 - assign \perm [3] \rb64_52 - case 8'00110101 - assign \perm [3] \rb64_53 - case 8'00110110 - assign \perm [3] \rb64_54 - case 8'00110111 - assign \perm [3] \rb64_55 - case 8'00111000 - assign \perm [3] \rb64_56 - case 8'00111001 - assign \perm [3] \rb64_57 - case 8'00111010 - assign \perm [3] \rb64_58 - case 8'00111011 - assign \perm [3] \rb64_59 - case 8'00111100 - assign \perm [3] \rb64_60 - case 8'00111101 - assign \perm [3] \rb64_61 - case 8'00111110 - assign \perm [3] \rb64_62 - case 8'-------- - assign \perm [3] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_4 - case 8'00000000 - assign \perm [4] \rb64_0 - case 8'00000001 - assign \perm [4] \rb64_1 - case 8'00000010 - assign \perm [4] \rb64_2 - case 8'00000011 - assign \perm [4] \rb64_3 - case 8'00000100 - assign \perm [4] \rb64_4 - case 8'00000101 - assign \perm [4] \rb64_5 - case 8'00000110 - assign \perm [4] \rb64_6 - case 8'00000111 - assign \perm [4] \rb64_7 - case 8'00001000 - assign \perm [4] \rb64_8 - case 8'00001001 - assign \perm [4] \rb64_9 - case 8'00001010 - assign \perm [4] \rb64_10 - case 8'00001011 - assign \perm [4] \rb64_11 - case 8'00001100 - assign \perm [4] \rb64_12 - case 8'00001101 - assign \perm [4] \rb64_13 - case 8'00001110 - assign \perm [4] \rb64_14 - case 8'00001111 - assign \perm [4] \rb64_15 - case 8'00010000 - assign \perm [4] \rb64_16 - case 8'00010001 - assign \perm [4] \rb64_17 - case 8'00010010 - assign \perm [4] \rb64_18 - case 8'00010011 - assign \perm [4] \rb64_19 - case 8'00010100 - assign \perm [4] \rb64_20 - case 8'00010101 - assign \perm [4] \rb64_21 - case 8'00010110 - assign \perm [4] \rb64_22 - case 8'00010111 - assign \perm [4] \rb64_23 - case 8'00011000 - assign \perm [4] \rb64_24 - case 8'00011001 - assign \perm [4] \rb64_25 - case 8'00011010 - assign \perm [4] \rb64_26 - case 8'00011011 - assign \perm [4] \rb64_27 - case 8'00011100 - assign \perm [4] \rb64_28 - case 8'00011101 - assign \perm [4] \rb64_29 - case 8'00011110 - assign \perm [4] \rb64_30 - case 8'00011111 - assign \perm [4] \rb64_31 - case 8'00100000 - assign \perm [4] \rb64_32 - case 8'00100001 - assign \perm [4] \rb64_33 - case 8'00100010 - assign \perm [4] \rb64_34 - case 8'00100011 - assign \perm [4] \rb64_35 - case 8'00100100 - assign \perm [4] \rb64_36 - case 8'00100101 - assign \perm [4] \rb64_37 - case 8'00100110 - assign \perm [4] \rb64_38 - case 8'00100111 - assign \perm [4] \rb64_39 - case 8'00101000 - assign \perm [4] \rb64_40 - case 8'00101001 - assign \perm [4] \rb64_41 - case 8'00101010 - assign \perm [4] \rb64_42 - case 8'00101011 - assign \perm [4] \rb64_43 - case 8'00101100 - assign \perm [4] \rb64_44 - case 8'00101101 - assign \perm [4] \rb64_45 - case 8'00101110 - assign \perm [4] \rb64_46 - case 8'00101111 - assign \perm [4] \rb64_47 - case 8'00110000 - assign \perm [4] \rb64_48 - case 8'00110001 - assign \perm [4] \rb64_49 - case 8'00110010 - assign \perm [4] \rb64_50 - case 8'00110011 - assign \perm [4] \rb64_51 - case 8'00110100 - assign \perm [4] \rb64_52 - case 8'00110101 - assign \perm [4] \rb64_53 - case 8'00110110 - assign \perm [4] \rb64_54 - case 8'00110111 - assign \perm [4] \rb64_55 - case 8'00111000 - assign \perm [4] \rb64_56 - case 8'00111001 - assign \perm [4] \rb64_57 - case 8'00111010 - assign \perm [4] \rb64_58 - case 8'00111011 - assign \perm [4] \rb64_59 - case 8'00111100 - assign \perm [4] \rb64_60 - case 8'00111101 - assign \perm [4] \rb64_61 - case 8'00111110 - assign \perm [4] \rb64_62 - case 8'-------- - assign \perm [4] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_5 - case 8'00000000 - assign \perm [5] \rb64_0 - case 8'00000001 - assign \perm [5] \rb64_1 - case 8'00000010 - assign \perm [5] \rb64_2 - case 8'00000011 - assign \perm [5] \rb64_3 - case 8'00000100 - assign \perm [5] \rb64_4 - case 8'00000101 - assign \perm [5] \rb64_5 - case 8'00000110 - assign \perm [5] \rb64_6 - case 8'00000111 - assign \perm [5] \rb64_7 - case 8'00001000 - assign \perm [5] \rb64_8 - case 8'00001001 - assign \perm [5] \rb64_9 - case 8'00001010 - assign \perm [5] \rb64_10 - case 8'00001011 - assign \perm [5] \rb64_11 - case 8'00001100 - assign \perm [5] \rb64_12 - case 8'00001101 - assign \perm [5] \rb64_13 - case 8'00001110 - assign \perm [5] \rb64_14 - case 8'00001111 - assign \perm [5] \rb64_15 - case 8'00010000 - assign \perm [5] \rb64_16 - case 8'00010001 - assign \perm [5] \rb64_17 - case 8'00010010 - assign \perm [5] \rb64_18 - case 8'00010011 - assign \perm [5] \rb64_19 - case 8'00010100 - assign \perm [5] \rb64_20 - case 8'00010101 - assign \perm [5] \rb64_21 - case 8'00010110 - assign \perm [5] \rb64_22 - case 8'00010111 - assign \perm [5] \rb64_23 - case 8'00011000 - assign \perm [5] \rb64_24 - case 8'00011001 - assign \perm [5] \rb64_25 - case 8'00011010 - assign \perm [5] \rb64_26 - case 8'00011011 - assign \perm [5] \rb64_27 - case 8'00011100 - assign \perm [5] \rb64_28 - case 8'00011101 - assign \perm [5] \rb64_29 - case 8'00011110 - assign \perm [5] \rb64_30 - case 8'00011111 - assign \perm [5] \rb64_31 - case 8'00100000 - assign \perm [5] \rb64_32 - case 8'00100001 - assign \perm [5] \rb64_33 - case 8'00100010 - assign \perm [5] \rb64_34 - case 8'00100011 - assign \perm [5] \rb64_35 - case 8'00100100 - assign \perm [5] \rb64_36 - case 8'00100101 - assign \perm [5] \rb64_37 - case 8'00100110 - assign \perm [5] \rb64_38 - case 8'00100111 - assign \perm [5] \rb64_39 - case 8'00101000 - assign \perm [5] \rb64_40 - case 8'00101001 - assign \perm [5] \rb64_41 - case 8'00101010 - assign \perm [5] \rb64_42 - case 8'00101011 - assign \perm [5] \rb64_43 - case 8'00101100 - assign \perm [5] \rb64_44 - case 8'00101101 - assign \perm [5] \rb64_45 - case 8'00101110 - assign \perm [5] \rb64_46 - case 8'00101111 - assign \perm [5] \rb64_47 - case 8'00110000 - assign \perm [5] \rb64_48 - case 8'00110001 - assign \perm [5] \rb64_49 - case 8'00110010 - assign \perm [5] \rb64_50 - case 8'00110011 - assign \perm [5] \rb64_51 - case 8'00110100 - assign \perm [5] \rb64_52 - case 8'00110101 - assign \perm [5] \rb64_53 - case 8'00110110 - assign \perm [5] \rb64_54 - case 8'00110111 - assign \perm [5] \rb64_55 - case 8'00111000 - assign \perm [5] \rb64_56 - case 8'00111001 - assign \perm [5] \rb64_57 - case 8'00111010 - assign \perm [5] \rb64_58 - case 8'00111011 - assign \perm [5] \rb64_59 - case 8'00111100 - assign \perm [5] \rb64_60 - case 8'00111101 - assign \perm [5] \rb64_61 - case 8'00111110 - assign \perm [5] \rb64_62 - case 8'-------- - assign \perm [5] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_6 - case 8'00000000 - assign \perm [6] \rb64_0 - case 8'00000001 - assign \perm [6] \rb64_1 - case 8'00000010 - assign \perm [6] \rb64_2 - case 8'00000011 - assign \perm [6] \rb64_3 - case 8'00000100 - assign \perm [6] \rb64_4 - case 8'00000101 - assign \perm [6] \rb64_5 - case 8'00000110 - assign \perm [6] \rb64_6 - case 8'00000111 - assign \perm [6] \rb64_7 - case 8'00001000 - assign \perm [6] \rb64_8 - case 8'00001001 - assign \perm [6] \rb64_9 - case 8'00001010 - assign \perm [6] \rb64_10 - case 8'00001011 - assign \perm [6] \rb64_11 - case 8'00001100 - assign \perm [6] \rb64_12 - case 8'00001101 - assign \perm [6] \rb64_13 - case 8'00001110 - assign \perm [6] \rb64_14 - case 8'00001111 - assign \perm [6] \rb64_15 - case 8'00010000 - assign \perm [6] \rb64_16 - case 8'00010001 - assign \perm [6] \rb64_17 - case 8'00010010 - assign \perm [6] \rb64_18 - case 8'00010011 - assign \perm [6] \rb64_19 - case 8'00010100 - assign \perm [6] \rb64_20 - case 8'00010101 - assign \perm [6] \rb64_21 - case 8'00010110 - assign \perm [6] \rb64_22 - case 8'00010111 - assign \perm [6] \rb64_23 - case 8'00011000 - assign \perm [6] \rb64_24 - case 8'00011001 - assign \perm [6] \rb64_25 - case 8'00011010 - assign \perm [6] \rb64_26 - case 8'00011011 - assign \perm [6] \rb64_27 - case 8'00011100 - assign \perm [6] \rb64_28 - case 8'00011101 - assign \perm [6] \rb64_29 - case 8'00011110 - assign \perm [6] \rb64_30 - case 8'00011111 - assign \perm [6] \rb64_31 - case 8'00100000 - assign \perm [6] \rb64_32 - case 8'00100001 - assign \perm [6] \rb64_33 - case 8'00100010 - assign \perm [6] \rb64_34 - case 8'00100011 - assign \perm [6] \rb64_35 - case 8'00100100 - assign \perm [6] \rb64_36 - case 8'00100101 - assign \perm [6] \rb64_37 - case 8'00100110 - assign \perm [6] \rb64_38 - case 8'00100111 - assign \perm [6] \rb64_39 - case 8'00101000 - assign \perm [6] \rb64_40 - case 8'00101001 - assign \perm [6] \rb64_41 - case 8'00101010 - assign \perm [6] \rb64_42 - case 8'00101011 - assign \perm [6] \rb64_43 - case 8'00101100 - assign \perm [6] \rb64_44 - case 8'00101101 - assign \perm [6] \rb64_45 - case 8'00101110 - assign \perm [6] \rb64_46 - case 8'00101111 - assign \perm [6] \rb64_47 - case 8'00110000 - assign \perm [6] \rb64_48 - case 8'00110001 - assign \perm [6] \rb64_49 - case 8'00110010 - assign \perm [6] \rb64_50 - case 8'00110011 - assign \perm [6] \rb64_51 - case 8'00110100 - assign \perm [6] \rb64_52 - case 8'00110101 - assign \perm [6] \rb64_53 - case 8'00110110 - assign \perm [6] \rb64_54 - case 8'00110111 - assign \perm [6] \rb64_55 - case 8'00111000 - assign \perm [6] \rb64_56 - case 8'00111001 - assign \perm [6] \rb64_57 - case 8'00111010 - assign \perm [6] \rb64_58 - case 8'00111011 - assign \perm [6] \rb64_59 - case 8'00111100 - assign \perm [6] \rb64_60 - case 8'00111101 - assign \perm [6] \rb64_61 - case 8'00111110 - assign \perm [6] \rb64_62 - case 8'-------- - assign \perm [6] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_7 - case 8'00000000 - assign \perm [7] \rb64_0 - case 8'00000001 - assign \perm [7] \rb64_1 - case 8'00000010 - assign \perm [7] \rb64_2 - case 8'00000011 - assign \perm [7] \rb64_3 - case 8'00000100 - assign \perm [7] \rb64_4 - case 8'00000101 - assign \perm [7] \rb64_5 - case 8'00000110 - assign \perm [7] \rb64_6 - case 8'00000111 - assign \perm [7] \rb64_7 - case 8'00001000 - assign \perm [7] \rb64_8 - case 8'00001001 - assign \perm [7] \rb64_9 - case 8'00001010 - assign \perm [7] \rb64_10 - case 8'00001011 - assign \perm [7] \rb64_11 - case 8'00001100 - assign \perm [7] \rb64_12 - case 8'00001101 - assign \perm [7] \rb64_13 - case 8'00001110 - assign \perm [7] \rb64_14 - case 8'00001111 - assign \perm [7] \rb64_15 - case 8'00010000 - assign \perm [7] \rb64_16 - case 8'00010001 - assign \perm [7] \rb64_17 - case 8'00010010 - assign \perm [7] \rb64_18 - case 8'00010011 - assign \perm [7] \rb64_19 - case 8'00010100 - assign \perm [7] \rb64_20 - case 8'00010101 - assign \perm [7] \rb64_21 - case 8'00010110 - assign \perm [7] \rb64_22 - case 8'00010111 - assign \perm [7] \rb64_23 - case 8'00011000 - assign \perm [7] \rb64_24 - case 8'00011001 - assign \perm [7] \rb64_25 - case 8'00011010 - assign \perm [7] \rb64_26 - case 8'00011011 - assign \perm [7] \rb64_27 - case 8'00011100 - assign \perm [7] \rb64_28 - case 8'00011101 - assign \perm [7] \rb64_29 - case 8'00011110 - assign \perm [7] \rb64_30 - case 8'00011111 - assign \perm [7] \rb64_31 - case 8'00100000 - assign \perm [7] \rb64_32 - case 8'00100001 - assign \perm [7] \rb64_33 - case 8'00100010 - assign \perm [7] \rb64_34 - case 8'00100011 - assign \perm [7] \rb64_35 - case 8'00100100 - assign \perm [7] \rb64_36 - case 8'00100101 - assign \perm [7] \rb64_37 - case 8'00100110 - assign \perm [7] \rb64_38 - case 8'00100111 - assign \perm [7] \rb64_39 - case 8'00101000 - assign \perm [7] \rb64_40 - case 8'00101001 - assign \perm [7] \rb64_41 - case 8'00101010 - assign \perm [7] \rb64_42 - case 8'00101011 - assign \perm [7] \rb64_43 - case 8'00101100 - assign \perm [7] \rb64_44 - case 8'00101101 - assign \perm [7] \rb64_45 - case 8'00101110 - assign \perm [7] \rb64_46 - case 8'00101111 - assign \perm [7] \rb64_47 - case 8'00110000 - assign \perm [7] \rb64_48 - case 8'00110001 - assign \perm [7] \rb64_49 - case 8'00110010 - assign \perm [7] \rb64_50 - case 8'00110011 - assign \perm [7] \rb64_51 - case 8'00110100 - assign \perm [7] \rb64_52 - case 8'00110101 - assign \perm [7] \rb64_53 - case 8'00110110 - assign \perm [7] \rb64_54 - case 8'00110111 - assign \perm [7] \rb64_55 - case 8'00111000 - assign \perm [7] \rb64_56 - case 8'00111001 - assign \perm [7] \rb64_57 - case 8'00111010 - assign \perm [7] \rb64_58 - case 8'00111011 - assign \perm [7] \rb64_59 - case 8'00111100 - assign \perm [7] \rb64_60 - case 8'00111101 - assign \perm [7] \rb64_61 - case 8'00111110 - assign \perm [7] \rb64_62 - case 8'-------- - assign \perm [7] \rb64_63 - end - end - sync init - end - process $group_66 - assign \idx_1 8'00000000 - assign \idx_1 \rs [15:8] - sync init - end - process $group_67 - assign \idx_2 8'00000000 - assign \idx_2 \rs [23:16] - sync init - end - process $group_68 - assign \idx_3 8'00000000 - assign \idx_3 \rs [31:24] - sync init - end - process $group_69 - assign \idx_4 8'00000000 - assign \idx_4 \rs [39:32] - sync init - end - process $group_70 - assign \idx_5 8'00000000 - assign \idx_5 \rs [47:40] - sync init - end - process $group_71 - assign \idx_6 8'00000000 - assign \idx_6 \rs [55:48] - sync init - end - process $group_72 - assign \idx_7 8'00000000 - assign \idx_7 \rs [63:56] - sync init - end - process $group_73 - assign \ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra [7:0] \perm [7:0] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main.popcount" -module \popcount - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" - wire width 64 input 0 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" - wire width 64 input 1 \data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" - wire width 64 output 2 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [0] } - connect \B { 1'0 \a [1] } - connect \Y $2 - end - connect $1 $2 - process $group_0 - assign \pop_2_0 2'00 - assign \pop_2_0 $1 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [2] } - connect \B { 1'0 \a [3] } - connect \Y $5 - end - connect $4 $5 - process $group_1 - assign \pop_2_1 2'00 - assign \pop_2_1 $4 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [4] } - connect \B { 1'0 \a [5] } - connect \Y $8 - end - connect $7 $8 - process $group_2 - assign \pop_2_2 2'00 - assign \pop_2_2 $7 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [6] } - connect \B { 1'0 \a [7] } - connect \Y $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_1_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_1_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_1_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_1_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_1_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_1_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_1_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_1_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_1_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_1_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_1_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_1_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_1_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_1_muxid$67 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_1_logical_op__insn_type$68 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_1_logical_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_1_logical_op__imm_data__imm$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__imm_data__imm_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__rc__rc_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_1_logical_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__invert_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__write_cr0$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_1_logical_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_1_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_1_logical_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_1_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_1_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_1_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_1_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_1_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_1_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_1_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_1_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_1_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_1_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_1_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_1_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_1_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_1_compare_rhs$99 + cell \core_calculate_stage_1 \core_calculate_stage_1 + connect \muxid \core_calculate_stage_1_muxid + connect \logical_op__insn_type \core_calculate_stage_1_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_1_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_1_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_1_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_1_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_1_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_1_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_1_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_1_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_1_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_1_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_1_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_1_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_1_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_1_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_1_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_1_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_1_logical_op__insn + connect \ra \core_calculate_stage_1_ra + connect \rb \core_calculate_stage_1_rb + connect \xer_so \core_calculate_stage_1_xer_so + connect \divisor_neg \core_calculate_stage_1_divisor_neg + connect \dividend_neg \core_calculate_stage_1_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_1_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_1_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_1_div_by_zero + connect \divisor_radicand \core_calculate_stage_1_divisor_radicand + connect \operation \core_calculate_stage_1_operation + connect \quotient_root \core_calculate_stage_1_quotient_root + connect \root_times_radicand \core_calculate_stage_1_root_times_radicand + connect \compare_lhs \core_calculate_stage_1_compare_lhs + connect \compare_rhs \core_calculate_stage_1_compare_rhs + connect \muxid$1 \core_calculate_stage_1_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_1_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_1_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_1_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_1_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_1_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_1_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_1_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_1_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_1_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_1_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_1_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_1_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_1_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_1_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_1_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_1_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_1_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_1_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_1_ra$86 + connect \rb$21 \core_calculate_stage_1_rb$87 + connect \xer_so$22 \core_calculate_stage_1_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_1_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_1_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_1_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_1_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_1_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_1_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_1_operation$95 + connect \quotient_root$30 \core_calculate_stage_1_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_1_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_1_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_1_compare_rhs$99 end - connect $10 $11 - process $group_3 - assign \pop_2_3 2'00 - assign \pop_2_3 $10 [1:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_2_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_2_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_2_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_2_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_2_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_2_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_2_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_2_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_2_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_2_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_2_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_2_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_2_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_2_muxid$100 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_2_logical_op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_2_logical_op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_2_logical_op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__rc__rc$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__rc__rc_ok$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__oe__oe$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_2_logical_op__input_carry$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__invert_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__write_cr0$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__output_carry$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__is_32bit$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_2_logical_op__is_signed$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_2_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_2_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_2_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_2_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_2_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_2_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_2_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_2_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_2_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_2_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_2_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_2_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_2_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_2_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_2_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_2_compare_rhs$132 + cell \core_calculate_stage_2 \core_calculate_stage_2 + connect \muxid \core_calculate_stage_2_muxid + connect \logical_op__insn_type \core_calculate_stage_2_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_2_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_2_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_2_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_2_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_2_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_2_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_2_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_2_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_2_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_2_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_2_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_2_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_2_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_2_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_2_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_2_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_2_logical_op__insn + connect \ra \core_calculate_stage_2_ra + connect \rb \core_calculate_stage_2_rb + connect \xer_so \core_calculate_stage_2_xer_so + connect \divisor_neg \core_calculate_stage_2_divisor_neg + connect \dividend_neg \core_calculate_stage_2_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_2_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_2_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_2_div_by_zero + connect \divisor_radicand \core_calculate_stage_2_divisor_radicand + connect \operation \core_calculate_stage_2_operation + connect \quotient_root \core_calculate_stage_2_quotient_root + connect \root_times_radicand \core_calculate_stage_2_root_times_radicand + connect \compare_lhs \core_calculate_stage_2_compare_lhs + connect \compare_rhs \core_calculate_stage_2_compare_rhs + connect \muxid$1 \core_calculate_stage_2_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_2_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_2_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_2_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_2_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_2_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_2_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_2_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_2_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_2_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_2_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_2_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_2_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_2_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_2_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_2_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_2_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_2_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_2_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_2_ra$119 + connect \rb$21 \core_calculate_stage_2_rb$120 + connect \xer_so$22 \core_calculate_stage_2_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_2_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_2_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_2_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_2_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_2_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_2_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_2_operation$128 + connect \quotient_root$30 \core_calculate_stage_2_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_2_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_2_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_2_compare_rhs$132 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_3_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_3_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_3_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_3_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_3_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_3_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_3_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_3_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_3_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_3_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_3_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_3_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_3_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_3_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_3_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_3_muxid$133 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_3_logical_op__insn_type$134 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_3_logical_op__fn_unit$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_3_logical_op__imm_data__imm$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__imm_data__imm_ok$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__rc__rc$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__rc__rc_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__oe__oe$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__oe__oe_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__invert_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_3_logical_op__input_carry$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__invert_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__write_cr0$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__output_carry$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_3_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_3_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_3_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_3_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_3_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_3_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_3_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_3_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_3_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_3_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_3_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_3_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_3_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_3_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_3_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_3_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_3_compare_rhs$165 + cell \core_calculate_stage_3 \core_calculate_stage_3 + connect \muxid \core_calculate_stage_3_muxid + connect \logical_op__insn_type \core_calculate_stage_3_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_3_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_3_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_3_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_3_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_3_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_3_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_3_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_3_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_3_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_3_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_3_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_3_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_3_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_3_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_3_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_3_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_3_logical_op__insn + connect \ra \core_calculate_stage_3_ra + connect \rb \core_calculate_stage_3_rb + connect \xer_so \core_calculate_stage_3_xer_so + connect \divisor_neg \core_calculate_stage_3_divisor_neg + connect \dividend_neg \core_calculate_stage_3_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_3_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_3_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_3_div_by_zero + connect \divisor_radicand \core_calculate_stage_3_divisor_radicand + connect \operation \core_calculate_stage_3_operation + connect \quotient_root \core_calculate_stage_3_quotient_root + connect \root_times_radicand \core_calculate_stage_3_root_times_radicand + connect \compare_lhs \core_calculate_stage_3_compare_lhs + connect \compare_rhs \core_calculate_stage_3_compare_rhs + connect \muxid$1 \core_calculate_stage_3_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_3_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_3_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_3_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_3_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_3_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_3_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_3_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_3_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_3_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_3_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_3_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_3_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_3_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_3_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_3_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_3_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_3_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_3_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_3_ra$152 + connect \rb$21 \core_calculate_stage_3_rb$153 + connect \xer_so$22 \core_calculate_stage_3_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_3_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_3_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_3_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_3_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_3_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_3_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_3_operation$161 + connect \quotient_root$30 \core_calculate_stage_3_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_3_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_3_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_3_compare_rhs$165 + end + process $group_0 + assign \core_calculate_stage_0_muxid 2'00 + assign \core_calculate_stage_0_muxid \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [8] } - connect \B { 1'0 \a [9] } - connect \Y $14 + process $group_1 + assign \core_calculate_stage_0_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_0_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_0_logical_op__rc__rc 1'0 + assign \core_calculate_stage_0_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_0_logical_op__oe__oe 1'0 + assign \core_calculate_stage_0_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_0_logical_op__invert_in 1'0 + assign \core_calculate_stage_0_logical_op__zero_a 1'0 + assign \core_calculate_stage_0_logical_op__input_carry 2'00 + assign \core_calculate_stage_0_logical_op__invert_out 1'0 + assign \core_calculate_stage_0_logical_op__write_cr0 1'0 + assign \core_calculate_stage_0_logical_op__output_carry 1'0 + assign \core_calculate_stage_0_logical_op__is_32bit 1'0 + assign \core_calculate_stage_0_logical_op__is_signed 1'0 + assign \core_calculate_stage_0_logical_op__data_len 4'0000 + assign \core_calculate_stage_0_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_0_logical_op__insn \core_calculate_stage_0_logical_op__data_len \core_calculate_stage_0_logical_op__is_signed \core_calculate_stage_0_logical_op__is_32bit \core_calculate_stage_0_logical_op__output_carry \core_calculate_stage_0_logical_op__write_cr0 \core_calculate_stage_0_logical_op__invert_out \core_calculate_stage_0_logical_op__input_carry \core_calculate_stage_0_logical_op__zero_a \core_calculate_stage_0_logical_op__invert_in { \core_calculate_stage_0_logical_op__oe__oe_ok \core_calculate_stage_0_logical_op__oe__oe } { \core_calculate_stage_0_logical_op__rc__rc_ok \core_calculate_stage_0_logical_op__rc__rc } { \core_calculate_stage_0_logical_op__imm_data__imm_ok \core_calculate_stage_0_logical_op__imm_data__imm } \core_calculate_stage_0_logical_op__fn_unit \core_calculate_stage_0_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - connect $13 $14 - process $group_4 - assign \pop_2_4 2'00 - assign \pop_2_4 $13 [1:0] + process $group_19 + assign \core_calculate_stage_0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_ra \ra sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [10] } - connect \B { 1'0 \a [11] } - connect \Y $17 + process $group_20 + assign \core_calculate_stage_0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_rb \rb + sync init end - connect $16 $17 - process $group_5 - assign \pop_2_5 2'00 - assign \pop_2_5 $16 [1:0] + process $group_21 + assign \core_calculate_stage_0_xer_so 1'0 + assign \core_calculate_stage_0_xer_so \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [12] } - connect \B { 1'0 \a [13] } - connect \Y $20 + process $group_22 + assign \core_calculate_stage_0_divisor_neg 1'0 + assign \core_calculate_stage_0_divisor_neg \divisor_neg + sync init end - connect $19 $20 - process $group_6 - assign \pop_2_6 2'00 - assign \pop_2_6 $19 [1:0] + process $group_23 + assign \core_calculate_stage_0_dividend_neg 1'0 + assign \core_calculate_stage_0_dividend_neg \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [14] } - connect \B { 1'0 \a [15] } - connect \Y $23 + process $group_24 + assign \core_calculate_stage_0_dive_abs_ov32 1'0 + assign \core_calculate_stage_0_dive_abs_ov32 \dive_abs_ov32 + sync init end - connect $22 $23 - process $group_7 - assign \pop_2_7 2'00 - assign \pop_2_7 $22 [1:0] + process $group_25 + assign \core_calculate_stage_0_dive_abs_ov64 1'0 + assign \core_calculate_stage_0_dive_abs_ov64 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [16] } - connect \B { 1'0 \a [17] } - connect \Y $26 + process $group_26 + assign \core_calculate_stage_0_div_by_zero 1'0 + assign \core_calculate_stage_0_div_by_zero \div_by_zero + sync init end - connect $25 $26 - process $group_8 - assign \pop_2_8 2'00 - assign \pop_2_8 $25 [1:0] + process $group_27 + assign \core_calculate_stage_0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [18] } - connect \B { 1'0 \a [19] } - connect \Y $29 + process $group_28 + assign \core_calculate_stage_0_operation 2'00 + assign \core_calculate_stage_0_operation \operation + sync init end - connect $28 $29 - process $group_9 - assign \pop_2_9 2'00 - assign \pop_2_9 $28 [1:0] + process $group_29 + assign \core_calculate_stage_0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [20] } - connect \B { 1'0 \a [21] } - connect \Y $32 + process $group_30 + assign \core_calculate_stage_0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_root_times_radicand \root_times_radicand + sync init end - connect $31 $32 - process $group_10 - assign \pop_2_10 2'00 - assign \pop_2_10 $31 [1:0] + process $group_31 + assign \core_calculate_stage_0_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_compare_lhs \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [22] } - connect \B { 1'0 \a [23] } - connect \Y $35 + process $group_32 + assign \core_calculate_stage_0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_compare_rhs \compare_rhs + sync init end - connect $34 $35 - process $group_11 - assign \pop_2_11 2'00 - assign \pop_2_11 $34 [1:0] + process $group_33 + assign \core_calculate_stage_1_muxid 2'00 + assign \core_calculate_stage_1_muxid \core_calculate_stage_0_muxid$34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [24] } - connect \B { 1'0 \a [25] } - connect \Y $38 + process $group_34 + assign \core_calculate_stage_1_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_1_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_1_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_1_logical_op__rc__rc 1'0 + assign \core_calculate_stage_1_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_1_logical_op__oe__oe 1'0 + assign \core_calculate_stage_1_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_1_logical_op__invert_in 1'0 + assign \core_calculate_stage_1_logical_op__zero_a 1'0 + assign \core_calculate_stage_1_logical_op__input_carry 2'00 + assign \core_calculate_stage_1_logical_op__invert_out 1'0 + assign \core_calculate_stage_1_logical_op__write_cr0 1'0 + assign \core_calculate_stage_1_logical_op__output_carry 1'0 + assign \core_calculate_stage_1_logical_op__is_32bit 1'0 + assign \core_calculate_stage_1_logical_op__is_signed 1'0 + assign \core_calculate_stage_1_logical_op__data_len 4'0000 + assign \core_calculate_stage_1_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_1_logical_op__insn \core_calculate_stage_1_logical_op__data_len \core_calculate_stage_1_logical_op__is_signed \core_calculate_stage_1_logical_op__is_32bit \core_calculate_stage_1_logical_op__output_carry \core_calculate_stage_1_logical_op__write_cr0 \core_calculate_stage_1_logical_op__invert_out \core_calculate_stage_1_logical_op__input_carry \core_calculate_stage_1_logical_op__zero_a \core_calculate_stage_1_logical_op__invert_in { \core_calculate_stage_1_logical_op__oe__oe_ok \core_calculate_stage_1_logical_op__oe__oe } { \core_calculate_stage_1_logical_op__rc__rc_ok \core_calculate_stage_1_logical_op__rc__rc } { \core_calculate_stage_1_logical_op__imm_data__imm_ok \core_calculate_stage_1_logical_op__imm_data__imm } \core_calculate_stage_1_logical_op__fn_unit \core_calculate_stage_1_logical_op__insn_type } { \core_calculate_stage_0_logical_op__insn$52 \core_calculate_stage_0_logical_op__data_len$51 \core_calculate_stage_0_logical_op__is_signed$50 \core_calculate_stage_0_logical_op__is_32bit$49 \core_calculate_stage_0_logical_op__output_carry$48 \core_calculate_stage_0_logical_op__write_cr0$47 \core_calculate_stage_0_logical_op__invert_out$46 \core_calculate_stage_0_logical_op__input_carry$45 \core_calculate_stage_0_logical_op__zero_a$44 \core_calculate_stage_0_logical_op__invert_in$43 { \core_calculate_stage_0_logical_op__oe__oe_ok$42 \core_calculate_stage_0_logical_op__oe__oe$41 } { \core_calculate_stage_0_logical_op__rc__rc_ok$40 \core_calculate_stage_0_logical_op__rc__rc$39 } { \core_calculate_stage_0_logical_op__imm_data__imm_ok$38 \core_calculate_stage_0_logical_op__imm_data__imm$37 } \core_calculate_stage_0_logical_op__fn_unit$36 \core_calculate_stage_0_logical_op__insn_type$35 } + sync init end - connect $37 $38 - process $group_12 - assign \pop_2_12 2'00 - assign \pop_2_12 $37 [1:0] + process $group_52 + assign \core_calculate_stage_1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_ra \core_calculate_stage_0_ra$53 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [26] } - connect \B { 1'0 \a [27] } - connect \Y $41 + process $group_53 + assign \core_calculate_stage_1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_rb \core_calculate_stage_0_rb$54 + sync init end - connect $40 $41 - process $group_13 - assign \pop_2_13 2'00 - assign \pop_2_13 $40 [1:0] + process $group_54 + assign \core_calculate_stage_1_xer_so 1'0 + assign \core_calculate_stage_1_xer_so \core_calculate_stage_0_xer_so$55 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [28] } - connect \B { 1'0 \a [29] } - connect \Y $44 + process $group_55 + assign \core_calculate_stage_1_divisor_neg 1'0 + assign \core_calculate_stage_1_divisor_neg \core_calculate_stage_0_divisor_neg$56 + sync init end - connect $43 $44 - process $group_14 - assign \pop_2_14 2'00 - assign \pop_2_14 $43 [1:0] + process $group_56 + assign \core_calculate_stage_1_dividend_neg 1'0 + assign \core_calculate_stage_1_dividend_neg \core_calculate_stage_0_dividend_neg$57 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [30] } - connect \B { 1'0 \a [31] } - connect \Y $47 + process $group_57 + assign \core_calculate_stage_1_dive_abs_ov32 1'0 + assign \core_calculate_stage_1_dive_abs_ov32 \core_calculate_stage_0_dive_abs_ov32$58 + sync init end - connect $46 $47 - process $group_15 - assign \pop_2_15 2'00 - assign \pop_2_15 $46 [1:0] + process $group_58 + assign \core_calculate_stage_1_dive_abs_ov64 1'0 + assign \core_calculate_stage_1_dive_abs_ov64 \core_calculate_stage_0_dive_abs_ov64$59 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [32] } - connect \B { 1'0 \a [33] } - connect \Y $50 + process $group_59 + assign \core_calculate_stage_1_div_by_zero 1'0 + assign \core_calculate_stage_1_div_by_zero \core_calculate_stage_0_div_by_zero$60 + sync init end - connect $49 $50 - process $group_16 - assign \pop_2_16 2'00 - assign \pop_2_16 $49 [1:0] + process $group_60 + assign \core_calculate_stage_1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_divisor_radicand \core_calculate_stage_0_divisor_radicand$61 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [34] } - connect \B { 1'0 \a [35] } - connect \Y $53 + process $group_61 + assign \core_calculate_stage_1_operation 2'00 + assign \core_calculate_stage_1_operation \core_calculate_stage_0_operation$62 + sync init end - connect $52 $53 - process $group_17 - assign \pop_2_17 2'00 - assign \pop_2_17 $52 [1:0] + process $group_62 + assign \core_calculate_stage_1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_quotient_root \core_calculate_stage_0_quotient_root$63 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [36] } - connect \B { 1'0 \a [37] } - connect \Y $56 + process $group_63 + assign \core_calculate_stage_1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_root_times_radicand \core_calculate_stage_0_root_times_radicand$64 + sync init end - connect $55 $56 - process $group_18 - assign \pop_2_18 2'00 - assign \pop_2_18 $55 [1:0] + process $group_64 + assign \core_calculate_stage_1_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_compare_lhs \core_calculate_stage_0_compare_lhs$65 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [38] } - connect \B { 1'0 \a [39] } - connect \Y $59 + process $group_65 + assign \core_calculate_stage_1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_compare_rhs \core_calculate_stage_0_compare_rhs$66 + sync init end - connect $58 $59 - process $group_19 - assign \pop_2_19 2'00 - assign \pop_2_19 $58 [1:0] + process $group_66 + assign \core_calculate_stage_2_muxid 2'00 + assign \core_calculate_stage_2_muxid \core_calculate_stage_1_muxid$67 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [40] } - connect \B { 1'0 \a [41] } - connect \Y $62 + process $group_67 + assign \core_calculate_stage_2_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_2_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_2_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_2_logical_op__rc__rc 1'0 + assign \core_calculate_stage_2_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_2_logical_op__oe__oe 1'0 + assign \core_calculate_stage_2_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_2_logical_op__invert_in 1'0 + assign \core_calculate_stage_2_logical_op__zero_a 1'0 + assign \core_calculate_stage_2_logical_op__input_carry 2'00 + assign \core_calculate_stage_2_logical_op__invert_out 1'0 + assign \core_calculate_stage_2_logical_op__write_cr0 1'0 + assign \core_calculate_stage_2_logical_op__output_carry 1'0 + assign \core_calculate_stage_2_logical_op__is_32bit 1'0 + assign \core_calculate_stage_2_logical_op__is_signed 1'0 + assign \core_calculate_stage_2_logical_op__data_len 4'0000 + assign \core_calculate_stage_2_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_2_logical_op__insn \core_calculate_stage_2_logical_op__data_len \core_calculate_stage_2_logical_op__is_signed \core_calculate_stage_2_logical_op__is_32bit \core_calculate_stage_2_logical_op__output_carry \core_calculate_stage_2_logical_op__write_cr0 \core_calculate_stage_2_logical_op__invert_out \core_calculate_stage_2_logical_op__input_carry \core_calculate_stage_2_logical_op__zero_a \core_calculate_stage_2_logical_op__invert_in { \core_calculate_stage_2_logical_op__oe__oe_ok \core_calculate_stage_2_logical_op__oe__oe } { \core_calculate_stage_2_logical_op__rc__rc_ok \core_calculate_stage_2_logical_op__rc__rc } { \core_calculate_stage_2_logical_op__imm_data__imm_ok \core_calculate_stage_2_logical_op__imm_data__imm } \core_calculate_stage_2_logical_op__fn_unit \core_calculate_stage_2_logical_op__insn_type } { \core_calculate_stage_1_logical_op__insn$85 \core_calculate_stage_1_logical_op__data_len$84 \core_calculate_stage_1_logical_op__is_signed$83 \core_calculate_stage_1_logical_op__is_32bit$82 \core_calculate_stage_1_logical_op__output_carry$81 \core_calculate_stage_1_logical_op__write_cr0$80 \core_calculate_stage_1_logical_op__invert_out$79 \core_calculate_stage_1_logical_op__input_carry$78 \core_calculate_stage_1_logical_op__zero_a$77 \core_calculate_stage_1_logical_op__invert_in$76 { \core_calculate_stage_1_logical_op__oe__oe_ok$75 \core_calculate_stage_1_logical_op__oe__oe$74 } { \core_calculate_stage_1_logical_op__rc__rc_ok$73 \core_calculate_stage_1_logical_op__rc__rc$72 } { \core_calculate_stage_1_logical_op__imm_data__imm_ok$71 \core_calculate_stage_1_logical_op__imm_data__imm$70 } \core_calculate_stage_1_logical_op__fn_unit$69 \core_calculate_stage_1_logical_op__insn_type$68 } + sync init end - connect $61 $62 - process $group_20 - assign \pop_2_20 2'00 - assign \pop_2_20 $61 [1:0] + process $group_85 + assign \core_calculate_stage_2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_ra \core_calculate_stage_1_ra$86 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [42] } - connect \B { 1'0 \a [43] } - connect \Y $65 + process $group_86 + assign \core_calculate_stage_2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_rb \core_calculate_stage_1_rb$87 + sync init end - connect $64 $65 - process $group_21 - assign \pop_2_21 2'00 - assign \pop_2_21 $64 [1:0] + process $group_87 + assign \core_calculate_stage_2_xer_so 1'0 + assign \core_calculate_stage_2_xer_so \core_calculate_stage_1_xer_so$88 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [44] } - connect \B { 1'0 \a [45] } - connect \Y $68 + process $group_88 + assign \core_calculate_stage_2_divisor_neg 1'0 + assign \core_calculate_stage_2_divisor_neg \core_calculate_stage_1_divisor_neg$89 + sync init end - connect $67 $68 - process $group_22 - assign \pop_2_22 2'00 - assign \pop_2_22 $67 [1:0] + process $group_89 + assign \core_calculate_stage_2_dividend_neg 1'0 + assign \core_calculate_stage_2_dividend_neg \core_calculate_stage_1_dividend_neg$90 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [46] } - connect \B { 1'0 \a [47] } - connect \Y $71 + process $group_90 + assign \core_calculate_stage_2_dive_abs_ov32 1'0 + assign \core_calculate_stage_2_dive_abs_ov32 \core_calculate_stage_1_dive_abs_ov32$91 + sync init end - connect $70 $71 - process $group_23 - assign \pop_2_23 2'00 - assign \pop_2_23 $70 [1:0] + process $group_91 + assign \core_calculate_stage_2_dive_abs_ov64 1'0 + assign \core_calculate_stage_2_dive_abs_ov64 \core_calculate_stage_1_dive_abs_ov64$92 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [48] } - connect \B { 1'0 \a [49] } - connect \Y $74 + process $group_92 + assign \core_calculate_stage_2_div_by_zero 1'0 + assign \core_calculate_stage_2_div_by_zero \core_calculate_stage_1_div_by_zero$93 + sync init end - connect $73 $74 - process $group_24 - assign \pop_2_24 2'00 - assign \pop_2_24 $73 [1:0] + process $group_93 + assign \core_calculate_stage_2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_divisor_radicand \core_calculate_stage_1_divisor_radicand$94 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [50] } - connect \B { 1'0 \a [51] } - connect \Y $77 + process $group_94 + assign \core_calculate_stage_2_operation 2'00 + assign \core_calculate_stage_2_operation \core_calculate_stage_1_operation$95 + sync init end - connect $76 $77 - process $group_25 - assign \pop_2_25 2'00 - assign \pop_2_25 $76 [1:0] + process $group_95 + assign \core_calculate_stage_2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_quotient_root \core_calculate_stage_1_quotient_root$96 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [52] } - connect \B { 1'0 \a [53] } - connect \Y $80 + process $group_96 + assign \core_calculate_stage_2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_root_times_radicand \core_calculate_stage_1_root_times_radicand$97 + sync init end - connect $79 $80 - process $group_26 - assign \pop_2_26 2'00 - assign \pop_2_26 $79 [1:0] + process $group_97 + assign \core_calculate_stage_2_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_compare_lhs \core_calculate_stage_1_compare_lhs$98 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [54] } - connect \B { 1'0 \a [55] } - connect \Y $83 + process $group_98 + assign \core_calculate_stage_2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_compare_rhs \core_calculate_stage_1_compare_rhs$99 + sync init end - connect $82 $83 - process $group_27 - assign \pop_2_27 2'00 - assign \pop_2_27 $82 [1:0] + process $group_99 + assign \core_calculate_stage_3_muxid 2'00 + assign \core_calculate_stage_3_muxid \core_calculate_stage_2_muxid$100 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [56] } - connect \B { 1'0 \a [57] } - connect \Y $86 + process $group_100 + assign \core_calculate_stage_3_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_3_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_3_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_3_logical_op__rc__rc 1'0 + assign \core_calculate_stage_3_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_3_logical_op__oe__oe 1'0 + assign \core_calculate_stage_3_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_3_logical_op__invert_in 1'0 + assign \core_calculate_stage_3_logical_op__zero_a 1'0 + assign \core_calculate_stage_3_logical_op__input_carry 2'00 + assign \core_calculate_stage_3_logical_op__invert_out 1'0 + assign \core_calculate_stage_3_logical_op__write_cr0 1'0 + assign \core_calculate_stage_3_logical_op__output_carry 1'0 + assign \core_calculate_stage_3_logical_op__is_32bit 1'0 + assign \core_calculate_stage_3_logical_op__is_signed 1'0 + assign \core_calculate_stage_3_logical_op__data_len 4'0000 + assign \core_calculate_stage_3_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_3_logical_op__insn \core_calculate_stage_3_logical_op__data_len \core_calculate_stage_3_logical_op__is_signed \core_calculate_stage_3_logical_op__is_32bit \core_calculate_stage_3_logical_op__output_carry \core_calculate_stage_3_logical_op__write_cr0 \core_calculate_stage_3_logical_op__invert_out \core_calculate_stage_3_logical_op__input_carry \core_calculate_stage_3_logical_op__zero_a \core_calculate_stage_3_logical_op__invert_in { \core_calculate_stage_3_logical_op__oe__oe_ok \core_calculate_stage_3_logical_op__oe__oe } { \core_calculate_stage_3_logical_op__rc__rc_ok \core_calculate_stage_3_logical_op__rc__rc } { \core_calculate_stage_3_logical_op__imm_data__imm_ok \core_calculate_stage_3_logical_op__imm_data__imm } \core_calculate_stage_3_logical_op__fn_unit \core_calculate_stage_3_logical_op__insn_type } { \core_calculate_stage_2_logical_op__insn$118 \core_calculate_stage_2_logical_op__data_len$117 \core_calculate_stage_2_logical_op__is_signed$116 \core_calculate_stage_2_logical_op__is_32bit$115 \core_calculate_stage_2_logical_op__output_carry$114 \core_calculate_stage_2_logical_op__write_cr0$113 \core_calculate_stage_2_logical_op__invert_out$112 \core_calculate_stage_2_logical_op__input_carry$111 \core_calculate_stage_2_logical_op__zero_a$110 \core_calculate_stage_2_logical_op__invert_in$109 { \core_calculate_stage_2_logical_op__oe__oe_ok$108 \core_calculate_stage_2_logical_op__oe__oe$107 } { \core_calculate_stage_2_logical_op__rc__rc_ok$106 \core_calculate_stage_2_logical_op__rc__rc$105 } { \core_calculate_stage_2_logical_op__imm_data__imm_ok$104 \core_calculate_stage_2_logical_op__imm_data__imm$103 } \core_calculate_stage_2_logical_op__fn_unit$102 \core_calculate_stage_2_logical_op__insn_type$101 } + sync init end - connect $85 $86 - process $group_28 - assign \pop_2_28 2'00 - assign \pop_2_28 $85 [1:0] + process $group_118 + assign \core_calculate_stage_3_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_ra \core_calculate_stage_2_ra$119 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [58] } - connect \B { 1'0 \a [59] } - connect \Y $89 + process $group_119 + assign \core_calculate_stage_3_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_rb \core_calculate_stage_2_rb$120 + sync init end - connect $88 $89 - process $group_29 - assign \pop_2_29 2'00 - assign \pop_2_29 $88 [1:0] + process $group_120 + assign \core_calculate_stage_3_xer_so 1'0 + assign \core_calculate_stage_3_xer_so \core_calculate_stage_2_xer_so$121 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [60] } - connect \B { 1'0 \a [61] } - connect \Y $92 + process $group_121 + assign \core_calculate_stage_3_divisor_neg 1'0 + assign \core_calculate_stage_3_divisor_neg \core_calculate_stage_2_divisor_neg$122 + sync init end - connect $91 $92 - process $group_30 - assign \pop_2_30 2'00 - assign \pop_2_30 $91 [1:0] + process $group_122 + assign \core_calculate_stage_3_dividend_neg 1'0 + assign \core_calculate_stage_3_dividend_neg \core_calculate_stage_2_dividend_neg$123 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [62] } - connect \B { 1'0 \a [63] } - connect \Y $95 + process $group_123 + assign \core_calculate_stage_3_dive_abs_ov32 1'0 + assign \core_calculate_stage_3_dive_abs_ov32 \core_calculate_stage_2_dive_abs_ov32$124 + sync init end - connect $94 $95 - process $group_31 - assign \pop_2_31 2'00 - assign \pop_2_31 $94 [1:0] + process $group_124 + assign \core_calculate_stage_3_dive_abs_ov64 1'0 + assign \core_calculate_stage_3_dive_abs_ov64 \core_calculate_stage_2_dive_abs_ov64$125 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_0 } - connect \B { 1'0 \pop_2_1 } - connect \Y $98 + process $group_125 + assign \core_calculate_stage_3_div_by_zero 1'0 + assign \core_calculate_stage_3_div_by_zero \core_calculate_stage_2_div_by_zero$126 + sync init end - connect $97 $98 - process $group_32 - assign \pop_3_0 3'000 - assign \pop_3_0 $97 [2:0] + process $group_126 + assign \core_calculate_stage_3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_divisor_radicand \core_calculate_stage_2_divisor_radicand$127 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_2 } - connect \B { 1'0 \pop_2_3 } - connect \Y $101 + process $group_127 + assign \core_calculate_stage_3_operation 2'00 + assign \core_calculate_stage_3_operation \core_calculate_stage_2_operation$128 + sync init end - connect $100 $101 - process $group_33 - assign \pop_3_1 3'000 - assign \pop_3_1 $100 [2:0] + process $group_128 + assign \core_calculate_stage_3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_quotient_root \core_calculate_stage_2_quotient_root$129 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_4 } - connect \B { 1'0 \pop_2_5 } - connect \Y $104 + process $group_129 + assign \core_calculate_stage_3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_root_times_radicand \core_calculate_stage_2_root_times_radicand$130 + sync init end - connect $103 $104 - process $group_34 - assign \pop_3_2 3'000 - assign \pop_3_2 $103 [2:0] + process $group_130 + assign \core_calculate_stage_3_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_compare_lhs \core_calculate_stage_2_compare_lhs$131 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_6 } - connect \B { 1'0 \pop_2_7 } - connect \Y $107 + process $group_131 + assign \core_calculate_stage_3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_compare_rhs \core_calculate_stage_2_compare_rhs$132 + sync init end - connect $106 $107 - process $group_35 - assign \pop_3_3 3'000 - assign \pop_3_3 $106 [2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_8 } - connect \B { 1'0 \pop_2_9 } - connect \Y $110 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 end - connect $109 $110 - process $group_36 - assign \pop_3_4 3'000 - assign \pop_3_4 $109 [2:0] + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_10 } - connect \B { 1'0 \pop_2_11 } - connect \Y $113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_3_muxid$133 + sync init end - connect $112 $113 - process $group_37 - assign \pop_3_5 3'000 - assign \pop_3_5 $112 [2:0] + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_3_logical_op__insn$151 \core_calculate_stage_3_logical_op__data_len$150 \core_calculate_stage_3_logical_op__is_signed$149 \core_calculate_stage_3_logical_op__is_32bit$148 \core_calculate_stage_3_logical_op__output_carry$147 \core_calculate_stage_3_logical_op__write_cr0$146 \core_calculate_stage_3_logical_op__invert_out$145 \core_calculate_stage_3_logical_op__input_carry$144 \core_calculate_stage_3_logical_op__zero_a$143 \core_calculate_stage_3_logical_op__invert_in$142 { \core_calculate_stage_3_logical_op__oe__oe_ok$141 \core_calculate_stage_3_logical_op__oe__oe$140 } { \core_calculate_stage_3_logical_op__rc__rc_ok$139 \core_calculate_stage_3_logical_op__rc__rc$138 } { \core_calculate_stage_3_logical_op__imm_data__imm_ok$137 \core_calculate_stage_3_logical_op__imm_data__imm$136 } \core_calculate_stage_3_logical_op__fn_unit$135 \core_calculate_stage_3_logical_op__insn_type$134 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_12 } - connect \B { 1'0 \pop_2_13 } - connect \Y $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_3_ra$152 + sync init end - connect $115 $116 - process $group_38 - assign \pop_3_6 3'000 - assign \pop_3_6 $115 [2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_3_rb$153 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_14 } - connect \B { 1'0 \pop_2_15 } - connect \Y $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_3_xer_so$154 + sync init end - connect $118 $119 - process $group_39 - assign \pop_3_7 3'000 - assign \pop_3_7 $118 [2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_3_divisor_neg$155 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_16 } - connect \B { 1'0 \pop_2_17 } - connect \Y $122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_3_dividend_neg$156 + sync init end - connect $121 $122 - process $group_40 - assign \pop_3_8 3'000 - assign \pop_3_8 $121 [2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_3_dive_abs_ov32$157 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_18 } - connect \B { 1'0 \pop_2_19 } - connect \Y $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_3_dive_abs_ov64$158 + sync init end - connect $124 $125 - process $group_41 - assign \pop_3_9 3'000 - assign \pop_3_9 $124 [2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_3_div_by_zero$159 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_20 } - connect \B { 1'0 \pop_2_21 } - connect \Y $128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_3_divisor_radicand$160 + sync init end - connect $127 $128 - process $group_42 - assign \pop_3_10 3'000 - assign \pop_3_10 $127 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_3_operation$161 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_22 } - connect \B { 1'0 \pop_2_23 } - connect \Y $131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_3_quotient_root$162 + sync init end - connect $130 $131 - process $group_43 - assign \pop_3_11 3'000 - assign \pop_3_11 $130 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_3_root_times_radicand$163 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_24 } - connect \B { 1'0 \pop_2_25 } - connect \Y $134 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_3_compare_lhs$164 + sync init end - connect $133 $134 - process $group_44 - assign \pop_3_12 3'000 - assign \pop_3_12 $133 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_3_compare_rhs$165 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_26 } - connect \B { 1'0 \pop_2_27 } - connect \Y $137 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next end - connect $136 $137 - process $group_45 - assign \pop_3_13 3'000 - assign \pop_3_13 $136 [2:0] + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_28 } - connect \B { 1'0 \pop_2_29 } - connect \Y $140 + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next end - connect $139 $140 - process $group_46 - assign \pop_3_14 3'000 - assign \pop_3_14 $139 [2:0] + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_30 } - connect \B { 1'0 \pop_2_31 } - connect \Y $143 + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next end - connect $142 $143 - process $group_47 - assign \pop_3_15 3'000 - assign \pop_3_15 $142 [2:0] + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_0 } - connect \B { 1'0 \pop_3_1 } - connect \Y $146 + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end + sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next end - connect $145 $146 - process $group_48 - assign \pop_4_0 4'0000 - assign \pop_4_0 $145 [3:0] + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_2 } - connect \B { 1'0 \pop_3_3 } - connect \Y $149 + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next end - connect $148 $149 - process $group_49 - assign \pop_4_1 4'0000 - assign \pop_4_1 $148 [3:0] + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_4 } - connect \B { 1'0 \pop_3_5 } - connect \Y $152 + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next end - connect $151 $152 - process $group_50 - assign \pop_4_2 4'0000 - assign \pop_4_2 $151 [3:0] + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_6 } - connect \B { 1'0 \pop_3_7 } - connect \Y $155 + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next end - connect $154 $155 - process $group_51 - assign \pop_4_3 4'0000 - assign \pop_4_3 $154 [3:0] + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_8 } - connect \B { 1'0 \pop_3_9 } - connect \Y $158 + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next end - connect $157 $158 - process $group_52 - assign \pop_4_4 4'0000 - assign \pop_4_4 $157 [3:0] + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $162 + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.p" +module \p$92 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_10 } - connect \B { 1'0 \pop_3_11 } - connect \Y $161 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 end - connect $160 $161 - process $group_53 - assign \pop_4_5 4'0000 - assign \pop_4_5 $160 [3:0] + process $group_0 + assign \trigger 1'0 + assign \trigger $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $165 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.n" +module \n$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_12 } - connect \B { 1'0 \pop_3_13 } - connect \Y $164 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 end - connect $163 $164 - process $group_54 - assign \pop_4_6 4'0000 - assign \pop_4_6 $163 [3:0] + process $group_0 + assign \trigger 1'0 + assign \trigger $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $168 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_4.core.trial0" +module \trial0$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_14 } - connect \B { 1'0 \pop_3_15 } - connect \Y $167 - end - connect $166 $167 - process $group_55 - assign \pop_4_7 4'0000 - assign \pop_4_7 $166 [3:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'0 \pop_4_0 } - connect \B { 1'0 \pop_4_1 } - connect \Y $170 - end - connect $169 $170 - process $group_56 - assign \pop_5_0 5'00000 - assign \pop_5_0 $169 [4:0] - sync init + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $174 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'0 \pop_4_2 } - connect \B { 1'0 \pop_4_3 } - connect \Y $173 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - connect $172 $173 - process $group_57 - assign \pop_5_1 5'00000 - assign \pop_5_1 $172 [4:0] + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $177 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'0 \pop_4_4 } - connect \B { 1'0 \pop_4_5 } - connect \Y $176 - end - connect $175 $176 - process $group_58 - assign \pop_5_2 5'00000 - assign \pop_5_2 $175 [4:0] - sync init + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $180 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'0 \pop_4_6 } - connect \B { 1'0 \pop_4_7 } - connect \Y $179 - end - connect $178 $179 - process $group_59 - assign \pop_5_3 5'00000 - assign \pop_5_3 $178 [4:0] - sync init + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111011 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 6 \pop_6_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 7 $181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 7 $182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $183 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A { 1'0 \pop_5_0 } - connect \B { 1'0 \pop_5_1 } - connect \Y $182 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - connect $181 $182 - process $group_60 - assign \pop_6_0 6'000000 - assign \pop_6_0 $181 [5:0] + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 6 \pop_6_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 7 $184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 7 $185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $186 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_4.core.trial1" +module \trial1$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A { 1'0 \pop_5_2 } - connect \B { 1'0 \pop_5_3 } - connect \Y $185 - end - connect $184 $185 - process $group_61 - assign \pop_6_1 6'000000 - assign \pop_6_1 $184 [5:0] - sync init + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 7 \pop_7_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 8 $187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 8 $188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $189 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A { 1'0 \pop_6_0 } - connect \B { 1'0 \pop_6_1 } - connect \Y $188 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - connect $187 $188 - process $group_62 - assign \pop_7_0 7'0000000 - assign \pop_7_0 $187 [6:0] + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - wire width 1 $190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $191 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_len + connect \A \operation connect \B 1'1 - connect \Y $190 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - wire width 1 $192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $193 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \data_len - connect \B 3'100 - connect \Y $192 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_0 - connect \Y $194 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_1 - connect \Y $196 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_2 - connect \Y $198 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_3 - connect \Y $200 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_4 - connect \Y $202 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_5 - connect \Y $204 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_6 - connect \Y $206 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111011 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $209 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_7 - connect \Y $208 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 32 $210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 32 - connect \A \pop_6_0 - connect \Y $210 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 32 $212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 32 - connect \A \pop_6_1 - connect \Y $212 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_4.core.pe" +module \pe$97 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 64 $214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $215 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \pop_7_0 - connect \Y $214 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_63 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - switch { $192 $190 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - case 2'-1 - assign \o [7:0] $194 - assign \o [15:8] $196 - assign \o [23:16] $198 - assign \o [31:24] $200 - assign \o [39:32] $202 - assign \o [47:40] $204 - assign \o [55:48] $206 - assign \o [63:56] $208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - case 2'1- - assign \o [31:0] $210 - assign \o [63:32] $212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:63" - case - assign \o $214 - end + process $group_1 + assign \n 1'0 + assign \n $1 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main.clz" -module \clz - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" - wire width 64 input 0 \sig_in - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - wire width 7 output 1 \lz - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair0 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_4.core" +module \core$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$95 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$96 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$97 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end process $group_0 - assign \pair0 2'00 - assign \pair0 \sig_in [1:0] + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_0 process $group_1 - assign \cnt_1_0 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_0 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_0 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_0 2'00 - end + assign \operation$2 2'00 + assign \operation$2 \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair2 process $group_2 - assign \pair2 2'00 - assign \pair2 \sig_in [3:2] + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_1 process $group_3 - assign \cnt_1_1 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_1 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_1 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_1 2'00 - end + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 process $group_4 - assign \pair4 2'00 - assign \pair4 \sig_in [5:4] + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 process $group_5 - assign \cnt_1_2 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_2 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_2 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_2 2'00 - end + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair6 process $group_6 - assign \pair6 2'00 - assign \pair6 \sig_in [7:6] + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_3 process $group_7 - assign \cnt_1_3 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_3 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_3 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_3 2'00 - end + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger process $group_8 - assign \pair8 2'00 - assign \pair8 \sig_in [9:8] + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_4 process $group_9 - assign \cnt_1_4 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_4 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_4 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_4 2'00 - end + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 process $group_10 - assign \pair10 2'00 - assign \pair10 \sig_in [11:10] + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 process $group_11 - assign \cnt_1_5 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_5 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_5 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_5 2'00 - end + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair12 process $group_12 - assign \pair12 2'00 - assign \pair12 \sig_in [13:12] + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_6 process $group_13 - assign \cnt_1_6 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_6 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_6 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_6 2'00 - end + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end process $group_14 - assign \pair14 2'00 - assign \pair14 \sig_in [15:14] + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags process $group_15 - assign \cnt_1_7 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_7 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_7 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_7 2'00 - end + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end process $group_16 - assign \pair16 2'00 - assign \pair16 \sig_in [17:16] + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 process $group_17 - assign \cnt_1_8 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_8 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_8 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" case - assign \cnt_1_8 2'00 + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair18 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end process $group_18 - assign \pair18 2'00 - assign \pair18 \sig_in [19:18] + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end process $group_19 - assign \cnt_1_9 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_9 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_9 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_9 2'00 - end + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end process $group_20 - assign \pair20 2'00 - assign \pair20 \sig_in [21:20] + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'111011 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end process $group_21 - assign \cnt_1_10 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_10 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_10 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_10 2'00 - end + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_4" +module \core_calculate_stage_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$94 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair22 process $group_22 - assign \pair22 2'00 - assign \pair22 \sig_in [23:22] + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_11 process $group_23 - assign \cnt_1_11 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_11 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_11 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_11 2'00 - end + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair24 process $group_24 - assign \pair24 2'00 - assign \pair24 \sig_in [25:24] + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_12 process $group_25 - assign \cnt_1_12 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_12 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_12 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_12 2'00 - end + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair26 process $group_26 - assign \pair26 2'00 - assign \pair26 \sig_in [27:26] + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_13 process $group_27 - assign \cnt_1_13 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_13 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_13 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_13 2'00 - end + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair28 process $group_28 - assign \pair28 2'00 - assign \pair28 \sig_in [29:28] + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_14 process $group_29 - assign \cnt_1_14 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_14 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_14 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_14 2'00 - end + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair30 process $group_30 - assign \pair30 2'00 - assign \pair30 \sig_in [31:30] + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_15 process $group_31 - assign \cnt_1_15 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_15 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_15 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_15 2'00 - end + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair32 process $group_32 - assign \pair32 2'00 - assign \pair32 \sig_in [33:32] + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_16 process $group_33 - assign \cnt_1_16 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_16 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_16 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_16 2'00 - end + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair34 process $group_34 - assign \pair34 2'00 - assign \pair34 \sig_in [35:34] + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_17 process $group_35 - assign \cnt_1_17 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_17 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_17 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_17 2'00 - end + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 process $group_36 - assign \pair36 2'00 - assign \pair36 \sig_in [37:36] + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_18 process $group_37 - assign \cnt_1_18 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_18 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_18 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_18 2'00 - end + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair38 process $group_38 - assign \pair38 2'00 - assign \pair38 \sig_in [39:38] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_19 - process $group_39 - assign \cnt_1_19 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair38 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_19 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_19 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_19 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair40 - process $group_40 - assign \pair40 2'00 - assign \pair40 \sig_in [41:40] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_20 - process $group_41 - assign \cnt_1_20 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_20 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_20 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_20 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair42 - process $group_42 - assign \pair42 2'00 - assign \pair42 \sig_in [43:42] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_21 - process $group_43 - assign \cnt_1_21 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair42 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_21 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_21 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_21 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair44 - process $group_44 - assign \pair44 2'00 - assign \pair44 \sig_in [45:44] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_22 - process $group_45 - assign \cnt_1_22 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_22 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_22 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_22 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair46 - process $group_46 - assign \pair46 2'00 - assign \pair46 \sig_in [47:46] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_23 - process $group_47 - assign \cnt_1_23 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_23 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_23 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_23 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair48 - process $group_48 - assign \pair48 2'00 - assign \pair48 \sig_in [49:48] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_24 - process $group_49 - assign \cnt_1_24 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_24 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_24 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_24 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair50 - process $group_50 - assign \pair50 2'00 - assign \pair50 \sig_in [51:50] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_25 - process $group_51 - assign \cnt_1_25 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_25 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_25 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_25 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair52 - process $group_52 - assign \pair52 2'00 - assign \pair52 \sig_in [53:52] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_26 - process $group_53 - assign \cnt_1_26 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_26 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_26 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_26 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair54 - process $group_54 - assign \pair54 2'00 - assign \pair54 \sig_in [55:54] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_27 - process $group_55 - assign \cnt_1_27 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair54 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_27 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_27 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_27 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair56 - process $group_56 - assign \pair56 2'00 - assign \pair56 \sig_in [57:56] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_28 - process $group_57 - assign \cnt_1_28 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair56 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_28 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_28 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_28 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair58 - process $group_58 - assign \pair58 2'00 - assign \pair58 \sig_in [59:58] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_29 - process $group_59 - assign \cnt_1_29 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_29 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_29 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_29 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair60 - process $group_60 - assign \pair60 2'00 - assign \pair60 \sig_in [61:60] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_30 - process $group_61 - assign \cnt_1_30 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair60 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_30 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_30 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_30 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair62 - process $group_62 - assign \pair62 2'00 - assign \pair62 \sig_in [63:62] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_31 - process $group_63 - assign \cnt_1_31 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_31 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_31 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_31 2'00 - end + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_5.core.trial0" +module \trial0$99 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_1 [1] + connect \A \operation connect \B 1'1 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_0 [1] - connect \B 1'1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_0 [0] } - connect \Y $5 - end - process $group_64 - assign \cnt_2_0 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_0 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_0 $5 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_0 { 1'0 \cnt_1_1 } + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_3 [1] + connect \A \operation connect \B 1'1 - connect \Y $7 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_2 [1] - connect \B 1'1 - connect \Y $9 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111010 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_2 [0] } - connect \Y $11 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_65 - assign \cnt_2_2 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_2 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_2 $11 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_2 { 1'0 \cnt_1_3 } + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $14 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_5.core.trial1" +module \trial1$100 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_5 [1] + connect \A \operation connect \B 1'1 - connect \Y $13 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_4 [1] + parameter \Y_WIDTH 65 + connect \A \divisor_radicand connect \B 1'1 - connect \Y $15 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_4 [0] } - connect \Y $17 + connect \Y $3 end - process $group_66 - assign \cnt_2_4 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_4 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_4 $17 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_4 { 1'0 \cnt_1_5 } + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_7 [1] + connect \A \operation connect \B 1'1 - connect \Y $19 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_6 [1] - connect \B 1'1 - connect \Y $21 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111010 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_6 [0] } - connect \Y $23 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_67 - assign \cnt_2_6 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $21 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_6 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_6 $23 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_6 { 1'0 \cnt_1_7 } + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $26 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_5.core.pe" +module \pe$101 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_9 [1] - connect \B 1'1 - connect \Y $25 + connect \A \i + connect \B 1'0 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $28 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_5.core" +module \core$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$99 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$100 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$101 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \cnt_1_8 [1] - connect \B 1'1 - connect \Y $27 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $30 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_8 [0] } - connect \Y $29 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - process $group_68 - assign \cnt_2_8 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $25 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $27 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_8 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_8 $29 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_8 { 1'0 \cnt_1_9 } - end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_11 [1] - connect \B 1'1 - connect \Y $31 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_10 [1] + parameter \Y_WIDTH 2 + connect \A \pe_o connect \B 1'1 - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_10 [0] } - connect \Y $35 + connect \Y $17 end - process $group_69 - assign \cnt_2_10 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $31 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $33 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_10 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_10 $35 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" case - assign \cnt_2_10 { 1'0 \cnt_1_11 } + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_13 [1] - connect \B 1'1 - connect \Y $37 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $40 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_12 [1] + connect \A \next_bits connect \B 1'1 - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_12 [0] } - connect \Y $41 + connect \Y $22 end - process $group_70 - assign \cnt_2_12 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $37 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $39 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_12 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_12 $41 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_12 { 1'0 \cnt_1_13 } - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $44 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_15 [1] - connect \B 1'1 - connect \Y $43 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $46 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_14 [1] - connect \B 1'1 - connect \Y $45 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_14 [0] } - connect \Y $47 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_71 - assign \cnt_2_14 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $43 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $45 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_14 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_14 $47 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_14 { 1'0 \cnt_1_15 } - end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $50 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_17 [1] - connect \B 1'1 - connect \Y $49 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'111010 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $52 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_16 [1] - connect \B 1'1 - connect \Y $51 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_16 [0] } - connect \Y $53 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init end - process $group_72 - assign \cnt_2_16 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $49 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $51 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_16 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_16 $53 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_16 { 1'0 \cnt_1_17 } - end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_5" +module \core_calculate_stage_5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$98 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_19 [1] - connect \B 1'1 - connect \Y $55 + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_18 [1] - connect \B 1'1 - connect \Y $57 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_18 [0] } - connect \Y $59 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - process $group_73 - assign \cnt_2_18 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $57 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_18 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_18 $59 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_18 { 1'0 \cnt_1_19 } - end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_21 [1] - connect \B 1'1 - connect \Y $61 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_20 [1] - connect \B 1'1 - connect \Y $63 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_20 [0] } - connect \Y $65 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - process $group_74 - assign \cnt_2_20 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $61 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $63 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_20 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_20 $65 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_20 { 1'0 \cnt_1_21 } - end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $68 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_6.core.trial0" +module \trial0$103 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_23 [1] + connect \A \operation connect \B 1'1 - connect \Y $67 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $70 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_22 [1] - connect \B 1'1 - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_22 [0] } - connect \Y $71 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_75 - assign \cnt_2_22 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $67 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_22 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_22 $71 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_22 { 1'0 \cnt_1_23 } + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $74 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_25 [1] + connect \A \operation connect \B 1'1 - connect \Y $73 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $76 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_24 [1] - connect \B 1'1 - connect \Y $75 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111001 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $78 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_24 [0] } - connect \Y $77 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_76 - assign \cnt_2_24 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_24 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_24 $77 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_24 { 1'0 \cnt_1_25 } + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $80 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_6.core.trial1" +module \trial1$104 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_27 [1] + connect \A \operation connect \B 1'1 - connect \Y $79 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $82 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_26 [1] + parameter \Y_WIDTH 65 + connect \A \divisor_radicand connect \B 1'1 - connect \Y $81 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_26 [0] } - connect \Y $83 + connect \Y $3 end - process $group_77 - assign \cnt_2_26 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $81 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_26 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_26 $83 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_26 { 1'0 \cnt_1_27 } + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $86 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_29 [1] + connect \A \operation connect \B 1'1 - connect \Y $85 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $88 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_28 [1] - connect \B 1'1 - connect \Y $87 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111001 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_28 [0] } - connect \Y $89 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_78 - assign \cnt_2_28 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $87 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_28 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_28 $89 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_28 { 1'0 \cnt_1_29 } + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $92 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_6.core.pe" +module \pe$105 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_1_31 [1] - connect \B 1'1 - connect \Y $91 + connect \A \i + connect \B 1'0 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $94 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_6.core" +module \core$102 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$103 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$104 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$105 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \cnt_1_30 [1] - connect \B 1'1 - connect \Y $93 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $96 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_30 [0] } - connect \Y $95 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - process $group_79 - assign \cnt_2_30 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $91 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $93 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_30 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_30 $95 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_30 { 1'0 \cnt_1_31 } - end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_2_2 [2] - connect \B 1'1 - connect \Y $97 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $100 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_0 [2] + parameter \Y_WIDTH 2 + connect \A \pe_o connect \B 1'1 - connect \Y $99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_0 [1:0] } - connect \Y $101 + connect \Y $17 end - process $group_80 - assign \cnt_3_0 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $97 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $99 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_0 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_0 $101 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" case - assign \cnt_3_0 { 1'0 \cnt_2_2 } + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $104 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_2_6 [2] - connect \B 1'1 - connect \Y $103 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $106 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cnt_2_4 [2] + connect \A \next_bits connect \B 1'1 - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_4 [1:0] } - connect \Y $107 + connect \Y $22 end - process $group_81 - assign \cnt_3_2 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $103 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $105 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_2 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_2 $107 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_2 { 1'0 \cnt_2_6 } - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $110 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_10 [2] - connect \B 1'1 - connect \Y $109 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $112 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_8 [2] - connect \B 1'1 - connect \Y $111 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $114 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_8 [1:0] } - connect \Y $113 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_82 - assign \cnt_3_4 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $109 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $111 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_4 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_4 $113 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_4 { 1'0 \cnt_2_10 } - end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $116 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_14 [2] - connect \B 1'1 - connect \Y $115 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'111001 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $118 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_12 [2] - connect \B 1'1 - connect \Y $117 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_12 [1:0] } - connect \Y $119 - end - process $group_83 - assign \cnt_3_6 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $115 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $117 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_6 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_6 $119 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_6 { 1'0 \cnt_2_14 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_18 [2] - connect \B 1'1 - connect \Y $121 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_16 [2] - connect \B 1'1 - connect \Y $123 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_16 [1:0] } - connect \Y $125 - end - process $group_84 - assign \cnt_3_8 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $121 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $123 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_8 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_8 $125 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_8 { 1'0 \cnt_2_18 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_22 [2] - connect \B 1'1 - connect \Y $127 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $129 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_20 [2] - connect \B 1'1 - connect \Y $129 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $131 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_20 [1:0] } - connect \Y $131 - end - process $group_85 - assign \cnt_3_10 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $127 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $129 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_10 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_10 $131 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_10 { 1'0 \cnt_2_22 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $133 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_26 [2] - connect \B 1'1 - connect \Y $133 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_24 [2] - connect \B 1'1 - connect \Y $135 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $137 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_24 [1:0] } - connect \Y $137 - end - process $group_86 - assign \cnt_3_12 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $133 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $135 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_12 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_12 $137 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_12 { 1'0 \cnt_2_26 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $139 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_30 [2] - connect \B 1'1 - connect \Y $139 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $141 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_28 [2] - connect \B 1'1 - connect \Y $141 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $143 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_28 [1:0] } - connect \Y $143 - end - process $group_87 - assign \cnt_3_14 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $139 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $141 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_14 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_14 $143 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_14 { 1'0 \cnt_2_30 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $145 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_2 [3] - connect \B 1'1 - connect \Y $145 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $147 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_0 [3] - connect \B 1'1 - connect \Y $147 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 5 $149 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'1 \cnt_3_0 [2:0] } - connect \Y $149 - end - process $group_88 - assign \cnt_4_0 5'00000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $145 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $147 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_4_0 { 1'1 { 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_4_0 $149 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_4_0 { 1'0 \cnt_3_2 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $151 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_6 [3] - connect \B 1'1 - connect \Y $151 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $153 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_4 [3] - connect \B 1'1 - connect \Y $153 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 5 $155 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'1 \cnt_3_4 [2:0] } - connect \Y $155 - end - process $group_89 - assign \cnt_4_2 5'00000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $151 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $153 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_4_2 { 1'1 { 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_4_2 $155 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_4_2 { 1'0 \cnt_3_6 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $157 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_10 [3] - connect \B 1'1 - connect \Y $157 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $159 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_8 [3] - connect \B 1'1 - connect \Y $159 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 5 $161 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'1 \cnt_3_8 [2:0] } - connect \Y $161 - end - process $group_90 - assign \cnt_4_4 5'00000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $157 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $159 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_4_4 { 1'1 { 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_4_4 $161 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_4_4 { 1'0 \cnt_3_10 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $163 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_14 [3] - connect \B 1'1 - connect \Y $163 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $165 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_12 [3] - connect \B 1'1 - connect \Y $165 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 5 $167 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'1 \cnt_3_12 [2:0] } - connect \Y $167 - end - process $group_91 - assign \cnt_4_6 5'00000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $163 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $165 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_4_6 { 1'1 { 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_4_6 $167 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_4_6 { 1'0 \cnt_3_14 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 6 \cnt_5_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_2 [4] - connect \B 1'1 - connect \Y $169 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $171 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_0 [4] - connect \B 1'1 - connect \Y $171 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 6 $173 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'1 \cnt_4_0 [3:0] } - connect \Y $173 - end - process $group_92 - assign \cnt_5_0 6'000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $169 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $171 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_5_0 { 1'1 { 1'0 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_5_0 $173 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_5_0 { 1'0 \cnt_4_2 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 6 \cnt_5_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $175 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_6 [4] - connect \B 1'1 - connect \Y $175 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $177 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_4 [4] - connect \B 1'1 - connect \Y $177 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 6 $179 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'1 \cnt_4_4 [3:0] } - connect \Y $179 - end - process $group_93 - assign \cnt_5_2 6'000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $175 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $177 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_5_2 { 1'1 { 1'0 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_5_2 $179 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_5_2 { 1'0 \cnt_4_6 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 7 \cnt_6_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $181 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_5_2 [5] - connect \B 1'1 - connect \Y $181 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $183 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_5_0 [5] - connect \B 1'1 - connect \Y $183 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 7 $185 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A { 1'1 \cnt_5_0 [4:0] } - connect \Y $185 - end - process $group_94 - assign \cnt_6_0 7'0000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $181 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $183 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_6_0 { 1'1 { 1'0 1'0 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_6_0 $185 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_6_0 { 1'0 \cnt_5_2 } - end - sync init + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_95 - assign \lz 7'0000000 - assign \lz \cnt_6_0 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main" -module \main$49 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_6" +module \core_calculate_stage_6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -75221,7 +60291,7 @@ module \main$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" @@ -75248,8 +60318,32 @@ module \main$49 wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -75324,7 +60418,7 @@ module \main$49 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \logical_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -75338,1579 +60432,1323 @@ module \main$49 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 23 \logical_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \logical_op__imm_data__imm$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \logical_op__imm_data__imm_ok$5 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \logical_op__rc__rc$6 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \logical_op__rc__rc_ok$7 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__oe__oe$8 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__oe__oe_ok$9 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__invert_a$10 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__zero_a$11 + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 32 \logical_op__input_carry$12 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__invert_out$13 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__write_cr0$14 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__output_carry$15 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__is_32bit$16 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__is_signed$17 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 38 \logical_op__data_len$18 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 39 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 40 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 41 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" - wire width 64 \bpermd_rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" - wire width 64 \bpermd_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" - wire width 64 \bpermd_ra - cell \bpermd \bpermd - connect \rs \bpermd_rs - connect \rb \bpermd_rb - connect \ra \bpermd_ra + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$102 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" - wire width 64 \popcount_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" - wire width 64 \popcount_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" - wire width 64 \popcount_o - cell \popcount \popcount - connect \a \popcount_a - connect \data_len \popcount_data_len - connect \o \popcount_o + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" - wire width 64 \clz_sig_in - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - wire width 7 \clz_lz - cell \clz \clz - connect \sig_in \clz_sig_in - connect \lz \clz_lz + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - wire width 64 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - cell $and $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $20 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - wire width 64 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - cell $or $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $22 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - wire width 64 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - cell $xor $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $24 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $26 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $29 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_7.core.trial0" +module \trial0$107 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $28 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $30 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $33 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $32 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $34 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111000 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $36 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $39 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_7.core.trial1" +module \trial1$108 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $38 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $41 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $40 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $43 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $42 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $45 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $44 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1111000 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $47 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $46 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $48 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $50 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_7.core.pe" +module \pe$109 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $53 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $52 + connect \A \i + connect \B 1'0 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $54 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $56 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_7.core" +module \core$106 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$107 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$108 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $59 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $58 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$109 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $61 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $60 + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $62 + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $65 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $64 + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $66 + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $68 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $70 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $72 + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $74 + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $76 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $79 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $78 + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $80 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $83 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $82 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $85 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $84 + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $86 + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $89 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $88 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $91 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $90 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $94 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $97 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $96 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $99 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $98 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $101 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $100 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $102 + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $105 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $104 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $106 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $109 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $108 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $110 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $113 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $112 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $115 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $114 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $116 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $118 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $121 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $120 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'111000 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $123 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $122 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $124 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $126 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1.core_calculate_stage_7" +module \core_calculate_stage_7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$106 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $128 + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $130 + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $132 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $134 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $136 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $138 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $140 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $142 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $144 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $146 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $148 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $150 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - wire width 1 $152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66" - cell $eq $153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $152 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - wire width 1 $154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $eq $155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__data_len [3] - connect \B 1'1 - connect \Y $154 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - wire width 64 $156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:83" - wire width 1 \par0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" - wire width 1 \par1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - wire width 1 $157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $xor $158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \par0 - connect \B \par1 - connect \Y $157 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $pos $159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 64 - connect \A $157 - connect \Y $156 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112" - wire width 64 $160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112" - wire width 8 $161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112" - cell $sub $162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 8 - connect \A \clz_lz - connect \B 6'100000 - connect \Y $161 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - wire width 8 $163 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A \clz_lz - connect \Y $163 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112" - wire width 8 $165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112" - cell $mux $166 - parameter \WIDTH 8 - connect \A $163 - connect \B $161 - connect \S \logical_op__is_32bit - connect \Y $165 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:112" - cell $pos $167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A $165 - connect \Y $160 - end - process $group_1 - assign \o_ok 1'0 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - assign \o $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - assign \o $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - assign \o $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - assign \o { { $138 $140 $142 $144 $146 $148 $150 $152 } { $122 $124 $126 $128 $130 $132 $134 $136 } { $106 $108 $110 $112 $114 $116 $118 $120 } { $90 $92 $94 $96 $98 $100 $102 $104 } { $74 $76 $78 $80 $82 $84 $86 $88 } { $58 $60 $62 $64 $66 $68 $70 $72 } { $42 $44 $46 $48 $50 $52 $54 $56 } { $26 $28 $30 $32 $34 $36 $38 $40 } } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - assign \o \popcount_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - switch { $154 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - case 1'1 - assign \o $156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - case - assign { \o_ok \o } [0] \par0 - assign { \o_ok \o } [32] \par1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - assign \o $160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - assign \o \bpermd_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - assign \o_ok 1'0 - end - sync init - end - process $group_2 - assign \popcount_a 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - assign \popcount_a \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28" - wire width 64 \b - process $group_3 - assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - assign \b \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 $168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 64 - connect \A \logical_op__data_len - connect \Y $168 - end - process $group_4 - assign \popcount_data_len 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - assign \popcount_data_len $168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" - wire width 1 $170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" - cell $reduce_xor $171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $170 - end - process $group_5 - assign \par0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - assign \par0 $170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - wire width 1 $172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $172 - end - process $group_6 - assign \par1 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - assign \par1 $172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:98" - wire width 1 \count_right - process $group_7 - assign \count_right 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - assign \count_right { \logical_op__insn [10] \logical_op__insn [9] \logical_op__insn [8] \logical_op__insn [7] \logical_op__insn [6] \logical_op__insn [5] \logical_op__insn [4] \logical_op__insn [3] \logical_op__insn [2] \logical_op__insn [1] } [9] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" - wire width 32 \a32 - process $group_8 - assign \a32 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - assign \a32 \ra [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:101" - wire width 64 \cntz_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" - wire width 64 $174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" - wire width 32 $175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" - cell $mux $176 - parameter \WIDTH 32 - connect \A \a32 - connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } - connect \S \count_right - connect \Y $175 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" - cell $pos $177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A $175 - connect \Y $174 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:108" - wire width 64 $178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:108" - cell $mux $179 - parameter \WIDTH 64 - connect \A \ra - connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } - connect \S \count_right - connect \Y $178 - end - process $group_9 - assign \cntz_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105" - switch { \logical_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105" - case 1'1 - assign \cntz_i $174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - case - assign \cntz_i $178 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end - sync init - end - process $group_10 - assign \clz_sig_in 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - assign \clz_sig_in \cntz_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end - sync init - end - process $group_11 - assign \bpermd_rs 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - assign \bpermd_rs \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init end - process $group_12 - assign \bpermd_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:47" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:72" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:117" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - assign \bpermd_rb \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:122" - attribute \nmigen.decoding "" - case - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end - process $group_13 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 sync init end - process $group_14 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_a$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.output" -module \output$50 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_1" +module \pipe_middle_1 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid + wire width 2 input 4 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -76985,7 +61823,7 @@ module \output$50 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -76999,53 +61837,79 @@ module \output$50 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit + wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm + wire width 64 input 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok + wire width 1 input 8 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc + wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__rc_ok + wire width 1 input 10 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe + wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__oe_ok + wire width 1 input 12 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_a + wire width 1 input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a + wire width 1 input 14 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry + wire width 2 input 15 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out + wire width 1 input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 + wire width 1 input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry + wire width 1 input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit + wire width 1 input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed + wire width 1 input 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len + wire width 4 input 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 22 \xer_ca + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -77120,7 +61984,9 @@ module \output$50 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \logical_op__insn_type$2 + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -77134,343 +62000,143 @@ module \output$50 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 25 \logical_op__fn_unit$3 + wire width 11 output 41 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \logical_op__imm_data__imm$4 + wire width 11 \logical_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \logical_op__imm_data__imm_ok$5 + wire width 64 output 42 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__rc__rc$6 + wire width 64 \logical_op__imm_data__imm$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__rc__rc_ok$7 + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__oe__oe$8 + wire width 1 \logical_op__imm_data__imm_ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__oe__oe_ok$9 + wire width 1 output 44 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__invert_a$10 + wire width 1 \logical_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__zero_a$11 + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 34 \logical_op__input_carry$12 + wire width 2 output 50 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__invert_out$13 + wire width 2 \logical_op__input_carry$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__write_cr0$14 + wire width 1 output 51 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__output_carry$15 + wire width 1 \logical_op__invert_out$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__is_32bit$16 + wire width 1 output 52 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__is_signed$17 + wire width 1 \logical_op__write_cr0$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 40 \logical_op__data_len$18 + wire width 1 output 53 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 42 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 43 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 44 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 45 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 46 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 65 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 64 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $not $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $pos $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A $26 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $29 - end - process $group_0 - assign \o$24 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" - switch { \logical_op__invert_out } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" - case 1'1 - assign \o$24 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - case - assign \o$24 $29 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" - wire width 64 \target - process $group_1 - assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$24 [63:0] - sync init - end - process $group_2 - assign \xer_ca$23 2'00 - assign \xer_ca$23 \xer_ca - sync init - end - process $group_3 - assign \xer_ca_ok 1'0 - assign \xer_ca_ok \logical_op__output_carry - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" - wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001010 - connect \Y $31 - end - process $group_4 - assign \is_cmp 1'0 - assign \is_cmp $31 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" - wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001100 - connect \Y $33 - end - process $group_5 - assign \is_cmpeqb 1'0 - assign \is_cmpeqb $33 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" - wire width 1 \msb_test - process $group_6 - assign \msb_test 1'0 - assign \msb_test \target [63] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $35 - end - process $group_7 - assign \is_nzero 1'0 - assign \is_nzero $35 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" - wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $37 - connect \Y $39 - end - process $group_8 - assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_positive $39 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $41 - connect \Y $43 - end - process $group_9 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_negative $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_negative \msb_test - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - cell $not $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $45 - end - process $group_10 - assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - case 1'1 - assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - case - assign \cr0 { \is_negative \is_positive $45 1'0 } - end - sync init - end - process $group_11 - assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$20 \o$24 [63:0] - sync init - end - process $group_12 - assign \o_ok$21 1'0 - assign \o_ok$21 \o_ok - sync init - end - process $group_13 - assign \cr_a$22 4'0000 - assign \cr_a$22 \cr0 - sync init - end - process $group_14 - assign \cr_a_ok 1'0 - assign \cr_a_ok \logical_op__write_cr0 - sync init - end - process $group_15 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$92 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_16 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_a$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init + cell \n$93 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe" -module \pipe$45 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid + wire width 2 \core_calculate_stage_4_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -77545,7 +62211,7 @@ module \pipe$45 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type + wire width 7 \core_calculate_stage_4_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -77559,55 +62225,73 @@ module \pipe$45 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \logical_op__fn_unit + wire width 11 \core_calculate_stage_4_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm + wire width 64 \core_calculate_stage_4_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_4_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc + wire width 1 \core_calculate_stage_4_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_4_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe + wire width 1 \core_calculate_stage_4_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_4_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_a + wire width 1 \core_calculate_stage_4_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a + wire width 1 \core_calculate_stage_4_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry + wire width 2 \core_calculate_stage_4_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out + wire width 1 \core_calculate_stage_4_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 + wire width 1 \core_calculate_stage_4_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry + wire width 1 \core_calculate_stage_4_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit + wire width 1 \core_calculate_stage_4_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed + wire width 1 \core_calculate_stage_4_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len + wire width 4 \core_calculate_stage_4_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn + wire width 32 \core_calculate_stage_4_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra + wire width 64 \core_calculate_stage_4_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 25 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 26 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 27 \muxid$1 + wire width 64 \core_calculate_stage_4_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_4_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_4_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_4_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_4_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_4_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_4_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_4_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_4_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next + wire width 2 \core_calculate_stage_4_muxid$34 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -77682,9 +62366,7 @@ module \pipe$45 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 28 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next + wire width 7 \core_calculate_stage_4_logical_op__insn_type$35 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -77698,111 +62380,141 @@ module \pipe$45 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 29 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 30 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next + wire width 11 \core_calculate_stage_4_logical_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__oe__oe$8 + wire width 64 \core_calculate_stage_4_logical_op__imm_data__imm$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next + wire width 1 \core_calculate_stage_4_logical_op__imm_data__imm_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__oe__oe_ok$9 + wire width 1 \core_calculate_stage_4_logical_op__rc__rc$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next + wire width 1 \core_calculate_stage_4_logical_op__rc__rc_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__invert_a$10 + wire width 1 \core_calculate_stage_4_logical_op__oe__oe$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_a$10$next + wire width 1 \core_calculate_stage_4_logical_op__oe__oe_ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__zero_a$11 + wire width 1 \core_calculate_stage_4_logical_op__invert_in$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next + wire width 1 \core_calculate_stage_4_logical_op__zero_a$44 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 38 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__is_32bit$16 + wire width 2 \core_calculate_stage_4_logical_op__input_carry$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next + wire width 1 \core_calculate_stage_4_logical_op__invert_out$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__is_signed$17 + wire width 1 \core_calculate_stage_4_logical_op__write_cr0$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next + wire width 1 \core_calculate_stage_4_logical_op__output_carry$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 44 \logical_op__data_len$18 + wire width 1 \core_calculate_stage_4_logical_op__is_32bit$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next + wire width 1 \core_calculate_stage_4_logical_op__is_signed$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 45 \logical_op__insn$19 + wire width 4 \core_calculate_stage_4_logical_op__data_len$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 46 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 48 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 50 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 51 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$next - cell \p$46 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$47 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + wire width 32 \core_calculate_stage_4_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_4_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_4_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_4_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_4_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_4_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_4_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_4_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_4_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_4_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_4_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_4_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_4_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_4_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_4_compare_rhs$66 + cell \core_calculate_stage_4 \core_calculate_stage_4 + connect \muxid \core_calculate_stage_4_muxid + connect \logical_op__insn_type \core_calculate_stage_4_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_4_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_4_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_4_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_4_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_4_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_4_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_4_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_4_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_4_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_4_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_4_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_4_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_4_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_4_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_4_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_4_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_4_logical_op__insn + connect \ra \core_calculate_stage_4_ra + connect \rb \core_calculate_stage_4_rb + connect \xer_so \core_calculate_stage_4_xer_so + connect \divisor_neg \core_calculate_stage_4_divisor_neg + connect \dividend_neg \core_calculate_stage_4_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_4_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_4_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_4_div_by_zero + connect \divisor_radicand \core_calculate_stage_4_divisor_radicand + connect \operation \core_calculate_stage_4_operation + connect \quotient_root \core_calculate_stage_4_quotient_root + connect \root_times_radicand \core_calculate_stage_4_root_times_radicand + connect \compare_lhs \core_calculate_stage_4_compare_lhs + connect \compare_rhs \core_calculate_stage_4_compare_rhs + connect \muxid$1 \core_calculate_stage_4_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_4_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_4_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_4_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_4_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_4_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_4_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_4_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_4_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_4_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_4_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_4_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_4_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_4_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_4_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_4_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_4_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_4_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_4_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_4_ra$53 + connect \rb$21 \core_calculate_stage_4_rb$54 + connect \xer_so$22 \core_calculate_stage_4_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_4_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_4_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_4_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_4_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_4_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_4_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_4_operation$62 + connect \quotient_root$30 \core_calculate_stage_4_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_4_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_4_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_4_compare_rhs$66 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid + wire width 2 \core_calculate_stage_5_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -77877,7 +62589,7 @@ module \pipe$45 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type + wire width 7 \core_calculate_stage_5_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -77891,49 +62603,73 @@ module \pipe$45 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_logical_op__fn_unit + wire width 11 \core_calculate_stage_5_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__imm + wire width 64 \core_calculate_stage_5_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_5_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc + wire width 1 \core_calculate_stage_5_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_5_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe + wire width 1 \core_calculate_stage_5_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_5_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__invert_a + wire width 1 \core_calculate_stage_5_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__zero_a + wire width 1 \core_calculate_stage_5_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry + wire width 2 \core_calculate_stage_5_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__invert_out + wire width 1 \core_calculate_stage_5_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__write_cr0 + wire width 1 \core_calculate_stage_5_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__output_carry + wire width 1 \core_calculate_stage_5_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__is_32bit + wire width 1 \core_calculate_stage_5_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__is_signed + wire width 1 \core_calculate_stage_5_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len + wire width 4 \core_calculate_stage_5_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn + wire width 32 \core_calculate_stage_5_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra + wire width 64 \core_calculate_stage_5_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb + wire width 64 \core_calculate_stage_5_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_5_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_5_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_5_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_5_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_5_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_5_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_5_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_5_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$20 + wire width 2 \core_calculate_stage_5_muxid$67 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -78008,7 +62744,7 @@ module \pipe$45 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type$21 + wire width 7 \core_calculate_stage_5_logical_op__insn_type$68 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -78022,93 +62758,141 @@ module \pipe$45 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_logical_op__fn_unit$22 + wire width 11 \core_calculate_stage_5_logical_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__imm$23 + wire width 64 \core_calculate_stage_5_logical_op__imm_data__imm$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__imm_data__imm_ok$24 + wire width 1 \core_calculate_stage_5_logical_op__imm_data__imm_ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc$25 + wire width 1 \core_calculate_stage_5_logical_op__rc__rc$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc_ok$26 + wire width 1 \core_calculate_stage_5_logical_op__rc__rc_ok$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe$27 + wire width 1 \core_calculate_stage_5_logical_op__oe__oe$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe_ok$28 + wire width 1 \core_calculate_stage_5_logical_op__oe__oe_ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__invert_a$29 + wire width 1 \core_calculate_stage_5_logical_op__invert_in$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__zero_a$30 + wire width 1 \core_calculate_stage_5_logical_op__zero_a$77 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry$31 + wire width 2 \core_calculate_stage_5_logical_op__input_carry$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__invert_out$32 + wire width 1 \core_calculate_stage_5_logical_op__invert_out$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__write_cr0$33 + wire width 1 \core_calculate_stage_5_logical_op__write_cr0$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__output_carry$34 + wire width 1 \core_calculate_stage_5_logical_op__output_carry$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__is_32bit$35 + wire width 1 \core_calculate_stage_5_logical_op__is_32bit$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__is_signed$36 + wire width 1 \core_calculate_stage_5_logical_op__is_signed$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len$37 + wire width 4 \core_calculate_stage_5_logical_op__data_len$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn$38 + wire width 32 \core_calculate_stage_5_logical_op__insn$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$39 + wire width 64 \core_calculate_stage_5_ra$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$40 - cell \input$48 \input - connect \muxid \input_muxid - connect \logical_op__insn_type \input_logical_op__insn_type - connect \logical_op__fn_unit \input_logical_op__fn_unit - connect \logical_op__imm_data__imm \input_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \input_logical_op__rc__rc - connect \logical_op__rc__rc_ok \input_logical_op__rc__rc_ok - connect \logical_op__oe__oe \input_logical_op__oe__oe - connect \logical_op__oe__oe_ok \input_logical_op__oe__oe_ok - connect \logical_op__invert_a \input_logical_op__invert_a - connect \logical_op__zero_a \input_logical_op__zero_a - connect \logical_op__input_carry \input_logical_op__input_carry - connect \logical_op__invert_out \input_logical_op__invert_out - connect \logical_op__write_cr0 \input_logical_op__write_cr0 - connect \logical_op__output_carry \input_logical_op__output_carry - connect \logical_op__is_32bit \input_logical_op__is_32bit - connect \logical_op__is_signed \input_logical_op__is_signed - connect \logical_op__data_len \input_logical_op__data_len - connect \logical_op__insn \input_logical_op__insn - connect \ra \input_ra - connect \rb \input_rb - connect \muxid$1 \input_muxid$20 - connect \logical_op__insn_type$2 \input_logical_op__insn_type$21 - connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$22 - connect \logical_op__imm_data__imm$4 \input_logical_op__imm_data__imm$23 - connect \logical_op__imm_data__imm_ok$5 \input_logical_op__imm_data__imm_ok$24 - connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$25 - connect \logical_op__rc__rc_ok$7 \input_logical_op__rc__rc_ok$26 - connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$27 - connect \logical_op__oe__oe_ok$9 \input_logical_op__oe__oe_ok$28 - connect \logical_op__invert_a$10 \input_logical_op__invert_a$29 - connect \logical_op__zero_a$11 \input_logical_op__zero_a$30 - connect \logical_op__input_carry$12 \input_logical_op__input_carry$31 - connect \logical_op__invert_out$13 \input_logical_op__invert_out$32 - connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$33 - connect \logical_op__output_carry$15 \input_logical_op__output_carry$34 - connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$35 - connect \logical_op__is_signed$17 \input_logical_op__is_signed$36 - connect \logical_op__data_len$18 \input_logical_op__data_len$37 - connect \logical_op__insn$19 \input_logical_op__insn$38 - connect \ra$20 \input_ra$39 - connect \rb$21 \input_rb$40 + wire width 64 \core_calculate_stage_5_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_5_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_5_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_5_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_5_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_5_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_5_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_5_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_5_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_5_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_5_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_5_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_5_compare_rhs$99 + cell \core_calculate_stage_5 \core_calculate_stage_5 + connect \muxid \core_calculate_stage_5_muxid + connect \logical_op__insn_type \core_calculate_stage_5_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_5_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_5_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_5_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_5_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_5_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_5_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_5_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_5_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_5_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_5_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_5_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_5_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_5_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_5_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_5_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_5_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_5_logical_op__insn + connect \ra \core_calculate_stage_5_ra + connect \rb \core_calculate_stage_5_rb + connect \xer_so \core_calculate_stage_5_xer_so + connect \divisor_neg \core_calculate_stage_5_divisor_neg + connect \dividend_neg \core_calculate_stage_5_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_5_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_5_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_5_div_by_zero + connect \divisor_radicand \core_calculate_stage_5_divisor_radicand + connect \operation \core_calculate_stage_5_operation + connect \quotient_root \core_calculate_stage_5_quotient_root + connect \root_times_radicand \core_calculate_stage_5_root_times_radicand + connect \compare_lhs \core_calculate_stage_5_compare_lhs + connect \compare_rhs \core_calculate_stage_5_compare_rhs + connect \muxid$1 \core_calculate_stage_5_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_5_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_5_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_5_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_5_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_5_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_5_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_5_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_5_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_5_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_5_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_5_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_5_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_5_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_5_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_5_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_5_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_5_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_5_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_5_ra$86 + connect \rb$21 \core_calculate_stage_5_rb$87 + connect \xer_so$22 \core_calculate_stage_5_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_5_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_5_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_5_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_5_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_5_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_5_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_5_operation$95 + connect \quotient_root$30 \core_calculate_stage_5_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_5_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_5_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_5_compare_rhs$99 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid + wire width 2 \core_calculate_stage_6_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -78183,7 +62967,7 @@ module \pipe$45 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_logical_op__insn_type + wire width 7 \core_calculate_stage_6_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -78197,49 +62981,73 @@ module \pipe$45 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_logical_op__fn_unit + wire width 11 \core_calculate_stage_6_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_logical_op__imm_data__imm + wire width 64 \core_calculate_stage_6_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_6_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__rc__rc + wire width 1 \core_calculate_stage_6_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_6_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__oe__oe + wire width 1 \core_calculate_stage_6_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_6_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__invert_a + wire width 1 \core_calculate_stage_6_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__zero_a + wire width 1 \core_calculate_stage_6_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_logical_op__input_carry + wire width 2 \core_calculate_stage_6_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__invert_out + wire width 1 \core_calculate_stage_6_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__write_cr0 + wire width 1 \core_calculate_stage_6_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__output_carry + wire width 1 \core_calculate_stage_6_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__is_32bit + wire width 1 \core_calculate_stage_6_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__is_signed + wire width 1 \core_calculate_stage_6_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_logical_op__data_len + wire width 4 \core_calculate_stage_6_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_logical_op__insn + wire width 32 \core_calculate_stage_6_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra + wire width 64 \core_calculate_stage_6_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb + wire width 64 \core_calculate_stage_6_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_6_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_6_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_6_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_6_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_6_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_6_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_6_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_6_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$41 + wire width 2 \core_calculate_stage_6_muxid$100 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -78314,7 +63122,7 @@ module \pipe$45 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_logical_op__insn_type$42 + wire width 7 \core_calculate_stage_6_logical_op__insn_type$101 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -78328,93 +63136,141 @@ module \pipe$45 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_logical_op__fn_unit$43 + wire width 11 \core_calculate_stage_6_logical_op__fn_unit$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_logical_op__imm_data__imm$44 + wire width 64 \core_calculate_stage_6_logical_op__imm_data__imm$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__imm_data__imm_ok$45 + wire width 1 \core_calculate_stage_6_logical_op__imm_data__imm_ok$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__rc__rc$46 + wire width 1 \core_calculate_stage_6_logical_op__rc__rc$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__rc__rc_ok$47 + wire width 1 \core_calculate_stage_6_logical_op__rc__rc_ok$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__oe__oe$48 + wire width 1 \core_calculate_stage_6_logical_op__oe__oe$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__oe__oe_ok$49 + wire width 1 \core_calculate_stage_6_logical_op__oe__oe_ok$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__invert_a$50 + wire width 1 \core_calculate_stage_6_logical_op__invert_in$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__zero_a$51 + wire width 1 \core_calculate_stage_6_logical_op__zero_a$110 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_logical_op__input_carry$52 + wire width 2 \core_calculate_stage_6_logical_op__input_carry$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__invert_out$53 + wire width 1 \core_calculate_stage_6_logical_op__invert_out$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__write_cr0$54 + wire width 1 \core_calculate_stage_6_logical_op__write_cr0$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__output_carry$55 + wire width 1 \core_calculate_stage_6_logical_op__output_carry$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__is_32bit$56 + wire width 1 \core_calculate_stage_6_logical_op__is_32bit$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_logical_op__is_signed$57 + wire width 1 \core_calculate_stage_6_logical_op__is_signed$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_logical_op__data_len$58 + wire width 4 \core_calculate_stage_6_logical_op__data_len$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_logical_op__insn$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_o_ok - cell \main$49 \main - connect \muxid \main_muxid - connect \logical_op__insn_type \main_logical_op__insn_type - connect \logical_op__fn_unit \main_logical_op__fn_unit - connect \logical_op__imm_data__imm \main_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \main_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \main_logical_op__rc__rc - connect \logical_op__rc__rc_ok \main_logical_op__rc__rc_ok - connect \logical_op__oe__oe \main_logical_op__oe__oe - connect \logical_op__oe__oe_ok \main_logical_op__oe__oe_ok - connect \logical_op__invert_a \main_logical_op__invert_a - connect \logical_op__zero_a \main_logical_op__zero_a - connect \logical_op__input_carry \main_logical_op__input_carry - connect \logical_op__invert_out \main_logical_op__invert_out - connect \logical_op__write_cr0 \main_logical_op__write_cr0 - connect \logical_op__output_carry \main_logical_op__output_carry - connect \logical_op__is_32bit \main_logical_op__is_32bit - connect \logical_op__is_signed \main_logical_op__is_signed - connect \logical_op__data_len \main_logical_op__data_len - connect \logical_op__insn \main_logical_op__insn - connect \ra \main_ra - connect \rb \main_rb - connect \muxid$1 \main_muxid$41 - connect \logical_op__insn_type$2 \main_logical_op__insn_type$42 - connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$43 - connect \logical_op__imm_data__imm$4 \main_logical_op__imm_data__imm$44 - connect \logical_op__imm_data__imm_ok$5 \main_logical_op__imm_data__imm_ok$45 - connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$46 - connect \logical_op__rc__rc_ok$7 \main_logical_op__rc__rc_ok$47 - connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$48 - connect \logical_op__oe__oe_ok$9 \main_logical_op__oe__oe_ok$49 - connect \logical_op__invert_a$10 \main_logical_op__invert_a$50 - connect \logical_op__zero_a$11 \main_logical_op__zero_a$51 - connect \logical_op__input_carry$12 \main_logical_op__input_carry$52 - connect \logical_op__invert_out$13 \main_logical_op__invert_out$53 - connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$54 - connect \logical_op__output_carry$15 \main_logical_op__output_carry$55 - connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$56 - connect \logical_op__is_signed$17 \main_logical_op__is_signed$57 - connect \logical_op__data_len$18 \main_logical_op__data_len$58 - connect \logical_op__insn$19 \main_logical_op__insn$59 - connect \o \main_o - connect \o_ok \main_o_ok + wire width 32 \core_calculate_stage_6_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_6_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_6_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_6_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_6_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_6_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_6_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_6_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_6_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_6_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_6_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_6_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_6_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_6_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_6_compare_rhs$132 + cell \core_calculate_stage_6 \core_calculate_stage_6 + connect \muxid \core_calculate_stage_6_muxid + connect \logical_op__insn_type \core_calculate_stage_6_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_6_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_6_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_6_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_6_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_6_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_6_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_6_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_6_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_6_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_6_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_6_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_6_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_6_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_6_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_6_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_6_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_6_logical_op__insn + connect \ra \core_calculate_stage_6_ra + connect \rb \core_calculate_stage_6_rb + connect \xer_so \core_calculate_stage_6_xer_so + connect \divisor_neg \core_calculate_stage_6_divisor_neg + connect \dividend_neg \core_calculate_stage_6_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_6_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_6_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_6_div_by_zero + connect \divisor_radicand \core_calculate_stage_6_divisor_radicand + connect \operation \core_calculate_stage_6_operation + connect \quotient_root \core_calculate_stage_6_quotient_root + connect \root_times_radicand \core_calculate_stage_6_root_times_radicand + connect \compare_lhs \core_calculate_stage_6_compare_lhs + connect \compare_rhs \core_calculate_stage_6_compare_rhs + connect \muxid$1 \core_calculate_stage_6_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_6_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_6_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_6_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_6_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_6_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_6_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_6_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_6_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_6_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_6_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_6_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_6_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_6_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_6_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_6_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_6_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_6_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_6_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_6_ra$119 + connect \rb$21 \core_calculate_stage_6_rb$120 + connect \xer_so$22 \core_calculate_stage_6_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_6_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_6_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_6_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_6_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_6_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_6_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_6_operation$128 + connect \quotient_root$30 \core_calculate_stage_6_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_6_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_6_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_6_compare_rhs$132 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid + wire width 2 \core_calculate_stage_7_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -78489,7 +63345,7 @@ module \pipe$45 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type + wire width 7 \core_calculate_stage_7_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -78503,53 +63359,73 @@ module \pipe$45 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_logical_op__fn_unit + wire width 11 \core_calculate_stage_7_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__imm + wire width 64 \core_calculate_stage_7_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_7_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc + wire width 1 \core_calculate_stage_7_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_7_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe + wire width 1 \core_calculate_stage_7_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_7_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__invert_a + wire width 1 \core_calculate_stage_7_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__zero_a + wire width 1 \core_calculate_stage_7_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry + wire width 2 \core_calculate_stage_7_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__invert_out + wire width 1 \core_calculate_stage_7_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__write_cr0 + wire width 1 \core_calculate_stage_7_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__output_carry + wire width 1 \core_calculate_stage_7_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__is_32bit + wire width 1 \core_calculate_stage_7_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__is_signed + wire width 1 \core_calculate_stage_7_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len + wire width 4 \core_calculate_stage_7_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca + wire width 32 \core_calculate_stage_7_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_7_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_7_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_7_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_7_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_7_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_7_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_7_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_7_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_7_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_7_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$60 + wire width 2 \core_calculate_stage_7_muxid$133 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -78624,7 +63500,7 @@ module \pipe$45 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type$61 + wire width 7 \core_calculate_stage_7_logical_op__insn_type$134 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -78638,246 +63514,537 @@ module \pipe$45 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_logical_op__fn_unit$62 + wire width 11 \core_calculate_stage_7_logical_op__fn_unit$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__imm$63 + wire width 64 \core_calculate_stage_7_logical_op__imm_data__imm$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__imm_data__imm_ok$64 + wire width 1 \core_calculate_stage_7_logical_op__imm_data__imm_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc$65 + wire width 1 \core_calculate_stage_7_logical_op__rc__rc$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc_ok$66 + wire width 1 \core_calculate_stage_7_logical_op__rc__rc_ok$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe$67 + wire width 1 \core_calculate_stage_7_logical_op__oe__oe$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe_ok$68 + wire width 1 \core_calculate_stage_7_logical_op__oe__oe_ok$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__invert_a$69 + wire width 1 \core_calculate_stage_7_logical_op__invert_in$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__zero_a$70 + wire width 1 \core_calculate_stage_7_logical_op__zero_a$143 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry$71 + wire width 2 \core_calculate_stage_7_logical_op__input_carry$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__invert_out$72 + wire width 1 \core_calculate_stage_7_logical_op__invert_out$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__write_cr0$73 + wire width 1 \core_calculate_stage_7_logical_op__write_cr0$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__output_carry$74 + wire width 1 \core_calculate_stage_7_logical_op__output_carry$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__is_32bit$75 + wire width 1 \core_calculate_stage_7_logical_op__is_32bit$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__is_signed$76 + wire width 1 \core_calculate_stage_7_logical_op__is_signed$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len$77 + wire width 4 \core_calculate_stage_7_logical_op__data_len$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_ca_ok - cell \output$50 \output - connect \muxid \output_muxid - connect \logical_op__insn_type \output_logical_op__insn_type - connect \logical_op__fn_unit \output_logical_op__fn_unit - connect \logical_op__imm_data__imm \output_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc_ok \output_logical_op__rc__rc_ok - connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe_ok \output_logical_op__oe__oe_ok - connect \logical_op__invert_a \output_logical_op__invert_a - connect \logical_op__zero_a \output_logical_op__zero_a - connect \logical_op__input_carry \output_logical_op__input_carry - connect \logical_op__invert_out \output_logical_op__invert_out - connect \logical_op__write_cr0 \output_logical_op__write_cr0 - connect \logical_op__output_carry \output_logical_op__output_carry - connect \logical_op__is_32bit \output_logical_op__is_32bit - connect \logical_op__is_signed \output_logical_op__is_signed - connect \logical_op__data_len \output_logical_op__data_len - connect \logical_op__insn \output_logical_op__insn - connect \o \output_o - connect \o_ok \output_o_ok - connect \cr_a \output_cr_a - connect \xer_ca \output_xer_ca - connect \muxid$1 \output_muxid$60 - connect \logical_op__insn_type$2 \output_logical_op__insn_type$61 - connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$62 - connect \logical_op__imm_data__imm$4 \output_logical_op__imm_data__imm$63 - connect \logical_op__imm_data__imm_ok$5 \output_logical_op__imm_data__imm_ok$64 - connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$65 - connect \logical_op__rc__rc_ok$7 \output_logical_op__rc__rc_ok$66 - connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$67 - connect \logical_op__oe__oe_ok$9 \output_logical_op__oe__oe_ok$68 - connect \logical_op__invert_a$10 \output_logical_op__invert_a$69 - connect \logical_op__zero_a$11 \output_logical_op__zero_a$70 - connect \logical_op__input_carry$12 \output_logical_op__input_carry$71 - connect \logical_op__invert_out$13 \output_logical_op__invert_out$72 - connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$73 - connect \logical_op__output_carry$15 \output_logical_op__output_carry$74 - connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$75 - connect \logical_op__is_signed$17 \output_logical_op__is_signed$76 - connect \logical_op__data_len$18 \output_logical_op__data_len$77 - connect \logical_op__insn$19 \output_logical_op__insn$78 - connect \o$20 \output_o$79 - connect \o_ok$21 \output_o_ok$80 - connect \cr_a$22 \output_cr_a$81 - connect \cr_a_ok \output_cr_a_ok - connect \xer_ca$23 \output_xer_ca$82 - connect \xer_ca_ok \output_xer_ca_ok + wire width 32 \core_calculate_stage_7_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_7_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_7_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_7_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_7_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_7_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_7_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_7_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_7_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_7_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_7_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_7_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_7_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_7_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_7_compare_rhs$165 + cell \core_calculate_stage_7 \core_calculate_stage_7 + connect \muxid \core_calculate_stage_7_muxid + connect \logical_op__insn_type \core_calculate_stage_7_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_7_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_7_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_7_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_7_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_7_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_7_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_7_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_7_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_7_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_7_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_7_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_7_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_7_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_7_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_7_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_7_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_7_logical_op__insn + connect \ra \core_calculate_stage_7_ra + connect \rb \core_calculate_stage_7_rb + connect \xer_so \core_calculate_stage_7_xer_so + connect \divisor_neg \core_calculate_stage_7_divisor_neg + connect \dividend_neg \core_calculate_stage_7_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_7_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_7_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_7_div_by_zero + connect \divisor_radicand \core_calculate_stage_7_divisor_radicand + connect \operation \core_calculate_stage_7_operation + connect \quotient_root \core_calculate_stage_7_quotient_root + connect \root_times_radicand \core_calculate_stage_7_root_times_radicand + connect \compare_lhs \core_calculate_stage_7_compare_lhs + connect \compare_rhs \core_calculate_stage_7_compare_rhs + connect \muxid$1 \core_calculate_stage_7_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_7_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_7_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_7_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_7_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_7_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_7_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_7_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_7_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_7_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_7_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_7_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_7_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_7_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_7_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_7_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_7_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_7_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_7_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_7_ra$152 + connect \rb$21 \core_calculate_stage_7_rb$153 + connect \xer_so$22 \core_calculate_stage_7_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_7_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_7_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_7_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_7_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_7_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_7_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_7_operation$161 + connect \quotient_root$30 \core_calculate_stage_7_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_7_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_7_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_7_compare_rhs$165 end process $group_0 - assign \input_muxid 2'00 - assign \input_muxid \muxid + assign \core_calculate_stage_4_muxid 2'00 + assign \core_calculate_stage_4_muxid \muxid sync init end process $group_1 - assign \input_logical_op__insn_type 7'0000000 - assign \input_logical_op__fn_unit 11'00000000000 - assign \input_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_logical_op__imm_data__imm_ok 1'0 - assign \input_logical_op__rc__rc 1'0 - assign \input_logical_op__rc__rc_ok 1'0 - assign \input_logical_op__oe__oe 1'0 - assign \input_logical_op__oe__oe_ok 1'0 - assign \input_logical_op__invert_a 1'0 - assign \input_logical_op__zero_a 1'0 - assign \input_logical_op__input_carry 2'00 - assign \input_logical_op__invert_out 1'0 - assign \input_logical_op__write_cr0 1'0 - assign \input_logical_op__output_carry 1'0 - assign \input_logical_op__is_32bit 1'0 - assign \input_logical_op__is_signed 1'0 - assign \input_logical_op__data_len 4'0000 - assign \input_logical_op__insn 32'00000000000000000000000000000000 - assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_a { \input_logical_op__oe__oe_ok \input_logical_op__oe__oe } { \input_logical_op__rc__rc_ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign \core_calculate_stage_4_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_4_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_4_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_4_logical_op__rc__rc 1'0 + assign \core_calculate_stage_4_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_4_logical_op__oe__oe 1'0 + assign \core_calculate_stage_4_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_4_logical_op__invert_in 1'0 + assign \core_calculate_stage_4_logical_op__zero_a 1'0 + assign \core_calculate_stage_4_logical_op__input_carry 2'00 + assign \core_calculate_stage_4_logical_op__invert_out 1'0 + assign \core_calculate_stage_4_logical_op__write_cr0 1'0 + assign \core_calculate_stage_4_logical_op__output_carry 1'0 + assign \core_calculate_stage_4_logical_op__is_32bit 1'0 + assign \core_calculate_stage_4_logical_op__is_signed 1'0 + assign \core_calculate_stage_4_logical_op__data_len 4'0000 + assign \core_calculate_stage_4_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_4_logical_op__insn \core_calculate_stage_4_logical_op__data_len \core_calculate_stage_4_logical_op__is_signed \core_calculate_stage_4_logical_op__is_32bit \core_calculate_stage_4_logical_op__output_carry \core_calculate_stage_4_logical_op__write_cr0 \core_calculate_stage_4_logical_op__invert_out \core_calculate_stage_4_logical_op__input_carry \core_calculate_stage_4_logical_op__zero_a \core_calculate_stage_4_logical_op__invert_in { \core_calculate_stage_4_logical_op__oe__oe_ok \core_calculate_stage_4_logical_op__oe__oe } { \core_calculate_stage_4_logical_op__rc__rc_ok \core_calculate_stage_4_logical_op__rc__rc } { \core_calculate_stage_4_logical_op__imm_data__imm_ok \core_calculate_stage_4_logical_op__imm_data__imm } \core_calculate_stage_4_logical_op__fn_unit \core_calculate_stage_4_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end process $group_19 - assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_ra \ra + assign \core_calculate_stage_4_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_ra \ra sync init end process $group_20 - assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_rb \rb + assign \core_calculate_stage_4_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_rb \rb sync init end process $group_21 - assign \main_muxid 2'00 - assign \main_muxid \input_muxid$20 + assign \core_calculate_stage_4_xer_so 1'0 + assign \core_calculate_stage_4_xer_so \xer_so sync init end process $group_22 - assign \main_logical_op__insn_type 7'0000000 - assign \main_logical_op__fn_unit 11'00000000000 - assign \main_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_logical_op__imm_data__imm_ok 1'0 - assign \main_logical_op__rc__rc 1'0 - assign \main_logical_op__rc__rc_ok 1'0 - assign \main_logical_op__oe__oe 1'0 - assign \main_logical_op__oe__oe_ok 1'0 - assign \main_logical_op__invert_a 1'0 - assign \main_logical_op__zero_a 1'0 - assign \main_logical_op__input_carry 2'00 - assign \main_logical_op__invert_out 1'0 - assign \main_logical_op__write_cr0 1'0 - assign \main_logical_op__output_carry 1'0 - assign \main_logical_op__is_32bit 1'0 - assign \main_logical_op__is_signed 1'0 - assign \main_logical_op__data_len 4'0000 - assign \main_logical_op__insn 32'00000000000000000000000000000000 - assign { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_a { \main_logical_op__oe__oe_ok \main_logical_op__oe__oe } { \main_logical_op__rc__rc_ok \main_logical_op__rc__rc } { \main_logical_op__imm_data__imm_ok \main_logical_op__imm_data__imm } \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$38 \input_logical_op__data_len$37 \input_logical_op__is_signed$36 \input_logical_op__is_32bit$35 \input_logical_op__output_carry$34 \input_logical_op__write_cr0$33 \input_logical_op__invert_out$32 \input_logical_op__input_carry$31 \input_logical_op__zero_a$30 \input_logical_op__invert_a$29 { \input_logical_op__oe__oe_ok$28 \input_logical_op__oe__oe$27 } { \input_logical_op__rc__rc_ok$26 \input_logical_op__rc__rc$25 } { \input_logical_op__imm_data__imm_ok$24 \input_logical_op__imm_data__imm$23 } \input_logical_op__fn_unit$22 \input_logical_op__insn_type$21 } + assign \core_calculate_stage_4_divisor_neg 1'0 + assign \core_calculate_stage_4_divisor_neg \divisor_neg sync init end - process $group_40 - assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \input_ra$39 + process $group_23 + assign \core_calculate_stage_4_dividend_neg 1'0 + assign \core_calculate_stage_4_dividend_neg \dividend_neg sync init end - process $group_41 - assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \input_rb$40 + process $group_24 + assign \core_calculate_stage_4_dive_abs_ov32 1'0 + assign \core_calculate_stage_4_dive_abs_ov32 \dive_abs_ov32 sync init end - process $group_42 - assign \output_muxid 2'00 - assign \output_muxid \main_muxid$41 + process $group_25 + assign \core_calculate_stage_4_dive_abs_ov64 1'0 + assign \core_calculate_stage_4_dive_abs_ov64 \dive_abs_ov64 sync init end - process $group_43 - assign \output_logical_op__insn_type 7'0000000 - assign \output_logical_op__fn_unit 11'00000000000 - assign \output_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_logical_op__imm_data__imm_ok 1'0 - assign \output_logical_op__rc__rc 1'0 - assign \output_logical_op__rc__rc_ok 1'0 - assign \output_logical_op__oe__oe 1'0 - assign \output_logical_op__oe__oe_ok 1'0 - assign \output_logical_op__invert_a 1'0 - assign \output_logical_op__zero_a 1'0 - assign \output_logical_op__input_carry 2'00 - assign \output_logical_op__invert_out 1'0 - assign \output_logical_op__write_cr0 1'0 - assign \output_logical_op__output_carry 1'0 - assign \output_logical_op__is_32bit 1'0 - assign \output_logical_op__is_signed 1'0 - assign \output_logical_op__data_len 4'0000 - assign \output_logical_op__insn 32'00000000000000000000000000000000 - assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_a { \output_logical_op__oe__oe_ok \output_logical_op__oe__oe } { \output_logical_op__rc__rc_ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm } \output_logical_op__fn_unit \output_logical_op__insn_type } { \main_logical_op__insn$59 \main_logical_op__data_len$58 \main_logical_op__is_signed$57 \main_logical_op__is_32bit$56 \main_logical_op__output_carry$55 \main_logical_op__write_cr0$54 \main_logical_op__invert_out$53 \main_logical_op__input_carry$52 \main_logical_op__zero_a$51 \main_logical_op__invert_a$50 { \main_logical_op__oe__oe_ok$49 \main_logical_op__oe__oe$48 } { \main_logical_op__rc__rc_ok$47 \main_logical_op__rc__rc$46 } { \main_logical_op__imm_data__imm_ok$45 \main_logical_op__imm_data__imm$44 } \main_logical_op__fn_unit$43 \main_logical_op__insn_type$42 } + process $group_26 + assign \core_calculate_stage_4_div_by_zero 1'0 + assign \core_calculate_stage_4_div_by_zero \div_by_zero + sync init + end + process $group_27 + assign \core_calculate_stage_4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_calculate_stage_4_operation 2'00 + assign \core_calculate_stage_4_operation \operation + sync init + end + process $group_29 + assign \core_calculate_stage_4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_calculate_stage_4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_calculate_stage_4_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_calculate_stage_4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \core_calculate_stage_5_muxid 2'00 + assign \core_calculate_stage_5_muxid \core_calculate_stage_4_muxid$34 + sync init + end + process $group_34 + assign \core_calculate_stage_5_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_5_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_5_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_5_logical_op__rc__rc 1'0 + assign \core_calculate_stage_5_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_5_logical_op__oe__oe 1'0 + assign \core_calculate_stage_5_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_5_logical_op__invert_in 1'0 + assign \core_calculate_stage_5_logical_op__zero_a 1'0 + assign \core_calculate_stage_5_logical_op__input_carry 2'00 + assign \core_calculate_stage_5_logical_op__invert_out 1'0 + assign \core_calculate_stage_5_logical_op__write_cr0 1'0 + assign \core_calculate_stage_5_logical_op__output_carry 1'0 + assign \core_calculate_stage_5_logical_op__is_32bit 1'0 + assign \core_calculate_stage_5_logical_op__is_signed 1'0 + assign \core_calculate_stage_5_logical_op__data_len 4'0000 + assign \core_calculate_stage_5_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_5_logical_op__insn \core_calculate_stage_5_logical_op__data_len \core_calculate_stage_5_logical_op__is_signed \core_calculate_stage_5_logical_op__is_32bit \core_calculate_stage_5_logical_op__output_carry \core_calculate_stage_5_logical_op__write_cr0 \core_calculate_stage_5_logical_op__invert_out \core_calculate_stage_5_logical_op__input_carry \core_calculate_stage_5_logical_op__zero_a \core_calculate_stage_5_logical_op__invert_in { \core_calculate_stage_5_logical_op__oe__oe_ok \core_calculate_stage_5_logical_op__oe__oe } { \core_calculate_stage_5_logical_op__rc__rc_ok \core_calculate_stage_5_logical_op__rc__rc } { \core_calculate_stage_5_logical_op__imm_data__imm_ok \core_calculate_stage_5_logical_op__imm_data__imm } \core_calculate_stage_5_logical_op__fn_unit \core_calculate_stage_5_logical_op__insn_type } { \core_calculate_stage_4_logical_op__insn$52 \core_calculate_stage_4_logical_op__data_len$51 \core_calculate_stage_4_logical_op__is_signed$50 \core_calculate_stage_4_logical_op__is_32bit$49 \core_calculate_stage_4_logical_op__output_carry$48 \core_calculate_stage_4_logical_op__write_cr0$47 \core_calculate_stage_4_logical_op__invert_out$46 \core_calculate_stage_4_logical_op__input_carry$45 \core_calculate_stage_4_logical_op__zero_a$44 \core_calculate_stage_4_logical_op__invert_in$43 { \core_calculate_stage_4_logical_op__oe__oe_ok$42 \core_calculate_stage_4_logical_op__oe__oe$41 } { \core_calculate_stage_4_logical_op__rc__rc_ok$40 \core_calculate_stage_4_logical_op__rc__rc$39 } { \core_calculate_stage_4_logical_op__imm_data__imm_ok$38 \core_calculate_stage_4_logical_op__imm_data__imm$37 } \core_calculate_stage_4_logical_op__fn_unit$36 \core_calculate_stage_4_logical_op__insn_type$35 } + sync init + end + process $group_52 + assign \core_calculate_stage_5_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_ra \core_calculate_stage_4_ra$53 + sync init + end + process $group_53 + assign \core_calculate_stage_5_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_rb \core_calculate_stage_4_rb$54 + sync init + end + process $group_54 + assign \core_calculate_stage_5_xer_so 1'0 + assign \core_calculate_stage_5_xer_so \core_calculate_stage_4_xer_so$55 + sync init + end + process $group_55 + assign \core_calculate_stage_5_divisor_neg 1'0 + assign \core_calculate_stage_5_divisor_neg \core_calculate_stage_4_divisor_neg$56 + sync init + end + process $group_56 + assign \core_calculate_stage_5_dividend_neg 1'0 + assign \core_calculate_stage_5_dividend_neg \core_calculate_stage_4_dividend_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_5_dive_abs_ov32 1'0 + assign \core_calculate_stage_5_dive_abs_ov32 \core_calculate_stage_4_dive_abs_ov32$58 + sync init + end + process $group_58 + assign \core_calculate_stage_5_dive_abs_ov64 1'0 + assign \core_calculate_stage_5_dive_abs_ov64 \core_calculate_stage_4_dive_abs_ov64$59 + sync init + end + process $group_59 + assign \core_calculate_stage_5_div_by_zero 1'0 + assign \core_calculate_stage_5_div_by_zero \core_calculate_stage_4_div_by_zero$60 + sync init + end + process $group_60 + assign \core_calculate_stage_5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_divisor_radicand \core_calculate_stage_4_divisor_radicand$61 sync init end process $group_61 - assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_o_ok 1'0 - assign { \output_o_ok \output_o } { \main_o_ok \main_o } + assign \core_calculate_stage_5_operation 2'00 + assign \core_calculate_stage_5_operation \core_calculate_stage_4_operation$62 + sync init + end + process $group_62 + assign \core_calculate_stage_5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_quotient_root \core_calculate_stage_4_quotient_root$63 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$85 process $group_63 - assign \output_cr_a 4'0000 - assign \cr_a_ok$83 1'0 - assign { \cr_a_ok$83 \output_cr_a } { \cr_a_ok$85 \cr_a$84 } + assign \core_calculate_stage_5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_root_times_radicand \core_calculate_stage_4_root_times_radicand$64 + sync init + end + process $group_64 + assign \core_calculate_stage_5_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_compare_lhs \core_calculate_stage_4_compare_lhs$65 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$88 process $group_65 - assign \output_xer_ca 2'00 - assign \xer_ca_ok$86 1'0 - assign { \xer_ca_ok$86 \output_xer_ca } { \xer_ca_ok$88 \xer_ca$87 } + assign \core_calculate_stage_5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_compare_rhs \core_calculate_stage_4_compare_rhs$66 + sync init + end + process $group_66 + assign \core_calculate_stage_6_muxid 2'00 + assign \core_calculate_stage_6_muxid \core_calculate_stage_5_muxid$67 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$89 process $group_67 - assign \p_valid_i$89 1'0 - assign \p_valid_i$89 \p_valid_i + assign \core_calculate_stage_6_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_6_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_6_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_6_logical_op__rc__rc 1'0 + assign \core_calculate_stage_6_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_6_logical_op__oe__oe 1'0 + assign \core_calculate_stage_6_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_6_logical_op__invert_in 1'0 + assign \core_calculate_stage_6_logical_op__zero_a 1'0 + assign \core_calculate_stage_6_logical_op__input_carry 2'00 + assign \core_calculate_stage_6_logical_op__invert_out 1'0 + assign \core_calculate_stage_6_logical_op__write_cr0 1'0 + assign \core_calculate_stage_6_logical_op__output_carry 1'0 + assign \core_calculate_stage_6_logical_op__is_32bit 1'0 + assign \core_calculate_stage_6_logical_op__is_signed 1'0 + assign \core_calculate_stage_6_logical_op__data_len 4'0000 + assign \core_calculate_stage_6_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_6_logical_op__insn \core_calculate_stage_6_logical_op__data_len \core_calculate_stage_6_logical_op__is_signed \core_calculate_stage_6_logical_op__is_32bit \core_calculate_stage_6_logical_op__output_carry \core_calculate_stage_6_logical_op__write_cr0 \core_calculate_stage_6_logical_op__invert_out \core_calculate_stage_6_logical_op__input_carry \core_calculate_stage_6_logical_op__zero_a \core_calculate_stage_6_logical_op__invert_in { \core_calculate_stage_6_logical_op__oe__oe_ok \core_calculate_stage_6_logical_op__oe__oe } { \core_calculate_stage_6_logical_op__rc__rc_ok \core_calculate_stage_6_logical_op__rc__rc } { \core_calculate_stage_6_logical_op__imm_data__imm_ok \core_calculate_stage_6_logical_op__imm_data__imm } \core_calculate_stage_6_logical_op__fn_unit \core_calculate_stage_6_logical_op__insn_type } { \core_calculate_stage_5_logical_op__insn$85 \core_calculate_stage_5_logical_op__data_len$84 \core_calculate_stage_5_logical_op__is_signed$83 \core_calculate_stage_5_logical_op__is_32bit$82 \core_calculate_stage_5_logical_op__output_carry$81 \core_calculate_stage_5_logical_op__write_cr0$80 \core_calculate_stage_5_logical_op__invert_out$79 \core_calculate_stage_5_logical_op__input_carry$78 \core_calculate_stage_5_logical_op__zero_a$77 \core_calculate_stage_5_logical_op__invert_in$76 { \core_calculate_stage_5_logical_op__oe__oe_ok$75 \core_calculate_stage_5_logical_op__oe__oe$74 } { \core_calculate_stage_5_logical_op__rc__rc_ok$73 \core_calculate_stage_5_logical_op__rc__rc$72 } { \core_calculate_stage_5_logical_op__imm_data__imm_ok$71 \core_calculate_stage_5_logical_op__imm_data__imm$70 } \core_calculate_stage_5_logical_op__fn_unit$69 \core_calculate_stage_5_logical_op__insn_type$68 } + sync init + end + process $group_85 + assign \core_calculate_stage_6_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_ra \core_calculate_stage_5_ra$86 + sync init + end + process $group_86 + assign \core_calculate_stage_6_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_rb \core_calculate_stage_5_rb$87 + sync init + end + process $group_87 + assign \core_calculate_stage_6_xer_so 1'0 + assign \core_calculate_stage_6_xer_so \core_calculate_stage_5_xer_so$88 + sync init + end + process $group_88 + assign \core_calculate_stage_6_divisor_neg 1'0 + assign \core_calculate_stage_6_divisor_neg \core_calculate_stage_5_divisor_neg$89 + sync init + end + process $group_89 + assign \core_calculate_stage_6_dividend_neg 1'0 + assign \core_calculate_stage_6_dividend_neg \core_calculate_stage_5_dividend_neg$90 + sync init + end + process $group_90 + assign \core_calculate_stage_6_dive_abs_ov32 1'0 + assign \core_calculate_stage_6_dive_abs_ov32 \core_calculate_stage_5_dive_abs_ov32$91 + sync init + end + process $group_91 + assign \core_calculate_stage_6_dive_abs_ov64 1'0 + assign \core_calculate_stage_6_dive_abs_ov64 \core_calculate_stage_5_dive_abs_ov64$92 + sync init + end + process $group_92 + assign \core_calculate_stage_6_div_by_zero 1'0 + assign \core_calculate_stage_6_div_by_zero \core_calculate_stage_5_div_by_zero$93 + sync init + end + process $group_93 + assign \core_calculate_stage_6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_divisor_radicand \core_calculate_stage_5_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_6_operation 2'00 + assign \core_calculate_stage_6_operation \core_calculate_stage_5_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_quotient_root \core_calculate_stage_5_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_root_times_radicand \core_calculate_stage_5_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_6_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_compare_lhs \core_calculate_stage_5_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_compare_rhs \core_calculate_stage_5_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_7_muxid 2'00 + assign \core_calculate_stage_7_muxid \core_calculate_stage_6_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_7_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_7_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_7_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_7_logical_op__rc__rc 1'0 + assign \core_calculate_stage_7_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_7_logical_op__oe__oe 1'0 + assign \core_calculate_stage_7_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_7_logical_op__invert_in 1'0 + assign \core_calculate_stage_7_logical_op__zero_a 1'0 + assign \core_calculate_stage_7_logical_op__input_carry 2'00 + assign \core_calculate_stage_7_logical_op__invert_out 1'0 + assign \core_calculate_stage_7_logical_op__write_cr0 1'0 + assign \core_calculate_stage_7_logical_op__output_carry 1'0 + assign \core_calculate_stage_7_logical_op__is_32bit 1'0 + assign \core_calculate_stage_7_logical_op__is_signed 1'0 + assign \core_calculate_stage_7_logical_op__data_len 4'0000 + assign \core_calculate_stage_7_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_7_logical_op__insn \core_calculate_stage_7_logical_op__data_len \core_calculate_stage_7_logical_op__is_signed \core_calculate_stage_7_logical_op__is_32bit \core_calculate_stage_7_logical_op__output_carry \core_calculate_stage_7_logical_op__write_cr0 \core_calculate_stage_7_logical_op__invert_out \core_calculate_stage_7_logical_op__input_carry \core_calculate_stage_7_logical_op__zero_a \core_calculate_stage_7_logical_op__invert_in { \core_calculate_stage_7_logical_op__oe__oe_ok \core_calculate_stage_7_logical_op__oe__oe } { \core_calculate_stage_7_logical_op__rc__rc_ok \core_calculate_stage_7_logical_op__rc__rc } { \core_calculate_stage_7_logical_op__imm_data__imm_ok \core_calculate_stage_7_logical_op__imm_data__imm } \core_calculate_stage_7_logical_op__fn_unit \core_calculate_stage_7_logical_op__insn_type } { \core_calculate_stage_6_logical_op__insn$118 \core_calculate_stage_6_logical_op__data_len$117 \core_calculate_stage_6_logical_op__is_signed$116 \core_calculate_stage_6_logical_op__is_32bit$115 \core_calculate_stage_6_logical_op__output_carry$114 \core_calculate_stage_6_logical_op__write_cr0$113 \core_calculate_stage_6_logical_op__invert_out$112 \core_calculate_stage_6_logical_op__input_carry$111 \core_calculate_stage_6_logical_op__zero_a$110 \core_calculate_stage_6_logical_op__invert_in$109 { \core_calculate_stage_6_logical_op__oe__oe_ok$108 \core_calculate_stage_6_logical_op__oe__oe$107 } { \core_calculate_stage_6_logical_op__rc__rc_ok$106 \core_calculate_stage_6_logical_op__rc__rc$105 } { \core_calculate_stage_6_logical_op__imm_data__imm_ok$104 \core_calculate_stage_6_logical_op__imm_data__imm$103 } \core_calculate_stage_6_logical_op__fn_unit$102 \core_calculate_stage_6_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_7_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_ra \core_calculate_stage_6_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_7_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_rb \core_calculate_stage_6_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_7_xer_so 1'0 + assign \core_calculate_stage_7_xer_so \core_calculate_stage_6_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_7_divisor_neg 1'0 + assign \core_calculate_stage_7_divisor_neg \core_calculate_stage_6_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_7_dividend_neg 1'0 + assign \core_calculate_stage_7_dividend_neg \core_calculate_stage_6_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_7_dive_abs_ov32 1'0 + assign \core_calculate_stage_7_dive_abs_ov32 \core_calculate_stage_6_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_7_dive_abs_ov64 1'0 + assign \core_calculate_stage_7_dive_abs_ov64 \core_calculate_stage_6_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_7_div_by_zero 1'0 + assign \core_calculate_stage_7_div_by_zero \core_calculate_stage_6_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_divisor_radicand \core_calculate_stage_6_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_7_operation 2'00 + assign \core_calculate_stage_7_operation \core_calculate_stage_6_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_quotient_root \core_calculate_stage_6_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_root_times_radicand \core_calculate_stage_6_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_7_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_compare_lhs \core_calculate_stage_6_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_compare_rhs \core_calculate_stage_6_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" wire width 1 \n_i_rdy_data - process $group_68 + process $group_133 assign \n_i_rdy_data 1'0 assign \n_i_rdy_data \n_ready_i sync init @@ -78885,28 +64052,28 @@ module \pipe$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire width 1 \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $90 + wire width 1 $167 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $91 + cell $and $168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$89 + connect \A \p_valid_i$166 connect \B \p_ready_o - connect \Y $90 + connect \Y $167 end - process $group_69 + process $group_134 assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $90 + assign \p_valid_i_p_ready_o $167 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$92 - process $group_70 - assign \muxid$92 2'00 - assign \muxid$92 \output_muxid$60 + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_7_muxid$133 sync init end attribute \enum_base_type "MicrOp" @@ -78983,7 +64150,7 @@ module \pipe$45 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$93 + wire width 7 \logical_op__insn_type$170 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -78997,100 +64164,168 @@ module \pipe$45 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$94 + wire width 11 \logical_op__fn_unit$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$95 + wire width 64 \logical_op__imm_data__imm$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$96 + wire width 1 \logical_op__imm_data__imm_ok$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$97 + wire width 1 \logical_op__rc__rc$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$98 + wire width 1 \logical_op__rc__rc_ok$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$99 + wire width 1 \logical_op__oe__oe$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$100 + wire width 1 \logical_op__oe__oe_ok$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_a$101 + wire width 1 \logical_op__invert_in$178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$102 + wire width 1 \logical_op__zero_a$179 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$103 + wire width 2 \logical_op__input_carry$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$104 + wire width 1 \logical_op__invert_out$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$105 + wire width 1 \logical_op__write_cr0$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$106 + wire width 1 \logical_op__output_carry$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$107 + wire width 1 \logical_op__is_32bit$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$108 + wire width 1 \logical_op__is_signed$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$109 + wire width 4 \logical_op__data_len$186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$110 - process $group_71 - assign \logical_op__insn_type$93 7'0000000 - assign \logical_op__fn_unit$94 11'00000000000 - assign \logical_op__imm_data__imm$95 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$96 1'0 - assign \logical_op__rc__rc$97 1'0 - assign \logical_op__rc__rc_ok$98 1'0 - assign \logical_op__oe__oe$99 1'0 - assign \logical_op__oe__oe_ok$100 1'0 - assign \logical_op__invert_a$101 1'0 - assign \logical_op__zero_a$102 1'0 - assign \logical_op__input_carry$103 2'00 - assign \logical_op__invert_out$104 1'0 - assign \logical_op__write_cr0$105 1'0 - assign \logical_op__output_carry$106 1'0 - assign \logical_op__is_32bit$107 1'0 - assign \logical_op__is_signed$108 1'0 - assign \logical_op__data_len$109 4'0000 - assign \logical_op__insn$110 32'00000000000000000000000000000000 - assign { \logical_op__insn$110 \logical_op__data_len$109 \logical_op__is_signed$108 \logical_op__is_32bit$107 \logical_op__output_carry$106 \logical_op__write_cr0$105 \logical_op__invert_out$104 \logical_op__input_carry$103 \logical_op__zero_a$102 \logical_op__invert_a$101 { \logical_op__oe__oe_ok$100 \logical_op__oe__oe$99 } { \logical_op__rc__rc_ok$98 \logical_op__rc__rc$97 } { \logical_op__imm_data__imm_ok$96 \logical_op__imm_data__imm$95 } \logical_op__fn_unit$94 \logical_op__insn_type$93 } { \output_logical_op__insn$78 \output_logical_op__data_len$77 \output_logical_op__is_signed$76 \output_logical_op__is_32bit$75 \output_logical_op__output_carry$74 \output_logical_op__write_cr0$73 \output_logical_op__invert_out$72 \output_logical_op__input_carry$71 \output_logical_op__zero_a$70 \output_logical_op__invert_a$69 { \output_logical_op__oe__oe_ok$68 \output_logical_op__oe__oe$67 } { \output_logical_op__rc__rc_ok$66 \output_logical_op__rc__rc$65 } { \output_logical_op__imm_data__imm_ok$64 \output_logical_op__imm_data__imm$63 } \output_logical_op__fn_unit$62 \output_logical_op__insn_type$61 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$112 - process $group_89 - assign \o$111 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$112 1'0 - assign { \o_ok$112 \o$111 } { \output_o_ok$80 \output_o$79 } + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_7_logical_op__insn$151 \core_calculate_stage_7_logical_op__data_len$150 \core_calculate_stage_7_logical_op__is_signed$149 \core_calculate_stage_7_logical_op__is_32bit$148 \core_calculate_stage_7_logical_op__output_carry$147 \core_calculate_stage_7_logical_op__write_cr0$146 \core_calculate_stage_7_logical_op__invert_out$145 \core_calculate_stage_7_logical_op__input_carry$144 \core_calculate_stage_7_logical_op__zero_a$143 \core_calculate_stage_7_logical_op__invert_in$142 { \core_calculate_stage_7_logical_op__oe__oe_ok$141 \core_calculate_stage_7_logical_op__oe__oe$140 } { \core_calculate_stage_7_logical_op__rc__rc_ok$139 \core_calculate_stage_7_logical_op__rc__rc$138 } { \core_calculate_stage_7_logical_op__imm_data__imm_ok$137 \core_calculate_stage_7_logical_op__imm_data__imm$136 } \core_calculate_stage_7_logical_op__fn_unit$135 \core_calculate_stage_7_logical_op__insn_type$134 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$114 - process $group_91 - assign \cr_a$113 4'0000 - assign \cr_a_ok$114 1'0 - assign { \cr_a_ok$114 \cr_a$113 } { \output_cr_a_ok \output_cr_a$81 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_7_ra$152 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$116 - process $group_93 - assign \xer_ca$115 2'00 - assign \xer_ca_ok$116 1'0 - assign { \xer_ca_ok$116 \xer_ca$115 } { \output_xer_ca_ok \output_xer_ca$82 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_7_rb$153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_7_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_7_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_7_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_7_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_7_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_7_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_7_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_7_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_7_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_7_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_7_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_7_compare_rhs$165 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy$next - process $group_95 + process $group_168 assign \r_busy$next \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } @@ -79111,23 +64346,23 @@ module \pipe$45 sync posedge \coresync_clk update \r_busy \r_busy$next end - process $group_96 + process $group_169 assign \muxid$1$next \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$1$next \muxid$92 + assign \muxid$1$next \muxid$169 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$1$next \muxid$92 + assign \muxid$1$next \muxid$169 end sync init update \muxid$1 2'00 sync posedge \coresync_clk update \muxid$1 \muxid$1$next end - process $group_97 + process $group_170 assign \logical_op__insn_type$2$next \logical_op__insn_type$2 assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 @@ -79136,7 +64371,7 @@ module \pipe$45 assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_a$10$next \logical_op__invert_a$10 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 assign \logical_op__zero_a$11$next \logical_op__zero_a$11 assign \logical_op__input_carry$12$next \logical_op__input_carry$12 assign \logical_op__invert_out$13$next \logical_op__invert_out$13 @@ -79150,10 +64385,10 @@ module \pipe$45 switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_a$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$110 \logical_op__data_len$109 \logical_op__is_signed$108 \logical_op__is_32bit$107 \logical_op__output_carry$106 \logical_op__write_cr0$105 \logical_op__invert_out$104 \logical_op__input_carry$103 \logical_op__zero_a$102 \logical_op__invert_a$101 { \logical_op__oe__oe_ok$100 \logical_op__oe__oe$99 } { \logical_op__rc__rc_ok$98 \logical_op__rc__rc$97 } { \logical_op__imm_data__imm_ok$96 \logical_op__imm_data__imm$95 } \logical_op__fn_unit$94 \logical_op__insn_type$93 } + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_a$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$110 \logical_op__data_len$109 \logical_op__is_signed$108 \logical_op__is_32bit$107 \logical_op__output_carry$106 \logical_op__write_cr0$105 \logical_op__invert_out$104 \logical_op__input_carry$103 \logical_op__zero_a$102 \logical_op__invert_a$101 { \logical_op__oe__oe_ok$100 \logical_op__oe__oe$99 } { \logical_op__rc__rc_ok$98 \logical_op__rc__rc$97 } { \logical_op__imm_data__imm_ok$96 \logical_op__imm_data__imm$95 } \logical_op__fn_unit$94 \logical_op__insn_type$93 } + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst @@ -79174,7 +64409,7 @@ module \pipe$45 update \logical_op__rc__rc_ok$7 1'0 update \logical_op__oe__oe$8 1'0 update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_a$10 1'0 + update \logical_op__invert_in$10 1'0 update \logical_op__zero_a$11 1'0 update \logical_op__input_carry$12 2'00 update \logical_op__invert_out$13 1'0 @@ -79193,7 +64428,7 @@ module \pipe$45 update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_a$10 \logical_op__invert_a$10$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next update \logical_op__zero_a$11 \logical_op__zero_a$11$next update \logical_op__input_carry$12 \logical_op__input_carry$12$next update \logical_op__invert_out$13 \logical_op__invert_out$13$next @@ -79204,473 +64439,971 @@ module \pipe$45 update \logical_op__data_len$18 \logical_op__data_len$18$next update \logical_op__insn$19 \logical_op__insn$19$next end - process $group_115 - assign \o$next \o - assign \o_ok$next \o_ok + process $group_188 + assign \ra$20$next \ra$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$112 \o$111 } + assign \ra$20$next \ra$188 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \o_ok$next \o$next } { \o_ok$112 \o$111 } + assign \ra$20$next \ra$188 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 end sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next + update \rb$21 \rb$21$next end - process $group_117 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok + process $group_190 + assign \xer_so$22$next \xer_so$22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$114 \cr_a$113 } + assign \xer_so$22$next \xer_so$190 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$114 \cr_a$113 } + assign \xer_so$22$next \xer_so$190 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 end sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 + update \divisor_neg$23 1'0 sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next + update \divisor_neg$23 \divisor_neg$23$next end - process $group_119 - assign \xer_ca$next \xer_ca - assign \xer_ca_ok$next \xer_ca_ok + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$116 \xer_ca$115 } + assign \dividend_neg$24$next \dividend_neg$192 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$116 \xer_ca$115 } + assign \dividend_neg$24$next \dividend_neg$192 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ca_ok$next 1'0 + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 end sync init - update \xer_ca 2'00 - update \xer_ca_ok 1'0 + update \dive_abs_ov32$25 1'0 sync posedge \coresync_clk - update \xer_ca \xer_ca$next - update \xer_ca_ok \xer_ca_ok$next + update \dive_abs_ov32$25 \dive_abs_ov32$25$next end - process $group_121 + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 assign \n_valid_o 1'0 assign \n_valid_o \r_busy sync init end - process $group_122 + process $group_203 assign \p_ready_o 1'0 assign \p_ready_o \n_i_rdy_data sync init end - connect \cr_a$84 4'0000 - connect \cr_a_ok$85 1'0 - connect \xer_ca$87 2'00 - connect \xer_ca_ok$88 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0" -module \alu_logical0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ca_ok - attribute \src "simple/issuer.py:89" - wire width 1 input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 7 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 8 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 9 \xer_ca - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 10 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 11 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 12 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 20 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 21 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 22 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 23 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 24 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 25 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 26 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 27 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 28 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 29 \rb +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.p" +module \p$110 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 30 \p_valid_i + wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 31 \p_ready_o - cell \p$43 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 end - cell \n$44 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.n" +module \n$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_n_valid_o + wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 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"OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_8.core.trial0" +module \trial0$113 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_8.core.trial1" +module \trial1$114 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_8.core.pe" +module \pe$115 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_8.core" +module \core$112 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$113 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$114 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$115 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'110111 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_8" +module \core_calculate_stage_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_logical_op__insn_type$2 + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -79684,175 +65417,73 @@ module \alu_logical0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_logical_op__fn_unit$3 + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_logical_op__imm_data__imm$4 + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__imm_data__imm_ok$5 + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__rc__rc$6 + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__rc__rc_ok$7 + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__oe__oe$8 + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__oe__oe_ok$9 + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__invert_a$10 + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__zero_a$11 + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_logical_op__input_carry$12 + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__invert_out$13 + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__write_cr0$14 + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__output_carry$15 + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__is_32bit$16 + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_logical_op__is_signed$17 + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_logical_op__data_len$18 + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_ca_ok - cell \pipe$45 \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_p_valid_i - connect \p_ready_o \pipe_p_ready_o - connect \muxid \pipe_muxid - connect \logical_op__insn_type \pipe_logical_op__insn_type - connect \logical_op__fn_unit \pipe_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_logical_op__oe__oe_ok - connect \logical_op__invert_a \pipe_logical_op__invert_a - connect \logical_op__zero_a \pipe_logical_op__zero_a - connect \logical_op__input_carry \pipe_logical_op__input_carry - connect \logical_op__invert_out \pipe_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_logical_op__output_carry - connect \logical_op__is_32bit \pipe_logical_op__is_32bit - connect \logical_op__is_signed \pipe_logical_op__is_signed - connect \logical_op__data_len \pipe_logical_op__data_len - connect \logical_op__insn \pipe_logical_op__insn - connect \ra \pipe_ra - connect \rb \pipe_rb - connect \n_valid_o \pipe_n_valid_o - connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$1 - connect \logical_op__insn_type$2 \pipe_logical_op__insn_type$2 - connect \logical_op__fn_unit$3 \pipe_logical_op__fn_unit$3 - connect \logical_op__imm_data__imm$4 \pipe_logical_op__imm_data__imm$4 - connect \logical_op__imm_data__imm_ok$5 \pipe_logical_op__imm_data__imm_ok$5 - connect \logical_op__rc__rc$6 \pipe_logical_op__rc__rc$6 - connect \logical_op__rc__rc_ok$7 \pipe_logical_op__rc__rc_ok$7 - connect \logical_op__oe__oe$8 \pipe_logical_op__oe__oe$8 - connect \logical_op__oe__oe_ok$9 \pipe_logical_op__oe__oe_ok$9 - connect \logical_op__invert_a$10 \pipe_logical_op__invert_a$10 - connect \logical_op__zero_a$11 \pipe_logical_op__zero_a$11 - connect \logical_op__input_carry$12 \pipe_logical_op__input_carry$12 - connect \logical_op__invert_out$13 \pipe_logical_op__invert_out$13 - connect \logical_op__write_cr0$14 \pipe_logical_op__write_cr0$14 - connect \logical_op__output_carry$15 \pipe_logical_op__output_carry$15 - connect \logical_op__is_32bit$16 \pipe_logical_op__is_32bit$16 - connect \logical_op__is_signed$17 \pipe_logical_op__is_signed$17 - connect \logical_op__data_len$18 \pipe_logical_op__data_len$18 - connect \logical_op__insn$19 \pipe_logical_op__insn$19 - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \cr_a \pipe_cr_a - connect \cr_a_ok \pipe_cr_a_ok - connect \xer_ca \pipe_xer_ca - connect \xer_ca_ok \pipe_xer_ca_ok - end - process $group_0 - assign \pipe_p_valid_i 1'0 - assign \pipe_p_valid_i \p_valid_i - sync init - end - process $group_1 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_2 - assign \pipe_muxid 2'00 - assign \pipe_muxid \muxid - sync init - end - process $group_3 - assign \pipe_logical_op__insn_type 7'0000000 - assign \pipe_logical_op__fn_unit 11'00000000000 - assign \pipe_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_logical_op__imm_data__imm_ok 1'0 - assign \pipe_logical_op__rc__rc 1'0 - assign \pipe_logical_op__rc__rc_ok 1'0 - assign \pipe_logical_op__oe__oe 1'0 - assign \pipe_logical_op__oe__oe_ok 1'0 - assign \pipe_logical_op__invert_a 1'0 - assign \pipe_logical_op__zero_a 1'0 - assign \pipe_logical_op__input_carry 2'00 - assign \pipe_logical_op__invert_out 1'0 - assign \pipe_logical_op__write_cr0 1'0 - assign \pipe_logical_op__output_carry 1'0 - assign \pipe_logical_op__is_32bit 1'0 - assign \pipe_logical_op__is_signed 1'0 - assign \pipe_logical_op__data_len 4'0000 - assign \pipe_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_logical_op__insn \pipe_logical_op__data_len \pipe_logical_op__is_signed \pipe_logical_op__is_32bit \pipe_logical_op__output_carry \pipe_logical_op__write_cr0 \pipe_logical_op__invert_out \pipe_logical_op__input_carry \pipe_logical_op__zero_a \pipe_logical_op__invert_a { \pipe_logical_op__oe__oe_ok \pipe_logical_op__oe__oe } { \pipe_logical_op__rc__rc_ok \pipe_logical_op__rc__rc } { \pipe_logical_op__imm_data__imm_ok \pipe_logical_op__imm_data__imm } \pipe_logical_op__fn_unit \pipe_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_21 - assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_ra \ra - sync init - end - process $group_22 - assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_rb \rb - sync init - end - process $group_23 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_n_valid_o - sync init - end - process $group_24 - assign \pipe_n_ready_i 1'0 - assign \pipe_n_ready_i \n_ready_i - sync init - end + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$20 - process $group_25 - assign \muxid$20 2'00 - assign \muxid$20 \pipe_muxid$1 - sync init - end + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -79927,7 +65558,7 @@ module \alu_logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$21 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -79941,1105 +65572,836 @@ module \alu_logical0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$22 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$23 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$24 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$25 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$26 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$27 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$28 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_a$29 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$30 + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$31 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$32 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$33 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$34 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$35 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$36 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$37 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$38 + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$112 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end process $group_26 - assign \logical_op__insn_type$21 7'0000000 - assign \logical_op__fn_unit$22 11'00000000000 - assign \logical_op__imm_data__imm$23 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$24 1'0 - assign \logical_op__rc__rc$25 1'0 - assign \logical_op__rc__rc_ok$26 1'0 - assign \logical_op__oe__oe$27 1'0 - assign \logical_op__oe__oe_ok$28 1'0 - assign \logical_op__invert_a$29 1'0 - assign \logical_op__zero_a$30 1'0 - assign \logical_op__input_carry$31 2'00 - assign \logical_op__invert_out$32 1'0 - assign \logical_op__write_cr0$33 1'0 - assign \logical_op__output_carry$34 1'0 - assign \logical_op__is_32bit$35 1'0 - assign \logical_op__is_signed$36 1'0 - assign \logical_op__data_len$37 4'0000 - assign \logical_op__insn$38 32'00000000000000000000000000000000 - assign { \logical_op__insn$38 \logical_op__data_len$37 \logical_op__is_signed$36 \logical_op__is_32bit$35 \logical_op__output_carry$34 \logical_op__write_cr0$33 \logical_op__invert_out$32 \logical_op__input_carry$31 \logical_op__zero_a$30 \logical_op__invert_a$29 { \logical_op__oe__oe_ok$28 \logical_op__oe__oe$27 } { \logical_op__rc__rc_ok$26 \logical_op__rc__rc$25 } { \logical_op__imm_data__imm_ok$24 \logical_op__imm_data__imm$23 } \logical_op__fn_unit$22 \logical_op__insn_type$21 } { \pipe_logical_op__insn$19 \pipe_logical_op__data_len$18 \pipe_logical_op__is_signed$17 \pipe_logical_op__is_32bit$16 \pipe_logical_op__output_carry$15 \pipe_logical_op__write_cr0$14 \pipe_logical_op__invert_out$13 \pipe_logical_op__input_carry$12 \pipe_logical_op__zero_a$11 \pipe_logical_op__invert_a$10 { \pipe_logical_op__oe__oe_ok$9 \pipe_logical_op__oe__oe$8 } { \pipe_logical_op__rc__rc_ok$7 \pipe_logical_op__rc__rc$6 } { \pipe_logical_op__imm_data__imm_ok$5 \pipe_logical_op__imm_data__imm$4 } \pipe_logical_op__fn_unit$3 \pipe_logical_op__insn_type$2 } + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - process $group_44 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_o_ok \pipe_o } + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - process $group_46 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a } + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - process $group_48 - assign \xer_ca 2'00 - assign \xer_ca_ok 1'0 - assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca } + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - connect \muxid 2'00 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" -module \src_l$51 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 2 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 2 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 2 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_9.core.trial0" +module \trial0$117 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \r_src + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_int - connect \B $1 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $3 - connect \B \s_src - connect \Y $5 - end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \q_int$next 2'00 + assign \dr_times_trial_bits $3 end sync init - update \q_int 2'00 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \r_src - connect \Y $7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_int - connect \B $7 - connect \Y $9 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110110 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $9 - connect \B \s_src - connect \Y $11 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end + connect $7 $10 process $group_1 - assign \q_src 2'00 - assign \q_src $11 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 2 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 2 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_9.core.trial1" +module \trial1$118 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_src - connect \Y $13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - process $group_2 - assign \qn_src 2'00 - assign \qn_src $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 2 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 2 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_src - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_3 - assign \qlq_src 2'00 - assign \qlq_src $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110110 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" -module \opc_l$52 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_9.core.pe" +module \pe$119 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r_opc + connect \A \i + connect \B 1'0 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_9.core" +module \core$116 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$117 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$118 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$119 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" -module \req_l$53 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end - sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 3'000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 3'000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 3'000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" -module \rst_l$54 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" -module \rok_l$55 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" -module \alui_l$56 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 - end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 - end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" -module \alu_l$57 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 - end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 - end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 - sync init + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'110110 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0" -module \logical0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_9" +module \core_calculate_stage_9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -81114,7 +66476,7 @@ module \logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_logical0__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -81128,85 +66490,73 @@ module \logical0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_logical0__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_logical0__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_logical0__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \oper_i_alu_logical0__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_logical0__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \oper_i_alu_logical0__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_logical0__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \oper_i_alu_logical0__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \oper_i_alu_logical0__zero_a + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \oper_i_alu_logical0__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_alu_logical0__invert_out + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \oper_i_alu_logical0__write_cr0 + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_alu_logical0__output_carry + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \oper_i_alu_logical0__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \oper_i_alu_logical0__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \oper_i_alu_logical0__data_len + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \oper_i_alu_logical0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 19 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 20 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 2 input 21 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 22 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 input 23 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 24 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 25 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 26 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 27 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 28 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 29 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 30 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 31 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 32 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 33 \dest3_o - attribute \src "simple/issuer.py:89" - wire width 1 input 34 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_logical0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_logical0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_logical0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_logical0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_logical0_xer_ca + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -81281,7 +66631,7 @@ module \logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_logical0_logical_op__insn_type + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -81295,834 +66645,836 @@ module \logical0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_logical0_logical_op__fn_unit + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_logical0_logical_op__imm_data__imm + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__imm_data__imm_ok + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__rc__rc + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__rc__rc_ok + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__oe__oe + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__oe__oe_ok + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__invert_a + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__zero_a + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_logical0_logical_op__input_carry + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__invert_out + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__write_cr0 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__output_carry + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__is_32bit + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__is_signed + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_logical0_logical_op__data_len + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_logical0_logical_op__insn + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_logical0_ra + wire width 64 output 52 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_logical0_rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_logical0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_logical0_p_ready_o - cell \alu_logical0 \alu_logical0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \cr_a_ok \cr_a_ok - connect \xer_ca_ok \xer_ca_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_logical0_n_valid_o - connect \n_ready_i \alu_logical0_n_ready_i - connect \o \alu_logical0_o - connect \cr_a \alu_logical0_cr_a - connect \xer_ca \alu_logical0_xer_ca - connect \logical_op__insn_type \alu_logical0_logical_op__insn_type - connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit - connect \logical_op__imm_data__imm \alu_logical0_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \alu_logical0_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc - connect \logical_op__rc__rc_ok \alu_logical0_logical_op__rc__rc_ok - connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe - connect \logical_op__oe__oe_ok \alu_logical0_logical_op__oe__oe_ok - connect \logical_op__invert_a \alu_logical0_logical_op__invert_a - connect \logical_op__zero_a \alu_logical0_logical_op__zero_a - connect \logical_op__input_carry \alu_logical0_logical_op__input_carry - connect \logical_op__invert_out \alu_logical0_logical_op__invert_out - connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 - connect \logical_op__output_carry \alu_logical0_logical_op__output_carry - connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit - connect \logical_op__is_signed \alu_logical0_logical_op__is_signed - connect \logical_op__data_len \alu_logical0_logical_op__data_len - connect \logical_op__insn \alu_logical0_logical_op__insn - connect \ra \alu_logical0_ra - connect \rb \alu_logical0_rb - connect \p_valid_i \alu_logical0_p_valid_i - connect \p_ready_o \alu_logical0_p_ready_o + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$116 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 2 \src_l_q_src - cell \src_l$51 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$52 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req$next - cell \req_l$53 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - cell \rst_l$54 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$55 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$56 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$57 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $1 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 2 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_rd__rel_o - connect \Y $4 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 2 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $or $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $4 - connect \B \cu_rd__go_i - connect \Y $6 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $reduce_and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A $6 - connect \Y $3 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B $3 - connect \Y $9 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $9 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $not $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $11 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $and $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $11 - connect \Y $13 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_2 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse $13 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_done - process $group_3 - assign \alu_done 1'0 - assign \alu_done \alu_logical0_n_valid_o + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly$next - process $group_4 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $not $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $and $18 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_10.core.trial0" +module \trial0$121 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $15 - connect \Y $17 - end - process $group_5 - assign \alu_pulse 1'0 - assign \alu_pulse $17 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" - wire width 3 \alu_pulsem - process $group_6 - assign \alu_pulsem 3'000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - sync init + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 3 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - cell $and $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $19 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_7 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $19 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \prev_wr_go$next 3'000 + assign \dr_times_trial_bits $3 end sync init - update \prev_wr_go 3'000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wrmask_o - connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__rel_o - connect \B $23 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $reduce_bool $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $25 - connect \Y $22 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $22 - connect \Y $21 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $21 - connect \Y $29 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_8 - assign \cu_done_o 1'0 - assign \cu_done_o $29 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $34 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_10.core.trial1" +module \trial1$122 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $33 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $or $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $31 - connect \B $33 - connect \Y $35 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_9 - assign \wr_any 1'0 - assign \wr_any $35 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $not $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_n_ready_i - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $and $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $37 - connect \Y $39 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 3 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $42 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $41 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $eq $44 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $41 - connect \B 1'0 - connect \Y $43 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $39 - connect \B $43 - connect \Y $45 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $eq $48 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_10.core.pe" +module \pe$123 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o + connect \A \i connect \B 1'0 - connect \Y $47 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $50 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_10.core" +module \core$120 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$121 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$122 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$123 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A $47 - connect \B \alu_logical0_n_ready_i - connect \Y $49 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $52 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $49 - connect \B \alu_logical0_n_valid_o - connect \Y $51 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $54 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $51 - connect \B \cu_busy_o - connect \Y $53 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_10 - assign \req_done 1'0 - assign \req_done $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - switch { $53 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \req_done 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $56 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $55 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_11 - assign \reset 1'0 - assign \reset $55 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - cell $or $58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $57 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_12 - assign \rst_r 1'0 - assign \rst_r $57 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - wire width 3 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - cell $or $60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $59 - end - process $group_13 - assign \reset_w 3'000 - assign \reset_w $59 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 2 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - wire width 2 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - cell $or $62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $61 - end - process $group_14 - assign \reset_r 2'00 - assign \reset_r $61 - sync init - end - process $group_15 - assign \rok_l_s_rdok 1'0 - assign \rok_l_s_rdok \cu_issue_i - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - cell $and $64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_n_valid_o - connect \B \cu_busy_o - connect \Y $63 - end - process $group_16 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $63 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_17 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \all_rd - sync init - end - process $group_18 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \rst_r - sync init - end - process $group_19 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end process $group_20 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_21 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 2'00 - end - sync init - update \src_l_s_src 2'00 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_22 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 2'11 - end + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init - update \src_l_r_src 2'11 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - wire width 3 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - cell $and $66 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $65 - end - process $group_23 - assign \req_l_s_req 3'000 - assign \req_l_s_req $65 - sync init + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'110101 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - cell $or $68 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $67 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_24 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $67 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 3'111 - end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init - update \req_l_r_req 3'111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_10" +module \core_calculate_stage_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -82197,7 +67549,7 @@ module \logical0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -82211,1036 +67563,989 @@ module \logical0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__zero_a + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__invert_out + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__write_cr0 + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__output_carry + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__input_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__input_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_out - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_out$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__data_len$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 132 $69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $70 - parameter \WIDTH 132 - connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry \oper_l__write_cr0 \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } - connect \B { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_a { \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe } { \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc } { \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm } \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } - connect \S \cu_issue_i - connect \Y $69 + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$120 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end process $group_25 - assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 11'00000000000 - assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__imm_data__imm_ok 1'0 - assign \oper_r__rc__rc 1'0 - assign \oper_r__rc__rc_ok 1'0 - assign \oper_r__oe__oe 1'0 - assign \oper_r__oe__oe_ok 1'0 - assign \oper_r__invert_a 1'0 - assign \oper_r__zero_a 1'0 - assign \oper_r__input_carry 2'00 - assign \oper_r__invert_out 1'0 - assign \oper_r__write_cr0 1'0 - assign \oper_r__output_carry 1'0 - assign \oper_r__is_32bit 1'0 - assign \oper_r__is_signed 1'0 - assign \oper_r__data_len 4'0000 - assign \oper_r__insn 32'00000000000000000000000000000000 - assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - process $group_43 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__rc__rc$next \oper_l__rc__rc - assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok - assign \oper_l__oe__oe$next \oper_l__oe__oe - assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok - assign \oper_l__invert_a$next \oper_l__invert_a - assign \oper_l__zero_a$next \oper_l__zero_a - assign \oper_l__input_carry$next \oper_l__input_carry - assign \oper_l__invert_out$next \oper_l__invert_out - assign \oper_l__write_cr0$next \oper_l__write_cr0 - assign \oper_l__output_carry$next \oper_l__output_carry - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__data_len$next \oper_l__data_len - assign \oper_l__insn$next \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_a { \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe } { \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc } { \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm } \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - assign \oper_l__rc__rc$next 1'0 - assign \oper_l__rc__rc_ok$next 1'0 - assign \oper_l__oe__oe$next 1'0 - assign \oper_l__oe__oe_ok$next 1'0 - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 11'00000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__rc__rc 1'0 - update \oper_l__rc__rc_ok 1'0 - update \oper_l__oe__oe 1'0 - update \oper_l__oe__oe_ok 1'0 - update \oper_l__invert_a 1'0 - update \oper_l__zero_a 1'0 - update \oper_l__input_carry 2'00 - update \oper_l__invert_out 1'0 - update \oper_l__write_cr0 1'0 - update \oper_l__output_carry 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__data_len 4'0000 - update \oper_l__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__rc__rc \oper_l__rc__rc$next - update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next - update \oper_l__oe__oe \oper_l__oe__oe$next - update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next - update \oper_l__invert_a \oper_l__invert_a$next - update \oper_l__zero_a \oper_l__zero_a$next - update \oper_l__input_carry \oper_l__input_carry$next - update \oper_l__invert_out \oper_l__invert_out$next - update \oper_l__write_cr0 \oper_l__write_cr0$next - update \oper_l__output_carry \oper_l__output_carry$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__data_len \oper_l__data_len$next - update \oper_l__insn \oper_l__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $71 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $72 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $72 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $74 - parameter \WIDTH 65 - connect \A { \data_r0_l__o_ok \data_r0_l__o } - connect \B { \o_ok \alu_logical0_o } - connect \S $72 - connect \Y $71 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - process $group_61 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - assign { \data_r0__o_ok \data_r0__o } $71 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $75 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - process $group_63 - assign \data_r0_l__o$next \data_r0_l__o - assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_logical0_o } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0_l__o_ok$next 1'0 - end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init - update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0_l__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0_l__o \data_r0_l__o$next - update \data_r0_l__o_ok \data_r0_l__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 5 $77 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $78 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $79 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $78 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $80 - parameter \WIDTH 5 - connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a } - connect \B { \cr_a_ok \alu_logical0_cr_a } - connect \S $78 - connect \Y $77 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_65 - assign \data_r1__cr_a 4'0000 - assign \data_r1__cr_a_ok 1'0 - assign { \data_r1__cr_a_ok \data_r1__cr_a } $77 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $81 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - process $group_67 - assign \data_r1_l__cr_a$next \data_r1_l__cr_a - assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $81 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_logical0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1_l__cr_a_ok$next 1'0 - end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init - update \data_r1_l__cr_a 4'0000 - update \data_r1_l__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r1_l__cr_a \data_r1_l__cr_a$next - update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 3 $83 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $84 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $85 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $84 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $86 - parameter \WIDTH 3 - connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } - connect \B { \xer_ca_ok \alu_logical0_xer_ca } - connect \S $84 - connect \Y $83 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init end - process $group_69 - assign \data_r2__xer_ca 2'00 - assign \data_r2__xer_ca_ok 1'0 - assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $83 + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $88 + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_11.core.trial0" +module \trial0$125 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $87 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - process $group_71 - assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca - assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $87 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \alu_logical0_xer_ca } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \data_r2_l__xer_ca_ok$next 1'0 + assign \dr_times_trial_bits $3 end sync init - update \data_r2_l__xer_ca 2'00 - update \data_r2_l__xer_ca_ok 1'0 - sync posedge \coresync_clk - update \data_r2_l__xer_ca \data_r2_l__xer_ca$next - update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r0__o_ok - connect \B \cu_busy_o - connect \Y $89 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r1__cr_a_ok - connect \B \cu_busy_o - connect \Y $91 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110100 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_11.core.trial1" +module \trial1$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r2__xer_ca_ok - connect \B \cu_busy_o - connect \Y $93 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - process $group_73 - assign \cu_wrmask_o 3'000 - assign \cu_wrmask_o { $93 $91 $89 } - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_74 - assign \alu_logical0_logical_op__insn_type 7'0000000 - assign \alu_logical0_logical_op__fn_unit 11'00000000000 - assign \alu_logical0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_logical_op__imm_data__imm_ok 1'0 - assign \alu_logical0_logical_op__rc__rc 1'0 - assign \alu_logical0_logical_op__rc__rc_ok 1'0 - assign \alu_logical0_logical_op__oe__oe 1'0 - assign \alu_logical0_logical_op__oe__oe_ok 1'0 - assign \alu_logical0_logical_op__invert_a 1'0 - assign \alu_logical0_logical_op__zero_a 1'0 - assign \alu_logical0_logical_op__input_carry 2'00 - assign \alu_logical0_logical_op__invert_out 1'0 - assign \alu_logical0_logical_op__write_cr0 1'0 - assign \alu_logical0_logical_op__output_carry 1'0 - assign \alu_logical0_logical_op__is_32bit 1'0 - assign \alu_logical0_logical_op__is_signed 1'0 - assign \alu_logical0_logical_op__data_len 4'0000 - assign \alu_logical0_logical_op__insn 32'00000000000000000000000000000000 - assign { \alu_logical0_logical_op__insn \alu_logical0_logical_op__data_len \alu_logical0_logical_op__is_signed \alu_logical0_logical_op__is_32bit \alu_logical0_logical_op__output_carry \alu_logical0_logical_op__write_cr0 \alu_logical0_logical_op__invert_out \alu_logical0_logical_op__input_carry \alu_logical0_logical_op__zero_a \alu_logical0_logical_op__invert_a { \alu_logical0_logical_op__oe__oe_ok \alu_logical0_logical_op__oe__oe } { \alu_logical0_logical_op__rc__rc_ok \alu_logical0_logical_op__rc__rc } { \alu_logical0_logical_op__imm_data__imm_ok \alu_logical0_logical_op__imm_data__imm } \alu_logical0_logical_op__fn_unit \alu_logical0_logical_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - cell $mux $96 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \oper_r__zero_a - connect \Y $95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_92 - assign \src_sel 1'0 - assign \src_sel $95 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110100 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 64 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $98 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \oper_r__zero_a - connect \Y $97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_93 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $97 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 1 \src_sel$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 $100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - cell $mux $101 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \oper_r__imm_data__imm_ok - connect \Y $100 - end - process $group_94 - assign \src_sel$99 1'0 - assign \src_sel$99 $100 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_11.core.pe" +module \pe$127 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165" - wire width 64 \src_or_imm$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 64 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $104 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \oper_r__imm_data__imm - connect \S \oper_r__imm_data__imm_ok - connect \Y $103 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_95 - assign \src_or_imm$102 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$102 $103 + process $group_1 + assign \n 1'0 + assign \n $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $106 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $105 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_11.core" +module \core$124 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$125 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$126 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - process $group_96 - assign \alu_logical0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_ra $105 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$127 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - process $group_97 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src_or_imm - end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $108 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$102 - connect \S \src_sel$99 - connect \Y $107 + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init end - process $group_98 - assign \alu_logical0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_rb $107 + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - process $group_99 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel$99 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src_or_imm$102 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next end - process $group_100 - assign \alu_logical0_p_valid_i 1'0 - assign \alu_logical0_p_valid_i \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - cell $and $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $109 + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init end - process $group_101 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $109 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next end - process $group_102 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end - process $group_103 - assign \alu_logical0_n_ready_i 1'0 - assign \alu_logical0_n_ready_i \alu_l_q_alu + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - cell $and $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $111 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init end - process $group_104 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $111 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next end - process $group_105 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end - process $group_106 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 2 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $114 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o } - connect \Y $113 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - cell $not $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \oper_r__zero_a - connect \Y $115 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - cell $not $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \oper_r__imm_data__imm_ok - connect \Y $117 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 2 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $113 - connect \B { $117 $115 } - connect \Y $119 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 2 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $not $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_rdmaskn_i - connect \Y $121 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 2 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $124 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $119 - connect \B $121 - connect \Y $123 + connect \A \pass_flags + connect \Y $12 end - process $group_107 - assign \cu_rd__rel_o 2'00 - assign \cu_rd__rel_o $123 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $125 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $127 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $129 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 3 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B { $125 $127 $129 } - connect \Y $131 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 3 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $131 - connect \B \cu_wrmask_o - connect \Y $133 - end - process $group_108 - assign \cu_wr__rel_o 3'000 - assign \cu_wr__rel_o $133 - sync init + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $136 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $135 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_109 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $135 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $138 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $137 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_110 - assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $137 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $140 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $139 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_111 - assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $139 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.p" -module \p$58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.n" -module \n$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.p" -module \p$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'110100 + connect \Y $30 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.n" -module \n$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.spr_main" -module \spr_main +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2.core_calculate_stage_11" +module \core_calculate_stage_11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -83317,7 +68622,7 @@ module \spr_main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \spr_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -83331,23 +68636,73 @@ module \spr_main attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \spr_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \spr_op__insn + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 5 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 6 \fast1 + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 7 \xer_so + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 8 \xer_ov + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 9 \xer_ca + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 10 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -83422,7 +68777,7 @@ module \spr_main attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 11 \spr_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -83436,256 +68791,243 @@ module \spr_main attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 12 \spr_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 13 \spr_op__insn$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 14 \spr_op__is_32bit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 15 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 16 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 17 \fast1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 18 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 19 \xer_so$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 20 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 21 \xer_ov$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 22 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 23 \xer_ca$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 24 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" - wire width 10 \spr + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$124 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end process $group_0 - assign \spr 10'0000000000 - assign \spr { { \spr_op__insn [15] \spr_op__insn [14] \spr_op__insn [13] \spr_op__insn [12] \spr_op__insn [11] } { \spr_op__insn [20] \spr_op__insn [19] \spr_op__insn [18] \spr_op__insn [17] \spr_op__insn [16] } } + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end process $group_1 - assign \fast1$6 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - assign \fast1$6 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - process $group_2 - assign \fast1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - assign \fast1_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init end - process $group_3 - assign \xer_so$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_so$7 \ra [31] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end - process $group_4 - assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_so_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - process $group_5 - assign \xer_ov$8 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_ov$8 [0] \ra [30] - assign \xer_ov$8 [1] \ra [19] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - process $group_6 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_ov_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - process $group_7 - assign \xer_ca$9 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_ca$9 [0] \ra [29] - assign \xer_ca$9 [1] \ra [18] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init end - process $group_8 - assign \xer_ca_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" - case 10'0000000001 - assign \xer_ca_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - process $group_10 - assign \o_ok 1'0 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:72" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:74" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 - assign \o \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" - case 10'0000000001 - assign { \o_ok \o } [31] \xer_so - assign { \o_ok \o } [30] \xer_ov [0] - assign { \o_ok \o } [19] \xer_ov [1] - assign { \o_ok \o } [29] \xer_ca [0] - assign { \o_ok \o } [18] \xer_ca [1] - end - end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - process $group_11 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - process $group_12 - assign \spr_op__insn_type$2 7'0000000 - assign \spr_op__fn_unit$3 11'00000000000 - assign \spr_op__insn$4 32'00000000000000000000000000000000 - assign \spr_op__is_32bit$5 1'0 - assign { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe" -module \pipe$60 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_2" +module \pipe_middle_2 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 2 \p_valid_i @@ -83767,7 +69109,7 @@ module \pipe$60 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \spr_op__insn_type + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -83781,29 +69123,77 @@ module \pipe$60 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \spr_op__fn_unit + wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \spr_op__insn + wire width 64 input 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \fast1 + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 12 \xer_so + wire width 64 input 23 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 13 \xer_ov + wire width 64 input 24 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 14 \xer_ca + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 15 \n_valid_o + wire width 1 output 37 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 16 \n_ready_i + wire width 1 input 38 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 17 \muxid$1 + wire width 2 output 39 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" @@ -83880,9 +69270,9 @@ module \pipe$60 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 18 \spr_op__insn_type$2 + wire width 7 output 40 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$2$next + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -83896,75 +69286,143 @@ module \pipe$60 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 19 \spr_op__fn_unit$3 + wire width 11 output 41 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \spr_op__fn_unit$3$next + wire width 11 \logical_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 20 \spr_op__insn$4 + wire width 64 output 42 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$4$next + wire width 64 \logical_op__imm_data__imm$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 21 \spr_op__is_32bit$5 + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \spr_op__is_32bit$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \spr1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr1$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 25 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 26 \fast1$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 27 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 28 \xer_so$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 29 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 30 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 31 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 32 \xer_ca$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 33 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$next - cell \p$61 \p + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$110 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$62 \n + cell \n$111 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \spr_main_muxid + wire width 2 \core_calculate_stage_8_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -84039,7 +69497,7 @@ module \pipe$60 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_main_spr_op__insn_type + wire width 7 \core_calculate_stage_8_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -84053,23 +69511,73 @@ module \pipe$60 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \spr_main_spr_op__fn_unit + wire width 11 \core_calculate_stage_8_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_main_spr_op__insn + wire width 64 \core_calculate_stage_8_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \spr_main_spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_fast1 + wire width 1 \core_calculate_stage_8_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_8_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_8_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_8_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \spr_main_xer_so + wire width 64 \core_calculate_stage_8_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \spr_main_xer_ov + wire width 64 \core_calculate_stage_8_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \spr_main_xer_ca + wire width 1 \core_calculate_stage_8_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_8_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_8_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_8_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_8_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_8_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_8_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_8_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_8_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_8_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_8_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_8_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \spr_main_muxid$11 + wire width 2 \core_calculate_stage_8_muxid$34 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -84144,7 +69652,7 @@ module \pipe$60 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_main_spr_op__insn_type$12 + wire width 7 \core_calculate_stage_8_logical_op__insn_type$35 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -84158,144 +69666,141 @@ module \pipe$60 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \spr_main_spr_op__fn_unit$13 + wire width 11 \core_calculate_stage_8_logical_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_main_spr_op__insn$14 + wire width 64 \core_calculate_stage_8_logical_op__imm_data__imm$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \spr_main_spr_op__is_32bit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr_main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr_main_fast1$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_xer_so$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \spr_main_xer_ov$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \spr_main_xer_ca$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_xer_ca_ok - cell \spr_main \spr_main - connect \muxid \spr_main_muxid - connect \spr_op__insn_type \spr_main_spr_op__insn_type - connect \spr_op__fn_unit \spr_main_spr_op__fn_unit - connect \spr_op__insn \spr_main_spr_op__insn - connect \spr_op__is_32bit \spr_main_spr_op__is_32bit - connect \ra \spr_main_ra - connect \fast1 \spr_main_fast1 - connect \xer_so \spr_main_xer_so - connect \xer_ov \spr_main_xer_ov - connect \xer_ca \spr_main_xer_ca - connect \muxid$1 \spr_main_muxid$11 - connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 - connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 - connect \spr_op__insn$4 \spr_main_spr_op__insn$14 - connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 - connect \o \spr_main_o - connect \o_ok \spr_main_o_ok - connect \fast1$6 \spr_main_fast1$16 - connect \fast1_ok \spr_main_fast1_ok - connect \xer_so$7 \spr_main_xer_so$17 - connect \xer_so_ok \spr_main_xer_so_ok - connect \xer_ov$8 \spr_main_xer_ov$18 - connect \xer_ov_ok \spr_main_xer_ov_ok - connect \xer_ca$9 \spr_main_xer_ca$19 - connect \xer_ca_ok \spr_main_xer_ca_ok - end - process $group_0 - assign \spr_main_muxid 2'00 - assign \spr_main_muxid \muxid - sync init - end - process $group_1 - assign \spr_main_spr_op__insn_type 7'0000000 - assign \spr_main_spr_op__fn_unit 11'00000000000 - assign \spr_main_spr_op__insn 32'00000000000000000000000000000000 - assign \spr_main_spr_op__is_32bit 1'0 - assign { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - sync init - end - process $group_5 - assign \spr_main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr_main_ra \ra - sync init - end + wire width 1 \core_calculate_stage_8_logical_op__imm_data__imm_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__invert_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_8_logical_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__write_cr0$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_8_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_8_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_8_logical_op__insn$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr1$20 - process $group_6 - assign \spr1$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr1$20 \spr1 - sync init - end - process $group_7 - assign \spr_main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr_main_fast1 \fast1 - sync init - end - process $group_8 - assign \spr_main_xer_so 1'0 - assign \spr_main_xer_so \xer_so - sync init - end - process $group_9 - assign \spr_main_xer_ov 2'00 - assign \spr_main_xer_ov \xer_ov - sync init - end - process $group_10 - assign \spr_main_xer_ca 2'00 - assign \spr_main_xer_ca \xer_ca - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$21 - process $group_11 - assign \p_valid_i$21 1'0 - assign \p_valid_i$21 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_12 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$21 - connect \B \p_ready_o - connect \Y $22 - end - process $group_13 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $22 - sync init + wire width 64 \core_calculate_stage_8_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_8_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_8_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_8_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_8_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_8_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_8_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_8_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_8_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_8_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_8_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_8_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_8_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_8_compare_rhs$66 + cell \core_calculate_stage_8 \core_calculate_stage_8 + connect \muxid \core_calculate_stage_8_muxid + connect \logical_op__insn_type \core_calculate_stage_8_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_8_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_8_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_8_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_8_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_8_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_8_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_8_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_8_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_8_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_8_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_8_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_8_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_8_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_8_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_8_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_8_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_8_logical_op__insn + connect \ra \core_calculate_stage_8_ra + connect \rb \core_calculate_stage_8_rb + connect \xer_so \core_calculate_stage_8_xer_so + connect \divisor_neg \core_calculate_stage_8_divisor_neg + connect \dividend_neg \core_calculate_stage_8_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_8_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_8_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_8_div_by_zero + connect \divisor_radicand \core_calculate_stage_8_divisor_radicand + connect \operation \core_calculate_stage_8_operation + connect \quotient_root \core_calculate_stage_8_quotient_root + connect \root_times_radicand \core_calculate_stage_8_root_times_radicand + connect \compare_lhs \core_calculate_stage_8_compare_lhs + connect \compare_rhs \core_calculate_stage_8_compare_rhs + connect \muxid$1 \core_calculate_stage_8_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_8_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_8_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_8_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_8_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_8_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_8_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_8_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_8_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_8_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_8_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_8_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_8_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_8_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_8_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_8_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_8_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_8_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_8_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_8_ra$53 + connect \rb$21 \core_calculate_stage_8_rb$54 + connect \xer_so$22 \core_calculate_stage_8_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_8_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_8_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_8_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_8_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_8_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_8_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_8_operation$62 + connect \quotient_root$30 \core_calculate_stage_8_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_8_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_8_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_8_compare_rhs$66 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$24 - process $group_14 - assign \muxid$24 2'00 - assign \muxid$24 \spr_main_muxid$11 - sync init - end + wire width 2 \core_calculate_stage_9_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -84370,7 +69875,7 @@ module \pipe$60 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$25 + wire width 7 \core_calculate_stage_9_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -84384,341 +69889,73 @@ module \pipe$60 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \spr_op__fn_unit$26 + wire width 11 \core_calculate_stage_9_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$27 + wire width 64 \core_calculate_stage_9_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \spr_op__is_32bit$28 - process $group_15 - assign \spr_op__insn_type$25 7'0000000 - assign \spr_op__fn_unit$26 11'00000000000 - assign \spr_op__insn$27 32'00000000000000000000000000000000 - assign \spr_op__is_32bit$28 1'0 - assign { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$30 - process $group_19 - assign \o$29 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$30 1'0 - assign { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr1$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr1_ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr1$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr1_ok$34 - process $group_21 - assign \spr1$31 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr1_ok$32 1'0 - assign { \spr1_ok$32 \spr1$31 } { \spr1_ok$34 \spr1$33 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast1_ok$36 - process $group_23 - assign \fast1$35 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok$36 1'0 - assign { \fast1_ok$36 \fast1$35 } { \spr_main_fast1_ok \spr_main_fast1$16 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$38 - process $group_25 - assign \xer_so$37 1'0 - assign \xer_so_ok$38 1'0 - assign { \xer_so_ok$38 \xer_so$37 } { \spr_main_xer_so_ok \spr_main_xer_so$17 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$40 - process $group_27 - assign \xer_ov$39 2'00 - assign \xer_ov_ok$40 1'0 - assign { \xer_ov_ok$40 \xer_ov$39 } { \spr_main_xer_ov_ok \spr_main_xer_ov$18 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$42 - process $group_29 - assign \xer_ca$41 2'00 - assign \xer_ca_ok$42 1'0 - assign { \xer_ca_ok$42 \xer_ca$41 } { \spr_main_xer_ca_ok \spr_main_xer_ca$19 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_31 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_32 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$24 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_33 - assign \spr_op__insn_type$2$next \spr_op__insn_type$2 - assign \spr_op__fn_unit$3$next \spr_op__fn_unit$3 - assign \spr_op__insn$4$next \spr_op__insn$4 - assign \spr_op__is_32bit$5$next \spr_op__is_32bit$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \spr_op__is_32bit$5$next \spr_op__insn$4$next \spr_op__fn_unit$3$next \spr_op__insn_type$2$next } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \spr_op__is_32bit$5$next \spr_op__insn$4$next \spr_op__fn_unit$3$next \spr_op__insn_type$2$next } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } - end - sync init - update \spr_op__insn_type$2 7'0000000 - update \spr_op__fn_unit$3 11'00000000000 - update \spr_op__insn$4 32'00000000000000000000000000000000 - update \spr_op__is_32bit$5 1'0 - sync posedge \coresync_clk - update \spr_op__insn_type$2 \spr_op__insn_type$2$next - update \spr_op__fn_unit$3 \spr_op__fn_unit$3$next - update \spr_op__insn$4 \spr_op__insn$4$next - update \spr_op__is_32bit$5 \spr_op__is_32bit$5$next - end - process $group_37 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$30 \o$29 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$30 \o$29 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_39 - assign \spr1$6$next \spr1$6 - assign \spr1_ok$next \spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \spr1_ok$next \spr1$6$next } { \spr1_ok$32 \spr1$31 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \spr1_ok$next \spr1$6$next } { \spr1_ok$32 \spr1$31 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \spr1_ok$next 1'0 - end - sync init - update \spr1$6 64'0000000000000000000000000000000000000000000000000000000000000000 - update \spr1_ok 1'0 - sync posedge \coresync_clk - update \spr1$6 \spr1$6$next - update \spr1_ok \spr1_ok$next - end - process $group_41 - assign \fast1$7$next \fast1$7 - assign \fast1_ok$next \fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$36 \fast1$35 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$36 \fast1$35 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \fast1_ok$next 1'0 - end - sync init - update \fast1$7 64'0000000000000000000000000000000000000000000000000000000000000000 - update \fast1_ok 1'0 - sync posedge \coresync_clk - update \fast1$7 \fast1$7$next - update \fast1_ok \fast1_ok$next - end - process $group_43 - assign \xer_so$8$next \xer_so$8 - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$38 \xer_so$37 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$38 \xer_so$37 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so$8 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so$8 \xer_so$8$next - update \xer_so_ok \xer_so_ok$next - end - process $group_45 - assign \xer_ov$9$next \xer_ov$9 - assign \xer_ov_ok$next \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$40 \xer_ov$39 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$40 \xer_ov$39 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ov_ok$next 1'0 - end - sync init - update \xer_ov$9 2'00 - update \xer_ov_ok 1'0 - sync posedge \coresync_clk - update \xer_ov$9 \xer_ov$9$next - update \xer_ov_ok \xer_ov_ok$next - end - process $group_47 - assign \xer_ca$10$next \xer_ca$10 - assign \xer_ca_ok$next \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$42 \xer_ca$41 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$42 \xer_ca$41 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ca_ok$next 1'0 - end - sync init - update \xer_ca$10 2'00 - update \xer_ca_ok 1'0 - sync posedge \coresync_clk - update \xer_ca$10 \xer_ca$10$next - update \xer_ca_ok \xer_ca_ok$next - end - process $group_49 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_50 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \spr1$33 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \spr1_ok$34 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0" -module \alu_spr0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 6 \spr1_ok - attribute \src "simple/issuer.py:89" - wire width 1 input 7 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 8 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 9 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 10 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 11 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 12 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 13 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 14 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 15 \xer_ca + wire width 1 \core_calculate_stage_9_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_9_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_9_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_9_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_9_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_9_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_9_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_9_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_9_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_9_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_9_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_9_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_9_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_9_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_9_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_9_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_9_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_9_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_9_muxid$67 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -84793,7 +70030,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 16 \spr_op__insn_type + wire width 7 \core_calculate_stage_9_logical_op__insn_type$68 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -84807,41 +70044,141 @@ module \alu_spr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 17 \spr_op__fn_unit + wire width 11 \core_calculate_stage_9_logical_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \spr_op__insn + wire width 64 \core_calculate_stage_9_logical_op__imm_data__imm$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 21 \spr1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 22 \fast1$2 + wire width 1 \core_calculate_stage_9_logical_op__imm_data__imm_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__rc__rc_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_9_logical_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__invert_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__write_cr0$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_9_logical_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_9_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_9_logical_op__insn$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 23 \xer_so$3 + wire width 64 \core_calculate_stage_9_ra$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 24 \xer_ov$4 + wire width 64 \core_calculate_stage_9_rb$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 25 \xer_ca$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 26 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 27 \p_ready_o - cell \p$58 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$59 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + wire width 1 \core_calculate_stage_9_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_9_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_9_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_9_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_9_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_9_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_9_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_9_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_9_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_9_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_9_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_9_compare_rhs$99 + cell \core_calculate_stage_9 \core_calculate_stage_9 + connect \muxid \core_calculate_stage_9_muxid + connect \logical_op__insn_type \core_calculate_stage_9_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_9_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_9_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_9_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_9_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_9_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_9_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_9_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_9_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_9_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_9_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_9_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_9_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_9_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_9_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_9_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_9_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_9_logical_op__insn + connect \ra \core_calculate_stage_9_ra + connect \rb \core_calculate_stage_9_rb + connect \xer_so \core_calculate_stage_9_xer_so + connect \divisor_neg \core_calculate_stage_9_divisor_neg + connect \dividend_neg \core_calculate_stage_9_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_9_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_9_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_9_div_by_zero + connect \divisor_radicand \core_calculate_stage_9_divisor_radicand + connect \operation \core_calculate_stage_9_operation + connect \quotient_root \core_calculate_stage_9_quotient_root + connect \root_times_radicand \core_calculate_stage_9_root_times_radicand + connect \compare_lhs \core_calculate_stage_9_compare_lhs + connect \compare_rhs \core_calculate_stage_9_compare_rhs + connect \muxid$1 \core_calculate_stage_9_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_9_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_9_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_9_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_9_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_9_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_9_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_9_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_9_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_9_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_9_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_9_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_9_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_9_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_9_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_9_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_9_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_9_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_9_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_9_ra$86 + connect \rb$21 \core_calculate_stage_9_rb$87 + connect \xer_so$22 \core_calculate_stage_9_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_9_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_9_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_9_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_9_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_9_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_9_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_9_operation$95 + connect \quotient_root$30 \core_calculate_stage_9_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_9_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_9_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_9_compare_rhs$99 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid + wire width 2 \core_calculate_stage_10_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -84916,7 +70253,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_spr_op__insn_type + wire width 7 \core_calculate_stage_10_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -84930,29 +70267,296 @@ module \alu_spr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_spr_op__fn_unit + wire width 11 \core_calculate_stage_10_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_spr_op__insn + wire width 64 \core_calculate_stage_10_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_spr_op__is_32bit + wire width 1 \core_calculate_stage_10_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_10_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_10_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_10_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra + wire width 64 \core_calculate_stage_10_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_spr1 + wire width 64 \core_calculate_stage_10_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast1 + wire width 1 \core_calculate_stage_10_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_10_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_10_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_10_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_10_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_10_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_10_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_10_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_10_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_10_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_10_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_10_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_10_muxid$100 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_10_logical_op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_10_logical_op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_10_logical_op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__rc__rc$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__rc__rc_ok$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__oe__oe$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_10_logical_op__input_carry$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__invert_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__write_cr0$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__output_carry$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__is_32bit$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_10_logical_op__is_signed$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_10_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_10_logical_op__insn$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_xer_so + wire width 64 \core_calculate_stage_10_ra$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe_xer_ov + wire width 64 \core_calculate_stage_10_rb$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_n_ready_i + wire width 1 \core_calculate_stage_10_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_10_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_10_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_10_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_10_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_10_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_10_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_10_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_10_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_10_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_10_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_10_compare_rhs$132 + cell \core_calculate_stage_10 \core_calculate_stage_10 + connect \muxid \core_calculate_stage_10_muxid + connect \logical_op__insn_type \core_calculate_stage_10_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_10_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_10_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_10_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_10_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_10_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_10_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_10_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_10_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_10_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_10_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_10_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_10_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_10_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_10_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_10_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_10_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_10_logical_op__insn + connect \ra \core_calculate_stage_10_ra + connect \rb \core_calculate_stage_10_rb + connect \xer_so \core_calculate_stage_10_xer_so + connect \divisor_neg \core_calculate_stage_10_divisor_neg + connect \dividend_neg \core_calculate_stage_10_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_10_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_10_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_10_div_by_zero + connect \divisor_radicand \core_calculate_stage_10_divisor_radicand + connect \operation \core_calculate_stage_10_operation + connect \quotient_root \core_calculate_stage_10_quotient_root + connect \root_times_radicand \core_calculate_stage_10_root_times_radicand + connect \compare_lhs \core_calculate_stage_10_compare_lhs + connect \compare_rhs \core_calculate_stage_10_compare_rhs + connect \muxid$1 \core_calculate_stage_10_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_10_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_10_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_10_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_10_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_10_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_10_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_10_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_10_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_10_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_10_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_10_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_10_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_10_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_10_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_10_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_10_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_10_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_10_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_10_ra$119 + connect \rb$21 \core_calculate_stage_10_rb$120 + connect \xer_so$22 \core_calculate_stage_10_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_10_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_10_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_10_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_10_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_10_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_10_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_10_operation$128 + connect \quotient_root$30 \core_calculate_stage_10_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_10_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_10_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_10_compare_rhs$132 + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$6 + wire width 2 \core_calculate_stage_11_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -85027,7 +70631,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_spr_op__insn_type$7 + wire width 7 \core_calculate_stage_11_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -85041,143 +70645,73 @@ module \alu_spr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_spr_op__fn_unit$8 + wire width 11 \core_calculate_stage_11_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_spr_op__insn$9 + wire width 64 \core_calculate_stage_11_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_spr_op__is_32bit$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_spr1$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_so$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_xer_ov$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_xer_ca$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_ca_ok - cell \pipe$60 \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_p_valid_i - connect \p_ready_o \pipe_p_ready_o - connect \muxid \pipe_muxid - connect \spr_op__insn_type \pipe_spr_op__insn_type - connect \spr_op__fn_unit \pipe_spr_op__fn_unit - connect \spr_op__insn \pipe_spr_op__insn - connect \spr_op__is_32bit \pipe_spr_op__is_32bit - connect \ra \pipe_ra - connect \spr1 \pipe_spr1 - connect \fast1 \pipe_fast1 - connect \xer_so \pipe_xer_so - connect \xer_ov \pipe_xer_ov - connect \xer_ca \pipe_xer_ca - connect \n_valid_o \pipe_n_valid_o - connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$6 - connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 - connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 - connect \spr_op__insn$4 \pipe_spr_op__insn$9 - connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \spr1$6 \pipe_spr1$11 - connect \spr1_ok \pipe_spr1_ok - connect \fast1$7 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \xer_so$8 \pipe_xer_so$13 - connect \xer_so_ok \pipe_xer_so_ok - connect \xer_ov$9 \pipe_xer_ov$14 - connect \xer_ov_ok \pipe_xer_ov_ok - connect \xer_ca$10 \pipe_xer_ca$15 - connect \xer_ca_ok \pipe_xer_ca_ok - end - process $group_0 - assign \pipe_p_valid_i 1'0 - assign \pipe_p_valid_i \p_valid_i - sync init - end - process $group_1 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_2 - assign \pipe_muxid 2'00 - assign \pipe_muxid \muxid - sync init - end - process $group_3 - assign \pipe_spr_op__insn_type 7'0000000 - assign \pipe_spr_op__fn_unit 11'00000000000 - assign \pipe_spr_op__insn 32'00000000000000000000000000000000 - assign \pipe_spr_op__is_32bit 1'0 - assign { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - sync init - end - process $group_7 - assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_ra \ra - sync init - end - process $group_8 - assign \pipe_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_spr1 \spr1$1 - sync init - end - process $group_9 - assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_fast1 \fast1$2 - sync init - end - process $group_10 - assign \pipe_xer_so 1'0 - assign \pipe_xer_so \xer_so$3 - sync init - end - process $group_11 - assign \pipe_xer_ov 2'00 - assign \pipe_xer_ov \xer_ov$4 - sync init - end - process $group_12 - assign \pipe_xer_ca 2'00 - assign \pipe_xer_ca \xer_ca$5 - sync init - end - process $group_13 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_n_valid_o - sync init - end - process $group_14 - assign \pipe_n_ready_i 1'0 - assign \pipe_n_ready_i \n_ready_i - sync init - end + wire width 1 \core_calculate_stage_11_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_11_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_11_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_11_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_11_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_11_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_11_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_11_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_11_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_11_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_11_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_11_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_11_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_11_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_11_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_11_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_11_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_11_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$16 - process $group_15 - assign \muxid$16 2'00 - assign \muxid$16 \pipe_muxid$6 - sync init - end + wire width 2 \core_calculate_stage_11_muxid$133 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -85252,7 +70786,7 @@ module \alu_spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$17 + wire width 7 \core_calculate_stage_11_logical_op__insn_type$134 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -85266,1077 +70800,1821 @@ module \alu_spr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \spr_op__fn_unit$18 + wire width 11 \core_calculate_stage_11_logical_op__fn_unit$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$19 + wire width 64 \core_calculate_stage_11_logical_op__imm_data__imm$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \spr_op__is_32bit$20 - process $group_16 - assign \spr_op__insn_type$17 7'0000000 - assign \spr_op__fn_unit$18 11'00000000000 - assign \spr_op__insn$19 32'00000000000000000000000000000000 - assign \spr_op__is_32bit$20 1'0 - assign { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } + wire width 1 \core_calculate_stage_11_logical_op__imm_data__imm_ok$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__rc__rc$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__rc__rc_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__oe__oe$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__oe__oe_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__invert_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_11_logical_op__input_carry$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__invert_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__write_cr0$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__output_carry$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_11_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_11_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_11_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_11_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_11_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_11_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_11_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_11_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_11_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_11_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_11_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_11_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_11_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_11_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_11_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_11_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_11_compare_rhs$165 + cell \core_calculate_stage_11 \core_calculate_stage_11 + connect \muxid \core_calculate_stage_11_muxid + connect \logical_op__insn_type \core_calculate_stage_11_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_11_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_11_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_11_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_11_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_11_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_11_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_11_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_11_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_11_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_11_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_11_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_11_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_11_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_11_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_11_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_11_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_11_logical_op__insn + connect \ra \core_calculate_stage_11_ra + connect \rb \core_calculate_stage_11_rb + connect \xer_so \core_calculate_stage_11_xer_so + connect \divisor_neg \core_calculate_stage_11_divisor_neg + connect \dividend_neg \core_calculate_stage_11_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_11_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_11_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_11_div_by_zero + connect \divisor_radicand \core_calculate_stage_11_divisor_radicand + connect \operation \core_calculate_stage_11_operation + connect \quotient_root \core_calculate_stage_11_quotient_root + connect \root_times_radicand \core_calculate_stage_11_root_times_radicand + connect \compare_lhs \core_calculate_stage_11_compare_lhs + connect \compare_rhs \core_calculate_stage_11_compare_rhs + connect \muxid$1 \core_calculate_stage_11_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_11_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_11_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_11_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_11_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_11_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_11_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_11_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_11_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_11_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_11_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_11_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_11_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_11_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_11_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_11_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_11_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_11_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_11_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_11_ra$152 + connect \rb$21 \core_calculate_stage_11_rb$153 + connect \xer_so$22 \core_calculate_stage_11_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_11_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_11_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_11_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_11_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_11_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_11_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_11_operation$161 + connect \quotient_root$30 \core_calculate_stage_11_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_11_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_11_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_11_compare_rhs$165 + end + process $group_0 + assign \core_calculate_stage_8_muxid 2'00 + assign \core_calculate_stage_8_muxid \muxid sync init end - process $group_20 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_o_ok \pipe_o } + process $group_1 + assign \core_calculate_stage_8_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_8_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_8_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_8_logical_op__rc__rc 1'0 + assign \core_calculate_stage_8_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_8_logical_op__oe__oe 1'0 + assign \core_calculate_stage_8_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_8_logical_op__invert_in 1'0 + assign \core_calculate_stage_8_logical_op__zero_a 1'0 + assign \core_calculate_stage_8_logical_op__input_carry 2'00 + assign \core_calculate_stage_8_logical_op__invert_out 1'0 + assign \core_calculate_stage_8_logical_op__write_cr0 1'0 + assign \core_calculate_stage_8_logical_op__output_carry 1'0 + assign \core_calculate_stage_8_logical_op__is_32bit 1'0 + assign \core_calculate_stage_8_logical_op__is_signed 1'0 + assign \core_calculate_stage_8_logical_op__data_len 4'0000 + assign \core_calculate_stage_8_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_8_logical_op__insn \core_calculate_stage_8_logical_op__data_len \core_calculate_stage_8_logical_op__is_signed \core_calculate_stage_8_logical_op__is_32bit \core_calculate_stage_8_logical_op__output_carry \core_calculate_stage_8_logical_op__write_cr0 \core_calculate_stage_8_logical_op__invert_out \core_calculate_stage_8_logical_op__input_carry \core_calculate_stage_8_logical_op__zero_a \core_calculate_stage_8_logical_op__invert_in { \core_calculate_stage_8_logical_op__oe__oe_ok \core_calculate_stage_8_logical_op__oe__oe } { \core_calculate_stage_8_logical_op__rc__rc_ok \core_calculate_stage_8_logical_op__rc__rc } { \core_calculate_stage_8_logical_op__imm_data__imm_ok \core_calculate_stage_8_logical_op__imm_data__imm } \core_calculate_stage_8_logical_op__fn_unit \core_calculate_stage_8_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - process $group_22 - assign \spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr1_ok 1'0 - assign { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } + process $group_19 + assign \core_calculate_stage_8_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_ra \ra sync init end - process $group_24 - assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok 1'0 - assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + process $group_20 + assign \core_calculate_stage_8_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_rb \rb sync init end - process $group_26 - assign \xer_so 1'0 - assign \xer_so_ok 1'0 - assign { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } + process $group_21 + assign \core_calculate_stage_8_xer_so 1'0 + assign \core_calculate_stage_8_xer_so \xer_so sync init end - process $group_28 - assign \xer_ov 2'00 - assign \xer_ov_ok 1'0 - assign { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } + process $group_22 + assign \core_calculate_stage_8_divisor_neg 1'0 + assign \core_calculate_stage_8_divisor_neg \divisor_neg sync init end - process $group_30 - assign \xer_ca 2'00 - assign \xer_ca_ok 1'0 - assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } + process $group_23 + assign \core_calculate_stage_8_dividend_neg 1'0 + assign \core_calculate_stage_8_dividend_neg \dividend_neg sync init end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l" -module \src_l$63 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $1 + process $group_24 + assign \core_calculate_stage_8_dive_abs_ov32 1'0 + assign \core_calculate_stage_8_dive_abs_ov32 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B $1 - connect \Y $3 + process $group_25 + assign \core_calculate_stage_8_dive_abs_ov64 1'0 + assign \core_calculate_stage_8_dive_abs_ov64 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $3 - connect \B \s_src - connect \Y $5 + process $group_26 + assign \core_calculate_stage_8_div_by_zero 1'0 + assign \core_calculate_stage_8_div_by_zero \div_by_zero + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 6'000000 - end + process $group_27 + assign \core_calculate_stage_8_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_divisor_radicand \divisor_radicand sync init - update \q_int 6'000000 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $7 + process $group_28 + assign \core_calculate_stage_8_operation 2'00 + assign \core_calculate_stage_8_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_29 + assign \core_calculate_stage_8_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_quotient_root \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $9 - connect \B \s_src - connect \Y $11 + process $group_30 + assign \core_calculate_stage_8_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_root_times_radicand \root_times_radicand + sync init end - process $group_1 - assign \q_src 6'000000 - assign \q_src $11 + process $group_31 + assign \core_calculate_stage_8_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_compare_lhs \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \Y $13 + process $group_32 + assign \core_calculate_stage_8_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_compare_rhs \compare_rhs + sync init end - process $group_2 - assign \qn_src 6'000000 - assign \qn_src $13 + process $group_33 + assign \core_calculate_stage_9_muxid 2'00 + assign \core_calculate_stage_9_muxid \core_calculate_stage_8_muxid$34 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \B \q_int - connect \Y $15 + process $group_34 + assign \core_calculate_stage_9_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_9_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_9_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_9_logical_op__rc__rc 1'0 + assign \core_calculate_stage_9_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_9_logical_op__oe__oe 1'0 + assign \core_calculate_stage_9_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_9_logical_op__invert_in 1'0 + assign \core_calculate_stage_9_logical_op__zero_a 1'0 + assign \core_calculate_stage_9_logical_op__input_carry 2'00 + assign \core_calculate_stage_9_logical_op__invert_out 1'0 + assign \core_calculate_stage_9_logical_op__write_cr0 1'0 + assign \core_calculate_stage_9_logical_op__output_carry 1'0 + assign \core_calculate_stage_9_logical_op__is_32bit 1'0 + assign \core_calculate_stage_9_logical_op__is_signed 1'0 + assign \core_calculate_stage_9_logical_op__data_len 4'0000 + assign \core_calculate_stage_9_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_9_logical_op__insn \core_calculate_stage_9_logical_op__data_len \core_calculate_stage_9_logical_op__is_signed \core_calculate_stage_9_logical_op__is_32bit \core_calculate_stage_9_logical_op__output_carry \core_calculate_stage_9_logical_op__write_cr0 \core_calculate_stage_9_logical_op__invert_out \core_calculate_stage_9_logical_op__input_carry \core_calculate_stage_9_logical_op__zero_a \core_calculate_stage_9_logical_op__invert_in { \core_calculate_stage_9_logical_op__oe__oe_ok \core_calculate_stage_9_logical_op__oe__oe } { \core_calculate_stage_9_logical_op__rc__rc_ok \core_calculate_stage_9_logical_op__rc__rc } { \core_calculate_stage_9_logical_op__imm_data__imm_ok \core_calculate_stage_9_logical_op__imm_data__imm } \core_calculate_stage_9_logical_op__fn_unit \core_calculate_stage_9_logical_op__insn_type } { \core_calculate_stage_8_logical_op__insn$52 \core_calculate_stage_8_logical_op__data_len$51 \core_calculate_stage_8_logical_op__is_signed$50 \core_calculate_stage_8_logical_op__is_32bit$49 \core_calculate_stage_8_logical_op__output_carry$48 \core_calculate_stage_8_logical_op__write_cr0$47 \core_calculate_stage_8_logical_op__invert_out$46 \core_calculate_stage_8_logical_op__input_carry$45 \core_calculate_stage_8_logical_op__zero_a$44 \core_calculate_stage_8_logical_op__invert_in$43 { \core_calculate_stage_8_logical_op__oe__oe_ok$42 \core_calculate_stage_8_logical_op__oe__oe$41 } { \core_calculate_stage_8_logical_op__rc__rc_ok$40 \core_calculate_stage_8_logical_op__rc__rc$39 } { \core_calculate_stage_8_logical_op__imm_data__imm_ok$38 \core_calculate_stage_8_logical_op__imm_data__imm$37 } \core_calculate_stage_8_logical_op__fn_unit$36 \core_calculate_stage_8_logical_op__insn_type$35 } + sync init end - process $group_3 - assign \qlq_src 6'000000 - assign \qlq_src $15 + process $group_52 + assign \core_calculate_stage_9_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_ra \core_calculate_stage_8_ra$53 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l" -module \opc_l$64 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 + process $group_53 + assign \core_calculate_stage_9_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_rb \core_calculate_stage_8_rb$54 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + process $group_54 + assign \core_calculate_stage_9_xer_so 1'0 + assign \core_calculate_stage_9_xer_so \core_calculate_stage_8_xer_so$55 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 + process $group_55 + assign \core_calculate_stage_9_divisor_neg 1'0 + assign \core_calculate_stage_9_divisor_neg \core_calculate_stage_8_divisor_neg$56 + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_56 + assign \core_calculate_stage_9_dividend_neg 1'0 + assign \core_calculate_stage_9_dividend_neg \core_calculate_stage_8_dividend_neg$57 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 + process $group_57 + assign \core_calculate_stage_9_dive_abs_ov32 1'0 + assign \core_calculate_stage_9_dive_abs_ov32 \core_calculate_stage_8_dive_abs_ov32$58 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_58 + assign \core_calculate_stage_9_dive_abs_ov64 1'0 + assign \core_calculate_stage_9_dive_abs_ov64 \core_calculate_stage_8_dive_abs_ov64$59 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 + process $group_59 + assign \core_calculate_stage_9_div_by_zero 1'0 + assign \core_calculate_stage_9_div_by_zero \core_calculate_stage_8_div_by_zero$60 + sync init end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 + process $group_60 + assign \core_calculate_stage_9_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_divisor_radicand \core_calculate_stage_8_divisor_radicand$61 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 + process $group_61 + assign \core_calculate_stage_9_operation 2'00 + assign \core_calculate_stage_9_operation \core_calculate_stage_8_operation$62 + sync init end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 + process $group_62 + assign \core_calculate_stage_9_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_quotient_root \core_calculate_stage_8_quotient_root$63 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 + process $group_63 + assign \core_calculate_stage_9_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_root_times_radicand \core_calculate_stage_8_root_times_radicand$64 + sync init end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 + process $group_64 + assign \core_calculate_stage_9_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_compare_lhs \core_calculate_stage_8_compare_lhs$65 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l" -module \req_l$65 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_req - connect \Y $1 + process $group_65 + assign \core_calculate_stage_9_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_compare_rhs \core_calculate_stage_8_compare_rhs$66 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B $1 - connect \Y $3 + process $group_66 + assign \core_calculate_stage_10_muxid 2'00 + assign \core_calculate_stage_10_muxid \core_calculate_stage_9_muxid$67 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $3 - connect \B \s_req - connect \Y $5 + process $group_67 + assign \core_calculate_stage_10_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_10_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_10_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_10_logical_op__rc__rc 1'0 + assign \core_calculate_stage_10_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_10_logical_op__oe__oe 1'0 + assign \core_calculate_stage_10_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_10_logical_op__invert_in 1'0 + assign \core_calculate_stage_10_logical_op__zero_a 1'0 + assign \core_calculate_stage_10_logical_op__input_carry 2'00 + assign \core_calculate_stage_10_logical_op__invert_out 1'0 + assign \core_calculate_stage_10_logical_op__write_cr0 1'0 + assign \core_calculate_stage_10_logical_op__output_carry 1'0 + assign \core_calculate_stage_10_logical_op__is_32bit 1'0 + assign \core_calculate_stage_10_logical_op__is_signed 1'0 + assign \core_calculate_stage_10_logical_op__data_len 4'0000 + assign \core_calculate_stage_10_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_10_logical_op__insn \core_calculate_stage_10_logical_op__data_len \core_calculate_stage_10_logical_op__is_signed \core_calculate_stage_10_logical_op__is_32bit \core_calculate_stage_10_logical_op__output_carry \core_calculate_stage_10_logical_op__write_cr0 \core_calculate_stage_10_logical_op__invert_out \core_calculate_stage_10_logical_op__input_carry \core_calculate_stage_10_logical_op__zero_a \core_calculate_stage_10_logical_op__invert_in { \core_calculate_stage_10_logical_op__oe__oe_ok \core_calculate_stage_10_logical_op__oe__oe } { \core_calculate_stage_10_logical_op__rc__rc_ok \core_calculate_stage_10_logical_op__rc__rc } { \core_calculate_stage_10_logical_op__imm_data__imm_ok \core_calculate_stage_10_logical_op__imm_data__imm } \core_calculate_stage_10_logical_op__fn_unit \core_calculate_stage_10_logical_op__insn_type } { \core_calculate_stage_9_logical_op__insn$85 \core_calculate_stage_9_logical_op__data_len$84 \core_calculate_stage_9_logical_op__is_signed$83 \core_calculate_stage_9_logical_op__is_32bit$82 \core_calculate_stage_9_logical_op__output_carry$81 \core_calculate_stage_9_logical_op__write_cr0$80 \core_calculate_stage_9_logical_op__invert_out$79 \core_calculate_stage_9_logical_op__input_carry$78 \core_calculate_stage_9_logical_op__zero_a$77 \core_calculate_stage_9_logical_op__invert_in$76 { \core_calculate_stage_9_logical_op__oe__oe_ok$75 \core_calculate_stage_9_logical_op__oe__oe$74 } { \core_calculate_stage_9_logical_op__rc__rc_ok$73 \core_calculate_stage_9_logical_op__rc__rc$72 } { \core_calculate_stage_9_logical_op__imm_data__imm_ok$71 \core_calculate_stage_9_logical_op__imm_data__imm$70 } \core_calculate_stage_9_logical_op__fn_unit$69 \core_calculate_stage_9_logical_op__insn_type$68 } + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 6'000000 - end + process $group_85 + assign \core_calculate_stage_10_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_ra \core_calculate_stage_9_ra$86 sync init - update \q_int 6'000000 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_req - connect \Y $7 + process $group_86 + assign \core_calculate_stage_10_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_rb \core_calculate_stage_9_rb$87 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_87 + assign \core_calculate_stage_10_xer_so 1'0 + assign \core_calculate_stage_10_xer_so \core_calculate_stage_9_xer_so$88 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $9 - connect \B \s_req - connect \Y $11 + process $group_88 + assign \core_calculate_stage_10_divisor_neg 1'0 + assign \core_calculate_stage_10_divisor_neg \core_calculate_stage_9_divisor_neg$89 + sync init end - process $group_1 - assign \q_req 6'000000 - assign \q_req $11 + process $group_89 + assign \core_calculate_stage_10_dividend_neg 1'0 + assign \core_calculate_stage_10_dividend_neg \core_calculate_stage_9_dividend_neg$90 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_req - connect \Y $13 + process $group_90 + assign \core_calculate_stage_10_dive_abs_ov32 1'0 + assign \core_calculate_stage_10_dive_abs_ov32 \core_calculate_stage_9_dive_abs_ov32$91 + sync init end - process $group_2 - assign \qn_req 6'000000 - assign \qn_req $13 + process $group_91 + assign \core_calculate_stage_10_dive_abs_ov64 1'0 + assign \core_calculate_stage_10_dive_abs_ov64 \core_calculate_stage_9_dive_abs_ov64$92 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_req - connect \B \q_int - connect \Y $15 + process $group_92 + assign \core_calculate_stage_10_div_by_zero 1'0 + assign \core_calculate_stage_10_div_by_zero \core_calculate_stage_9_div_by_zero$93 + sync init end - process $group_3 - assign \qlq_req 6'000000 - assign \qlq_req $15 + process $group_93 + assign \core_calculate_stage_10_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_divisor_radicand \core_calculate_stage_9_divisor_radicand$94 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l" -module \rst_l$66 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 + process $group_94 + assign \core_calculate_stage_10_operation 2'00 + assign \core_calculate_stage_10_operation \core_calculate_stage_9_operation$95 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + process $group_95 + assign \core_calculate_stage_10_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_quotient_root \core_calculate_stage_9_quotient_root$96 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 + process $group_96 + assign \core_calculate_stage_10_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_root_times_radicand \core_calculate_stage_9_root_times_radicand$97 + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_97 + assign \core_calculate_stage_10_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_compare_lhs \core_calculate_stage_9_compare_lhs$98 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 + process $group_98 + assign \core_calculate_stage_10_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_compare_rhs \core_calculate_stage_9_compare_rhs$99 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_99 + assign \core_calculate_stage_11_muxid 2'00 + assign \core_calculate_stage_11_muxid \core_calculate_stage_10_muxid$100 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 + process $group_100 + assign \core_calculate_stage_11_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_11_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_11_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_11_logical_op__rc__rc 1'0 + assign \core_calculate_stage_11_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_11_logical_op__oe__oe 1'0 + assign \core_calculate_stage_11_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_11_logical_op__invert_in 1'0 + assign \core_calculate_stage_11_logical_op__zero_a 1'0 + assign \core_calculate_stage_11_logical_op__input_carry 2'00 + assign \core_calculate_stage_11_logical_op__invert_out 1'0 + assign \core_calculate_stage_11_logical_op__write_cr0 1'0 + assign \core_calculate_stage_11_logical_op__output_carry 1'0 + assign \core_calculate_stage_11_logical_op__is_32bit 1'0 + assign \core_calculate_stage_11_logical_op__is_signed 1'0 + assign \core_calculate_stage_11_logical_op__data_len 4'0000 + assign \core_calculate_stage_11_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_11_logical_op__insn \core_calculate_stage_11_logical_op__data_len \core_calculate_stage_11_logical_op__is_signed \core_calculate_stage_11_logical_op__is_32bit \core_calculate_stage_11_logical_op__output_carry \core_calculate_stage_11_logical_op__write_cr0 \core_calculate_stage_11_logical_op__invert_out \core_calculate_stage_11_logical_op__input_carry \core_calculate_stage_11_logical_op__zero_a \core_calculate_stage_11_logical_op__invert_in { \core_calculate_stage_11_logical_op__oe__oe_ok \core_calculate_stage_11_logical_op__oe__oe } { \core_calculate_stage_11_logical_op__rc__rc_ok \core_calculate_stage_11_logical_op__rc__rc } { \core_calculate_stage_11_logical_op__imm_data__imm_ok \core_calculate_stage_11_logical_op__imm_data__imm } \core_calculate_stage_11_logical_op__fn_unit \core_calculate_stage_11_logical_op__insn_type } { \core_calculate_stage_10_logical_op__insn$118 \core_calculate_stage_10_logical_op__data_len$117 \core_calculate_stage_10_logical_op__is_signed$116 \core_calculate_stage_10_logical_op__is_32bit$115 \core_calculate_stage_10_logical_op__output_carry$114 \core_calculate_stage_10_logical_op__write_cr0$113 \core_calculate_stage_10_logical_op__invert_out$112 \core_calculate_stage_10_logical_op__input_carry$111 \core_calculate_stage_10_logical_op__zero_a$110 \core_calculate_stage_10_logical_op__invert_in$109 { \core_calculate_stage_10_logical_op__oe__oe_ok$108 \core_calculate_stage_10_logical_op__oe__oe$107 } { \core_calculate_stage_10_logical_op__rc__rc_ok$106 \core_calculate_stage_10_logical_op__rc__rc$105 } { \core_calculate_stage_10_logical_op__imm_data__imm_ok$104 \core_calculate_stage_10_logical_op__imm_data__imm$103 } \core_calculate_stage_10_logical_op__fn_unit$102 \core_calculate_stage_10_logical_op__insn_type$101 } + sync init end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 + process $group_118 + assign \core_calculate_stage_11_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_ra \core_calculate_stage_10_ra$119 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 + process $group_119 + assign \core_calculate_stage_11_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_rb \core_calculate_stage_10_rb$120 + sync init end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 + process $group_120 + assign \core_calculate_stage_11_xer_so 1'0 + assign \core_calculate_stage_11_xer_so \core_calculate_stage_10_xer_so$121 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 + process $group_121 + assign \core_calculate_stage_11_divisor_neg 1'0 + assign \core_calculate_stage_11_divisor_neg \core_calculate_stage_10_divisor_neg$122 + sync init end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 + process $group_122 + assign \core_calculate_stage_11_dividend_neg 1'0 + assign \core_calculate_stage_11_dividend_neg \core_calculate_stage_10_dividend_neg$123 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l" -module \rok_l$67 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 + process $group_123 + assign \core_calculate_stage_11_dive_abs_ov32 1'0 + assign \core_calculate_stage_11_dive_abs_ov32 \core_calculate_stage_10_dive_abs_ov32$124 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + process $group_124 + assign \core_calculate_stage_11_dive_abs_ov64 1'0 + assign \core_calculate_stage_11_dive_abs_ov64 \core_calculate_stage_10_dive_abs_ov64$125 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 + process $group_125 + assign \core_calculate_stage_11_div_by_zero 1'0 + assign \core_calculate_stage_11_div_by_zero \core_calculate_stage_10_div_by_zero$126 + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_126 + assign \core_calculate_stage_11_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_divisor_radicand \core_calculate_stage_10_divisor_radicand$127 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 + process $group_127 + assign \core_calculate_stage_11_operation 2'00 + assign \core_calculate_stage_11_operation \core_calculate_stage_10_operation$128 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_128 + assign \core_calculate_stage_11_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_quotient_root \core_calculate_stage_10_quotient_root$129 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 + process $group_129 + assign \core_calculate_stage_11_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_root_times_radicand \core_calculate_stage_10_root_times_radicand$130 + sync init end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 + process $group_130 + assign \core_calculate_stage_11_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_compare_lhs \core_calculate_stage_10_compare_lhs$131 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 + process $group_131 + assign \core_calculate_stage_11_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_compare_rhs \core_calculate_stage_10_compare_rhs$132 + sync init end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l" -module \alui_l$68 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_11_muxid$133 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_11_logical_op__insn$151 \core_calculate_stage_11_logical_op__data_len$150 \core_calculate_stage_11_logical_op__is_signed$149 \core_calculate_stage_11_logical_op__is_32bit$148 \core_calculate_stage_11_logical_op__output_carry$147 \core_calculate_stage_11_logical_op__write_cr0$146 \core_calculate_stage_11_logical_op__invert_out$145 \core_calculate_stage_11_logical_op__input_carry$144 \core_calculate_stage_11_logical_op__zero_a$143 \core_calculate_stage_11_logical_op__invert_in$142 { \core_calculate_stage_11_logical_op__oe__oe_ok$141 \core_calculate_stage_11_logical_op__oe__oe$140 } { \core_calculate_stage_11_logical_op__rc__rc_ok$139 \core_calculate_stage_11_logical_op__rc__rc$138 } { \core_calculate_stage_11_logical_op__imm_data__imm_ok$137 \core_calculate_stage_11_logical_op__imm_data__imm$136 } \core_calculate_stage_11_logical_op__fn_unit$135 \core_calculate_stage_11_logical_op__insn_type$134 } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_11_ra$152 + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_11_rb$153 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_11_xer_so$154 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_11_divisor_neg$155 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_11_dividend_neg$156 + sync init end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_11_dive_abs_ov32$157 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_11_dive_abs_ov64$158 + sync init end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_11_div_by_zero$159 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_11_divisor_radicand$160 + sync init end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_11_operation$161 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l" -module \alu_l$69 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_11_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_11_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_11_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_11_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next + end + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end + sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next + end + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.p" +module \p$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r_alu + connect \A \p_valid_i + connect \B \p_ready_o connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.n" +module \n$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_12.core.trial0" +module \trial0$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu + connect \A \operation + connect \B 1'1 connect \Y $5 end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110011 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \q_int$next 1'0 + assign \trial_compare_rhs $7 [191:0] end sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_12.core.trial1" +module \trial1$132 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110011 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_12.core.pe" +module \pe$133 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 + connect \A \i + connect \B 1'0 + connect \Y $1 end process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 + assign \n 1'0 + assign \n $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_12.core" +module \core$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$131 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$132 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$133 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 + connect \A \pe_n + connect \Y $14 end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'110011 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0" -module \spr0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_12" +module \core_calculate_stage_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -86411,7 +72689,7 @@ module \spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_spr0__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -86425,79 +72703,73 @@ module \spr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_spr0__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \oper_i_alu_spr0__insn + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_spr0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 5 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 6 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 6 input 7 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 8 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 input 9 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 10 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 1 input 11 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 2 input 12 \src6_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 2 input 13 \src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 14 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 15 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 16 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 17 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 input 18 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 19 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 20 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 21 \dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 22 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 23 \dest5_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 24 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 output 25 \dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 26 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 27 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 28 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 29 \dest2_o - attribute \src "simple/issuer.py:89" - wire width 1 input 30 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_spr0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_spr0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_spr0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_spr0_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_spr0_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \alu_spr0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_spr0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_spr0_xer_ca + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -86572,7 +72844,7 @@ module \spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_spr0_spr_op__insn_type + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -86586,806 +72858,836 @@ module \spr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_spr0_spr_op__fn_unit + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_spr0_spr_op__insn + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_spr0_spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_spr0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_spr0_spr1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_spr0_fast1$2 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \alu_spr0_xer_so$3 + wire width 64 output 52 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_spr0_xer_ov$4 + wire width 64 output 53 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_spr0_xer_ca$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_spr0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_spr0_p_ready_o - cell \alu_spr0 \alu_spr0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - connect \fast1_ok \fast1_ok - connect \spr1_ok \spr1_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_spr0_n_valid_o - connect \n_ready_i \alu_spr0_n_ready_i - connect \o \alu_spr0_o - connect \spr1 \alu_spr0_spr1 - connect \fast1 \alu_spr0_fast1 - connect \xer_so \alu_spr0_xer_so - connect \xer_ov \alu_spr0_xer_ov - connect \xer_ca \alu_spr0_xer_ca - connect \spr_op__insn_type \alu_spr0_spr_op__insn_type - connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit - connect \spr_op__insn \alu_spr0_spr_op__insn - connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit - connect \ra \alu_spr0_ra - connect \spr1$1 \alu_spr0_spr1$1 - connect \fast1$2 \alu_spr0_fast1$2 - connect \xer_so$3 \alu_spr0_xer_so$3 - connect \xer_ov$4 \alu_spr0_xer_ov$4 - connect \xer_ca$5 \alu_spr0_xer_ca$5 - connect \p_valid_i \alu_spr0_p_valid_i - connect \p_ready_o \alu_spr0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 \src_l_q_src - cell \src_l$63 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$130 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$64 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \req_l_r_req$next - cell \req_l$65 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - cell \rst_l$66 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$67 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$68 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$69 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - cell $and $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $6 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 6 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__rel_o - connect \Y $9 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 6 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $9 - connect \B \cu_rd__go_i - connect \Y $11 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $reduce_and $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A $11 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $6 - connect \B $8 - connect \Y $14 - end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $14 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $and $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $16 - connect \Y $18 end - process $group_2 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse $18 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_done - process $group_3 - assign \alu_done 1'0 - assign \alu_done \alu_spr0_n_valid_o + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly$next - process $group_4 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $not $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $and $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $20 - connect \Y $22 end - process $group_5 - assign \alu_pulse 1'0 - assign \alu_pulse $22 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" - wire width 6 \alu_pulsem - process $group_6 - assign \alu_pulsem 6'000000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 6 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 6 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 6 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $24 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - process $group_7 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $24 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 6'000000 - end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init - update \prev_wr_go 6'000000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 6 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wrmask_o - connect \Y $28 + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 6 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wr__rel_o - connect \B $28 - connect \Y $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A $30 - connect \Y $27 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $26 + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $35 + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_13.core.trial0" +module \trial0$135 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $26 - connect \Y $34 - end - process $group_8 - assign \cu_done_o 1'0 - assign \cu_done_o $34 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $36 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $38 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $or $41 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $36 - connect \B $38 - connect \Y $40 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_9 - assign \wr_any 1'0 - assign \wr_any $40 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $not $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_n_ready_i - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $and $45 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $42 - connect \Y $44 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 6 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $47 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $46 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110010 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $eq $49 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $46 - connect \B 1'0 - connect \Y $48 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $51 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_13.core.trial1" +module \trial1$136 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $44 - connect \B $48 - connect \Y $50 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $eq $53 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $52 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $55 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $52 - connect \B \alu_spr0_n_ready_i - connect \Y $54 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $57 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $54 - connect \B \alu_spr0_n_valid_o - connect \Y $56 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110010 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $56 - connect \B \cu_busy_o - connect \Y $58 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_10 - assign \req_done 1'0 - assign \req_done $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - switch { $58 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \req_done 1'1 + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 1 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $61 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_13.core.pe" +module \pe$137 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $60 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_11 - assign \reset 1'0 - assign \reset $60 + process $group_1 + assign \n 1'0 + assign \n $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - wire width 1 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - cell $or $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $62 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_13.core" +module \core$134 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$135 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$136 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - process $group_12 - assign \rst_r 1'0 - assign \rst_r $62 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$137 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 6 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - wire width 6 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - cell $or $65 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $64 + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init end process $group_13 - assign \reset_w 6'000000 - assign \reset_w $64 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 6 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - wire width 6 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - cell $or $67 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $66 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end process $group_14 - assign \reset_r 6'000000 - assign \reset_r $66 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags process $group_15 - assign \rok_l_s_rdok 1'0 - assign \rok_l_s_rdok \cu_issue_i + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - wire width 1 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - cell $and $69 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_n_valid_o - connect \B \cu_busy_o - connect \Y $68 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_16 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $68 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \rok_l_r_rdok$next 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next end - process $group_17 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \all_rd - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end process $group_18 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \rst_r + assign \nbe 1'0 + assign \nbe $19 sync init end - process $group_19 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_20 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next end - process $group_21 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 6'000000 - end - sync init - update \src_l_s_src 6'000000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - process $group_22 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 6'111111 - end - sync init - update \src_l_r_src 6'111111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - wire width 6 $70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - cell $and $71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $70 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_23 - assign \req_l_s_req 6'000000 - assign \req_l_s_req $70 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - wire width 6 $72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - cell $or $73 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $72 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'110010 + connect \Y $30 end - process $group_24 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $72 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 6'111111 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init - update \req_l_r_req 6'111111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_13" +module \core_calculate_stage_13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -87460,7 +73762,7 @@ module \spr0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -87474,1262 +73776,989 @@ module \spr0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 51 $74 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $75 - parameter \WIDTH 51 - connect \A { \oper_l__is_32bit \oper_l__insn \oper_l__fn_unit \oper_l__insn_type } - connect \B { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } - connect \S \cu_issue_i - connect \Y $74 + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$134 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end process $group_25 - assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 11'00000000000 - assign \oper_r__insn 32'00000000000000000000000000000000 - assign \oper_r__is_32bit 1'0 - assign { \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $74 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end process $group_29 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__insn$next \oper_l__insn - assign \oper_l__is_32bit$next \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \oper_l__is_32bit$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } - end + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 11'00000000000 - update \oper_l__insn 32'00000000000000000000000000000000 - update \oper_l__is_32bit 1'0 - sync posedge \coresync_clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__insn \oper_l__insn$next - update \oper_l__is_32bit \oper_l__is_32bit$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $76 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $77 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $79 - parameter \WIDTH 65 - connect \A { \data_r0_l__o_ok \data_r0_l__o } - connect \B { \o_ok \alu_spr0_o } - connect \S $77 - connect \Y $76 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end process $group_33 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - assign { \data_r0__o_ok \data_r0__o } $76 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $80 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $80 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end process $group_35 - assign \data_r0_l__o$next \data_r0_l__o - assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $80 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_spr0_o } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0_l__o_ok$next 1'0 - end + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init - update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0_l__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0_l__o \data_r0_l__o$next - update \data_r0_l__o_ok \data_r0_l__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r1__spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r1__spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r1_l__spr1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r1_l__spr1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__spr1_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $82 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $83 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $85 - parameter \WIDTH 65 - connect \A { \data_r1_l__spr1_ok \data_r1_l__spr1 } - connect \B { \spr1_ok \alu_spr0_spr1 } - connect \S $83 - connect \Y $82 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end process $group_37 - assign \data_r1__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r1__spr1_ok 1'0 - assign { \data_r1__spr1_ok \data_r1__spr1 } $82 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $87 + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_14.core.trial0" +module \trial0$139 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $86 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - process $group_39 - assign \data_r1_l__spr1$next \data_r1_l__spr1 - assign \data_r1_l__spr1_ok$next \data_r1_l__spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $86 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r1_l__spr1_ok$next \data_r1_l__spr1$next } { \spr1_ok \alu_spr0_spr1 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \data_r1_l__spr1_ok$next 1'0 + assign \dr_times_trial_bits $3 end sync init - update \data_r1_l__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r1_l__spr1_ok 1'0 - sync posedge \coresync_clk - update \data_r1_l__spr1 \data_r1_l__spr1$next - update \data_r1_l__spr1_ok \data_r1_l__spr1_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r2__fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r2__fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r2_l__fast1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r2_l__fast1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $88 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $89 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $91 - parameter \WIDTH 65 - connect \A { \data_r2_l__fast1_ok \data_r2_l__fast1 } - connect \B { \fast1_ok \alu_spr0_fast1 } - connect \S $89 - connect \Y $88 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110001 + connect \Y $8 end - process $group_41 - assign \data_r2__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r2__fast1_ok 1'0 - assign { \data_r2__fast1_ok \data_r2__fast1 } $88 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $92 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $92 - end - process $group_43 - assign \data_r2_l__fast1$next \data_r2_l__fast1 - assign \data_r2_l__fast1_ok$next \data_r2_l__fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $92 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r2_l__fast1_ok$next \data_r2_l__fast1$next } { \fast1_ok \alu_spr0_fast1 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2_l__fast1_ok$next 1'0 - end - sync init - update \data_r2_l__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r2_l__fast1_ok 1'0 - sync posedge \coresync_clk - update \data_r2_l__fast1 \data_r2_l__fast1$next - update \data_r2_l__fast1_ok \data_r2_l__fast1_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r3__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $94 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $96 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_14.core.trial1" +module \trial1$140 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $97 - parameter \WIDTH 2 - connect \A { \data_r3_l__xer_so_ok \data_r3_l__xer_so } - connect \B { \xer_so_ok \alu_spr0_xer_so } - connect \S $95 - connect \Y $94 - end - process $group_45 - assign \data_r3__xer_so 1'0 - assign \data_r3__xer_so_ok 1'0 - assign { \data_r3__xer_so_ok \data_r3__xer_so } $94 - sync init + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $98 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $99 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $98 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_47 - assign \data_r3_l__xer_so$next \data_r3_l__xer_so - assign \data_r3_l__xer_so_ok$next \data_r3_l__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $98 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \alu_spr0_xer_so } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \data_r3_l__xer_so_ok$next 1'0 + assign \dr_times_trial_bits $3 end sync init - update \data_r3_l__xer_so 1'0 - update \data_r3_l__xer_so_ok 1'0 - sync posedge \coresync_clk - update \data_r3_l__xer_so \data_r3_l__xer_so$next - update \data_r3_l__xer_so_ok \data_r3_l__xer_so_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 2 \data_r4__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r4__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r4_l__xer_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r4_l__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r4_l__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r4_l__xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 3 $100 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $102 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $103 - parameter \WIDTH 3 - connect \A { \data_r4_l__xer_ov_ok \data_r4_l__xer_ov } - connect \B { \xer_ov_ok \alu_spr0_xer_ov } - connect \S $101 - connect \Y $100 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_49 - assign \data_r4__xer_ov 2'00 - assign \data_r4__xer_ov_ok 1'0 - assign { \data_r4__xer_ov_ok \data_r4__xer_ov } $100 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110001 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $104 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $105 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $104 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_51 - assign \data_r4_l__xer_ov$next \data_r4_l__xer_ov - assign \data_r4_l__xer_ov_ok$next \data_r4_l__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $104 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r4_l__xer_ov_ok$next \data_r4_l__xer_ov$next } { \xer_ov_ok \alu_spr0_xer_ov } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \data_r4_l__xer_ov_ok$next 1'0 + assign \trial_compare_rhs $7 [191:0] end sync init - update \data_r4_l__xer_ov 2'00 - update \data_r4_l__xer_ov_ok 1'0 - sync posedge \coresync_clk - update \data_r4_l__xer_ov \data_r4_l__xer_ov$next - update \data_r4_l__xer_ov_ok \data_r4_l__xer_ov_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 2 \data_r5__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r5__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r5_l__xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r5_l__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r5_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r5_l__xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 3 $106 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $109 - parameter \WIDTH 3 - connect \A { \data_r5_l__xer_ca_ok \data_r5_l__xer_ca } - connect \B { \xer_ca_ok \alu_spr0_xer_ca } - connect \S $107 - connect \Y $106 - end - process $group_53 - assign \data_r5__xer_ca 2'00 - assign \data_r5__xer_ca_ok 1'0 - assign { \data_r5__xer_ca_ok \data_r5__xer_ca } $106 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $110 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $110 end - process $group_55 - assign \data_r5_l__xer_ca$next \data_r5_l__xer_ca - assign \data_r5_l__xer_ca_ok$next \data_r5_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $110 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_14.core.pe" +module \pe$141 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign { \data_r5_l__xer_ca_ok$next \data_r5_l__xer_ca$next } { \xer_ca_ok \alu_spr0_xer_ca } + assign \o 1'1 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \data_r5_l__xer_ca_ok$next 1'0 + assign \o 1'0 end sync init - update \data_r5_l__xer_ca 2'00 - update \data_r5_l__xer_ca_ok 1'0 - sync posedge \coresync_clk - update \data_r5_l__xer_ca \data_r5_l__xer_ca$next - update \data_r5_l__xer_ca_ok \data_r5_l__xer_ca_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r0__o_ok - connect \B \cu_busy_o - connect \Y $112 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r1__spr1_ok - connect \B \cu_busy_o - connect \Y $114 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r2__fast1_ok - connect \B \cu_busy_o - connect \Y $116 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r3__xer_so_ok - connect \B \cu_busy_o - connect \Y $118 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r4__xer_ov_ok - connect \B \cu_busy_o - connect \Y $120 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $123 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r5__xer_ca_ok - connect \B \cu_busy_o - connect \Y $122 - end - process $group_57 - assign \cu_wrmask_o 6'000000 - assign \cu_wrmask_o { $122 $120 $118 $116 $114 $112 } - sync init - end - process $group_58 - assign \alu_spr0_spr_op__insn_type 7'0000000 - assign \alu_spr0_spr_op__fn_unit 11'00000000000 - assign \alu_spr0_spr_op__insn 32'00000000000000000000000000000000 - assign \alu_spr0_spr_op__is_32bit 1'0 - assign { \alu_spr0_spr_op__is_32bit \alu_spr0_spr_op__insn \alu_spr0_spr_op__fn_unit \alu_spr0_spr_op__insn_type } { \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $124 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $125 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $124 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_62 - assign \alu_spr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_spr0_ra $124 + process $group_1 + assign \n 1'0 + assign \n $1 sync init end - process $group_63 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src1_i - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_14.core" +module \core$138 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$139 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$140 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $126 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $127 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $126 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$141 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end - process $group_64 - assign \alu_spr0_spr1$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_spr0_spr1$1 $126 + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - process $group_65 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src2_i - end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $128 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $129 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $128 end - process $group_66 - assign \alu_spr0_fast1$2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_spr0_fast1$2 $128 + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init end - process $group_67 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init - update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $130 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $131 - parameter \WIDTH 1 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $130 end - process $group_68 - assign \alu_spr0_xer_so$3 1'0 - assign \alu_spr0_xer_so$3 $130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init end - process $group_69 - assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r3$next \src4_i - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init - update \src_r3 1'0 - sync posedge \coresync_clk - update \src_r3 \src_r3$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $132 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $133 - parameter \WIDTH 2 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $132 end - process $group_70 - assign \alu_spr0_xer_ov$4 2'00 - assign \alu_spr0_xer_ov$4 $132 + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end - process $group_71 - assign \src_r4$next \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [4] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r4$next \src5_i - end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init - update \src_r4 2'00 - sync posedge \coresync_clk - update \src_r4 \src_r4$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r5$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $134 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $135 - parameter \WIDTH 2 - connect \A \src_r5 - connect \B \src6_i - connect \S \src_l_q_src [5] - connect \Y $134 end - process $group_72 - assign \alu_spr0_xer_ca$5 2'00 - assign \alu_spr0_xer_ca$5 $134 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end - process $group_73 - assign \src_r5$next \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [5] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r5$next \src6_i - end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init - update \src_r5 2'00 - sync posedge \coresync_clk - update \src_r5 \src_r5$next end - process $group_74 - assign \alu_spr0_p_valid_i 1'0 - assign \alu_spr0_p_valid_i \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - wire width 1 $136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - cell $and $137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $136 - end - process $group_75 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $136 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next end - process $group_76 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end - process $group_77 - assign \alu_spr0_n_ready_i 1'0 - assign \alu_spr0_n_ready_i \alu_l_q_alu + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - wire width 1 $138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - cell $and $139 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \alu_spr0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $138 - end - process $group_78 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $138 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_79 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_80 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 6 $140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $140 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 6 $142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $140 - connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 } - connect \Y $142 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 6 $144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $not $145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rdmaskn_i - connect \Y $144 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 6 $146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $142 - connect \B $144 - connect \Y $146 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - process $group_81 - assign \cu_rd__rel_o 6'000000 - assign \cu_rd__rel_o $146 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $148 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $150 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $152 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $154 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $156 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $158 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 6 $160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \req_l_q_req - connect \B { $148 $150 $152 $154 $156 $158 } - connect \Y $160 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 6 $162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $160 - connect \B \cu_wrmask_o - connect \Y $162 - end - process $group_82 - assign \cu_wr__rel_o 6'000000 - assign \cu_wr__rel_o $162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $165 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $164 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - process $group_83 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $164 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $167 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $166 - end - process $group_84 - assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $166 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest2_o { \data_r1__spr1_ok \data_r1__spr1 } [63:0] - end - sync init + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $169 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $168 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_85 - assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $168 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \dest3_o { \data_r2__fast1_ok \data_r2__fast1 } [63:0] + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $171 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $170 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_86 - assign \dest4_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $170 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0] - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $173 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [4] - connect \B \cu_busy_o - connect \Y $172 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_87 - assign \dest5_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $172 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest5_o { \data_r4__xer_ov_ok \data_r4__xer_ov } [1:0] - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $175 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [5] - connect \B \cu_busy_o - connect \Y $174 - end - process $group_88 - assign \dest6_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $174 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest6_o { \data_r5__xer_ca_ok \data_r5__xer_ca } [1:0] - end - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.p" -module \p$70 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.n" -module \n$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.p" -module \p$72 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'110001 + connect \Y $30 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.n" -module \n$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.input" -module \input$74 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_14" +module \core_calculate_stage_14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -88834,7 +74863,7 @@ module \input$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" @@ -88863,8 +74892,30 @@ module \input$74 wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -88939,7 +74990,7 @@ module \input$74 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -88953,95 +75004,112 @@ module \input$74 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 24 \logical_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__imm$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \logical_op__imm_data__imm_ok$5 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \logical_op__rc__rc$6 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__rc__rc_ok$7 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__oe__oe$8 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__oe__oe_ok$9 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__invert_a$10 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__zero_a$11 + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__invert_out$13 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__write_cr0$14 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__output_carry$15 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__is_32bit$16 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__is_signed$17 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \ra$20 + wire width 64 output 52 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \rb$21 + wire width 64 output 53 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 43 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24" - wire width 64 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24" - cell $not $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $23 + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$138 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23" - switch { \logical_op__invert_a } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23" - case 1'1 - assign \a $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25" - case - assign \a \ra - end - sync init - end - process $group_1 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \a - sync init - end - process $group_2 - assign \xer_so$22 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47" - switch { \logical_op__oe__oe_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47" - case 1'1 - assign \xer_so$22 \xer_so - end - sync init - end - process $group_3 assign \muxid$1 2'00 assign \muxid$1 \muxid sync init end - process $group_4 + process $group_1 assign \logical_op__insn_type$2 7'0000000 assign \logical_op__fn_unit$3 11'00000000000 assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -89050,7 +75118,7 @@ module \input$74 assign \logical_op__rc__rc_ok$7 1'0 assign \logical_op__oe__oe$8 1'0 assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_a$10 1'0 + assign \logical_op__invert_in$10 1'0 assign \logical_op__zero_a$11 1'0 assign \logical_op__input_carry$12 2'00 assign \logical_op__invert_out$13 1'0 @@ -89060,115 +75128,807 @@ module \input$74 assign \logical_op__is_signed$17 1'0 assign \logical_op__data_len$18 4'0000 assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - process $group_22 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 assign \rb$21 \rb sync init end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.setup_stage" -module \setup_stage - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_15.core.trial0" +module \trial0$143 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110000 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_15.core.trial1" +module \trial1$144 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1110000 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_15.core.pe" +module \pe$145 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_15.core" +module \core$142 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$143 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$144 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$145 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'110000 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3.core_calculate_stage_15" +module \core_calculate_stage_15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -89176,7 +75936,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" @@ -89205,8 +75965,30 @@ module \setup_stage wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -89281,7 +76063,7 @@ module \setup_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -89295,448 +76077,250 @@ module \setup_stage attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 24 \logical_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__imm$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \logical_op__imm_data__imm_ok$5 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \logical_op__rc__rc$6 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__rc__rc_ok$7 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__oe__oe$8 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__oe__oe_ok$9 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__invert_a$10 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__zero_a$11 + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__invert_out$13 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__write_cr0$14 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__output_carry$15 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__is_32bit$16 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__is_signed$17 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 41 \xer_so$20 + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 42 \divisor_neg + wire width 1 output 55 \divisor_neg$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 43 \dividend_neg + wire width 1 output 56 \dividend_neg$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 44 \dive_abs_ov32 + wire width 1 output 57 \dive_abs_ov32$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 45 \dive_abs_ov64 + wire width 1 output 58 \dive_abs_ov64$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 46 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 output 47 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 output 48 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 output 49 \operation - wire width 1 $verilog_initial_trigger + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$142 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end process $group_0 - assign \operation 2'00 - assign \operation 2'01 - assign $verilog_initial_trigger $verilog_initial_trigger + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init - update $verilog_initial_trigger 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $22 - parameter \WIDTH 1 - connect \A \ra [63] - connect \B \ra [31] - connect \S \logical_op__is_32bit - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $21 - connect \B \logical_op__is_signed - connect \Y $23 end process $group_1 - assign \dividend_neg 1'0 - assign \dividend_neg $23 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $26 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \logical_op__is_32bit - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $25 - connect \B \logical_op__is_signed - connect \Y $27 - end - process $group_2 - assign \divisor_neg 1'0 - assign \divisor_neg $27 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" - wire width 64 \abs_dor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - wire width 65 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - wire width 65 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 65 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - wire width 65 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $35 - parameter \WIDTH 65 - connect \A $32 - connect \B $30 - connect \S \divisor_neg - connect \Y $34 - end - connect $29 $34 - process $group_3 - assign \abs_dor 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \abs_dor $29 [63:0] + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" - wire width 64 \abs_dend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 65 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $42 - parameter \WIDTH 65 - connect \A $39 - connect \B $37 - connect \S \dividend_neg - connect \Y $41 - end - connect $36 $41 - process $group_4 - assign \abs_dend 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \abs_dend $36 [63:0] + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \abs_dend - connect \B \abs_dor - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0011110 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $43 - connect \B $45 - connect \Y $47 - end - process $group_5 - assign \dive_abs_ov64 1'0 - assign \dive_abs_ov64 $47 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \abs_dend [31:0] - connect \B \abs_dor [31:0] - connect \Y $49 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0011110 - connect \Y $51 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $49 - connect \B $51 - connect \Y $53 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - process $group_6 - assign \dive_abs_ov32 1'0 - assign \dive_abs_ov32 $53 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - wire width 32 $55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $56 - parameter \WIDTH 32 - connect \A \abs_dor [63:32] - connect \B 32'00000000000000000000000000000000 - connect \S \logical_op__is_32bit - connect \Y $55 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - process $group_7 - assign \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand [31:0] \abs_dor [31:0] - assign \divisor_radicand [63:32] $55 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $57 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - process $group_8 - assign \div_by_zero 1'0 - assign \div_by_zero $57 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - wire width 32 $59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $60 - parameter \WIDTH 32 - connect \A \abs_dend [63:32] - connect \B 32'00000000000000000000000000000000 - connect \S \logical_op__is_32bit - connect \Y $59 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - wire width 128 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - wire width 95 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 95 - connect \A \abs_dend [31:0] - connect \B 6'100000 - connect \Y $62 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 95 - parameter \Y_WIDTH 128 - connect \A $62 - connect \Y $61 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - wire width 191 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - wire width 191 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 191 - connect \A \abs_dend - connect \B 7'1000000 - connect \Y $66 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - connect $65 $66 - process $group_9 - assign \dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:74" - attribute \nmigen.decoding "OP_DIV/29|OP_MOD/47" - case 7'0011101, 7'0101111 - assign \dividend [31:0] \abs_dend [31:0] - assign \dividend [63:32] $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:77" - attribute \nmigen.decoding "OP_DIVE/30" - case 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" - switch { \logical_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" - case 1'1 - assign \dividend $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:80" - case - assign \dividend $65 [127:0] - end - end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init end - process $group_10 - assign \xer_so$20 1'0 - assign \xer_so$20 \xer_so + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end - process $group_11 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 sync init end - process $group_12 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_a$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start" -module \pipe_start - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_3" +module \pipe_middle_3 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next + wire width 2 input 4 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -89811,9 +76395,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$next + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -89827,127 +76409,79 @@ module \pipe_start attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 6 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \logical_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \logical_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \logical_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$next + wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 11 \logical_op__oe__oe + wire width 64 input 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$next + wire width 1 input 8 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \logical_op__oe__oe_ok + wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$next + wire width 1 input 10 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 13 \logical_op__invert_a + wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_a$next + wire width 1 input 12 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 14 \logical_op__zero_a + wire width 1 input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$next + wire width 1 input 14 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 15 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 19 \logical_op__is_32bit + wire width 2 input 15 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$next + wire width 1 input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 20 \logical_op__is_signed + wire width 1 input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$next + wire width 1 input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 21 \logical_op__data_len + wire width 1 input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$next + wire width 1 input 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \logical_op__insn + wire width 4 input 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 24 \rb + wire width 32 input 22 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next + wire width 64 input 23 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 25 \xer_so + wire width 64 input 24 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 26 \divisor_neg + wire width 1 input 25 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 27 \dividend_neg + wire width 1 input 26 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 28 \dive_abs_ov32 + wire width 1 input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 29 \dive_abs_ov64 + wire width 1 input 28 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 30 \div_by_zero + wire width 1 input 29 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 output 31 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 output 32 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 output 33 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 34 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 35 \p_ready_o + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 36 \muxid$1 + wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -90022,7 +76556,9 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 37 \logical_op__insn_type$2 + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -90036,59 +76572,143 @@ module \pipe_start attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 38 \logical_op__fn_unit$3 + wire width 11 output 41 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 39 \logical_op__imm_data__imm$4 + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 40 \logical_op__imm_data__imm_ok$5 + wire width 1 output 46 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 41 \logical_op__rc__rc$6 + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 42 \logical_op__rc__rc_ok$7 + wire width 1 \logical_op__oe__oe_ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 43 \logical_op__oe__oe$8 + wire width 1 output 48 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 44 \logical_op__oe__oe_ok$9 + wire width 1 \logical_op__invert_in$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 45 \logical_op__invert_a$10 + wire width 1 output 49 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 46 \logical_op__zero_a$11 + wire width 1 \logical_op__zero_a$11$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 47 \logical_op__input_carry$12 + wire width 2 output 50 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 48 \logical_op__invert_out$13 + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 49 \logical_op__write_cr0$14 + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 50 \logical_op__output_carry$15 + wire width 1 output 55 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 51 \logical_op__is_32bit$16 + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 52 \logical_op__is_signed$17 + wire width 4 \logical_op__data_len$18$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 53 \logical_op__data_len$18 + wire width 32 output 57 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 54 \logical_op__insn$19 + wire width 32 \logical_op__insn$19$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 55 \ra$20 + wire width 64 output 58 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 56 \rb$21 + wire width 64 \ra$20$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 57 \xer_so$22 - cell \p$72 \p + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$128 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$73 \n + cell \n$129 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid + wire width 2 \core_calculate_stage_12_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -90163,7 +76783,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type + wire width 7 \core_calculate_stage_12_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -90177,51 +76797,73 @@ module \pipe_start attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_logical_op__fn_unit + wire width 11 \core_calculate_stage_12_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__imm + wire width 64 \core_calculate_stage_12_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_12_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc + wire width 1 \core_calculate_stage_12_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_12_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe + wire width 1 \core_calculate_stage_12_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_12_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__invert_a + wire width 1 \core_calculate_stage_12_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__zero_a + wire width 1 \core_calculate_stage_12_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry + wire width 2 \core_calculate_stage_12_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__invert_out + wire width 1 \core_calculate_stage_12_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__write_cr0 + wire width 1 \core_calculate_stage_12_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__output_carry + wire width 1 \core_calculate_stage_12_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__is_32bit + wire width 1 \core_calculate_stage_12_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__is_signed + wire width 1 \core_calculate_stage_12_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len + wire width 4 \core_calculate_stage_12_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn + wire width 32 \core_calculate_stage_12_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra + wire width 64 \core_calculate_stage_12_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb + wire width 64 \core_calculate_stage_12_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \input_xer_so + wire width 1 \core_calculate_stage_12_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_12_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_12_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_12_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_12_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_12_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_12_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_12_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_12_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_12_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_12_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_12_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$23 + wire width 2 \core_calculate_stage_12_muxid$34 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -90296,7 +76938,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type$24 + wire width 7 \core_calculate_stage_12_logical_op__insn_type$35 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -90310,97 +76952,141 @@ module \pipe_start attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_logical_op__fn_unit$25 + wire width 11 \core_calculate_stage_12_logical_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__imm$26 + wire width 64 \core_calculate_stage_12_logical_op__imm_data__imm$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__imm_data__imm_ok$27 + wire width 1 \core_calculate_stage_12_logical_op__imm_data__imm_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc$28 + wire width 1 \core_calculate_stage_12_logical_op__rc__rc$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__rc__rc_ok$29 + wire width 1 \core_calculate_stage_12_logical_op__rc__rc_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe$30 + wire width 1 \core_calculate_stage_12_logical_op__oe__oe$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__oe__oe_ok$31 + wire width 1 \core_calculate_stage_12_logical_op__oe__oe_ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__invert_a$32 + wire width 1 \core_calculate_stage_12_logical_op__invert_in$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__zero_a$33 + wire width 1 \core_calculate_stage_12_logical_op__zero_a$44 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry$34 + wire width 2 \core_calculate_stage_12_logical_op__input_carry$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__invert_out$35 + wire width 1 \core_calculate_stage_12_logical_op__invert_out$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__write_cr0$36 + wire width 1 \core_calculate_stage_12_logical_op__write_cr0$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__output_carry$37 + wire width 1 \core_calculate_stage_12_logical_op__output_carry$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__is_32bit$38 + wire width 1 \core_calculate_stage_12_logical_op__is_32bit$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_logical_op__is_signed$39 + wire width 1 \core_calculate_stage_12_logical_op__is_signed$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len$40 + wire width 4 \core_calculate_stage_12_logical_op__data_len$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn$41 + wire width 32 \core_calculate_stage_12_logical_op__insn$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$42 + wire width 64 \core_calculate_stage_12_ra$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$43 + wire width 64 \core_calculate_stage_12_rb$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \input_xer_so$44 - cell \input$74 \input - connect \muxid \input_muxid - connect \logical_op__insn_type \input_logical_op__insn_type - connect \logical_op__fn_unit \input_logical_op__fn_unit - connect \logical_op__imm_data__imm \input_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \input_logical_op__rc__rc - connect \logical_op__rc__rc_ok \input_logical_op__rc__rc_ok - connect \logical_op__oe__oe \input_logical_op__oe__oe - connect \logical_op__oe__oe_ok \input_logical_op__oe__oe_ok - connect \logical_op__invert_a \input_logical_op__invert_a - connect \logical_op__zero_a \input_logical_op__zero_a - connect \logical_op__input_carry \input_logical_op__input_carry - connect \logical_op__invert_out \input_logical_op__invert_out - connect \logical_op__write_cr0 \input_logical_op__write_cr0 - connect \logical_op__output_carry \input_logical_op__output_carry - connect \logical_op__is_32bit \input_logical_op__is_32bit - connect \logical_op__is_signed \input_logical_op__is_signed - connect \logical_op__data_len \input_logical_op__data_len - connect \logical_op__insn \input_logical_op__insn - connect \ra \input_ra - connect \rb \input_rb - connect \xer_so \input_xer_so - connect \muxid$1 \input_muxid$23 - connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 - connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 - connect \logical_op__imm_data__imm$4 \input_logical_op__imm_data__imm$26 - connect \logical_op__imm_data__imm_ok$5 \input_logical_op__imm_data__imm_ok$27 - connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 - connect \logical_op__rc__rc_ok$7 \input_logical_op__rc__rc_ok$29 - connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 - connect \logical_op__oe__oe_ok$9 \input_logical_op__oe__oe_ok$31 - connect \logical_op__invert_a$10 \input_logical_op__invert_a$32 - connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 - connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 - connect \logical_op__invert_out$13 \input_logical_op__invert_out$35 - connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 - connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 - connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38 - connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 - connect \logical_op__data_len$18 \input_logical_op__data_len$40 - connect \logical_op__insn$19 \input_logical_op__insn$41 - connect \ra$20 \input_ra$42 - connect \rb$21 \input_rb$43 - connect \xer_so$22 \input_xer_so$44 + wire width 1 \core_calculate_stage_12_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_12_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_12_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_12_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_12_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_12_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_12_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_12_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_12_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_12_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_12_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_12_compare_rhs$66 + cell \core_calculate_stage_12 \core_calculate_stage_12 + connect \muxid \core_calculate_stage_12_muxid + connect \logical_op__insn_type \core_calculate_stage_12_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_12_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_12_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_12_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_12_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_12_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_12_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_12_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_12_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_12_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_12_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_12_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_12_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_12_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_12_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_12_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_12_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_12_logical_op__insn + connect \ra \core_calculate_stage_12_ra + connect \rb \core_calculate_stage_12_rb + connect \xer_so \core_calculate_stage_12_xer_so + connect \divisor_neg \core_calculate_stage_12_divisor_neg + connect \dividend_neg \core_calculate_stage_12_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_12_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_12_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_12_div_by_zero + connect \divisor_radicand \core_calculate_stage_12_divisor_radicand + connect \operation \core_calculate_stage_12_operation + connect \quotient_root \core_calculate_stage_12_quotient_root + connect \root_times_radicand \core_calculate_stage_12_root_times_radicand + connect \compare_lhs \core_calculate_stage_12_compare_lhs + connect \compare_rhs \core_calculate_stage_12_compare_rhs + connect \muxid$1 \core_calculate_stage_12_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_12_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_12_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_12_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_12_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_12_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_12_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_12_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_12_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_12_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_12_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_12_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_12_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_12_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_12_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_12_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_12_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_12_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_12_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_12_ra$53 + connect \rb$21 \core_calculate_stage_12_rb$54 + connect \xer_so$22 \core_calculate_stage_12_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_12_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_12_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_12_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_12_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_12_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_12_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_12_operation$62 + connect \quotient_root$30 \core_calculate_stage_12_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_12_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_12_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_12_compare_rhs$66 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \setup_stage_muxid + wire width 2 \core_calculate_stage_13_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -90475,7 +77161,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \setup_stage_logical_op__insn_type + wire width 7 \core_calculate_stage_13_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -90489,51 +77175,73 @@ module \pipe_start attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \setup_stage_logical_op__fn_unit + wire width 11 \core_calculate_stage_13_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__imm + wire width 64 \core_calculate_stage_13_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_13_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__rc__rc + wire width 1 \core_calculate_stage_13_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_13_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__oe__oe + wire width 1 \core_calculate_stage_13_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_13_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__invert_a + wire width 1 \core_calculate_stage_13_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__zero_a + wire width 1 \core_calculate_stage_13_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \setup_stage_logical_op__input_carry + wire width 2 \core_calculate_stage_13_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__invert_out + wire width 1 \core_calculate_stage_13_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__write_cr0 + wire width 1 \core_calculate_stage_13_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__output_carry + wire width 1 \core_calculate_stage_13_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__is_32bit + wire width 1 \core_calculate_stage_13_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__is_signed + wire width 1 \core_calculate_stage_13_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len + wire width 4 \core_calculate_stage_13_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \setup_stage_logical_op__insn + wire width 32 \core_calculate_stage_13_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \setup_stage_ra + wire width 64 \core_calculate_stage_13_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \setup_stage_rb + wire width 64 \core_calculate_stage_13_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \setup_stage_xer_so + wire width 1 \core_calculate_stage_13_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_13_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_13_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_13_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_13_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_13_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_13_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_13_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_13_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_13_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_13_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_13_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \setup_stage_muxid$45 + wire width 2 \core_calculate_stage_13_muxid$67 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -90608,7 +77316,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \setup_stage_logical_op__insn_type$46 + wire width 7 \core_calculate_stage_13_logical_op__insn_type$68 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -90622,238 +77330,141 @@ module \pipe_start attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \setup_stage_logical_op__fn_unit$47 + wire width 11 \core_calculate_stage_13_logical_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__imm$48 + wire width 64 \core_calculate_stage_13_logical_op__imm_data__imm$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__imm_data__imm_ok$49 + wire width 1 \core_calculate_stage_13_logical_op__imm_data__imm_ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__rc__rc$50 + wire width 1 \core_calculate_stage_13_logical_op__rc__rc$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__rc__rc_ok$51 + wire width 1 \core_calculate_stage_13_logical_op__rc__rc_ok$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__oe__oe$52 + wire width 1 \core_calculate_stage_13_logical_op__oe__oe$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__oe__oe_ok$53 + wire width 1 \core_calculate_stage_13_logical_op__oe__oe_ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__invert_a$54 + wire width 1 \core_calculate_stage_13_logical_op__invert_in$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__zero_a$55 + wire width 1 \core_calculate_stage_13_logical_op__zero_a$77 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \setup_stage_logical_op__input_carry$56 + wire width 2 \core_calculate_stage_13_logical_op__input_carry$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__invert_out$57 + wire width 1 \core_calculate_stage_13_logical_op__invert_out$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__write_cr0$58 + wire width 1 \core_calculate_stage_13_logical_op__write_cr0$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__output_carry$59 + wire width 1 \core_calculate_stage_13_logical_op__output_carry$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__is_32bit$60 + wire width 1 \core_calculate_stage_13_logical_op__is_32bit$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__is_signed$61 + wire width 1 \core_calculate_stage_13_logical_op__is_signed$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len$62 + wire width 4 \core_calculate_stage_13_logical_op__data_len$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \setup_stage_logical_op__insn$63 + wire width 32 \core_calculate_stage_13_logical_op__insn$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \setup_stage_xer_so$64 + wire width 64 \core_calculate_stage_13_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_13_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_13_xer_so$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \setup_stage_divisor_neg + wire width 1 \core_calculate_stage_13_divisor_neg$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \setup_stage_dividend_neg + wire width 1 \core_calculate_stage_13_dividend_neg$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \setup_stage_dive_abs_ov32 + wire width 1 \core_calculate_stage_13_dive_abs_ov32$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \setup_stage_dive_abs_ov64 + wire width 1 \core_calculate_stage_13_dive_abs_ov64$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \setup_stage_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \setup_stage_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \setup_stage_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \setup_stage_operation - cell \setup_stage \setup_stage - connect \muxid \setup_stage_muxid - connect \logical_op__insn_type \setup_stage_logical_op__insn_type - connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit - connect \logical_op__imm_data__imm \setup_stage_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \setup_stage_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc - connect \logical_op__rc__rc_ok \setup_stage_logical_op__rc__rc_ok - connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe - connect \logical_op__oe__oe_ok \setup_stage_logical_op__oe__oe_ok - connect \logical_op__invert_a \setup_stage_logical_op__invert_a - connect \logical_op__zero_a \setup_stage_logical_op__zero_a - connect \logical_op__input_carry \setup_stage_logical_op__input_carry - connect \logical_op__invert_out \setup_stage_logical_op__invert_out - connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 - connect \logical_op__output_carry \setup_stage_logical_op__output_carry - connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit - connect \logical_op__is_signed \setup_stage_logical_op__is_signed - connect \logical_op__data_len \setup_stage_logical_op__data_len - connect \logical_op__insn \setup_stage_logical_op__insn - connect \ra \setup_stage_ra - connect \rb \setup_stage_rb - connect \xer_so \setup_stage_xer_so - connect \muxid$1 \setup_stage_muxid$45 - connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 - connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 - connect \logical_op__imm_data__imm$4 \setup_stage_logical_op__imm_data__imm$48 - connect \logical_op__imm_data__imm_ok$5 \setup_stage_logical_op__imm_data__imm_ok$49 - connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 - connect \logical_op__rc__rc_ok$7 \setup_stage_logical_op__rc__rc_ok$51 - connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 - connect \logical_op__oe__oe_ok$9 \setup_stage_logical_op__oe__oe_ok$53 - connect \logical_op__invert_a$10 \setup_stage_logical_op__invert_a$54 - connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 - connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 - connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 - connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 - connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 - connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 - connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 - connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 - connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 - connect \xer_so$20 \setup_stage_xer_so$64 - connect \divisor_neg \setup_stage_divisor_neg - connect \dividend_neg \setup_stage_dividend_neg - connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 - connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 - connect \div_by_zero \setup_stage_div_by_zero - connect \dividend \setup_stage_dividend - connect \divisor_radicand \setup_stage_divisor_radicand - connect \operation \setup_stage_operation - end - process $group_0 - assign \input_muxid 2'00 - assign \input_muxid \muxid$1 - sync init - end - process $group_1 - assign \input_logical_op__insn_type 7'0000000 - assign \input_logical_op__fn_unit 11'00000000000 - assign \input_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_logical_op__imm_data__imm_ok 1'0 - assign \input_logical_op__rc__rc 1'0 - assign \input_logical_op__rc__rc_ok 1'0 - assign \input_logical_op__oe__oe 1'0 - assign \input_logical_op__oe__oe_ok 1'0 - assign \input_logical_op__invert_a 1'0 - assign \input_logical_op__zero_a 1'0 - assign \input_logical_op__input_carry 2'00 - assign \input_logical_op__invert_out 1'0 - assign \input_logical_op__write_cr0 1'0 - assign \input_logical_op__output_carry 1'0 - assign \input_logical_op__is_32bit 1'0 - assign \input_logical_op__is_signed 1'0 - assign \input_logical_op__data_len 4'0000 - assign \input_logical_op__insn 32'00000000000000000000000000000000 - assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_a { \input_logical_op__oe__oe_ok \input_logical_op__oe__oe } { \input_logical_op__rc__rc_ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } - sync init - end - process $group_19 - assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_ra \ra$20 - sync init - end - process $group_20 - assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_rb \rb$21 - sync init - end - process $group_21 - assign \input_xer_so 1'0 - assign \input_xer_so \xer_so$22 - sync init - end - process $group_22 - assign \setup_stage_muxid 2'00 - assign \setup_stage_muxid \input_muxid$23 - sync init - end - process $group_23 - assign \setup_stage_logical_op__insn_type 7'0000000 - assign \setup_stage_logical_op__fn_unit 11'00000000000 - assign \setup_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \setup_stage_logical_op__imm_data__imm_ok 1'0 - assign \setup_stage_logical_op__rc__rc 1'0 - assign \setup_stage_logical_op__rc__rc_ok 1'0 - assign \setup_stage_logical_op__oe__oe 1'0 - assign \setup_stage_logical_op__oe__oe_ok 1'0 - assign \setup_stage_logical_op__invert_a 1'0 - assign \setup_stage_logical_op__zero_a 1'0 - assign \setup_stage_logical_op__input_carry 2'00 - assign \setup_stage_logical_op__invert_out 1'0 - assign \setup_stage_logical_op__write_cr0 1'0 - assign \setup_stage_logical_op__output_carry 1'0 - assign \setup_stage_logical_op__is_32bit 1'0 - assign \setup_stage_logical_op__is_signed 1'0 - assign \setup_stage_logical_op__data_len 4'0000 - assign \setup_stage_logical_op__insn 32'00000000000000000000000000000000 - assign { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_a { \setup_stage_logical_op__oe__oe_ok \setup_stage_logical_op__oe__oe } { \setup_stage_logical_op__rc__rc_ok \setup_stage_logical_op__rc__rc } { \setup_stage_logical_op__imm_data__imm_ok \setup_stage_logical_op__imm_data__imm } \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_a$32 { \input_logical_op__oe__oe_ok$31 \input_logical_op__oe__oe$30 } { \input_logical_op__rc__rc_ok$29 \input_logical_op__rc__rc$28 } { \input_logical_op__imm_data__imm_ok$27 \input_logical_op__imm_data__imm$26 } \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } - sync init - end - process $group_41 - assign \setup_stage_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \setup_stage_ra \input_ra$42 - sync init - end - process $group_42 - assign \setup_stage_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \setup_stage_rb \input_rb$43 - sync init - end - process $group_43 - assign \setup_stage_xer_so 1'0 - assign \setup_stage_xer_so \input_xer_so$44 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$65 - process $group_44 - assign \p_valid_i$65 1'0 - assign \p_valid_i$65 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_45 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$65 - connect \B \p_ready_o - connect \Y $66 - end - process $group_46 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $66 - sync init + wire width 1 \core_calculate_stage_13_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_13_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_13_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_13_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_13_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_13_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_13_compare_rhs$99 + cell \core_calculate_stage_13 \core_calculate_stage_13 + connect \muxid \core_calculate_stage_13_muxid + connect \logical_op__insn_type \core_calculate_stage_13_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_13_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_13_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_13_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_13_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_13_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_13_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_13_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_13_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_13_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_13_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_13_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_13_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_13_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_13_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_13_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_13_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_13_logical_op__insn + connect \ra \core_calculate_stage_13_ra + connect \rb \core_calculate_stage_13_rb + connect \xer_so \core_calculate_stage_13_xer_so + connect \divisor_neg \core_calculate_stage_13_divisor_neg + connect \dividend_neg \core_calculate_stage_13_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_13_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_13_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_13_div_by_zero + connect \divisor_radicand \core_calculate_stage_13_divisor_radicand + connect \operation \core_calculate_stage_13_operation + connect \quotient_root \core_calculate_stage_13_quotient_root + connect \root_times_radicand \core_calculate_stage_13_root_times_radicand + connect \compare_lhs \core_calculate_stage_13_compare_lhs + connect \compare_rhs \core_calculate_stage_13_compare_rhs + connect \muxid$1 \core_calculate_stage_13_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_13_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_13_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_13_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_13_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_13_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_13_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_13_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_13_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_13_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_13_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_13_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_13_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_13_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_13_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_13_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_13_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_13_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_13_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_13_ra$86 + connect \rb$21 \core_calculate_stage_13_rb$87 + connect \xer_so$22 \core_calculate_stage_13_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_13_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_13_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_13_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_13_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_13_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_13_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_13_operation$95 + connect \quotient_root$30 \core_calculate_stage_13_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_13_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_13_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_13_compare_rhs$99 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$68 - process $group_47 - assign \muxid$68 2'00 - assign \muxid$68 \setup_stage_muxid$45 - sync init - end + wire width 2 \core_calculate_stage_14_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -90928,7 +77539,7 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$69 + wire width 7 \core_calculate_stage_14_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -90942,695 +77553,73 @@ module \pipe_start attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$70 + wire width 11 \core_calculate_stage_14_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$71 + wire width 64 \core_calculate_stage_14_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$72 + wire width 1 \core_calculate_stage_14_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$73 + wire width 1 \core_calculate_stage_14_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$74 + wire width 1 \core_calculate_stage_14_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$75 + wire width 1 \core_calculate_stage_14_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$76 + wire width 1 \core_calculate_stage_14_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_a$77 + wire width 1 \core_calculate_stage_14_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$78 + wire width 1 \core_calculate_stage_14_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$79 + wire width 2 \core_calculate_stage_14_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$80 + wire width 1 \core_calculate_stage_14_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$81 + wire width 1 \core_calculate_stage_14_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$82 + wire width 1 \core_calculate_stage_14_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$83 + wire width 1 \core_calculate_stage_14_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$84 + wire width 1 \core_calculate_stage_14_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$85 + wire width 4 \core_calculate_stage_14_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$86 - process $group_48 - assign \logical_op__insn_type$69 7'0000000 - assign \logical_op__fn_unit$70 11'00000000000 - assign \logical_op__imm_data__imm$71 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$72 1'0 - assign \logical_op__rc__rc$73 1'0 - assign \logical_op__rc__rc_ok$74 1'0 - assign \logical_op__oe__oe$75 1'0 - assign \logical_op__oe__oe_ok$76 1'0 - assign \logical_op__invert_a$77 1'0 - assign \logical_op__zero_a$78 1'0 - assign \logical_op__input_carry$79 2'00 - assign \logical_op__invert_out$80 1'0 - assign \logical_op__write_cr0$81 1'0 - assign \logical_op__output_carry$82 1'0 - assign \logical_op__is_32bit$83 1'0 - assign \logical_op__is_signed$84 1'0 - assign \logical_op__data_len$85 4'0000 - assign \logical_op__insn$86 32'00000000000000000000000000000000 - assign { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_a$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_a$54 { \setup_stage_logical_op__oe__oe_ok$53 \setup_stage_logical_op__oe__oe$52 } { \setup_stage_logical_op__rc__rc_ok$51 \setup_stage_logical_op__rc__rc$50 } { \setup_stage_logical_op__imm_data__imm_ok$49 \setup_stage_logical_op__imm_data__imm$48 } \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$88 - process $group_66 - assign \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$87 \ra$88 - sync init - end + wire width 32 \core_calculate_stage_14_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$89 + wire width 64 \core_calculate_stage_14_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$90 - process $group_67 - assign \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$89 \rb$90 - sync init - end + wire width 64 \core_calculate_stage_14_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$91 - process $group_68 - assign \xer_so$91 1'0 - assign \xer_so$91 \setup_stage_xer_so$64 - sync init - end + wire width 1 \core_calculate_stage_14_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$92 - process $group_69 - assign \divisor_neg$92 1'0 - assign \divisor_neg$92 \setup_stage_divisor_neg - sync init - end + wire width 1 \core_calculate_stage_14_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$93 - process $group_70 - assign \dividend_neg$93 1'0 - assign \dividend_neg$93 \setup_stage_dividend_neg - sync init - end + wire width 1 \core_calculate_stage_14_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$94 - process $group_71 - assign \dive_abs_ov32$94 1'0 - assign \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 - sync init - end + wire width 1 \core_calculate_stage_14_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$95 - process $group_72 - assign \dive_abs_ov64$95 1'0 - assign \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 - sync init - end + wire width 1 \core_calculate_stage_14_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$96 - process $group_73 - assign \div_by_zero$96 1'0 - assign \div_by_zero$96 \setup_stage_div_by_zero - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$97 - process $group_74 - assign \dividend$97 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \dividend$97 \setup_stage_dividend - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$98 - process $group_75 - assign \divisor_radicand$98 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$98 \setup_stage_divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$99 - process $group_76 - assign \operation$99 2'00 - assign \operation$99 \setup_stage_operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_77 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_78 - assign \muxid$next \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$next \muxid$68 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$next \muxid$68 - end - sync init - update \muxid 2'00 - sync posedge \coresync_clk - update \muxid \muxid$next - end - process $group_79 - assign \logical_op__insn_type$next \logical_op__insn_type - assign \logical_op__fn_unit$next \logical_op__fn_unit - assign \logical_op__imm_data__imm$next \logical_op__imm_data__imm - assign \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm_ok - assign \logical_op__rc__rc$next \logical_op__rc__rc - assign \logical_op__rc__rc_ok$next \logical_op__rc__rc_ok - assign \logical_op__oe__oe$next \logical_op__oe__oe - assign \logical_op__oe__oe_ok$next \logical_op__oe__oe_ok - assign \logical_op__invert_a$next \logical_op__invert_a - assign \logical_op__zero_a$next \logical_op__zero_a - assign \logical_op__input_carry$next \logical_op__input_carry - assign \logical_op__invert_out$next \logical_op__invert_out - assign \logical_op__write_cr0$next \logical_op__write_cr0 - assign \logical_op__output_carry$next \logical_op__output_carry - assign \logical_op__is_32bit$next \logical_op__is_32bit - assign \logical_op__is_signed$next \logical_op__is_signed - assign \logical_op__data_len$next \logical_op__data_len - assign \logical_op__insn$next \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_a$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_a$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_a$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_a$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$next 1'0 - assign \logical_op__rc__rc$next 1'0 - assign \logical_op__rc__rc_ok$next 1'0 - assign \logical_op__oe__oe$next 1'0 - assign \logical_op__oe__oe_ok$next 1'0 - end - sync init - update \logical_op__insn_type 7'0000000 - update \logical_op__fn_unit 11'00000000000 - update \logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok 1'0 - update \logical_op__rc__rc 1'0 - update \logical_op__rc__rc_ok 1'0 - update \logical_op__oe__oe 1'0 - update \logical_op__oe__oe_ok 1'0 - update \logical_op__invert_a 1'0 - update \logical_op__zero_a 1'0 - update \logical_op__input_carry 2'00 - update \logical_op__invert_out 1'0 - update \logical_op__write_cr0 1'0 - update \logical_op__output_carry 1'0 - update \logical_op__is_32bit 1'0 - update \logical_op__is_signed 1'0 - update \logical_op__data_len 4'0000 - update \logical_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type \logical_op__insn_type$next - update \logical_op__fn_unit \logical_op__fn_unit$next - update \logical_op__imm_data__imm \logical_op__imm_data__imm$next - update \logical_op__imm_data__imm_ok \logical_op__imm_data__imm_ok$next - update \logical_op__rc__rc \logical_op__rc__rc$next - update \logical_op__rc__rc_ok \logical_op__rc__rc_ok$next - update \logical_op__oe__oe \logical_op__oe__oe$next - update \logical_op__oe__oe_ok \logical_op__oe__oe_ok$next - update \logical_op__invert_a \logical_op__invert_a$next - update \logical_op__zero_a \logical_op__zero_a$next - update \logical_op__input_carry \logical_op__input_carry$next - update \logical_op__invert_out \logical_op__invert_out$next - update \logical_op__write_cr0 \logical_op__write_cr0$next - update \logical_op__output_carry \logical_op__output_carry$next - update \logical_op__is_32bit \logical_op__is_32bit$next - update \logical_op__is_signed \logical_op__is_signed$next - update \logical_op__data_len \logical_op__data_len$next - update \logical_op__insn \logical_op__insn$next - end - process $group_97 - assign \ra$next \ra - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$next \ra$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$next \ra$87 - end - sync init - update \ra 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra \ra$next - end - process $group_98 - assign \rb$next \rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$next \rb$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$next \rb$89 - end - sync init - update \rb 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb \rb$next - end - process $group_99 - assign \xer_so$next \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$next \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$next \xer_so$91 - end - sync init - update \xer_so 1'0 - sync posedge \coresync_clk - update \xer_so \xer_so$next - end - process $group_100 - assign \divisor_neg$next \divisor_neg - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$next \divisor_neg$92 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$next \divisor_neg$92 - end - sync init - update \divisor_neg 1'0 - sync posedge \coresync_clk - update \divisor_neg \divisor_neg$next - end - process $group_101 - assign \dividend_neg$next \dividend_neg - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$next \dividend_neg$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$next \dividend_neg$93 - end - sync init - update \dividend_neg 1'0 - sync posedge \coresync_clk - update \dividend_neg \dividend_neg$next - end - process $group_102 - assign \dive_abs_ov32$next \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$next \dive_abs_ov32$94 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$next \dive_abs_ov32$94 - end - sync init - update \dive_abs_ov32 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32 \dive_abs_ov32$next - end - process $group_103 - assign \dive_abs_ov64$next \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$next \dive_abs_ov64$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$next \dive_abs_ov64$95 - end - sync init - update \dive_abs_ov64 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64 \dive_abs_ov64$next - end - process $group_104 - assign \div_by_zero$next \div_by_zero - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$next \div_by_zero$96 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$next \div_by_zero$96 - end - sync init - update \div_by_zero 1'0 - sync posedge \coresync_clk - update \div_by_zero \div_by_zero$next - end - process $group_105 - assign \dividend$next \dividend - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend$next \dividend$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend$next \dividend$97 - end - sync init - update \dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \dividend \dividend$next - end - process $group_106 - assign \divisor_radicand$next \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$next \divisor_radicand$98 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$next \divisor_radicand$98 - end - sync init - update \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand \divisor_radicand$next - end - process $group_107 - assign \operation$next \operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$next \operation$99 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$next \operation$99 - end - sync init - update \operation 2'00 - sync posedge \coresync_clk - update \operation \operation$next - end - process $group_108 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_109 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.p" -module \p$75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.n" -module \n$76 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" -module \div_state_next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 output 0 \o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 output 1 \o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 input 2 \i_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 input 3 \i_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" - wire width 64 input 4 \divisor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:82" - wire width 128 \difference - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" - wire width 129 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" - wire width 127 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" - cell $sshl $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 127 - connect \A \divisor - connect \B 6'111111 - connect \Y $2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" - wire width 129 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" - cell $sub $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \B_SIGNED 0 - parameter \B_WIDTH 127 - parameter \Y_WIDTH 129 - connect \A \i_dividend_quotient - connect \B $2 - connect \Y $4 - end - connect $1 $4 - process $group_0 - assign \difference 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \difference $1 [127:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:86" - wire width 1 \next_quotient_bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:88" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:88" - cell $not $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \difference [127] - connect \Y $6 - end - process $group_1 - assign \next_quotient_bit 1'0 - assign \next_quotient_bit $6 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" - wire width 128 \value - process $group_2 - assign \value 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:90" - switch { \next_quotient_bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:90" - case 1'1 - assign \value \difference - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:92" - case - assign \value \i_dividend_quotient - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - cell $eq $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \i_q_bits_known - connect \B 7'1000000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99" - wire width 8 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99" - wire width 8 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99" - cell $add $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \i_q_bits_known - connect \B 1'1 - connect \Y $11 - end - connect $10 $11 - process $group_3 - assign \o_q_bits_known 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" - case 1'1 - assign \o_q_bits_known \i_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:97" - case - assign \o_q_bits_known $10 [6:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - cell $eq $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \i_q_bits_known - connect \B 7'1000000 - connect \Y $13 - end - process $group_4 - assign \o_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" - case 1'1 - assign \o_dividend_quotient \i_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:97" - case - assign \o_dividend_quotient { \value \next_quotient_bit } [127:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" -module \div_state_init - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:107" - wire width 128 input 0 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 output 1 \o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 output 2 \o_dividend_quotient - wire width 1 $verilog_initial_trigger - process $group_0 - assign \o_q_bits_known 7'0000000 - assign \o_q_bits_known 7'0000000 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_1 - assign \o_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \o_dividend_quotient \dividend - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0" -module \pipe_middle_0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o + wire width 1 \core_calculate_stage_14_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_14_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_14_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_14_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_14_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_14_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_14_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid + wire width 2 \core_calculate_stage_14_muxid$100 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -91705,7 +77694,7 @@ module \pipe_middle_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type + wire width 7 \core_calculate_stage_14_logical_op__insn_type$101 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -91719,71 +77708,141 @@ module \pipe_middle_0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \logical_op__fn_unit + wire width 11 \core_calculate_stage_14_logical_op__fn_unit$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm + wire width 64 \core_calculate_stage_14_logical_op__imm_data__imm$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_14_logical_op__imm_data__imm_ok$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc + wire width 1 \core_calculate_stage_14_logical_op__rc__rc$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_14_logical_op__rc__rc_ok$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe + wire width 1 \core_calculate_stage_14_logical_op__oe__oe$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_14_logical_op__oe__oe_ok$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_a + wire width 1 \core_calculate_stage_14_logical_op__invert_in$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a + wire width 1 \core_calculate_stage_14_logical_op__zero_a$110 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry + wire width 2 \core_calculate_stage_14_logical_op__input_carry$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out + wire width 1 \core_calculate_stage_14_logical_op__invert_out$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 + wire width 1 \core_calculate_stage_14_logical_op__write_cr0$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry + wire width 1 \core_calculate_stage_14_logical_op__output_carry$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit + wire width 1 \core_calculate_stage_14_logical_op__is_32bit$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed + wire width 1 \core_calculate_stage_14_logical_op__is_signed$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len + wire width 4 \core_calculate_stage_14_logical_op__data_len$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn + wire width 32 \core_calculate_stage_14_logical_op__insn$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra + wire width 64 \core_calculate_stage_14_ra$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb + wire width 64 \core_calculate_stage_14_rb$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 25 \xer_so + wire width 1 \core_calculate_stage_14_xer_so$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 26 \divisor_neg + wire width 1 \core_calculate_stage_14_divisor_neg$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 27 \dividend_neg + wire width 1 \core_calculate_stage_14_dividend_neg$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 28 \dive_abs_ov32 + wire width 1 \core_calculate_stage_14_dive_abs_ov32$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 29 \dive_abs_ov64 + wire width 1 \core_calculate_stage_14_dive_abs_ov64$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 input 31 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 input 32 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 input 33 \operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 34 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 35 \n_ready_i + wire width 1 \core_calculate_stage_14_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_14_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_14_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_14_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_14_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_14_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_14_compare_rhs$132 + cell \core_calculate_stage_14 \core_calculate_stage_14 + connect \muxid \core_calculate_stage_14_muxid + connect \logical_op__insn_type \core_calculate_stage_14_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_14_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_14_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_14_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_14_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_14_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_14_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_14_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_14_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_14_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_14_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_14_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_14_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_14_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_14_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_14_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_14_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_14_logical_op__insn + connect \ra \core_calculate_stage_14_ra + connect \rb \core_calculate_stage_14_rb + connect \xer_so \core_calculate_stage_14_xer_so + connect \divisor_neg \core_calculate_stage_14_divisor_neg + connect \dividend_neg \core_calculate_stage_14_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_14_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_14_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_14_div_by_zero + connect \divisor_radicand \core_calculate_stage_14_divisor_radicand + connect \operation \core_calculate_stage_14_operation + connect \quotient_root \core_calculate_stage_14_quotient_root + connect \root_times_radicand \core_calculate_stage_14_root_times_radicand + connect \compare_lhs \core_calculate_stage_14_compare_lhs + connect \compare_rhs \core_calculate_stage_14_compare_rhs + connect \muxid$1 \core_calculate_stage_14_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_14_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_14_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_14_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_14_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_14_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_14_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_14_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_14_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_14_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_14_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_14_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_14_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_14_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_14_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_14_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_14_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_14_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_14_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_14_ra$119 + connect \rb$21 \core_calculate_stage_14_rb$120 + connect \xer_so$22 \core_calculate_stage_14_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_14_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_14_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_14_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_14_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_14_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_14_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_14_operation$128 + connect \quotient_root$30 \core_calculate_stage_14_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_14_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_14_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_14_compare_rhs$132 + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 36 \muxid$1 + wire width 2 \core_calculate_stage_15_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -91858,7 +77917,7 @@ module \pipe_middle_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 37 \logical_op__insn_type$2 + wire width 7 \core_calculate_stage_15_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -91872,113 +77931,73 @@ module \pipe_middle_0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 38 \logical_op__fn_unit$3 + wire width 11 \core_calculate_stage_15_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 39 \logical_op__imm_data__imm$4 + wire width 64 \core_calculate_stage_15_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__imm_data__imm_ok$5 + wire width 1 \core_calculate_stage_15_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__rc__rc$6 + wire width 1 \core_calculate_stage_15_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__rc__rc_ok$7 + wire width 1 \core_calculate_stage_15_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__oe__oe$8 + wire width 1 \core_calculate_stage_15_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__oe__oe_ok$9 + wire width 1 \core_calculate_stage_15_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__invert_a$10 + wire width 1 \core_calculate_stage_15_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 46 \logical_op__zero_a$11 + wire width 1 \core_calculate_stage_15_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 47 \logical_op__input_carry$12 + wire width 2 \core_calculate_stage_15_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__invert_out$13 + wire width 1 \core_calculate_stage_15_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__write_cr0$14 + wire width 1 \core_calculate_stage_15_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 50 \logical_op__output_carry$15 + wire width 1 \core_calculate_stage_15_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__is_32bit$16 + wire width 1 \core_calculate_stage_15_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 52 \logical_op__is_signed$17 + wire width 1 \core_calculate_stage_15_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 53 \logical_op__data_len$18 + wire width 4 \core_calculate_stage_15_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 54 \logical_op__insn$19 + wire width 32 \core_calculate_stage_15_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 55 \ra$20 + wire width 64 \core_calculate_stage_15_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 56 \rb$21 + wire width 64 \core_calculate_stage_15_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 57 \xer_so$22 + wire width 1 \core_calculate_stage_15_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 58 \divisor_neg$23 + wire width 1 \core_calculate_stage_15_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 59 \dividend_neg$24 + wire width 1 \core_calculate_stage_15_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 60 \dive_abs_ov32$25 + wire width 1 \core_calculate_stage_15_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 61 \dive_abs_ov64$26 + wire width 1 \core_calculate_stage_15_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 62 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 output 63 \quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 output 64 \remainder - cell \p$75 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$76 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 \div_state_next_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 \div_state_next_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 \div_state_next_i_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 \div_state_next_i_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" - wire width 64 \div_state_next_divisor - cell \div_state_next \div_state_next - connect \o_dividend_quotient \div_state_next_o_dividend_quotient - connect \o_q_bits_known \div_state_next_o_q_bits_known - connect \i_q_bits_known \div_state_next_i_q_bits_known - connect \i_dividend_quotient \div_state_next_i_dividend_quotient - connect \divisor \div_state_next_divisor - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:107" - wire width 128 \div_state_init_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 \div_state_init_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 \div_state_init_o_dividend_quotient - cell \div_state_init \div_state_init - connect \dividend \div_state_init_dividend - connect \o_q_bits_known \div_state_init_o_q_bits_known - connect \o_dividend_quotient \div_state_init_o_dividend_quotient - end - process $group_0 - assign \div_state_init_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \div_state_init_dividend \dividend - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$28 + wire width 1 \core_calculate_stage_15_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_15_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_15_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_15_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_15_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_15_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_15_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$28$next - process $group_1 - assign \muxid$1 2'00 - assign \muxid$1 \muxid$28 - sync init - end + wire width 2 \core_calculate_stage_15_muxid$133 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -92053,9 +78072,7 @@ module \pipe_middle_0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29$next + wire width 7 \core_calculate_stage_15_logical_op__insn_type$134 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -92069,695 +78086,1169 @@ module \pipe_middle_0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$30$next + wire width 11 \core_calculate_stage_15_logical_op__fn_unit$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$31 + wire width 64 \core_calculate_stage_15_logical_op__imm_data__imm$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$31$next + wire width 1 \core_calculate_stage_15_logical_op__imm_data__imm_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$32 + wire width 1 \core_calculate_stage_15_logical_op__rc__rc$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$32$next + wire width 1 \core_calculate_stage_15_logical_op__rc__rc_ok$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$33 + wire width 1 \core_calculate_stage_15_logical_op__oe__oe$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$33$next + wire width 1 \core_calculate_stage_15_logical_op__oe__oe_ok$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$34 + wire width 1 \core_calculate_stage_15_logical_op__invert_in$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$34$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$35$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$36$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_a$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_a$37$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$38$next + wire width 1 \core_calculate_stage_15_logical_op__zero_a$143 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$40$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$41$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$42$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$43 + wire width 2 \core_calculate_stage_15_logical_op__input_carry$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$43$next + wire width 1 \core_calculate_stage_15_logical_op__invert_out$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$44 + wire width 1 \core_calculate_stage_15_logical_op__write_cr0$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$44$next + wire width 1 \core_calculate_stage_15_logical_op__output_carry$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45 + wire width 1 \core_calculate_stage_15_logical_op__is_32bit$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45$next + wire width 1 \core_calculate_stage_15_logical_op__is_signed$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46 + wire width 4 \core_calculate_stage_15_logical_op__data_len$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46$next - process $group_2 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_a$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_a$37 { \logical_op__oe__oe_ok$36 \logical_op__oe__oe$35 } { \logical_op__rc__rc_ok$34 \logical_op__rc__rc$33 } { \logical_op__imm_data__imm_ok$32 \logical_op__imm_data__imm$31 } \logical_op__fn_unit$30 \logical_op__insn_type$29 } - sync init - end + wire width 32 \core_calculate_stage_15_logical_op__insn$151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$47 + wire width 64 \core_calculate_stage_15_ra$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$47$next + wire width 64 \core_calculate_stage_15_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_15_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_15_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_15_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_15_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_15_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_15_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_15_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_15_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_15_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_15_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_15_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_15_compare_rhs$165 + cell \core_calculate_stage_15 \core_calculate_stage_15 + connect \muxid \core_calculate_stage_15_muxid + connect \logical_op__insn_type \core_calculate_stage_15_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_15_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_15_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_15_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_15_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_15_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_15_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_15_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_15_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_15_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_15_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_15_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_15_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_15_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_15_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_15_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_15_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_15_logical_op__insn + connect \ra \core_calculate_stage_15_ra + connect \rb \core_calculate_stage_15_rb + connect \xer_so \core_calculate_stage_15_xer_so + connect \divisor_neg \core_calculate_stage_15_divisor_neg + connect \dividend_neg \core_calculate_stage_15_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_15_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_15_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_15_div_by_zero + connect \divisor_radicand \core_calculate_stage_15_divisor_radicand + connect \operation \core_calculate_stage_15_operation + connect \quotient_root \core_calculate_stage_15_quotient_root + connect \root_times_radicand \core_calculate_stage_15_root_times_radicand + connect \compare_lhs \core_calculate_stage_15_compare_lhs + connect \compare_rhs \core_calculate_stage_15_compare_rhs + connect \muxid$1 \core_calculate_stage_15_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_15_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_15_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_15_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_15_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_15_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_15_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_15_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_15_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_15_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_15_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_15_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_15_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_15_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_15_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_15_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_15_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_15_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_15_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_15_ra$152 + connect \rb$21 \core_calculate_stage_15_rb$153 + connect \xer_so$22 \core_calculate_stage_15_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_15_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_15_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_15_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_15_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_15_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_15_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_15_operation$161 + connect \quotient_root$30 \core_calculate_stage_15_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_15_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_15_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_15_compare_rhs$165 + end + process $group_0 + assign \core_calculate_stage_12_muxid 2'00 + assign \core_calculate_stage_12_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_12_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_12_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_12_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_12_logical_op__rc__rc 1'0 + assign \core_calculate_stage_12_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_12_logical_op__oe__oe 1'0 + assign \core_calculate_stage_12_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_12_logical_op__invert_in 1'0 + assign \core_calculate_stage_12_logical_op__zero_a 1'0 + assign \core_calculate_stage_12_logical_op__input_carry 2'00 + assign \core_calculate_stage_12_logical_op__invert_out 1'0 + assign \core_calculate_stage_12_logical_op__write_cr0 1'0 + assign \core_calculate_stage_12_logical_op__output_carry 1'0 + assign \core_calculate_stage_12_logical_op__is_32bit 1'0 + assign \core_calculate_stage_12_logical_op__is_signed 1'0 + assign \core_calculate_stage_12_logical_op__data_len 4'0000 + assign \core_calculate_stage_12_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_12_logical_op__insn \core_calculate_stage_12_logical_op__data_len \core_calculate_stage_12_logical_op__is_signed \core_calculate_stage_12_logical_op__is_32bit \core_calculate_stage_12_logical_op__output_carry \core_calculate_stage_12_logical_op__write_cr0 \core_calculate_stage_12_logical_op__invert_out \core_calculate_stage_12_logical_op__input_carry \core_calculate_stage_12_logical_op__zero_a \core_calculate_stage_12_logical_op__invert_in { \core_calculate_stage_12_logical_op__oe__oe_ok \core_calculate_stage_12_logical_op__oe__oe } { \core_calculate_stage_12_logical_op__rc__rc_ok \core_calculate_stage_12_logical_op__rc__rc } { \core_calculate_stage_12_logical_op__imm_data__imm_ok \core_calculate_stage_12_logical_op__imm_data__imm } \core_calculate_stage_12_logical_op__fn_unit \core_calculate_stage_12_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \core_calculate_stage_12_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_ra \ra + sync init + end process $group_20 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra$47 + assign \core_calculate_stage_12_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_rb \rb sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$48$next process $group_21 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb$48 + assign \core_calculate_stage_12_xer_so 1'0 + assign \core_calculate_stage_12_xer_so \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$49$next process $group_22 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so$49 + assign \core_calculate_stage_12_divisor_neg 1'0 + assign \core_calculate_stage_12_divisor_neg \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$50$next process $group_23 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg$50 + assign \core_calculate_stage_12_dividend_neg 1'0 + assign \core_calculate_stage_12_dividend_neg \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$51$next process $group_24 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg$51 + assign \core_calculate_stage_12_dive_abs_ov32 1'0 + assign \core_calculate_stage_12_dive_abs_ov32 \dive_abs_ov32 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$52$next process $group_25 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32$52 + assign \core_calculate_stage_12_dive_abs_ov64 1'0 + assign \core_calculate_stage_12_dive_abs_ov64 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$53$next process $group_26 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64$53 + assign \core_calculate_stage_12_div_by_zero 1'0 + assign \core_calculate_stage_12_div_by_zero \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$54$next process $group_27 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero$54 + assign \core_calculate_stage_12_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_divisor_radicand \divisor_radicand sync init end process $group_28 - assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root \div_state_next_o_dividend_quotient [63:0] + assign \core_calculate_stage_12_operation 2'00 + assign \core_calculate_stage_12_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 192 $55 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 192 - connect \A \div_state_next_o_dividend_quotient [127:64] - connect \Y $55 - end process $group_29 - assign \remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \remainder $55 + assign \core_calculate_stage_12_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:152" - wire width 1 \empty - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:152" - wire width 1 \empty$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - cell $not $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \empty - connect \Y $57 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - cell $eq $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \div_state_next_o_q_bits_known - connect \B 7'1000000 - connect \Y $59 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - cell $and $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $57 - connect \B $59 - connect \Y $61 - end process $group_30 - assign \n_valid_o 1'0 - assign \n_valid_o $61 + assign \core_calculate_stage_12_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_root_times_radicand \root_times_radicand sync init end process $group_31 - assign \p_ready_o 1'0 - assign \p_ready_o \empty + assign \core_calculate_stage_12_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_compare_lhs \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 \saved_state_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 \saved_state_q_bits_known$next process $group_32 - assign \saved_state_q_bits_known$next \saved_state_q_bits_known - assign \saved_state_q_bits_known$next \div_state_next_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \saved_state_q_bits_known$next 7'0000000 - end + assign \core_calculate_stage_12_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_compare_rhs \compare_rhs sync init - update \saved_state_q_bits_known 7'0000000 - sync posedge \coresync_clk - update \saved_state_q_bits_known \saved_state_q_bits_known$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 \saved_state_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 \saved_state_dividend_quotient$next process $group_33 - assign \saved_state_dividend_quotient$next \saved_state_dividend_quotient - assign \saved_state_dividend_quotient$next \div_state_next_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \saved_state_dividend_quotient$next 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - end + assign \core_calculate_stage_13_muxid 2'00 + assign \core_calculate_stage_13_muxid \core_calculate_stage_12_muxid$34 sync init - update \saved_state_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \saved_state_dividend_quotient \saved_state_dividend_quotient$next end process $group_34 - assign \div_state_next_i_q_bits_known 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - assign \div_state_next_i_q_bits_known \div_state_init_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - assign \div_state_next_i_q_bits_known \saved_state_q_bits_known - end + assign \core_calculate_stage_13_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_13_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_13_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_13_logical_op__rc__rc 1'0 + assign \core_calculate_stage_13_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_13_logical_op__oe__oe 1'0 + assign \core_calculate_stage_13_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_13_logical_op__invert_in 1'0 + assign \core_calculate_stage_13_logical_op__zero_a 1'0 + assign \core_calculate_stage_13_logical_op__input_carry 2'00 + assign \core_calculate_stage_13_logical_op__invert_out 1'0 + assign \core_calculate_stage_13_logical_op__write_cr0 1'0 + assign \core_calculate_stage_13_logical_op__output_carry 1'0 + assign \core_calculate_stage_13_logical_op__is_32bit 1'0 + assign \core_calculate_stage_13_logical_op__is_signed 1'0 + assign \core_calculate_stage_13_logical_op__data_len 4'0000 + assign \core_calculate_stage_13_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_13_logical_op__insn \core_calculate_stage_13_logical_op__data_len \core_calculate_stage_13_logical_op__is_signed \core_calculate_stage_13_logical_op__is_32bit \core_calculate_stage_13_logical_op__output_carry \core_calculate_stage_13_logical_op__write_cr0 \core_calculate_stage_13_logical_op__invert_out \core_calculate_stage_13_logical_op__input_carry \core_calculate_stage_13_logical_op__zero_a \core_calculate_stage_13_logical_op__invert_in { \core_calculate_stage_13_logical_op__oe__oe_ok \core_calculate_stage_13_logical_op__oe__oe } { \core_calculate_stage_13_logical_op__rc__rc_ok \core_calculate_stage_13_logical_op__rc__rc } { \core_calculate_stage_13_logical_op__imm_data__imm_ok \core_calculate_stage_13_logical_op__imm_data__imm } \core_calculate_stage_13_logical_op__fn_unit \core_calculate_stage_13_logical_op__insn_type } { \core_calculate_stage_12_logical_op__insn$52 \core_calculate_stage_12_logical_op__data_len$51 \core_calculate_stage_12_logical_op__is_signed$50 \core_calculate_stage_12_logical_op__is_32bit$49 \core_calculate_stage_12_logical_op__output_carry$48 \core_calculate_stage_12_logical_op__write_cr0$47 \core_calculate_stage_12_logical_op__invert_out$46 \core_calculate_stage_12_logical_op__input_carry$45 \core_calculate_stage_12_logical_op__zero_a$44 \core_calculate_stage_12_logical_op__invert_in$43 { \core_calculate_stage_12_logical_op__oe__oe_ok$42 \core_calculate_stage_12_logical_op__oe__oe$41 } { \core_calculate_stage_12_logical_op__rc__rc_ok$40 \core_calculate_stage_12_logical_op__rc__rc$39 } { \core_calculate_stage_12_logical_op__imm_data__imm_ok$38 \core_calculate_stage_12_logical_op__imm_data__imm$37 } \core_calculate_stage_12_logical_op__fn_unit$36 \core_calculate_stage_12_logical_op__insn_type$35 } sync init end - process $group_35 - assign \div_state_next_i_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - assign \div_state_next_i_dividend_quotient \div_state_init_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - assign \div_state_next_i_dividend_quotient \saved_state_dividend_quotient - end + process $group_52 + assign \core_calculate_stage_13_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_ra \core_calculate_stage_12_ra$53 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$63$next - process $group_36 - assign \div_state_next_divisor 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - assign \div_state_next_divisor \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - assign \div_state_next_divisor \divisor_radicand$63 - end + process $group_53 + assign \core_calculate_stage_13_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_rb \core_calculate_stage_12_rb$54 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" - cell $and $65 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $64 - end - process $group_37 - assign \empty$next \empty - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \empty$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" - switch { $64 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189" - case 1'1 - assign \empty$next 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \empty$next 1'1 - end + process $group_54 + assign \core_calculate_stage_13_xer_so 1'0 + assign \core_calculate_stage_13_xer_so \core_calculate_stage_12_xer_so$55 sync init - update \empty 1'1 - sync posedge \coresync_clk - update \empty \empty$next end - process $group_38 - assign \muxid$28$next \muxid$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \muxid$28$next \muxid - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + process $group_55 + assign \core_calculate_stage_13_divisor_neg 1'0 + assign \core_calculate_stage_13_divisor_neg \core_calculate_stage_12_divisor_neg$56 sync init - update \muxid$28 2'00 - sync posedge \coresync_clk - update \muxid$28 \muxid$28$next end - process $group_39 - assign \logical_op__insn_type$29$next \logical_op__insn_type$29 - assign \logical_op__fn_unit$30$next \logical_op__fn_unit$30 - assign \logical_op__imm_data__imm$31$next \logical_op__imm_data__imm$31 - assign \logical_op__imm_data__imm_ok$32$next \logical_op__imm_data__imm_ok$32 - assign \logical_op__rc__rc$33$next \logical_op__rc__rc$33 - assign \logical_op__rc__rc_ok$34$next \logical_op__rc__rc_ok$34 - assign \logical_op__oe__oe$35$next \logical_op__oe__oe$35 - assign \logical_op__oe__oe_ok$36$next \logical_op__oe__oe_ok$36 - assign \logical_op__invert_a$37$next \logical_op__invert_a$37 - assign \logical_op__zero_a$38$next \logical_op__zero_a$38 - assign \logical_op__input_carry$39$next \logical_op__input_carry$39 - assign \logical_op__invert_out$40$next \logical_op__invert_out$40 - assign \logical_op__write_cr0$41$next \logical_op__write_cr0$41 - assign \logical_op__output_carry$42$next \logical_op__output_carry$42 - assign \logical_op__is_32bit$43$next \logical_op__is_32bit$43 - assign \logical_op__is_signed$44$next \logical_op__is_signed$44 - assign \logical_op__data_len$45$next \logical_op__data_len$45 - assign \logical_op__insn$46$next \logical_op__insn$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign { \logical_op__insn$46$next \logical_op__data_len$45$next \logical_op__is_signed$44$next \logical_op__is_32bit$43$next \logical_op__output_carry$42$next \logical_op__write_cr0$41$next \logical_op__invert_out$40$next \logical_op__input_carry$39$next \logical_op__zero_a$38$next \logical_op__invert_a$37$next { \logical_op__oe__oe_ok$36$next \logical_op__oe__oe$35$next } { \logical_op__rc__rc_ok$34$next \logical_op__rc__rc$33$next } { \logical_op__imm_data__imm_ok$32$next \logical_op__imm_data__imm$31$next } \logical_op__fn_unit$30$next \logical_op__insn_type$29$next } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$31$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$32$next 1'0 - assign \logical_op__rc__rc$33$next 1'0 - assign \logical_op__rc__rc_ok$34$next 1'0 - assign \logical_op__oe__oe$35$next 1'0 - assign \logical_op__oe__oe_ok$36$next 1'0 - end - sync init - update \logical_op__insn_type$29 7'0000000 - update \logical_op__fn_unit$30 11'00000000000 - update \logical_op__imm_data__imm$31 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$32 1'0 - update \logical_op__rc__rc$33 1'0 - update \logical_op__rc__rc_ok$34 1'0 - update \logical_op__oe__oe$35 1'0 - update \logical_op__oe__oe_ok$36 1'0 - update \logical_op__invert_a$37 1'0 - update \logical_op__zero_a$38 1'0 - update \logical_op__input_carry$39 2'00 - update \logical_op__invert_out$40 1'0 - update \logical_op__write_cr0$41 1'0 - update \logical_op__output_carry$42 1'0 - update \logical_op__is_32bit$43 1'0 - update \logical_op__is_signed$44 1'0 - update \logical_op__data_len$45 4'0000 - update \logical_op__insn$46 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$29 \logical_op__insn_type$29$next - update \logical_op__fn_unit$30 \logical_op__fn_unit$30$next - update \logical_op__imm_data__imm$31 \logical_op__imm_data__imm$31$next - update \logical_op__imm_data__imm_ok$32 \logical_op__imm_data__imm_ok$32$next - update \logical_op__rc__rc$33 \logical_op__rc__rc$33$next - update \logical_op__rc__rc_ok$34 \logical_op__rc__rc_ok$34$next - update \logical_op__oe__oe$35 \logical_op__oe__oe$35$next - update \logical_op__oe__oe_ok$36 \logical_op__oe__oe_ok$36$next - update \logical_op__invert_a$37 \logical_op__invert_a$37$next - update \logical_op__zero_a$38 \logical_op__zero_a$38$next - update \logical_op__input_carry$39 \logical_op__input_carry$39$next - update \logical_op__invert_out$40 \logical_op__invert_out$40$next - update \logical_op__write_cr0$41 \logical_op__write_cr0$41$next - update \logical_op__output_carry$42 \logical_op__output_carry$42$next - update \logical_op__is_32bit$43 \logical_op__is_32bit$43$next - update \logical_op__is_signed$44 \logical_op__is_signed$44$next - update \logical_op__data_len$45 \logical_op__data_len$45$next - update \logical_op__insn$46 \logical_op__insn$46$next + process $group_56 + assign \core_calculate_stage_13_dividend_neg 1'0 + assign \core_calculate_stage_13_dividend_neg \core_calculate_stage_12_dividend_neg$57 + sync init end process $group_57 - assign \ra$47$next \ra$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \ra$47$next \ra - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + assign \core_calculate_stage_13_dive_abs_ov32 1'0 + assign \core_calculate_stage_13_dive_abs_ov32 \core_calculate_stage_12_dive_abs_ov32$58 sync init - update \ra$47 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$47 \ra$47$next end process $group_58 - assign \rb$48$next \rb$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \rb$48$next \rb - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + assign \core_calculate_stage_13_dive_abs_ov64 1'0 + assign \core_calculate_stage_13_dive_abs_ov64 \core_calculate_stage_12_dive_abs_ov64$59 sync init - update \rb$48 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$48 \rb$48$next end process $group_59 - assign \xer_so$49$next \xer_so$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \xer_so$49$next \xer_so - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + assign \core_calculate_stage_13_div_by_zero 1'0 + assign \core_calculate_stage_13_div_by_zero \core_calculate_stage_12_div_by_zero$60 sync init - update \xer_so$49 1'0 - sync posedge \coresync_clk - update \xer_so$49 \xer_so$49$next end process $group_60 - assign \divisor_neg$50$next \divisor_neg$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \divisor_neg$50$next \divisor_neg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + assign \core_calculate_stage_13_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_divisor_radicand \core_calculate_stage_12_divisor_radicand$61 sync init - update \divisor_neg$50 1'0 - sync posedge \coresync_clk - update \divisor_neg$50 \divisor_neg$50$next end process $group_61 - assign \dividend_neg$51$next \dividend_neg$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \dividend_neg$51$next \dividend_neg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + assign \core_calculate_stage_13_operation 2'00 + assign \core_calculate_stage_13_operation \core_calculate_stage_12_operation$62 sync init - update \dividend_neg$51 1'0 - sync posedge \coresync_clk - update \dividend_neg$51 \dividend_neg$51$next end process $group_62 - assign \dive_abs_ov32$52$next \dive_abs_ov32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \dive_abs_ov32$52$next \dive_abs_ov32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + assign \core_calculate_stage_13_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_quotient_root \core_calculate_stage_12_quotient_root$63 sync init - update \dive_abs_ov32$52 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$52 \dive_abs_ov32$52$next end process $group_63 - assign \dive_abs_ov64$53$next \dive_abs_ov64$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \dive_abs_ov64$53$next \dive_abs_ov64 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + assign \core_calculate_stage_13_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_root_times_radicand \core_calculate_stage_12_root_times_radicand$64 sync init - update \dive_abs_ov64$53 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$53 \dive_abs_ov64$53$next end process $group_64 - assign \div_by_zero$54$next \div_by_zero$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \div_by_zero$54$next \div_by_zero - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + assign \core_calculate_stage_13_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_compare_lhs \core_calculate_stage_12_compare_lhs$65 sync init - update \div_by_zero$54 1'0 - sync posedge \coresync_clk - update \div_by_zero$54 \div_by_zero$54$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$66$next process $group_65 - assign \dividend$66$next \dividend$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \dividend$66$next \dividend - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + assign \core_calculate_stage_13_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_compare_rhs \core_calculate_stage_12_compare_rhs$66 sync init - update \dividend$66 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \dividend$66 \dividend$66$next end process $group_66 - assign \divisor_radicand$63$next \divisor_radicand$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \divisor_radicand$63$next \divisor_radicand - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case - end + assign \core_calculate_stage_14_muxid 2'00 + assign \core_calculate_stage_14_muxid \core_calculate_stage_13_muxid$67 sync init - update \divisor_radicand$63 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$63 \divisor_radicand$63$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$67$next process $group_67 - assign \operation$67$next \operation$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182" - case 1'1 - assign \operation$67$next \operation - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case + assign \core_calculate_stage_14_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_14_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_14_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_14_logical_op__rc__rc 1'0 + assign \core_calculate_stage_14_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_14_logical_op__oe__oe 1'0 + assign \core_calculate_stage_14_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_14_logical_op__invert_in 1'0 + assign \core_calculate_stage_14_logical_op__zero_a 1'0 + assign \core_calculate_stage_14_logical_op__input_carry 2'00 + assign \core_calculate_stage_14_logical_op__invert_out 1'0 + assign \core_calculate_stage_14_logical_op__write_cr0 1'0 + assign \core_calculate_stage_14_logical_op__output_carry 1'0 + assign \core_calculate_stage_14_logical_op__is_32bit 1'0 + assign \core_calculate_stage_14_logical_op__is_signed 1'0 + assign \core_calculate_stage_14_logical_op__data_len 4'0000 + assign \core_calculate_stage_14_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_14_logical_op__insn \core_calculate_stage_14_logical_op__data_len \core_calculate_stage_14_logical_op__is_signed \core_calculate_stage_14_logical_op__is_32bit \core_calculate_stage_14_logical_op__output_carry \core_calculate_stage_14_logical_op__write_cr0 \core_calculate_stage_14_logical_op__invert_out \core_calculate_stage_14_logical_op__input_carry \core_calculate_stage_14_logical_op__zero_a \core_calculate_stage_14_logical_op__invert_in { \core_calculate_stage_14_logical_op__oe__oe_ok \core_calculate_stage_14_logical_op__oe__oe } { \core_calculate_stage_14_logical_op__rc__rc_ok \core_calculate_stage_14_logical_op__rc__rc } { \core_calculate_stage_14_logical_op__imm_data__imm_ok \core_calculate_stage_14_logical_op__imm_data__imm } \core_calculate_stage_14_logical_op__fn_unit \core_calculate_stage_14_logical_op__insn_type } { \core_calculate_stage_13_logical_op__insn$85 \core_calculate_stage_13_logical_op__data_len$84 \core_calculate_stage_13_logical_op__is_signed$83 \core_calculate_stage_13_logical_op__is_32bit$82 \core_calculate_stage_13_logical_op__output_carry$81 \core_calculate_stage_13_logical_op__write_cr0$80 \core_calculate_stage_13_logical_op__invert_out$79 \core_calculate_stage_13_logical_op__input_carry$78 \core_calculate_stage_13_logical_op__zero_a$77 \core_calculate_stage_13_logical_op__invert_in$76 { \core_calculate_stage_13_logical_op__oe__oe_ok$75 \core_calculate_stage_13_logical_op__oe__oe$74 } { \core_calculate_stage_13_logical_op__rc__rc_ok$73 \core_calculate_stage_13_logical_op__rc__rc$72 } { \core_calculate_stage_13_logical_op__imm_data__imm_ok$71 \core_calculate_stage_13_logical_op__imm_data__imm$70 } \core_calculate_stage_13_logical_op__fn_unit$69 \core_calculate_stage_13_logical_op__insn_type$68 } + sync init + end + process $group_85 + assign \core_calculate_stage_14_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_ra \core_calculate_stage_13_ra$86 + sync init + end + process $group_86 + assign \core_calculate_stage_14_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_rb \core_calculate_stage_13_rb$87 + sync init + end + process $group_87 + assign \core_calculate_stage_14_xer_so 1'0 + assign \core_calculate_stage_14_xer_so \core_calculate_stage_13_xer_so$88 + sync init + end + process $group_88 + assign \core_calculate_stage_14_divisor_neg 1'0 + assign \core_calculate_stage_14_divisor_neg \core_calculate_stage_13_divisor_neg$89 + sync init + end + process $group_89 + assign \core_calculate_stage_14_dividend_neg 1'0 + assign \core_calculate_stage_14_dividend_neg \core_calculate_stage_13_dividend_neg$90 + sync init + end + process $group_90 + assign \core_calculate_stage_14_dive_abs_ov32 1'0 + assign \core_calculate_stage_14_dive_abs_ov32 \core_calculate_stage_13_dive_abs_ov32$91 + sync init + end + process $group_91 + assign \core_calculate_stage_14_dive_abs_ov64 1'0 + assign \core_calculate_stage_14_dive_abs_ov64 \core_calculate_stage_13_dive_abs_ov64$92 + sync init + end + process $group_92 + assign \core_calculate_stage_14_div_by_zero 1'0 + assign \core_calculate_stage_14_div_by_zero \core_calculate_stage_13_div_by_zero$93 + sync init + end + process $group_93 + assign \core_calculate_stage_14_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_divisor_radicand \core_calculate_stage_13_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_14_operation 2'00 + assign \core_calculate_stage_14_operation \core_calculate_stage_13_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_14_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_quotient_root \core_calculate_stage_13_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_14_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_root_times_radicand \core_calculate_stage_13_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_14_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_compare_lhs \core_calculate_stage_13_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_14_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_compare_rhs \core_calculate_stage_13_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_15_muxid 2'00 + assign \core_calculate_stage_15_muxid \core_calculate_stage_14_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_15_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_15_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_15_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_15_logical_op__rc__rc 1'0 + assign \core_calculate_stage_15_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_15_logical_op__oe__oe 1'0 + assign \core_calculate_stage_15_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_15_logical_op__invert_in 1'0 + assign \core_calculate_stage_15_logical_op__zero_a 1'0 + assign \core_calculate_stage_15_logical_op__input_carry 2'00 + assign \core_calculate_stage_15_logical_op__invert_out 1'0 + assign \core_calculate_stage_15_logical_op__write_cr0 1'0 + assign \core_calculate_stage_15_logical_op__output_carry 1'0 + assign \core_calculate_stage_15_logical_op__is_32bit 1'0 + assign \core_calculate_stage_15_logical_op__is_signed 1'0 + assign \core_calculate_stage_15_logical_op__data_len 4'0000 + assign \core_calculate_stage_15_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_15_logical_op__insn \core_calculate_stage_15_logical_op__data_len \core_calculate_stage_15_logical_op__is_signed \core_calculate_stage_15_logical_op__is_32bit \core_calculate_stage_15_logical_op__output_carry \core_calculate_stage_15_logical_op__write_cr0 \core_calculate_stage_15_logical_op__invert_out \core_calculate_stage_15_logical_op__input_carry \core_calculate_stage_15_logical_op__zero_a \core_calculate_stage_15_logical_op__invert_in { \core_calculate_stage_15_logical_op__oe__oe_ok \core_calculate_stage_15_logical_op__oe__oe } { \core_calculate_stage_15_logical_op__rc__rc_ok \core_calculate_stage_15_logical_op__rc__rc } { \core_calculate_stage_15_logical_op__imm_data__imm_ok \core_calculate_stage_15_logical_op__imm_data__imm } \core_calculate_stage_15_logical_op__fn_unit \core_calculate_stage_15_logical_op__insn_type } { \core_calculate_stage_14_logical_op__insn$118 \core_calculate_stage_14_logical_op__data_len$117 \core_calculate_stage_14_logical_op__is_signed$116 \core_calculate_stage_14_logical_op__is_32bit$115 \core_calculate_stage_14_logical_op__output_carry$114 \core_calculate_stage_14_logical_op__write_cr0$113 \core_calculate_stage_14_logical_op__invert_out$112 \core_calculate_stage_14_logical_op__input_carry$111 \core_calculate_stage_14_logical_op__zero_a$110 \core_calculate_stage_14_logical_op__invert_in$109 { \core_calculate_stage_14_logical_op__oe__oe_ok$108 \core_calculate_stage_14_logical_op__oe__oe$107 } { \core_calculate_stage_14_logical_op__rc__rc_ok$106 \core_calculate_stage_14_logical_op__rc__rc$105 } { \core_calculate_stage_14_logical_op__imm_data__imm_ok$104 \core_calculate_stage_14_logical_op__imm_data__imm$103 } \core_calculate_stage_14_logical_op__fn_unit$102 \core_calculate_stage_14_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_15_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_ra \core_calculate_stage_14_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_15_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_rb \core_calculate_stage_14_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_15_xer_so 1'0 + assign \core_calculate_stage_15_xer_so \core_calculate_stage_14_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_15_divisor_neg 1'0 + assign \core_calculate_stage_15_divisor_neg \core_calculate_stage_14_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_15_dividend_neg 1'0 + assign \core_calculate_stage_15_dividend_neg \core_calculate_stage_14_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_15_dive_abs_ov32 1'0 + assign \core_calculate_stage_15_dive_abs_ov32 \core_calculate_stage_14_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_15_dive_abs_ov64 1'0 + assign \core_calculate_stage_15_dive_abs_ov64 \core_calculate_stage_14_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_15_div_by_zero 1'0 + assign \core_calculate_stage_15_div_by_zero \core_calculate_stage_14_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_15_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_divisor_radicand \core_calculate_stage_14_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_15_operation 2'00 + assign \core_calculate_stage_15_operation \core_calculate_stage_14_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_15_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_quotient_root \core_calculate_stage_14_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_15_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_root_times_radicand \core_calculate_stage_14_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_15_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_compare_lhs \core_calculate_stage_14_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_15_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_compare_rhs \core_calculate_stage_14_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 + end + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_15_muxid$133 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_15_logical_op__insn$151 \core_calculate_stage_15_logical_op__data_len$150 \core_calculate_stage_15_logical_op__is_signed$149 \core_calculate_stage_15_logical_op__is_32bit$148 \core_calculate_stage_15_logical_op__output_carry$147 \core_calculate_stage_15_logical_op__write_cr0$146 \core_calculate_stage_15_logical_op__invert_out$145 \core_calculate_stage_15_logical_op__input_carry$144 \core_calculate_stage_15_logical_op__zero_a$143 \core_calculate_stage_15_logical_op__invert_in$142 { \core_calculate_stage_15_logical_op__oe__oe_ok$141 \core_calculate_stage_15_logical_op__oe__oe$140 } { \core_calculate_stage_15_logical_op__rc__rc_ok$139 \core_calculate_stage_15_logical_op__rc__rc$138 } { \core_calculate_stage_15_logical_op__imm_data__imm_ok$137 \core_calculate_stage_15_logical_op__imm_data__imm$136 } \core_calculate_stage_15_logical_op__fn_unit$135 \core_calculate_stage_15_logical_op__insn_type$134 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_15_ra$152 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_15_rb$153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_15_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_15_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_15_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_15_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_15_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_15_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_15_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_15_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_15_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_15_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_15_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_15_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next + end + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end + sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next + end + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 end sync init - update \operation$67 2'00 + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \operation$67 \operation$67$next + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.p" -module \p$77 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.p" +module \p$146 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -92784,8 +79275,8 @@ module \p$77 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.n" -module \n$78 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.n" +module \n$147 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -92812,8 +79303,602 @@ module \n$78 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output_stage" -module \output_stage +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_16.core.trial0" +module \trial0$149 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_16.core.trial1" +module \trial1$150 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_16.core.pe" +module \pe$151 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_16.core" +module \core$148 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$149 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$150 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$151 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'101111 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_16" +module \core_calculate_stage_16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -92918,7 +80003,7 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" @@ -92942,23 +80027,35 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 19 \xer_so + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 20 \divisor_neg + wire width 1 input 22 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 21 \dividend_neg + wire width 1 input 23 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 22 \dive_abs_ov32 + wire width 1 input 24 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 23 \dive_abs_ov64 + wire width 1 input 25 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 24 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 input 25 \quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 input 26 \remainder + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 27 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -93033,7 +80130,7 @@ module \output_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 28 \logical_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -93047,436 +80144,834 @@ module \output_stage attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 29 \logical_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 30 \logical_op__imm_data__imm$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__imm_data__imm_ok$5 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__rc__rc$6 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__rc__rc_ok$7 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__oe__oe$8 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__oe__oe_ok$9 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__invert_a$10 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__zero_a$11 + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 38 \logical_op__input_carry$12 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__invert_out$13 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__write_cr0$14 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__output_carry$15 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__is_32bit$16 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__is_signed$17 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 44 \logical_op__data_len$18 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 45 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 46 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 50 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" - wire width 1 \quotient_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dividend_neg - connect \B \divisor_neg - connect \Y $21 + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$148 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \quotient_neg 1'0 - assign \quotient_neg $21 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" - wire width 1 \remainder_neg process $group_1 - assign \remainder_neg 1'0 - assign \remainder_neg \dividend_neg + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" - wire width 65 \quotient_65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - wire width 65 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \quotient_root - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 65 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \quotient_root - connect \Y $25 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - wire width 65 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $28 - parameter \WIDTH 65 - connect \A $25 - connect \B $23 - connect \S \quotient_neg - connect \Y $27 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - process $group_2 - assign \quotient_65 65'00000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_65 $27 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" - wire width 64 \remainder_64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - wire width 65 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - wire width 65 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \remainder [127:64] - connect \Y $30 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 65 $32 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $33 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_17.core.trial0" +module \trial0$153 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 65 - connect \A \remainder [127:64] - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - wire width 65 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $35 - parameter \WIDTH 65 - connect \A $32 - connect \B $30 - connect \S \remainder_neg - connect \Y $34 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - connect $29 $34 - process $group_3 - assign \remainder_64 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \remainder_64 $29 [63:0] + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - wire width 1 $verilog_initial_trigger - process $group_4 - assign \xer_ov_ok 1'0 - assign \xer_ov_ok 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101110 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init - update $verilog_initial_trigger 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" - wire width 1 \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $37 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_17.core.trial1" +module \trial1$154 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__is_32bit - connect \Y $36 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \quotient_65 [64] - connect \B \quotient_65 [63] - connect \Y $38 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $41 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__is_signed - connect \B $38 - connect \Y $40 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $43 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101110 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_17.core.pe" +module \pe$155 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \quotient_65 [32] - connect \B \quotient_65 [31] - connect \Y $42 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_17.core" +module \core$152 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$153 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$154 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$155 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 process $group_5 - assign \ov 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" - switch { \logical_op__is_signed $36 \div_by_zero } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" - case 3'--1 - assign \ov 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - case 3'-1- - assign \ov \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - switch { $40 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - case 1'1 - assign \ov 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:82" - case 3'1-- - assign \ov \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - switch { $42 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - case 1'1 - assign \ov 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:86" - case - assign \ov \dive_abs_ov32 - end + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end process $group_6 - assign \xer_ov 2'00 - assign \xer_ov { \ov \ov } + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end process $group_7 - assign \o_ok 1'0 - assign \o_ok 1'1 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - cell $not $45 + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \ov - connect \Y $44 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - wire width 64 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $pos $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $46 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" - wire width 64 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" - cell $pos $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $48 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" - wire width 64 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" - cell $pos $51 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $50 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" - wire width 64 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" - cell $pos $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $52 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" - wire width 64 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" - cell $pos $55 - parameter \A_SIGNED 1 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \remainder_64 [31:0] - connect \Y $54 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" - wire width 64 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" - cell $pos $57 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \remainder_64 [31:0] - connect \Y $56 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_8 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - switch { $44 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:98" - attribute \nmigen.decoding "OP_DIVE/30" - case 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" - switch { \logical_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" - switch { \logical_op__is_signed } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" - case 1'1 - assign \o $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" - case - assign \o $48 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" - case - assign \o \quotient_65 [63:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:107" - attribute \nmigen.decoding "OP_DIV/29" - case 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - switch { \logical_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" - switch { \logical_op__is_signed } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" - case 1'1 - assign \o $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:112" - case - assign \o $52 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" - case - assign \o \quotient_65 [63:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:116" - attribute \nmigen.decoding "OP_MOD/47" - case 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - switch { \logical_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" - switch { \logical_op__is_signed } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" - case 1'1 - assign \o $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:121" - case - assign \o $56 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" - case - assign \o \remainder_64 - end - end + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - process $group_9 - assign \xer_so$20 1'0 - assign \xer_so$20 \xer_so + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - process $group_10 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - process $group_11 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_a$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'101110 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output" -module \output$79 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_17" +module \core_calculate_stage_17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -93581,7 +81076,7 @@ module \output$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" @@ -93604,18 +81099,36 @@ module \output$79 wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 24 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -93690,7 +81203,7 @@ module \output$79 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 25 \logical_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -93704,422 +81217,836 @@ module \output$79 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 26 \logical_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 27 \logical_op__imm_data__imm$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__imm_data__imm_ok$5 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__rc__rc$6 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__rc__rc_ok$7 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__oe__oe$8 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__oe__oe_ok$9 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__invert_a$10 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__zero_a$11 + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 35 \logical_op__input_carry$12 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__invert_out$13 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__write_cr0$14 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__output_carry$15 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__is_32bit$16 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__is_signed$17 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 41 \logical_op__data_len$18 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 42 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 43 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 44 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 45 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 46 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 47 \xer_ov$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 48 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_so$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 50 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 65 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 64 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $not $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $27 + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$152 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $pos $29 + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_18.core.trial0" +module \trial0$157 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A $27 - connect \Y $26 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 65 - connect \A \o - connect \Y $30 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end process $group_0 - assign \o$25 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" - switch { \logical_op__invert_out } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \o$25 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - case - assign \o$25 $30 + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" - wire width 64 \target - process $group_1 - assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$25 [63:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" - wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001010 - connect \Y $32 - end - process $group_2 - assign \is_cmp 1'0 - assign \is_cmp $32 - sync init + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" - wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001100 - connect \Y $34 - end - process $group_3 - assign \is_cmpeqb 1'0 - assign \is_cmpeqb $34 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" - wire width 1 \msb_test - process $group_4 - assign \msb_test 1'0 - assign \msb_test \target [63] - sync init + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $36 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_5 - assign \is_nzero 1'0 - assign \is_nzero $36 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" - wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $39 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_18.core.trial1" +module \trial1$158 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $38 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $41 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $38 - connect \Y $40 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_6 - assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_positive $40 + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $43 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $42 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $45 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $42 - connect \Y $44 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101101 + connect \Y $8 end - process $group_7 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \is_negative $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_negative \msb_test + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - cell $not $47 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_18.core.pe" +module \pe$159 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $46 + connect \A \i + connect \B 1'0 + connect \Y $1 end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_18.core" +module \core$156 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$157 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$158 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$159 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger process $group_8 - assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - case 1'1 - assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - case - assign \cr0 { \is_negative \is_positive $46 \xer_so$24 } - end + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end process $group_9 - assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$20 \o$25 [63:0] + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 process $group_10 - assign \o_ok$21 1'0 - assign \o_ok$21 \o_ok + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 process $group_11 - assign \cr_a$22 4'0000 - assign \cr_a$22 \cr0 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init end process $group_12 - assign \cr_a_ok 1'0 - assign \cr_a_ok \logical_op__write_cr0 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end process $group_13 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - process $group_14 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__rc_ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__oe_ok$9 1'0 - assign \logical_op__invert_a$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" - wire width 1 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - cell $and $49 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__oe__oe - connect \B \logical_op__oe__oe_ok - connect \Y $48 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_32 - assign \oe 1'0 - assign \oe $48 + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" - wire width 1 \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - cell $or $51 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $50 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_33 - assign \so 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \so $50 - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - process $group_34 - assign \xer_so$24 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_so$24 \so - end - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_35 - assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_so_ok 1'1 - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - process $group_36 - assign \xer_ov$23 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_ov$23 \xer_ov - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - process $group_37 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_ov_ok 1'1 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'101101 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end" -module \pipe_end - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_18" +module \core_calculate_stage_18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94194,7 +82121,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -94208,71 +82135,73 @@ module \pipe_end attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \logical_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 25 \xer_so + wire width 1 input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 26 \divisor_neg + wire width 1 input 22 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 27 \dividend_neg + wire width 1 input 23 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 28 \dive_abs_ov32 + wire width 1 input 24 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 29 \dive_abs_ov64 + wire width 1 input 25 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 input 31 \quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 input 32 \remainder - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 34 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 35 \muxid$1 + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94347,9 +82276,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 36 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -94363,119 +82290,836 @@ module \pipe_end attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 37 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \logical_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$7$next + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__oe__oe$8 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$8$next + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__oe__oe_ok$9 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$9$next + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 44 \logical_op__invert_a$10 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_a$10$next + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 45 \logical_op__zero_a$11 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$11$next + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 46 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 47 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 48 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 49 \logical_op__output_carry$15 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 50 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$16$next + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \logical_op__is_signed$17 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$17$next + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \logical_op__data_len$18 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \logical_op__insn$19 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 54 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 55 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 56 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 57 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 58 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 59 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 60 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 61 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$next - cell \p$77 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$156 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - cell \n$78 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_19.core.trial0" +module \trial0$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101100 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_19.core.trial1" +module \trial1$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101100 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_19.core.pe" +module \pe$163 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_19.core" +module \core$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$161 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$162 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$163 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'101100 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4.core_calculate_stage_19" +module \core_calculate_stage_19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_stage_muxid + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94550,7 +83194,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -94564,61 +83208,73 @@ module \pipe_end attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_stage_logical_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__zero_a + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_stage_logical_op__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__invert_out + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__write_cr0 + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__output_carry + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_stage_logical_op__data_len + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_stage_logical_op__insn + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \output_stage_xer_so + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \output_stage_divisor_neg + wire width 1 input 22 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \output_stage_dividend_neg + wire width 1 input 23 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \output_stage_dive_abs_ov32 + wire width 1 input 24 \dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \output_stage_dive_abs_ov64 + wire width 1 input 25 \dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \output_stage_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 \output_stage_quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 \output_stage_remainder + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_stage_muxid$21 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94693,7 +83349,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type$22 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -94707,108 +83363,250 @@ module \pipe_end attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_stage_logical_op__fn_unit$23 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_stage_logical_op__imm_data__imm$24 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__imm_data__imm_ok$25 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__rc__rc$26 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__rc__rc_ok$27 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__oe__oe$28 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__oe__oe_ok$29 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__invert_a$30 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__zero_a$31 + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_stage_logical_op__input_carry$32 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__invert_out$33 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__write_cr0$34 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__output_carry$35 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__is_32bit$36 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_stage_logical_op__is_signed$37 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_stage_logical_op__data_len$38 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_stage_logical_op__insn$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_stage_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_stage_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_stage_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_stage_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_stage_xer_so$40 - cell \output_stage \output_stage - connect \muxid \output_stage_muxid - connect \logical_op__insn_type \output_stage_logical_op__insn_type - connect \logical_op__fn_unit \output_stage_logical_op__fn_unit - connect \logical_op__imm_data__imm \output_stage_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \output_stage_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \output_stage_logical_op__rc__rc - connect \logical_op__rc__rc_ok \output_stage_logical_op__rc__rc_ok - connect \logical_op__oe__oe \output_stage_logical_op__oe__oe - connect \logical_op__oe__oe_ok \output_stage_logical_op__oe__oe_ok - connect \logical_op__invert_a \output_stage_logical_op__invert_a - connect \logical_op__zero_a \output_stage_logical_op__zero_a - connect \logical_op__input_carry \output_stage_logical_op__input_carry - connect \logical_op__invert_out \output_stage_logical_op__invert_out - connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 - connect \logical_op__output_carry \output_stage_logical_op__output_carry - connect \logical_op__is_32bit \output_stage_logical_op__is_32bit - connect \logical_op__is_signed \output_stage_logical_op__is_signed - connect \logical_op__data_len \output_stage_logical_op__data_len - connect \logical_op__insn \output_stage_logical_op__insn - connect \xer_so \output_stage_xer_so - connect \divisor_neg \output_stage_divisor_neg - connect \dividend_neg \output_stage_dividend_neg - connect \dive_abs_ov32 \output_stage_dive_abs_ov32 - connect \dive_abs_ov64 \output_stage_dive_abs_ov64 - connect \div_by_zero \output_stage_div_by_zero - connect \quotient_root \output_stage_quotient_root - connect \remainder \output_stage_remainder - connect \muxid$1 \output_stage_muxid$21 - connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 - connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 - connect \logical_op__imm_data__imm$4 \output_stage_logical_op__imm_data__imm$24 - connect \logical_op__imm_data__imm_ok$5 \output_stage_logical_op__imm_data__imm_ok$25 - connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 - connect \logical_op__rc__rc_ok$7 \output_stage_logical_op__rc__rc_ok$27 - connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 - connect \logical_op__oe__oe_ok$9 \output_stage_logical_op__oe__oe_ok$29 - connect \logical_op__invert_a$10 \output_stage_logical_op__invert_a$30 - connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 - connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 - connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 - connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 - connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 - connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 - connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 - connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 - connect \logical_op__insn$19 \output_stage_logical_op__insn$39 - connect \o \output_stage_o - connect \o_ok \output_stage_o_ok - connect \xer_ov \output_stage_xer_ov - connect \xer_ov_ok \output_stage_xer_ov_ok - connect \xer_so$20 \output_stage_xer_so$40 + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$160 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_4" +module \pipe_middle_4 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid + wire width 2 input 4 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -94883,7 +83681,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -94897,55 +83695,79 @@ module \pipe_end attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_logical_op__fn_unit + wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__imm + wire width 64 input 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__imm_data__imm_ok + wire width 1 input 8 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc + wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc_ok + wire width 1 input 10 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe + wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe_ok + wire width 1 input 12 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__invert_a + wire width 1 input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__zero_a + wire width 1 input 14 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry + wire width 2 input 15 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__invert_out + wire width 1 input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__write_cr0 + wire width 1 input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__output_carry + wire width 1 input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__is_32bit + wire width 1 input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__is_signed + wire width 1 input 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len + wire width 4 input 21 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$41 + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -95020,7 +83842,9 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type$42 + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -95034,297 +83858,143 @@ module \pipe_end attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_logical_op__fn_unit$43 + wire width 11 output 41 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__imm$44 + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__imm_data__imm_ok$45 + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc$46 + wire width 1 output 46 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__rc__rc_ok$47 + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe$48 + wire width 1 output 48 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__oe__oe_ok$49 + wire width 1 \logical_op__invert_in$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__invert_a$50 + wire width 1 output 49 \logical_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__zero_a$51 + wire width 1 \logical_op__zero_a$11$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry$52 + wire width 2 output 50 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__invert_out$53 + wire width 2 \logical_op__input_carry$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__write_cr0$54 + wire width 1 output 51 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__output_carry$55 + wire width 1 \logical_op__invert_out$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__is_32bit$56 + wire width 1 output 52 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_logical_op__is_signed$57 + wire width 1 \logical_op__write_cr0$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len$58 + wire width 1 output 53 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so_ok - cell \output$79 \output - connect \muxid \output_muxid - connect \logical_op__insn_type \output_logical_op__insn_type - connect \logical_op__fn_unit \output_logical_op__fn_unit - connect \logical_op__imm_data__imm \output_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc_ok \output_logical_op__rc__rc_ok - connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe_ok \output_logical_op__oe__oe_ok - connect \logical_op__invert_a \output_logical_op__invert_a - connect \logical_op__zero_a \output_logical_op__zero_a - connect \logical_op__input_carry \output_logical_op__input_carry - connect \logical_op__invert_out \output_logical_op__invert_out - connect \logical_op__write_cr0 \output_logical_op__write_cr0 - connect \logical_op__output_carry \output_logical_op__output_carry - connect \logical_op__is_32bit \output_logical_op__is_32bit - connect \logical_op__is_signed \output_logical_op__is_signed - connect \logical_op__data_len \output_logical_op__data_len - connect \logical_op__insn \output_logical_op__insn - connect \o \output_o - connect \o_ok \output_o_ok - connect \cr_a \output_cr_a - connect \xer_ov \output_xer_ov - connect \xer_so \output_xer_so - connect \muxid$1 \output_muxid$41 - connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 - connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 - connect \logical_op__imm_data__imm$4 \output_logical_op__imm_data__imm$44 - connect \logical_op__imm_data__imm_ok$5 \output_logical_op__imm_data__imm_ok$45 - connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 - connect \logical_op__rc__rc_ok$7 \output_logical_op__rc__rc_ok$47 - connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 - connect \logical_op__oe__oe_ok$9 \output_logical_op__oe__oe_ok$49 - connect \logical_op__invert_a$10 \output_logical_op__invert_a$50 - connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 - connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 - connect \logical_op__invert_out$13 \output_logical_op__invert_out$53 - connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 - connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 - connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56 - connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 - connect \logical_op__data_len$18 \output_logical_op__data_len$58 - connect \logical_op__insn$19 \output_logical_op__insn$59 - connect \o$20 \output_o$60 - connect \o_ok$21 \output_o_ok$61 - connect \cr_a$22 \output_cr_a$62 - connect \cr_a_ok \output_cr_a_ok - connect \xer_ov$23 \output_xer_ov$63 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so$24 \output_xer_so$64 - connect \xer_so_ok \output_xer_so_ok - end - process $group_0 - assign \output_stage_muxid 2'00 - assign \output_stage_muxid \muxid - sync init - end - process $group_1 - assign \output_stage_logical_op__insn_type 7'0000000 - assign \output_stage_logical_op__fn_unit 11'00000000000 - assign \output_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_stage_logical_op__imm_data__imm_ok 1'0 - assign \output_stage_logical_op__rc__rc 1'0 - assign \output_stage_logical_op__rc__rc_ok 1'0 - assign \output_stage_logical_op__oe__oe 1'0 - assign \output_stage_logical_op__oe__oe_ok 1'0 - assign \output_stage_logical_op__invert_a 1'0 - assign \output_stage_logical_op__zero_a 1'0 - assign \output_stage_logical_op__input_carry 2'00 - assign \output_stage_logical_op__invert_out 1'0 - assign \output_stage_logical_op__write_cr0 1'0 - assign \output_stage_logical_op__output_carry 1'0 - assign \output_stage_logical_op__is_32bit 1'0 - assign \output_stage_logical_op__is_signed 1'0 - assign \output_stage_logical_op__data_len 4'0000 - assign \output_stage_logical_op__insn 32'00000000000000000000000000000000 - assign { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_a { \output_stage_logical_op__oe__oe_ok \output_stage_logical_op__oe__oe } { \output_stage_logical_op__rc__rc_ok \output_stage_logical_op__rc__rc } { \output_stage_logical_op__imm_data__imm_ok \output_stage_logical_op__imm_data__imm } \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } - sync init - end + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$65 - process $group_19 - assign \ra$65 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$65 \ra - sync init - end + wire width 64 output 58 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$66 - process $group_20 - assign \rb$66 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$66 \rb - sync init - end - process $group_21 - assign \output_stage_xer_so 1'0 - assign \output_stage_xer_so \xer_so - sync init - end - process $group_22 - assign \output_stage_divisor_neg 1'0 - assign \output_stage_divisor_neg \divisor_neg - sync init - end - process $group_23 - assign \output_stage_dividend_neg 1'0 - assign \output_stage_dividend_neg \dividend_neg - sync init - end - process $group_24 - assign \output_stage_dive_abs_ov32 1'0 - assign \output_stage_dive_abs_ov32 \dive_abs_ov32 - sync init - end - process $group_25 - assign \output_stage_dive_abs_ov64 1'0 - assign \output_stage_dive_abs_ov64 \dive_abs_ov64 - sync init - end - process $group_26 - assign \output_stage_div_by_zero 1'0 - assign \output_stage_div_by_zero \div_by_zero - sync init - end - process $group_27 - assign \output_stage_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_stage_quotient_root \quotient_root - sync init - end - process $group_28 - assign \output_stage_remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \output_stage_remainder \remainder - sync init - end - process $group_29 - assign \output_muxid 2'00 - assign \output_muxid \output_stage_muxid$21 - sync init - end - process $group_30 - assign \output_logical_op__insn_type 7'0000000 - assign \output_logical_op__fn_unit 11'00000000000 - assign \output_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_logical_op__imm_data__imm_ok 1'0 - assign \output_logical_op__rc__rc 1'0 - assign \output_logical_op__rc__rc_ok 1'0 - assign \output_logical_op__oe__oe 1'0 - assign \output_logical_op__oe__oe_ok 1'0 - assign \output_logical_op__invert_a 1'0 - assign \output_logical_op__zero_a 1'0 - assign \output_logical_op__input_carry 2'00 - assign \output_logical_op__invert_out 1'0 - assign \output_logical_op__write_cr0 1'0 - assign \output_logical_op__output_carry 1'0 - assign \output_logical_op__is_32bit 1'0 - assign \output_logical_op__is_signed 1'0 - assign \output_logical_op__data_len 4'0000 - assign \output_logical_op__insn 32'00000000000000000000000000000000 - assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_a { \output_logical_op__oe__oe_ok \output_logical_op__oe__oe } { \output_logical_op__rc__rc_ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm } \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_a$30 { \output_stage_logical_op__oe__oe_ok$29 \output_stage_logical_op__oe__oe$28 } { \output_stage_logical_op__rc__rc_ok$27 \output_stage_logical_op__rc__rc$26 } { \output_stage_logical_op__imm_data__imm_ok$25 \output_stage_logical_op__imm_data__imm$24 } \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } - sync init - end - process $group_48 - assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_o_ok 1'0 - assign { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$69 - process $group_50 - assign \output_cr_a 4'0000 - assign \cr_a_ok$67 1'0 - assign { \cr_a_ok$67 \output_cr_a } { \cr_a_ok$69 \cr_a$68 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$70 - process $group_52 - assign \output_xer_ov 2'00 - assign \xer_ov_ok$70 1'0 - assign { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$72 - process $group_54 - assign \output_xer_so 1'0 - assign \xer_so_ok$71 1'0 - assign { \xer_so_ok$71 \output_xer_so } { \xer_so_ok$72 \output_stage_xer_so$40 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$73 - process $group_56 - assign \p_valid_i$73 1'0 - assign \p_valid_i$73 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_57 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $74 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$73 - connect \B \p_ready_o - connect \Y $74 + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$146 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_58 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $74 - sync init + cell \n$147 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$76 - process $group_59 - assign \muxid$76 2'00 - assign \muxid$76 \output_muxid$41 - sync init - end + wire width 2 \core_calculate_stage_16_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -95399,7 +84069,7 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$77 + wire width 7 \core_calculate_stage_16_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -95413,360 +84083,73 @@ module \pipe_end attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$78 + wire width 11 \core_calculate_stage_16_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$79 + wire width 64 \core_calculate_stage_16_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$80 + wire width 1 \core_calculate_stage_16_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$81 + wire width 1 \core_calculate_stage_16_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$82 + wire width 1 \core_calculate_stage_16_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$83 + wire width 1 \core_calculate_stage_16_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$84 + wire width 1 \core_calculate_stage_16_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_a$85 + wire width 1 \core_calculate_stage_16_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$86 + wire width 1 \core_calculate_stage_16_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$87 + wire width 2 \core_calculate_stage_16_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$88 + wire width 1 \core_calculate_stage_16_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$89 + wire width 1 \core_calculate_stage_16_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$90 + wire width 1 \core_calculate_stage_16_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$91 + wire width 1 \core_calculate_stage_16_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$92 + wire width 1 \core_calculate_stage_16_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$93 + wire width 4 \core_calculate_stage_16_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$94 - process $group_60 - assign \logical_op__insn_type$77 7'0000000 - assign \logical_op__fn_unit$78 11'00000000000 - assign \logical_op__imm_data__imm$79 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$80 1'0 - assign \logical_op__rc__rc$81 1'0 - assign \logical_op__rc__rc_ok$82 1'0 - assign \logical_op__oe__oe$83 1'0 - assign \logical_op__oe__oe_ok$84 1'0 - assign \logical_op__invert_a$85 1'0 - assign \logical_op__zero_a$86 1'0 - assign \logical_op__input_carry$87 2'00 - assign \logical_op__invert_out$88 1'0 - assign \logical_op__write_cr0$89 1'0 - assign \logical_op__output_carry$90 1'0 - assign \logical_op__is_32bit$91 1'0 - assign \logical_op__is_signed$92 1'0 - assign \logical_op__data_len$93 4'0000 - assign \logical_op__insn$94 32'00000000000000000000000000000000 - assign { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_a$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_a$50 { \output_logical_op__oe__oe_ok$49 \output_logical_op__oe__oe$48 } { \output_logical_op__rc__rc_ok$47 \output_logical_op__rc__rc$46 } { \output_logical_op__imm_data__imm_ok$45 \output_logical_op__imm_data__imm$44 } \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$96 - process $group_78 - assign \o$95 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$96 1'0 - assign { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$98 - process $group_80 - assign \cr_a$97 4'0000 - assign \cr_a_ok$98 1'0 - assign { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$100 - process $group_82 - assign \xer_ov$99 2'00 - assign \xer_ov_ok$100 1'0 - assign { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$102 - process $group_84 - assign \xer_so$101 1'0 - assign \xer_so_ok$102 1'0 - assign { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_86 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_87 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$76 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$76 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_88 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 - assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 - assign \logical_op__invert_a$10$next \logical_op__invert_a$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_a$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_a$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_a$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_a$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__rc_ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__oe_ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__imm_ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__rc_ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__oe_ok$9 1'0 - update \logical_op__invert_a$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next - update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next - update \logical_op__invert_a$10 \logical_op__invert_a$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_106 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$96 \o$95 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$96 \o$95 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_108 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$98 \cr_a$97 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$98 \cr_a$97 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next - end - process $group_110 - assign \xer_ov$next \xer_ov - assign \xer_ov_ok$next \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$100 \xer_ov$99 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$100 \xer_ov$99 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ov_ok$next 1'0 - end - sync init - update \xer_ov 2'00 - update \xer_ov_ok 1'0 - sync posedge \coresync_clk - update \xer_ov \xer_ov$next - update \xer_ov_ok \xer_ov_ok$next - end - process $group_112 - assign \xer_so$20$next \xer_so$20 - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$102 \xer_so$101 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$102 \xer_so$101 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so$20 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so$20 \xer_so$20$next - update \xer_so_ok \xer_so_ok$next - end - process $group_114 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_115 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \cr_a$68 4'0000 - connect \cr_a_ok$69 1'0 - connect \xer_so_ok$72 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0" -module \alu_div0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \xer_so_ok - attribute \src "simple/issuer.py:89" - wire width 1 input 5 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 7 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 8 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 9 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 10 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 11 \xer_so + wire width 32 \core_calculate_stage_16_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_16_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_16_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_16_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_16_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_16_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_16_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_16_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_16_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_16_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_16_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_16_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_16_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_16_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_16_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_16_muxid$34 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -95841,7 +84224,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 12 \logical_op__insn_type + wire width 7 \core_calculate_stage_16_logical_op__insn_type$35 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -95855,67 +84238,141 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 13 \logical_op__fn_unit + wire width 11 \core_calculate_stage_16_logical_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 14 \logical_op__imm_data__imm + wire width 64 \core_calculate_stage_16_logical_op__imm_data__imm$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_16_logical_op__imm_data__imm_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__rc__rc + wire width 1 \core_calculate_stage_16_logical_op__rc__rc$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_16_logical_op__rc__rc_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__oe__oe + wire width 1 \core_calculate_stage_16_logical_op__oe__oe$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_16_logical_op__oe__oe_ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__invert_a + wire width 1 \core_calculate_stage_16_logical_op__invert_in$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 21 \logical_op__zero_a + wire width 1 \core_calculate_stage_16_logical_op__zero_a$44 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 22 \logical_op__input_carry + wire width 2 \core_calculate_stage_16_logical_op__input_carry$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 23 \logical_op__invert_out + wire width 1 \core_calculate_stage_16_logical_op__invert_out$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 24 \logical_op__write_cr0 + wire width 1 \core_calculate_stage_16_logical_op__write_cr0$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 25 \logical_op__output_carry + wire width 1 \core_calculate_stage_16_logical_op__output_carry$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 26 \logical_op__is_32bit + wire width 1 \core_calculate_stage_16_logical_op__is_32bit$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 27 \logical_op__is_signed + wire width 1 \core_calculate_stage_16_logical_op__is_signed$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 28 \logical_op__data_len + wire width 4 \core_calculate_stage_16_logical_op__data_len$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 29 \logical_op__insn + wire width 32 \core_calculate_stage_16_logical_op__insn$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 30 \ra + wire width 64 \core_calculate_stage_16_ra$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 31 \rb + wire width 64 \core_calculate_stage_16_rb$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 32 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 33 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 34 \p_ready_o - cell \p$70 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$71 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + wire width 1 \core_calculate_stage_16_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_16_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_16_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_16_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_16_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_16_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_16_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_16_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_16_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_16_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_16_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_16_compare_rhs$66 + cell \core_calculate_stage_16 \core_calculate_stage_16 + connect \muxid \core_calculate_stage_16_muxid + connect \logical_op__insn_type \core_calculate_stage_16_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_16_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_16_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_16_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_16_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_16_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_16_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_16_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_16_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_16_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_16_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_16_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_16_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_16_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_16_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_16_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_16_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_16_logical_op__insn + connect \ra \core_calculate_stage_16_ra + connect \rb \core_calculate_stage_16_rb + connect \xer_so \core_calculate_stage_16_xer_so + connect \divisor_neg \core_calculate_stage_16_divisor_neg + connect \dividend_neg \core_calculate_stage_16_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_16_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_16_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_16_div_by_zero + connect \divisor_radicand \core_calculate_stage_16_divisor_radicand + connect \operation \core_calculate_stage_16_operation + connect \quotient_root \core_calculate_stage_16_quotient_root + connect \root_times_radicand \core_calculate_stage_16_root_times_radicand + connect \compare_lhs \core_calculate_stage_16_compare_lhs + connect \compare_rhs \core_calculate_stage_16_compare_rhs + connect \muxid$1 \core_calculate_stage_16_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_16_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_16_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_16_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_16_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_16_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_16_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_16_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_16_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_16_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_16_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_16_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_16_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_16_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_16_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_16_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_16_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_16_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_16_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_16_ra$53 + connect \rb$21 \core_calculate_stage_16_rb$54 + connect \xer_so$22 \core_calculate_stage_16_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_16_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_16_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_16_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_16_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_16_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_16_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_16_operation$62 + connect \quotient_root$30 \core_calculate_stage_16_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_16_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_16_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_16_compare_rhs$66 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_start_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_start_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_start_muxid + wire width 2 \core_calculate_stage_17_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -95990,7 +84447,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_start_logical_op__insn_type + wire width 7 \core_calculate_stage_17_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -96004,71 +84461,73 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_start_logical_op__fn_unit + wire width 11 \core_calculate_stage_17_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_start_logical_op__imm_data__imm + wire width 64 \core_calculate_stage_17_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_17_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__rc__rc + wire width 1 \core_calculate_stage_17_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_17_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__oe__oe + wire width 1 \core_calculate_stage_17_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_17_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__invert_a + wire width 1 \core_calculate_stage_17_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__zero_a + wire width 1 \core_calculate_stage_17_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_start_logical_op__input_carry + wire width 2 \core_calculate_stage_17_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__invert_out + wire width 1 \core_calculate_stage_17_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__write_cr0 + wire width 1 \core_calculate_stage_17_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__output_carry + wire width 1 \core_calculate_stage_17_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__is_32bit + wire width 1 \core_calculate_stage_17_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__is_signed + wire width 1 \core_calculate_stage_17_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_start_logical_op__data_len + wire width 4 \core_calculate_stage_17_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_start_logical_op__insn + wire width 32 \core_calculate_stage_17_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_ra + wire width 64 \core_calculate_stage_17_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_rb + wire width 64 \core_calculate_stage_17_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_start_xer_so + wire width 1 \core_calculate_stage_17_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_start_divisor_neg + wire width 1 \core_calculate_stage_17_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_start_dividend_neg + wire width 1 \core_calculate_stage_17_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_start_dive_abs_ov32 + wire width 1 \core_calculate_stage_17_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_start_dive_abs_ov64 + wire width 1 \core_calculate_stage_17_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_start_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \pipe_start_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \pipe_start_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \pipe_start_operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_start_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_start_p_ready_o + wire width 1 \core_calculate_stage_17_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_17_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_17_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_17_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_17_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_17_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_17_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_start_muxid$2 + wire width 2 \core_calculate_stage_17_muxid$67 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -96143,7 +84602,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_start_logical_op__insn_type$3 + wire width 7 \core_calculate_stage_17_logical_op__insn_type$68 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -96157,115 +84616,141 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_start_logical_op__fn_unit$4 + wire width 11 \core_calculate_stage_17_logical_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_start_logical_op__imm_data__imm$5 + wire width 64 \core_calculate_stage_17_logical_op__imm_data__imm$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__imm_data__imm_ok$6 + wire width 1 \core_calculate_stage_17_logical_op__imm_data__imm_ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__rc__rc$7 + wire width 1 \core_calculate_stage_17_logical_op__rc__rc$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__rc__rc_ok$8 + wire width 1 \core_calculate_stage_17_logical_op__rc__rc_ok$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__oe__oe$9 + wire width 1 \core_calculate_stage_17_logical_op__oe__oe$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__oe__oe_ok$10 + wire width 1 \core_calculate_stage_17_logical_op__oe__oe_ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__invert_a$11 + wire width 1 \core_calculate_stage_17_logical_op__invert_in$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__zero_a$12 + wire width 1 \core_calculate_stage_17_logical_op__zero_a$77 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_start_logical_op__input_carry$13 + wire width 2 \core_calculate_stage_17_logical_op__input_carry$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__invert_out$14 + wire width 1 \core_calculate_stage_17_logical_op__invert_out$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__write_cr0$15 + wire width 1 \core_calculate_stage_17_logical_op__write_cr0$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__output_carry$16 + wire width 1 \core_calculate_stage_17_logical_op__output_carry$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__is_32bit$17 + wire width 1 \core_calculate_stage_17_logical_op__is_32bit$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__is_signed$18 + wire width 1 \core_calculate_stage_17_logical_op__is_signed$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_start_logical_op__data_len$19 + wire width 4 \core_calculate_stage_17_logical_op__data_len$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_start_logical_op__insn$20 + wire width 32 \core_calculate_stage_17_logical_op__insn$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_ra$21 + wire width 64 \core_calculate_stage_17_ra$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_rb$22 + wire width 64 \core_calculate_stage_17_rb$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_start_xer_so$23 - cell \pipe_start \pipe_start - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \n_valid_o \pipe_start_n_valid_o - connect \n_ready_i \pipe_start_n_ready_i - connect \muxid \pipe_start_muxid - connect \logical_op__insn_type \pipe_start_logical_op__insn_type - connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_start_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_start_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_start_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_start_logical_op__oe__oe_ok - connect \logical_op__invert_a \pipe_start_logical_op__invert_a - connect \logical_op__zero_a \pipe_start_logical_op__zero_a - connect \logical_op__input_carry \pipe_start_logical_op__input_carry - connect \logical_op__invert_out \pipe_start_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_start_logical_op__output_carry - connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit - connect \logical_op__is_signed \pipe_start_logical_op__is_signed - connect \logical_op__data_len \pipe_start_logical_op__data_len - connect \logical_op__insn \pipe_start_logical_op__insn - connect \ra \pipe_start_ra - connect \rb \pipe_start_rb - connect \xer_so \pipe_start_xer_so - connect \divisor_neg \pipe_start_divisor_neg - connect \dividend_neg \pipe_start_dividend_neg - connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 - connect \div_by_zero \pipe_start_div_by_zero - connect \dividend \pipe_start_dividend - connect \divisor_radicand \pipe_start_divisor_radicand - connect \operation \pipe_start_operation - connect \p_valid_i \pipe_start_p_valid_i - connect \p_ready_o \pipe_start_p_ready_o - connect \muxid$1 \pipe_start_muxid$2 - connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 - connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 - connect \logical_op__imm_data__imm$4 \pipe_start_logical_op__imm_data__imm$5 - connect \logical_op__imm_data__imm_ok$5 \pipe_start_logical_op__imm_data__imm_ok$6 - connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 - connect \logical_op__rc__rc_ok$7 \pipe_start_logical_op__rc__rc_ok$8 - connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 - connect \logical_op__oe__oe_ok$9 \pipe_start_logical_op__oe__oe_ok$10 - connect \logical_op__invert_a$10 \pipe_start_logical_op__invert_a$11 - connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 - connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 - connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 - connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 - connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 - connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 - connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 - connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 - connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 - connect \ra$20 \pipe_start_ra$21 - connect \rb$21 \pipe_start_rb$22 - connect \xer_so$22 \pipe_start_xer_so$23 + wire width 1 \core_calculate_stage_17_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_17_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_17_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_17_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_17_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_17_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_17_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_17_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_17_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_17_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_17_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_17_compare_rhs$99 + cell \core_calculate_stage_17 \core_calculate_stage_17 + connect \muxid \core_calculate_stage_17_muxid + connect \logical_op__insn_type \core_calculate_stage_17_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_17_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_17_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_17_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_17_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_17_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_17_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_17_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_17_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_17_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_17_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_17_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_17_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_17_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_17_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_17_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_17_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_17_logical_op__insn + connect \ra \core_calculate_stage_17_ra + connect \rb \core_calculate_stage_17_rb + connect \xer_so \core_calculate_stage_17_xer_so + connect \divisor_neg \core_calculate_stage_17_divisor_neg + connect \dividend_neg \core_calculate_stage_17_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_17_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_17_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_17_div_by_zero + connect \divisor_radicand \core_calculate_stage_17_divisor_radicand + connect \operation \core_calculate_stage_17_operation + connect \quotient_root \core_calculate_stage_17_quotient_root + connect \root_times_radicand \core_calculate_stage_17_root_times_radicand + connect \compare_lhs \core_calculate_stage_17_compare_lhs + connect \compare_rhs \core_calculate_stage_17_compare_rhs + connect \muxid$1 \core_calculate_stage_17_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_17_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_17_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_17_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_17_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_17_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_17_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_17_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_17_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_17_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_17_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_17_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_17_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_17_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_17_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_17_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_17_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_17_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_17_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_17_ra$86 + connect \rb$21 \core_calculate_stage_17_rb$87 + connect \xer_so$22 \core_calculate_stage_17_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_17_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_17_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_17_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_17_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_17_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_17_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_17_operation$95 + connect \quotient_root$30 \core_calculate_stage_17_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_17_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_17_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_17_compare_rhs$99 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_0_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_0_muxid + wire width 2 \core_calculate_stage_18_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -96340,7 +84825,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_0_logical_op__insn_type + wire width 7 \core_calculate_stage_18_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -96354,71 +84839,73 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_0_logical_op__fn_unit + wire width 11 \core_calculate_stage_18_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_0_logical_op__imm_data__imm + wire width 64 \core_calculate_stage_18_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_18_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc + wire width 1 \core_calculate_stage_18_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_18_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe + wire width 1 \core_calculate_stage_18_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_18_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_a + wire width 1 \core_calculate_stage_18_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__zero_a + wire width 1 \core_calculate_stage_18_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_0_logical_op__input_carry + wire width 2 \core_calculate_stage_18_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_out + wire width 1 \core_calculate_stage_18_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__write_cr0 + wire width 1 \core_calculate_stage_18_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__output_carry + wire width 1 \core_calculate_stage_18_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_32bit + wire width 1 \core_calculate_stage_18_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_signed + wire width 1 \core_calculate_stage_18_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_0_logical_op__data_len + wire width 4 \core_calculate_stage_18_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_0_logical_op__insn + wire width 32 \core_calculate_stage_18_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_ra + wire width 64 \core_calculate_stage_18_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_rb + wire width 64 \core_calculate_stage_18_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_0_xer_so + wire width 1 \core_calculate_stage_18_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_0_divisor_neg + wire width 1 \core_calculate_stage_18_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_0_dividend_neg + wire width 1 \core_calculate_stage_18_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_0_dive_abs_ov32 + wire width 1 \core_calculate_stage_18_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_0_dive_abs_ov64 + wire width 1 \core_calculate_stage_18_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_0_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \pipe_middle_0_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \pipe_middle_0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \pipe_middle_0_operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_0_n_ready_i + wire width 1 \core_calculate_stage_18_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_18_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_18_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_18_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_18_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_18_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_18_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_0_muxid$24 + wire width 2 \core_calculate_stage_18_muxid$100 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -96493,7 +84980,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_0_logical_op__insn_type$25 + wire width 7 \core_calculate_stage_18_logical_op__insn_type$101 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -96507,136 +84994,141 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_0_logical_op__fn_unit$26 + wire width 11 \core_calculate_stage_18_logical_op__fn_unit$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_0_logical_op__imm_data__imm$27 + wire width 64 \core_calculate_stage_18_logical_op__imm_data__imm$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok$28 + wire width 1 \core_calculate_stage_18_logical_op__imm_data__imm_ok$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc$29 + wire width 1 \core_calculate_stage_18_logical_op__rc__rc$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc_ok$30 + wire width 1 \core_calculate_stage_18_logical_op__rc__rc_ok$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe$31 + wire width 1 \core_calculate_stage_18_logical_op__oe__oe$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe_ok$32 + wire width 1 \core_calculate_stage_18_logical_op__oe__oe_ok$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_a$33 + wire width 1 \core_calculate_stage_18_logical_op__invert_in$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__zero_a$34 + wire width 1 \core_calculate_stage_18_logical_op__zero_a$110 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_0_logical_op__input_carry$35 + wire width 2 \core_calculate_stage_18_logical_op__input_carry$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_out$36 + wire width 1 \core_calculate_stage_18_logical_op__invert_out$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__write_cr0$37 + wire width 1 \core_calculate_stage_18_logical_op__write_cr0$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__output_carry$38 + wire width 1 \core_calculate_stage_18_logical_op__output_carry$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_32bit$39 + wire width 1 \core_calculate_stage_18_logical_op__is_32bit$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_signed$40 + wire width 1 \core_calculate_stage_18_logical_op__is_signed$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_0_logical_op__data_len$41 + wire width 4 \core_calculate_stage_18_logical_op__data_len$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_0_logical_op__insn$42 + wire width 32 \core_calculate_stage_18_logical_op__insn$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_ra$43 + wire width 64 \core_calculate_stage_18_ra$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_rb$44 + wire width 64 \core_calculate_stage_18_rb$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_0_xer_so$45 + wire width 1 \core_calculate_stage_18_xer_so$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_0_divisor_neg$46 + wire width 1 \core_calculate_stage_18_divisor_neg$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_0_dividend_neg$47 + wire width 1 \core_calculate_stage_18_dividend_neg$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_0_dive_abs_ov32$48 + wire width 1 \core_calculate_stage_18_dive_abs_ov32$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_0_dive_abs_ov64$49 + wire width 1 \core_calculate_stage_18_dive_abs_ov64$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_0_div_by_zero$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 \pipe_middle_0_quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 \pipe_middle_0_remainder - cell \pipe_middle_0 \pipe_middle_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_0_p_valid_i - connect \p_ready_o \pipe_middle_0_p_ready_o - connect \muxid \pipe_middle_0_muxid - connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_middle_0_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_middle_0_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_middle_0_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_middle_0_logical_op__oe__oe_ok - connect \logical_op__invert_a \pipe_middle_0_logical_op__invert_a - connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_0_logical_op__data_len - connect \logical_op__insn \pipe_middle_0_logical_op__insn - connect \ra \pipe_middle_0_ra - connect \rb \pipe_middle_0_rb - connect \xer_so \pipe_middle_0_xer_so - connect \divisor_neg \pipe_middle_0_divisor_neg - connect \dividend_neg \pipe_middle_0_dividend_neg - connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 - connect \div_by_zero \pipe_middle_0_div_by_zero - connect \dividend \pipe_middle_0_dividend - connect \divisor_radicand \pipe_middle_0_divisor_radicand - connect \operation \pipe_middle_0_operation - connect \n_valid_o \pipe_middle_0_n_valid_o - connect \n_ready_i \pipe_middle_0_n_ready_i - connect \muxid$1 \pipe_middle_0_muxid$24 - connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 - connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 - connect \logical_op__imm_data__imm$4 \pipe_middle_0_logical_op__imm_data__imm$27 - connect \logical_op__imm_data__imm_ok$5 \pipe_middle_0_logical_op__imm_data__imm_ok$28 - connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 - connect \logical_op__rc__rc_ok$7 \pipe_middle_0_logical_op__rc__rc_ok$30 - connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 - connect \logical_op__oe__oe_ok$9 \pipe_middle_0_logical_op__oe__oe_ok$32 - connect \logical_op__invert_a$10 \pipe_middle_0_logical_op__invert_a$33 - connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 - connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 - connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 - connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 - connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 - connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 - connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 - connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 - connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 - connect \ra$20 \pipe_middle_0_ra$43 - connect \rb$21 \pipe_middle_0_rb$44 - connect \xer_so$22 \pipe_middle_0_xer_so$45 - connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 - connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 - connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 - connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 - connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 - connect \quotient_root \pipe_middle_0_quotient_root - connect \remainder \pipe_middle_0_remainder + wire width 1 \core_calculate_stage_18_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_18_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_18_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_18_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_18_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_18_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_18_compare_rhs$132 + cell \core_calculate_stage_18 \core_calculate_stage_18 + connect \muxid \core_calculate_stage_18_muxid + connect \logical_op__insn_type \core_calculate_stage_18_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_18_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_18_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_18_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_18_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_18_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_18_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_18_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_18_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_18_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_18_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_18_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_18_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_18_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_18_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_18_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_18_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_18_logical_op__insn + connect \ra \core_calculate_stage_18_ra + connect \rb \core_calculate_stage_18_rb + connect \xer_so \core_calculate_stage_18_xer_so + connect \divisor_neg \core_calculate_stage_18_divisor_neg + connect \dividend_neg \core_calculate_stage_18_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_18_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_18_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_18_div_by_zero + connect \divisor_radicand \core_calculate_stage_18_divisor_radicand + connect \operation \core_calculate_stage_18_operation + connect \quotient_root \core_calculate_stage_18_quotient_root + connect \root_times_radicand \core_calculate_stage_18_root_times_radicand + connect \compare_lhs \core_calculate_stage_18_compare_lhs + connect \compare_rhs \core_calculate_stage_18_compare_rhs + connect \muxid$1 \core_calculate_stage_18_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_18_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_18_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_18_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_18_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_18_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_18_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_18_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_18_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_18_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_18_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_18_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_18_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_18_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_18_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_18_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_18_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_18_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_18_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_18_ra$119 + connect \rb$21 \core_calculate_stage_18_rb$120 + connect \xer_so$22 \core_calculate_stage_18_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_18_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_18_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_18_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_18_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_18_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_18_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_18_operation$128 + connect \quotient_root$30 \core_calculate_stage_18_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_18_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_18_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_18_compare_rhs$132 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_end_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_end_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_end_muxid + wire width 2 \core_calculate_stage_19_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -96711,7 +85203,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_end_logical_op__insn_type + wire width 7 \core_calculate_stage_19_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -96725,69 +85217,73 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_end_logical_op__fn_unit + wire width 11 \core_calculate_stage_19_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_end_logical_op__imm_data__imm + wire width 64 \core_calculate_stage_19_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_19_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__rc + wire width 1 \core_calculate_stage_19_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__rc_ok + wire width 1 \core_calculate_stage_19_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__oe + wire width 1 \core_calculate_stage_19_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__oe_ok + wire width 1 \core_calculate_stage_19_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__invert_a + wire width 1 \core_calculate_stage_19_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__zero_a + wire width 1 \core_calculate_stage_19_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_end_logical_op__input_carry + wire width 2 \core_calculate_stage_19_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__invert_out + wire width 1 \core_calculate_stage_19_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__write_cr0 + wire width 1 \core_calculate_stage_19_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__output_carry + wire width 1 \core_calculate_stage_19_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__is_32bit + wire width 1 \core_calculate_stage_19_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__is_signed + wire width 1 \core_calculate_stage_19_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_end_logical_op__data_len + wire width 4 \core_calculate_stage_19_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_end_logical_op__insn + wire width 32 \core_calculate_stage_19_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_end_ra + wire width 64 \core_calculate_stage_19_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_end_rb + wire width 64 \core_calculate_stage_19_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_end_xer_so + wire width 1 \core_calculate_stage_19_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_end_divisor_neg + wire width 1 \core_calculate_stage_19_divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_end_dividend_neg + wire width 1 \core_calculate_stage_19_dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_end_dive_abs_ov32 + wire width 1 \core_calculate_stage_19_dive_abs_ov32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_end_dive_abs_ov64 + wire width 1 \core_calculate_stage_19_dive_abs_ov64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_end_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 \pipe_end_quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 \pipe_end_remainder - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_end_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_end_n_ready_i + wire width 1 \core_calculate_stage_19_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_19_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_19_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_19_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_19_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_19_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_19_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_end_muxid$51 + wire width 2 \core_calculate_stage_19_muxid$133 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -96862,7 +85358,7 @@ module \alu_div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_end_logical_op__insn_type$52 + wire width 7 \core_calculate_stage_19_logical_op__insn_type$134 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -96876,1566 +85372,568 @@ module \alu_div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_end_logical_op__fn_unit$53 + wire width 11 \core_calculate_stage_19_logical_op__fn_unit$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_end_logical_op__imm_data__imm$54 + wire width 64 \core_calculate_stage_19_logical_op__imm_data__imm$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__imm_data__imm_ok$55 + wire width 1 \core_calculate_stage_19_logical_op__imm_data__imm_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__rc$56 + wire width 1 \core_calculate_stage_19_logical_op__rc__rc$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__rc_ok$57 + wire width 1 \core_calculate_stage_19_logical_op__rc__rc_ok$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__oe$58 + wire width 1 \core_calculate_stage_19_logical_op__oe__oe$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__oe_ok$59 + wire width 1 \core_calculate_stage_19_logical_op__oe__oe_ok$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__invert_a$60 + wire width 1 \core_calculate_stage_19_logical_op__invert_in$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__zero_a$61 + wire width 1 \core_calculate_stage_19_logical_op__zero_a$143 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_end_logical_op__input_carry$62 + wire width 2 \core_calculate_stage_19_logical_op__input_carry$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__invert_out$63 + wire width 1 \core_calculate_stage_19_logical_op__invert_out$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__write_cr0$64 + wire width 1 \core_calculate_stage_19_logical_op__write_cr0$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__output_carry$65 + wire width 1 \core_calculate_stage_19_logical_op__output_carry$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__is_32bit$66 + wire width 1 \core_calculate_stage_19_logical_op__is_32bit$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__is_signed$67 + wire width 1 \core_calculate_stage_19_logical_op__is_signed$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_end_logical_op__data_len$68 + wire width 4 \core_calculate_stage_19_logical_op__data_len$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_end_logical_op__insn$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_end_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe_end_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_end_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_xer_so$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_xer_so_ok - cell \pipe_end \pipe_end - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_end_p_valid_i - connect \p_ready_o \pipe_end_p_ready_o - connect \muxid \pipe_end_muxid - connect \logical_op__insn_type \pipe_end_logical_op__insn_type - connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit - connect \logical_op__imm_data__imm \pipe_end_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \pipe_end_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc - connect \logical_op__rc__rc_ok \pipe_end_logical_op__rc__rc_ok - connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe - connect \logical_op__oe__oe_ok \pipe_end_logical_op__oe__oe_ok - connect \logical_op__invert_a \pipe_end_logical_op__invert_a - connect \logical_op__zero_a \pipe_end_logical_op__zero_a - connect \logical_op__input_carry \pipe_end_logical_op__input_carry - connect \logical_op__invert_out \pipe_end_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_end_logical_op__output_carry - connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit - connect \logical_op__is_signed \pipe_end_logical_op__is_signed - connect \logical_op__data_len \pipe_end_logical_op__data_len - connect \logical_op__insn \pipe_end_logical_op__insn - connect \ra \pipe_end_ra - connect \rb \pipe_end_rb - connect \xer_so \pipe_end_xer_so - connect \divisor_neg \pipe_end_divisor_neg - connect \dividend_neg \pipe_end_dividend_neg - connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 - connect \div_by_zero \pipe_end_div_by_zero - connect \quotient_root \pipe_end_quotient_root - connect \remainder \pipe_end_remainder - connect \n_valid_o \pipe_end_n_valid_o - connect \n_ready_i \pipe_end_n_ready_i - connect \muxid$1 \pipe_end_muxid$51 - connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 - connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 - connect \logical_op__imm_data__imm$4 \pipe_end_logical_op__imm_data__imm$54 - connect \logical_op__imm_data__imm_ok$5 \pipe_end_logical_op__imm_data__imm_ok$55 - connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 - connect \logical_op__rc__rc_ok$7 \pipe_end_logical_op__rc__rc_ok$57 - connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 - connect \logical_op__oe__oe_ok$9 \pipe_end_logical_op__oe__oe_ok$59 - connect \logical_op__invert_a$10 \pipe_end_logical_op__invert_a$60 - connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 - connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 - connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 - connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 - connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 - connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 - connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 - connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 - connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 - connect \o \pipe_end_o - connect \o_ok \pipe_end_o_ok - connect \cr_a \pipe_end_cr_a - connect \cr_a_ok \pipe_end_cr_a_ok - connect \xer_ov \pipe_end_xer_ov - connect \xer_ov_ok \pipe_end_xer_ov_ok - connect \xer_so$20 \pipe_end_xer_so$70 - connect \xer_so_ok \pipe_end_xer_so_ok + wire width 32 \core_calculate_stage_19_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_19_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_19_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_19_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_19_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_19_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_19_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_19_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_19_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_19_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_19_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_19_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_19_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_19_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_19_compare_rhs$165 + cell \core_calculate_stage_19 \core_calculate_stage_19 + connect \muxid \core_calculate_stage_19_muxid + connect \logical_op__insn_type \core_calculate_stage_19_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_19_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_19_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_19_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_19_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_19_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_19_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_19_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_19_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_19_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_19_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_19_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_19_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_19_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_19_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_19_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_19_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_19_logical_op__insn + connect \ra \core_calculate_stage_19_ra + connect \rb \core_calculate_stage_19_rb + connect \xer_so \core_calculate_stage_19_xer_so + connect \divisor_neg \core_calculate_stage_19_divisor_neg + connect \dividend_neg \core_calculate_stage_19_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_19_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_19_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_19_div_by_zero + connect \divisor_radicand \core_calculate_stage_19_divisor_radicand + connect \operation \core_calculate_stage_19_operation + connect \quotient_root \core_calculate_stage_19_quotient_root + connect \root_times_radicand \core_calculate_stage_19_root_times_radicand + connect \compare_lhs \core_calculate_stage_19_compare_lhs + connect \compare_rhs \core_calculate_stage_19_compare_rhs + connect \muxid$1 \core_calculate_stage_19_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_19_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_19_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_19_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_19_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_19_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_19_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_19_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_19_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_19_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_19_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_19_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_19_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_19_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_19_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_19_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_19_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_19_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_19_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_19_ra$152 + connect \rb$21 \core_calculate_stage_19_rb$153 + connect \xer_so$22 \core_calculate_stage_19_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_19_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_19_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_19_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_19_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_19_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_19_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_19_operation$161 + connect \quotient_root$30 \core_calculate_stage_19_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_19_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_19_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_19_compare_rhs$165 end process $group_0 - assign \pipe_middle_0_p_valid_i 1'0 - assign \pipe_middle_0_p_valid_i \pipe_start_n_valid_o + assign \core_calculate_stage_16_muxid 2'00 + assign \core_calculate_stage_16_muxid \muxid sync init end process $group_1 - assign \pipe_start_n_ready_i 1'0 - assign \pipe_start_n_ready_i \pipe_middle_0_p_ready_o + assign \core_calculate_stage_16_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_16_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_16_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_16_logical_op__rc__rc 1'0 + assign \core_calculate_stage_16_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_16_logical_op__oe__oe 1'0 + assign \core_calculate_stage_16_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_16_logical_op__invert_in 1'0 + assign \core_calculate_stage_16_logical_op__zero_a 1'0 + assign \core_calculate_stage_16_logical_op__input_carry 2'00 + assign \core_calculate_stage_16_logical_op__invert_out 1'0 + assign \core_calculate_stage_16_logical_op__write_cr0 1'0 + assign \core_calculate_stage_16_logical_op__output_carry 1'0 + assign \core_calculate_stage_16_logical_op__is_32bit 1'0 + assign \core_calculate_stage_16_logical_op__is_signed 1'0 + assign \core_calculate_stage_16_logical_op__data_len 4'0000 + assign \core_calculate_stage_16_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_16_logical_op__insn \core_calculate_stage_16_logical_op__data_len \core_calculate_stage_16_logical_op__is_signed \core_calculate_stage_16_logical_op__is_32bit \core_calculate_stage_16_logical_op__output_carry \core_calculate_stage_16_logical_op__write_cr0 \core_calculate_stage_16_logical_op__invert_out \core_calculate_stage_16_logical_op__input_carry \core_calculate_stage_16_logical_op__zero_a \core_calculate_stage_16_logical_op__invert_in { \core_calculate_stage_16_logical_op__oe__oe_ok \core_calculate_stage_16_logical_op__oe__oe } { \core_calculate_stage_16_logical_op__rc__rc_ok \core_calculate_stage_16_logical_op__rc__rc } { \core_calculate_stage_16_logical_op__imm_data__imm_ok \core_calculate_stage_16_logical_op__imm_data__imm } \core_calculate_stage_16_logical_op__fn_unit \core_calculate_stage_16_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - process $group_2 - assign \pipe_middle_0_muxid 2'00 - assign \pipe_middle_0_muxid \pipe_start_muxid + process $group_19 + assign \core_calculate_stage_16_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_ra \ra sync init end - process $group_3 - assign \pipe_middle_0_logical_op__insn_type 7'0000000 - assign \pipe_middle_0_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_logical_op__imm_data__imm_ok 1'0 - assign \pipe_middle_0_logical_op__rc__rc 1'0 - assign \pipe_middle_0_logical_op__rc__rc_ok 1'0 - assign \pipe_middle_0_logical_op__oe__oe 1'0 - assign \pipe_middle_0_logical_op__oe__oe_ok 1'0 - assign \pipe_middle_0_logical_op__invert_a 1'0 - assign \pipe_middle_0_logical_op__zero_a 1'0 - assign \pipe_middle_0_logical_op__input_carry 2'00 - assign \pipe_middle_0_logical_op__invert_out 1'0 - assign \pipe_middle_0_logical_op__write_cr0 1'0 - assign \pipe_middle_0_logical_op__output_carry 1'0 - assign \pipe_middle_0_logical_op__is_32bit 1'0 - assign \pipe_middle_0_logical_op__is_signed 1'0 - assign \pipe_middle_0_logical_op__data_len 4'0000 - assign \pipe_middle_0_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_a { \pipe_middle_0_logical_op__oe__oe_ok \pipe_middle_0_logical_op__oe__oe } { \pipe_middle_0_logical_op__rc__rc_ok \pipe_middle_0_logical_op__rc__rc } { \pipe_middle_0_logical_op__imm_data__imm_ok \pipe_middle_0_logical_op__imm_data__imm } \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_a { \pipe_start_logical_op__oe__oe_ok \pipe_start_logical_op__oe__oe } { \pipe_start_logical_op__rc__rc_ok \pipe_start_logical_op__rc__rc } { \pipe_start_logical_op__imm_data__imm_ok \pipe_start_logical_op__imm_data__imm } \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } + process $group_20 + assign \core_calculate_stage_16_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_rb \rb sync init end process $group_21 - assign \pipe_middle_0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_ra \pipe_start_ra + assign \core_calculate_stage_16_xer_so 1'0 + assign \core_calculate_stage_16_xer_so \xer_so sync init end process $group_22 - assign \pipe_middle_0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_rb \pipe_start_rb + assign \core_calculate_stage_16_divisor_neg 1'0 + assign \core_calculate_stage_16_divisor_neg \divisor_neg sync init end process $group_23 - assign \pipe_middle_0_xer_so 1'0 - assign \pipe_middle_0_xer_so \pipe_start_xer_so + assign \core_calculate_stage_16_dividend_neg 1'0 + assign \core_calculate_stage_16_dividend_neg \dividend_neg sync init end process $group_24 - assign \pipe_middle_0_divisor_neg 1'0 - assign \pipe_middle_0_divisor_neg \pipe_start_divisor_neg + assign \core_calculate_stage_16_dive_abs_ov32 1'0 + assign \core_calculate_stage_16_dive_abs_ov32 \dive_abs_ov32 sync init end process $group_25 - assign \pipe_middle_0_dividend_neg 1'0 - assign \pipe_middle_0_dividend_neg \pipe_start_dividend_neg + assign \core_calculate_stage_16_dive_abs_ov64 1'0 + assign \core_calculate_stage_16_dive_abs_ov64 \dive_abs_ov64 sync init end process $group_26 - assign \pipe_middle_0_dive_abs_ov32 1'0 - assign \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 + assign \core_calculate_stage_16_div_by_zero 1'0 + assign \core_calculate_stage_16_div_by_zero \div_by_zero sync init end process $group_27 - assign \pipe_middle_0_dive_abs_ov64 1'0 - assign \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 + assign \core_calculate_stage_16_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_divisor_radicand \divisor_radicand sync init end process $group_28 - assign \pipe_middle_0_div_by_zero 1'0 - assign \pipe_middle_0_div_by_zero \pipe_start_div_by_zero + assign \core_calculate_stage_16_operation 2'00 + assign \core_calculate_stage_16_operation \operation sync init end process $group_29 - assign \pipe_middle_0_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_dividend \pipe_start_dividend + assign \core_calculate_stage_16_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_quotient_root \quotient_root sync init end process $group_30 - assign \pipe_middle_0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand + assign \core_calculate_stage_16_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_root_times_radicand \root_times_radicand sync init end process $group_31 - assign \pipe_middle_0_operation 2'00 - assign \pipe_middle_0_operation \pipe_start_operation + assign \core_calculate_stage_16_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_compare_lhs \compare_lhs sync init end process $group_32 - assign \pipe_end_p_valid_i 1'0 - assign \pipe_end_p_valid_i \pipe_middle_0_n_valid_o + assign \core_calculate_stage_16_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_compare_rhs \compare_rhs sync init end process $group_33 - assign \pipe_middle_0_n_ready_i 1'0 - assign \pipe_middle_0_n_ready_i \pipe_end_p_ready_o + assign \core_calculate_stage_17_muxid 2'00 + assign \core_calculate_stage_17_muxid \core_calculate_stage_16_muxid$34 sync init end process $group_34 - assign \pipe_end_muxid 2'00 - assign \pipe_end_muxid \pipe_middle_0_muxid$24 + assign \core_calculate_stage_17_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_17_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_17_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_17_logical_op__rc__rc 1'0 + assign \core_calculate_stage_17_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_17_logical_op__oe__oe 1'0 + assign \core_calculate_stage_17_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_17_logical_op__invert_in 1'0 + assign \core_calculate_stage_17_logical_op__zero_a 1'0 + assign \core_calculate_stage_17_logical_op__input_carry 2'00 + assign \core_calculate_stage_17_logical_op__invert_out 1'0 + assign \core_calculate_stage_17_logical_op__write_cr0 1'0 + assign \core_calculate_stage_17_logical_op__output_carry 1'0 + assign \core_calculate_stage_17_logical_op__is_32bit 1'0 + assign \core_calculate_stage_17_logical_op__is_signed 1'0 + assign \core_calculate_stage_17_logical_op__data_len 4'0000 + assign \core_calculate_stage_17_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_17_logical_op__insn \core_calculate_stage_17_logical_op__data_len \core_calculate_stage_17_logical_op__is_signed \core_calculate_stage_17_logical_op__is_32bit \core_calculate_stage_17_logical_op__output_carry \core_calculate_stage_17_logical_op__write_cr0 \core_calculate_stage_17_logical_op__invert_out \core_calculate_stage_17_logical_op__input_carry \core_calculate_stage_17_logical_op__zero_a \core_calculate_stage_17_logical_op__invert_in { \core_calculate_stage_17_logical_op__oe__oe_ok \core_calculate_stage_17_logical_op__oe__oe } { \core_calculate_stage_17_logical_op__rc__rc_ok \core_calculate_stage_17_logical_op__rc__rc } { \core_calculate_stage_17_logical_op__imm_data__imm_ok \core_calculate_stage_17_logical_op__imm_data__imm } \core_calculate_stage_17_logical_op__fn_unit \core_calculate_stage_17_logical_op__insn_type } { \core_calculate_stage_16_logical_op__insn$52 \core_calculate_stage_16_logical_op__data_len$51 \core_calculate_stage_16_logical_op__is_signed$50 \core_calculate_stage_16_logical_op__is_32bit$49 \core_calculate_stage_16_logical_op__output_carry$48 \core_calculate_stage_16_logical_op__write_cr0$47 \core_calculate_stage_16_logical_op__invert_out$46 \core_calculate_stage_16_logical_op__input_carry$45 \core_calculate_stage_16_logical_op__zero_a$44 \core_calculate_stage_16_logical_op__invert_in$43 { \core_calculate_stage_16_logical_op__oe__oe_ok$42 \core_calculate_stage_16_logical_op__oe__oe$41 } { \core_calculate_stage_16_logical_op__rc__rc_ok$40 \core_calculate_stage_16_logical_op__rc__rc$39 } { \core_calculate_stage_16_logical_op__imm_data__imm_ok$38 \core_calculate_stage_16_logical_op__imm_data__imm$37 } \core_calculate_stage_16_logical_op__fn_unit$36 \core_calculate_stage_16_logical_op__insn_type$35 } sync init end - process $group_35 - assign \pipe_end_logical_op__insn_type 7'0000000 - assign \pipe_end_logical_op__fn_unit 11'00000000000 - assign \pipe_end_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_logical_op__imm_data__imm_ok 1'0 - assign \pipe_end_logical_op__rc__rc 1'0 - assign \pipe_end_logical_op__rc__rc_ok 1'0 - assign \pipe_end_logical_op__oe__oe 1'0 - assign \pipe_end_logical_op__oe__oe_ok 1'0 - assign \pipe_end_logical_op__invert_a 1'0 - assign \pipe_end_logical_op__zero_a 1'0 - assign \pipe_end_logical_op__input_carry 2'00 - assign \pipe_end_logical_op__invert_out 1'0 - assign \pipe_end_logical_op__write_cr0 1'0 - assign \pipe_end_logical_op__output_carry 1'0 - assign \pipe_end_logical_op__is_32bit 1'0 - assign \pipe_end_logical_op__is_signed 1'0 - assign \pipe_end_logical_op__data_len 4'0000 - assign \pipe_end_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_a { \pipe_end_logical_op__oe__oe_ok \pipe_end_logical_op__oe__oe } { \pipe_end_logical_op__rc__rc_ok \pipe_end_logical_op__rc__rc } { \pipe_end_logical_op__imm_data__imm_ok \pipe_end_logical_op__imm_data__imm } \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_a$33 { \pipe_middle_0_logical_op__oe__oe_ok$32 \pipe_middle_0_logical_op__oe__oe$31 } { \pipe_middle_0_logical_op__rc__rc_ok$30 \pipe_middle_0_logical_op__rc__rc$29 } { \pipe_middle_0_logical_op__imm_data__imm_ok$28 \pipe_middle_0_logical_op__imm_data__imm$27 } \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } + process $group_52 + assign \core_calculate_stage_17_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_ra \core_calculate_stage_16_ra$53 sync init end process $group_53 - assign \pipe_end_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_ra \pipe_middle_0_ra$43 + assign \core_calculate_stage_17_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_rb \core_calculate_stage_16_rb$54 sync init end process $group_54 - assign \pipe_end_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_rb \pipe_middle_0_rb$44 + assign \core_calculate_stage_17_xer_so 1'0 + assign \core_calculate_stage_17_xer_so \core_calculate_stage_16_xer_so$55 sync init end process $group_55 - assign \pipe_end_xer_so 1'0 - assign \pipe_end_xer_so \pipe_middle_0_xer_so$45 + assign \core_calculate_stage_17_divisor_neg 1'0 + assign \core_calculate_stage_17_divisor_neg \core_calculate_stage_16_divisor_neg$56 sync init end process $group_56 - assign \pipe_end_divisor_neg 1'0 - assign \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 + assign \core_calculate_stage_17_dividend_neg 1'0 + assign \core_calculate_stage_17_dividend_neg \core_calculate_stage_16_dividend_neg$57 sync init end process $group_57 - assign \pipe_end_dividend_neg 1'0 - assign \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 + assign \core_calculate_stage_17_dive_abs_ov32 1'0 + assign \core_calculate_stage_17_dive_abs_ov32 \core_calculate_stage_16_dive_abs_ov32$58 sync init end process $group_58 - assign \pipe_end_dive_abs_ov32 1'0 - assign \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 + assign \core_calculate_stage_17_dive_abs_ov64 1'0 + assign \core_calculate_stage_17_dive_abs_ov64 \core_calculate_stage_16_dive_abs_ov64$59 sync init end process $group_59 - assign \pipe_end_dive_abs_ov64 1'0 - assign \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 + assign \core_calculate_stage_17_div_by_zero 1'0 + assign \core_calculate_stage_17_div_by_zero \core_calculate_stage_16_div_by_zero$60 sync init end process $group_60 - assign \pipe_end_div_by_zero 1'0 - assign \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 + assign \core_calculate_stage_17_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_divisor_radicand \core_calculate_stage_16_divisor_radicand$61 sync init end process $group_61 - assign \pipe_end_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_quotient_root \pipe_middle_0_quotient_root + assign \core_calculate_stage_17_operation 2'00 + assign \core_calculate_stage_17_operation \core_calculate_stage_16_operation$62 sync init end process $group_62 - assign \pipe_end_remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_remainder \pipe_middle_0_remainder + assign \core_calculate_stage_17_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_quotient_root \core_calculate_stage_16_quotient_root$63 sync init end process $group_63 - assign \pipe_start_p_valid_i 1'0 - assign \pipe_start_p_valid_i \p_valid_i + assign \core_calculate_stage_17_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_root_times_radicand \core_calculate_stage_16_root_times_radicand$64 sync init end process $group_64 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_start_p_ready_o + assign \core_calculate_stage_17_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_compare_lhs \core_calculate_stage_16_compare_lhs$65 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid process $group_65 - assign \pipe_start_muxid$2 2'00 - assign \pipe_start_muxid$2 \muxid + assign \core_calculate_stage_17_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_compare_rhs \core_calculate_stage_16_compare_rhs$66 sync init end process $group_66 - assign \pipe_start_logical_op__insn_type$3 7'0000000 - assign \pipe_start_logical_op__fn_unit$4 11'00000000000 - assign \pipe_start_logical_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_start_logical_op__imm_data__imm_ok$6 1'0 - assign \pipe_start_logical_op__rc__rc$7 1'0 - assign \pipe_start_logical_op__rc__rc_ok$8 1'0 - assign \pipe_start_logical_op__oe__oe$9 1'0 - assign \pipe_start_logical_op__oe__oe_ok$10 1'0 - assign \pipe_start_logical_op__invert_a$11 1'0 - assign \pipe_start_logical_op__zero_a$12 1'0 - assign \pipe_start_logical_op__input_carry$13 2'00 - assign \pipe_start_logical_op__invert_out$14 1'0 - assign \pipe_start_logical_op__write_cr0$15 1'0 - assign \pipe_start_logical_op__output_carry$16 1'0 - assign \pipe_start_logical_op__is_32bit$17 1'0 - assign \pipe_start_logical_op__is_signed$18 1'0 - assign \pipe_start_logical_op__data_len$19 4'0000 - assign \pipe_start_logical_op__insn$20 32'00000000000000000000000000000000 - assign { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_a$11 { \pipe_start_logical_op__oe__oe_ok$10 \pipe_start_logical_op__oe__oe$9 } { \pipe_start_logical_op__rc__rc_ok$8 \pipe_start_logical_op__rc__rc$7 } { \pipe_start_logical_op__imm_data__imm_ok$6 \pipe_start_logical_op__imm_data__imm$5 } \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + assign \core_calculate_stage_18_muxid 2'00 + assign \core_calculate_stage_18_muxid \core_calculate_stage_17_muxid$67 sync init end - process $group_84 - assign \pipe_start_ra$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_start_ra$21 \ra + process $group_67 + assign \core_calculate_stage_18_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_18_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_18_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_18_logical_op__rc__rc 1'0 + assign \core_calculate_stage_18_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_18_logical_op__oe__oe 1'0 + assign \core_calculate_stage_18_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_18_logical_op__invert_in 1'0 + assign \core_calculate_stage_18_logical_op__zero_a 1'0 + assign \core_calculate_stage_18_logical_op__input_carry 2'00 + assign \core_calculate_stage_18_logical_op__invert_out 1'0 + assign \core_calculate_stage_18_logical_op__write_cr0 1'0 + assign \core_calculate_stage_18_logical_op__output_carry 1'0 + assign \core_calculate_stage_18_logical_op__is_32bit 1'0 + assign \core_calculate_stage_18_logical_op__is_signed 1'0 + assign \core_calculate_stage_18_logical_op__data_len 4'0000 + assign \core_calculate_stage_18_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_18_logical_op__insn \core_calculate_stage_18_logical_op__data_len \core_calculate_stage_18_logical_op__is_signed \core_calculate_stage_18_logical_op__is_32bit \core_calculate_stage_18_logical_op__output_carry \core_calculate_stage_18_logical_op__write_cr0 \core_calculate_stage_18_logical_op__invert_out \core_calculate_stage_18_logical_op__input_carry \core_calculate_stage_18_logical_op__zero_a \core_calculate_stage_18_logical_op__invert_in { \core_calculate_stage_18_logical_op__oe__oe_ok \core_calculate_stage_18_logical_op__oe__oe } { \core_calculate_stage_18_logical_op__rc__rc_ok \core_calculate_stage_18_logical_op__rc__rc } { \core_calculate_stage_18_logical_op__imm_data__imm_ok \core_calculate_stage_18_logical_op__imm_data__imm } \core_calculate_stage_18_logical_op__fn_unit \core_calculate_stage_18_logical_op__insn_type } { \core_calculate_stage_17_logical_op__insn$85 \core_calculate_stage_17_logical_op__data_len$84 \core_calculate_stage_17_logical_op__is_signed$83 \core_calculate_stage_17_logical_op__is_32bit$82 \core_calculate_stage_17_logical_op__output_carry$81 \core_calculate_stage_17_logical_op__write_cr0$80 \core_calculate_stage_17_logical_op__invert_out$79 \core_calculate_stage_17_logical_op__input_carry$78 \core_calculate_stage_17_logical_op__zero_a$77 \core_calculate_stage_17_logical_op__invert_in$76 { \core_calculate_stage_17_logical_op__oe__oe_ok$75 \core_calculate_stage_17_logical_op__oe__oe$74 } { \core_calculate_stage_17_logical_op__rc__rc_ok$73 \core_calculate_stage_17_logical_op__rc__rc$72 } { \core_calculate_stage_17_logical_op__imm_data__imm_ok$71 \core_calculate_stage_17_logical_op__imm_data__imm$70 } \core_calculate_stage_17_logical_op__fn_unit$69 \core_calculate_stage_17_logical_op__insn_type$68 } sync init end process $group_85 - assign \pipe_start_rb$22 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_start_rb$22 \rb + assign \core_calculate_stage_18_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_ra \core_calculate_stage_17_ra$86 sync init end process $group_86 - assign \pipe_start_xer_so$23 1'0 - assign \pipe_start_xer_so$23 \xer_so$1 + assign \core_calculate_stage_18_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_rb \core_calculate_stage_17_rb$87 sync init end process $group_87 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_end_n_valid_o + assign \core_calculate_stage_18_xer_so 1'0 + assign \core_calculate_stage_18_xer_so \core_calculate_stage_17_xer_so$88 sync init end process $group_88 - assign \pipe_end_n_ready_i 1'0 - assign \pipe_end_n_ready_i \n_ready_i + assign \core_calculate_stage_18_divisor_neg 1'0 + assign \core_calculate_stage_18_divisor_neg \core_calculate_stage_17_divisor_neg$89 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$71 process $group_89 - assign \muxid$71 2'00 - assign \muxid$71 \pipe_end_muxid$51 + assign \core_calculate_stage_18_dividend_neg 1'0 + assign \core_calculate_stage_18_dividend_neg \core_calculate_stage_17_dividend_neg$90 sync init end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$72 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__imm$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__imm_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc_ok$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe_ok$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_a$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$81 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$89 process $group_90 - assign \logical_op__insn_type$72 7'0000000 - assign \logical_op__fn_unit$73 11'00000000000 - assign \logical_op__imm_data__imm$74 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__imm_ok$75 1'0 - assign \logical_op__rc__rc$76 1'0 - assign \logical_op__rc__rc_ok$77 1'0 - assign \logical_op__oe__oe$78 1'0 - assign \logical_op__oe__oe_ok$79 1'0 - assign \logical_op__invert_a$80 1'0 - assign \logical_op__zero_a$81 1'0 - assign \logical_op__input_carry$82 2'00 - assign \logical_op__invert_out$83 1'0 - assign \logical_op__write_cr0$84 1'0 - assign \logical_op__output_carry$85 1'0 - assign \logical_op__is_32bit$86 1'0 - assign \logical_op__is_signed$87 1'0 - assign \logical_op__data_len$88 4'0000 - assign \logical_op__insn$89 32'00000000000000000000000000000000 - assign { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_a$80 { \logical_op__oe__oe_ok$79 \logical_op__oe__oe$78 } { \logical_op__rc__rc_ok$77 \logical_op__rc__rc$76 } { \logical_op__imm_data__imm_ok$75 \logical_op__imm_data__imm$74 } \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_a$60 { \pipe_end_logical_op__oe__oe_ok$59 \pipe_end_logical_op__oe__oe$58 } { \pipe_end_logical_op__rc__rc_ok$57 \pipe_end_logical_op__rc__rc$56 } { \pipe_end_logical_op__imm_data__imm_ok$55 \pipe_end_logical_op__imm_data__imm$54 } \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } - sync init - end - process $group_108 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } - sync init - end - process $group_110 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } + assign \core_calculate_stage_18_dive_abs_ov32 1'0 + assign \core_calculate_stage_18_dive_abs_ov32 \core_calculate_stage_17_dive_abs_ov32$91 sync init end - process $group_112 - assign \xer_ov 2'00 - assign \xer_ov_ok 1'0 - assign { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } - sync init - end - process $group_114 - assign \xer_so 1'0 - assign \xer_so_ok 1'0 - assign { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } + process $group_91 + assign \core_calculate_stage_18_dive_abs_ov64 1'0 + assign \core_calculate_stage_18_dive_abs_ov64 \core_calculate_stage_17_dive_abs_ov64$92 sync init end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l" -module \src_l$80 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end + process $group_92 + assign \core_calculate_stage_18_div_by_zero 1'0 + assign \core_calculate_stage_18_div_by_zero \core_calculate_stage_17_div_by_zero$93 sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_src - connect \Y $11 end - process $group_1 - assign \q_src 3'000 - assign \q_src $11 + process $group_93 + assign \core_calculate_stage_18_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_divisor_radicand \core_calculate_stage_17_divisor_radicand$94 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 3'000 - assign \qn_src $13 + process $group_94 + assign \core_calculate_stage_18_operation 2'00 + assign \core_calculate_stage_18_operation \core_calculate_stage_17_operation$95 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 3'000 - assign \qlq_src $15 + process $group_95 + assign \core_calculate_stage_18_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_quotient_root \core_calculate_stage_17_quotient_root$96 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l" -module \opc_l$81 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_96 + assign \core_calculate_stage_18_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_root_times_radicand \core_calculate_stage_17_root_times_radicand$97 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 + process $group_97 + assign \core_calculate_stage_18_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_compare_lhs \core_calculate_stage_17_compare_lhs$98 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 + process $group_98 + assign \core_calculate_stage_18_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_compare_rhs \core_calculate_stage_17_compare_rhs$99 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 + process $group_99 + assign \core_calculate_stage_19_muxid 2'00 + assign \core_calculate_stage_19_muxid \core_calculate_stage_18_muxid$100 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l" -module \req_l$82 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 4'0000 - end + process $group_100 + assign \core_calculate_stage_19_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_19_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_19_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_19_logical_op__rc__rc 1'0 + assign \core_calculate_stage_19_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_19_logical_op__oe__oe 1'0 + assign \core_calculate_stage_19_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_19_logical_op__invert_in 1'0 + assign \core_calculate_stage_19_logical_op__zero_a 1'0 + assign \core_calculate_stage_19_logical_op__input_carry 2'00 + assign \core_calculate_stage_19_logical_op__invert_out 1'0 + assign \core_calculate_stage_19_logical_op__write_cr0 1'0 + assign \core_calculate_stage_19_logical_op__output_carry 1'0 + assign \core_calculate_stage_19_logical_op__is_32bit 1'0 + assign \core_calculate_stage_19_logical_op__is_signed 1'0 + assign \core_calculate_stage_19_logical_op__data_len 4'0000 + assign \core_calculate_stage_19_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_19_logical_op__insn \core_calculate_stage_19_logical_op__data_len \core_calculate_stage_19_logical_op__is_signed \core_calculate_stage_19_logical_op__is_32bit \core_calculate_stage_19_logical_op__output_carry \core_calculate_stage_19_logical_op__write_cr0 \core_calculate_stage_19_logical_op__invert_out \core_calculate_stage_19_logical_op__input_carry \core_calculate_stage_19_logical_op__zero_a \core_calculate_stage_19_logical_op__invert_in { \core_calculate_stage_19_logical_op__oe__oe_ok \core_calculate_stage_19_logical_op__oe__oe } { \core_calculate_stage_19_logical_op__rc__rc_ok \core_calculate_stage_19_logical_op__rc__rc } { \core_calculate_stage_19_logical_op__imm_data__imm_ok \core_calculate_stage_19_logical_op__imm_data__imm } \core_calculate_stage_19_logical_op__fn_unit \core_calculate_stage_19_logical_op__insn_type } { \core_calculate_stage_18_logical_op__insn$118 \core_calculate_stage_18_logical_op__data_len$117 \core_calculate_stage_18_logical_op__is_signed$116 \core_calculate_stage_18_logical_op__is_32bit$115 \core_calculate_stage_18_logical_op__output_carry$114 \core_calculate_stage_18_logical_op__write_cr0$113 \core_calculate_stage_18_logical_op__invert_out$112 \core_calculate_stage_18_logical_op__input_carry$111 \core_calculate_stage_18_logical_op__zero_a$110 \core_calculate_stage_18_logical_op__invert_in$109 { \core_calculate_stage_18_logical_op__oe__oe_ok$108 \core_calculate_stage_18_logical_op__oe__oe$107 } { \core_calculate_stage_18_logical_op__rc__rc_ok$106 \core_calculate_stage_18_logical_op__rc__rc$105 } { \core_calculate_stage_18_logical_op__imm_data__imm_ok$104 \core_calculate_stage_18_logical_op__imm_data__imm$103 } \core_calculate_stage_18_logical_op__fn_unit$102 \core_calculate_stage_18_logical_op__insn_type$101 } sync init - update \q_int 4'0000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $9 - connect \B \s_req - connect \Y $11 end - process $group_1 - assign \q_req 4'0000 - assign \q_req $11 + process $group_118 + assign \core_calculate_stage_19_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_ra \core_calculate_stage_18_ra$119 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 4'0000 - assign \qn_req $13 + process $group_119 + assign \core_calculate_stage_19_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_rb \core_calculate_stage_18_rb$120 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 4'0000 - assign \qlq_req $15 + process $group_120 + assign \core_calculate_stage_19_xer_so 1'0 + assign \core_calculate_stage_19_xer_so \core_calculate_stage_18_xer_so$121 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l" -module \rst_l$83 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_121 + assign \core_calculate_stage_19_divisor_neg 1'0 + assign \core_calculate_stage_19_divisor_neg \core_calculate_stage_18_divisor_neg$122 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 + process $group_122 + assign \core_calculate_stage_19_dividend_neg 1'0 + assign \core_calculate_stage_19_dividend_neg \core_calculate_stage_18_dividend_neg$123 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 + process $group_123 + assign \core_calculate_stage_19_dive_abs_ov32 1'0 + assign \core_calculate_stage_19_dive_abs_ov32 \core_calculate_stage_18_dive_abs_ov32$124 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 + process $group_124 + assign \core_calculate_stage_19_dive_abs_ov64 1'0 + assign \core_calculate_stage_19_dive_abs_ov64 \core_calculate_stage_18_dive_abs_ov64$125 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l" -module \rok_l$84 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_125 + assign \core_calculate_stage_19_div_by_zero 1'0 + assign \core_calculate_stage_19_div_by_zero \core_calculate_stage_18_div_by_zero$126 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 + process $group_126 + assign \core_calculate_stage_19_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_divisor_radicand \core_calculate_stage_18_divisor_radicand$127 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 + process $group_127 + assign \core_calculate_stage_19_operation 2'00 + assign \core_calculate_stage_19_operation \core_calculate_stage_18_operation$128 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 + process $group_128 + assign \core_calculate_stage_19_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_quotient_root \core_calculate_stage_18_quotient_root$129 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l" -module \alui_l$85 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_129 + assign \core_calculate_stage_19_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_root_times_radicand \core_calculate_stage_18_root_times_radicand$130 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 + process $group_130 + assign \core_calculate_stage_19_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_compare_lhs \core_calculate_stage_18_compare_lhs$131 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 - end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 + process $group_131 + assign \core_calculate_stage_19_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_compare_rhs \core_calculate_stage_18_compare_rhs$132 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l" -module \alu_l$86 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 - end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_19_muxid$133 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0" -module \div0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -98510,7 +86008,7 @@ module \div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_div0__insn_type + wire width 7 \logical_op__insn_type$170 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -98524,93 +86022,1171 @@ module \div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_div0__fn_unit + wire width 11 \logical_op__fn_unit$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_div0__imm_data__imm + wire width 64 \logical_op__imm_data__imm$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_div0__imm_data__imm_ok + wire width 1 \logical_op__imm_data__imm_ok$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \oper_i_alu_div0__rc__rc + wire width 1 \logical_op__rc__rc$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_div0__rc__rc_ok + wire width 1 \logical_op__rc__rc_ok$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \oper_i_alu_div0__oe__oe + wire width 1 \logical_op__oe__oe$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_div0__oe__oe_ok + wire width 1 \logical_op__oe__oe_ok$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \oper_i_alu_div0__invert_a + wire width 1 \logical_op__invert_in$178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \oper_i_alu_div0__zero_a + wire width 1 \logical_op__zero_a$179 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \oper_i_alu_div0__input_carry + wire width 2 \logical_op__input_carry$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_alu_div0__invert_out + wire width 1 \logical_op__invert_out$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \oper_i_alu_div0__write_cr0 + wire width 1 \logical_op__write_cr0$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_alu_div0__output_carry + wire width 1 \logical_op__output_carry$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \oper_i_alu_div0__is_32bit + wire width 1 \logical_op__is_32bit$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \oper_i_alu_div0__is_signed + wire width 1 \logical_op__is_signed$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \oper_i_alu_div0__data_len + wire width 4 \logical_op__data_len$186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \oper_i_alu_div0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 19 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 20 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 input 21 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 22 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 23 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 24 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 25 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 1 input 26 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 27 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 28 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 29 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 30 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 31 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 32 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 33 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 34 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 35 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 output 36 \dest4_o - attribute \src "simple/issuer.py:89" - wire width 1 input 37 \coresync_rst + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_19_logical_op__insn$151 \core_calculate_stage_19_logical_op__data_len$150 \core_calculate_stage_19_logical_op__is_signed$149 \core_calculate_stage_19_logical_op__is_32bit$148 \core_calculate_stage_19_logical_op__output_carry$147 \core_calculate_stage_19_logical_op__write_cr0$146 \core_calculate_stage_19_logical_op__invert_out$145 \core_calculate_stage_19_logical_op__input_carry$144 \core_calculate_stage_19_logical_op__zero_a$143 \core_calculate_stage_19_logical_op__invert_in$142 { \core_calculate_stage_19_logical_op__oe__oe_ok$141 \core_calculate_stage_19_logical_op__oe__oe$140 } { \core_calculate_stage_19_logical_op__rc__rc_ok$139 \core_calculate_stage_19_logical_op__rc__rc$138 } { \core_calculate_stage_19_logical_op__imm_data__imm_ok$137 \core_calculate_stage_19_logical_op__imm_data__imm$136 } \core_calculate_stage_19_logical_op__fn_unit$135 \core_calculate_stage_19_logical_op__insn_type$134 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_19_ra$152 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_19_rb$153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_19_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_19_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_19_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_19_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_19_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_19_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_19_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_19_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_19_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_19_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_19_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_19_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next + end + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end + sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next + end + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.p" +module \p$164 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.n" +module \n$165 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_div0_n_valid_o + wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_div0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_div0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_div0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_div0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \alu_div0_xer_so + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_20.core.trial0" +module \trial0$167 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101011 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_20.core.trial1" +module \trial1$168 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101011 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_20.core.pe" +module \pe$169 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_20.core" +module \core$166 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$167 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$168 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$169 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'101011 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_20" +module \core_calculate_stage_20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -98685,7 +87261,7 @@ module \div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_div0_logical_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -98699,839 +87275,991 @@ module \div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_div0_logical_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_div0_logical_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__zero_a + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_div0_logical_op__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__invert_out + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__write_cr0 + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__output_carry + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_div0_logical_op__data_len + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_div0_logical_op__insn + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_div0_ra + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_div0_rb + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \alu_div0_xer_so$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_div0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_div0_p_ready_o - cell \alu_div0 \alu_div0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \cr_a_ok \cr_a_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_div0_n_valid_o - connect \n_ready_i \alu_div0_n_ready_i - connect \o \alu_div0_o - connect \cr_a \alu_div0_cr_a - connect \xer_ov \alu_div0_xer_ov - connect \xer_so \alu_div0_xer_so - connect \logical_op__insn_type \alu_div0_logical_op__insn_type - connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit - connect \logical_op__imm_data__imm \alu_div0_logical_op__imm_data__imm - connect \logical_op__imm_data__imm_ok \alu_div0_logical_op__imm_data__imm_ok - connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc - connect \logical_op__rc__rc_ok \alu_div0_logical_op__rc__rc_ok - connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe - connect \logical_op__oe__oe_ok \alu_div0_logical_op__oe__oe_ok - connect \logical_op__invert_a \alu_div0_logical_op__invert_a - connect \logical_op__zero_a \alu_div0_logical_op__zero_a - connect \logical_op__input_carry \alu_div0_logical_op__input_carry - connect \logical_op__invert_out \alu_div0_logical_op__invert_out - connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 - connect \logical_op__output_carry \alu_div0_logical_op__output_carry - connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit - connect \logical_op__is_signed \alu_div0_logical_op__is_signed - connect \logical_op__data_len \alu_div0_logical_op__data_len - connect \logical_op__insn \alu_div0_logical_op__insn - connect \ra \alu_div0_ra - connect \rb \alu_div0_rb - connect \xer_so$1 \alu_div0_xer_so$1 - connect \p_valid_i \alu_div0_p_valid_i - connect \p_ready_o \alu_div0_p_ready_o + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$166 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - cell \src_l$80 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$81 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \req_l_r_req$next - cell \req_l$82 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - cell \rst_l$83 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$84 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$85 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$86 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - cell $and $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $2 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $5 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $5 - connect \B \cu_rd__go_i - connect \Y $7 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $reduce_and $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $7 - connect \Y $4 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $2 - connect \B $4 - connect \Y $10 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $10 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $12 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $and $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $12 - connect \Y $14 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_2 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse $14 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_done - process $group_3 - assign \alu_done 1'0 - assign \alu_done \alu_div0_n_valid_o + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly$next - process $group_4 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $and $19 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_21.core.trial0" +module \trial0$171 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $16 - connect \Y $18 - end - process $group_5 - assign \alu_pulse 1'0 - assign \alu_pulse $18 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" - wire width 4 \alu_pulsem - process $group_6 - assign \alu_pulsem 4'0000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - sync init + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 4 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 4 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 4 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - cell $and $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $20 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_7 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $20 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \prev_wr_go$next 4'0000 + assign \dr_times_trial_bits $3 end sync init - update \prev_wr_go 4'0000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 4 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wrmask_o - connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 4 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__rel_o - connect \B $24 - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $reduce_bool $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $26 - connect \Y $23 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $23 - connect \Y $22 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101010 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $22 - connect \Y $30 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_8 - assign \cu_done_o 1'0 - assign \cu_done_o $30 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $35 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_21.core.trial1" +module \trial1$172 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $34 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $or $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \B $34 - connect \Y $36 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_9 - assign \wr_any 1'0 - assign \wr_any $36 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $not $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_n_ready_i - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $and $41 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $38 - connect \Y $40 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 4 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $43 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $42 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101010 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $eq $45 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $42 - connect \B 1'0 - connect \Y $44 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $40 - connect \B $44 - connect \Y $46 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $eq $49 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_21.core.pe" +module \pe$173 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o + connect \A \i connect \B 1'0 - connect \Y $48 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $51 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_21.core" +module \core$170 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$171 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$172 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$173 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A $48 - connect \B \alu_div0_n_ready_i - connect \Y $50 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $53 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $50 - connect \B \alu_div0_n_valid_o - connect \Y $52 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $55 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $52 - connect \B \cu_busy_o - connect \Y $54 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_10 - assign \req_done 1'0 - assign \req_done $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - switch { $54 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \req_done 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $57 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $56 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_11 - assign \reset 1'0 - assign \reset $56 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - wire width 1 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - cell $or $59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $58 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_12 - assign \rst_r 1'0 - assign \rst_r $58 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 4 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - wire width 4 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - cell $or $61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $60 - end - process $group_13 - assign \reset_w 4'0000 - assign \reset_w $60 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - wire width 3 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - cell $or $63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $62 - end - process $group_14 - assign \reset_r 3'000 - assign \reset_r $62 - sync init - end - process $group_15 - assign \rok_l_s_rdok 1'0 - assign \rok_l_s_rdok \cu_issue_i - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - cell $and $65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_n_valid_o - connect \B \cu_busy_o - connect \Y $64 - end - process $group_16 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $64 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_17 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \all_rd - sync init - end - process $group_18 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \rst_r - sync init - end - process $group_19 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end process $group_20 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_21 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 3'000 - end - sync init - update \src_l_s_src 3'000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_22 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 3'111 - end + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init - update \src_l_r_src 3'111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - wire width 4 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - cell $and $67 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $66 - end - process $group_23 - assign \req_l_s_req 4'0000 - assign \req_l_s_req $66 - sync init + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'101010 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - wire width 4 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - cell $or $69 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $68 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_24 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $68 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 4'1111 - end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init - update \req_l_r_req 4'1111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_21" +module \core_calculate_stage_21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -99606,7 +88334,7 @@ module \div0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -99620,1186 +88348,989 @@ module \div0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__zero_a + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__invert_out + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__write_cr0 + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__output_carry + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__input_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__input_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_out - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_out$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__data_len$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 132 $70 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $71 - parameter \WIDTH 132 - connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry \oper_l__write_cr0 \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } - connect \B { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_a { \oper_i_alu_div0__oe__oe_ok \oper_i_alu_div0__oe__oe } { \oper_i_alu_div0__rc__rc_ok \oper_i_alu_div0__rc__rc } { \oper_i_alu_div0__imm_data__imm_ok \oper_i_alu_div0__imm_data__imm } \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } - connect \S \cu_issue_i - connect \Y $70 + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$170 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - process $group_25 - assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 11'00000000000 - assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__imm_data__imm_ok 1'0 - assign \oper_r__rc__rc 1'0 - assign \oper_r__rc__rc_ok 1'0 - assign \oper_r__oe__oe 1'0 - assign \oper_r__oe__oe_ok 1'0 - assign \oper_r__invert_a 1'0 - assign \oper_r__zero_a 1'0 - assign \oper_r__input_carry 2'00 - assign \oper_r__invert_out 1'0 - assign \oper_r__write_cr0 1'0 - assign \oper_r__output_carry 1'0 - assign \oper_r__is_32bit 1'0 - assign \oper_r__is_signed 1'0 - assign \oper_r__data_len 4'0000 - assign \oper_r__insn 32'00000000000000000000000000000000 - assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $70 + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - process $group_43 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__rc__rc$next \oper_l__rc__rc - assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok - assign \oper_l__oe__oe$next \oper_l__oe__oe - assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok - assign \oper_l__invert_a$next \oper_l__invert_a - assign \oper_l__zero_a$next \oper_l__zero_a - assign \oper_l__input_carry$next \oper_l__input_carry - assign \oper_l__invert_out$next \oper_l__invert_out - assign \oper_l__write_cr0$next \oper_l__write_cr0 - assign \oper_l__output_carry$next \oper_l__output_carry - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__data_len$next \oper_l__data_len - assign \oper_l__insn$next \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_a { \oper_i_alu_div0__oe__oe_ok \oper_i_alu_div0__oe__oe } { \oper_i_alu_div0__rc__rc_ok \oper_i_alu_div0__rc__rc } { \oper_i_alu_div0__imm_data__imm_ok \oper_i_alu_div0__imm_data__imm } \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - assign \oper_l__rc__rc$next 1'0 - assign \oper_l__rc__rc_ok$next 1'0 - assign \oper_l__oe__oe$next 1'0 - assign \oper_l__oe__oe_ok$next 1'0 - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 11'00000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__rc__rc 1'0 - update \oper_l__rc__rc_ok 1'0 - update \oper_l__oe__oe 1'0 - update \oper_l__oe__oe_ok 1'0 - update \oper_l__invert_a 1'0 - update \oper_l__zero_a 1'0 - update \oper_l__input_carry 2'00 - update \oper_l__invert_out 1'0 - update \oper_l__write_cr0 1'0 - update \oper_l__output_carry 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__data_len 4'0000 - update \oper_l__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__rc__rc \oper_l__rc__rc$next - update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next - update \oper_l__oe__oe \oper_l__oe__oe$next - update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next - update \oper_l__invert_a \oper_l__invert_a$next - update \oper_l__zero_a \oper_l__zero_a$next - update \oper_l__input_carry \oper_l__input_carry$next - update \oper_l__invert_out \oper_l__invert_out$next - update \oper_l__write_cr0 \oper_l__write_cr0$next - update \oper_l__output_carry \oper_l__output_carry$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__data_len \oper_l__data_len$next - update \oper_l__insn \oper_l__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $72 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $75 - parameter \WIDTH 65 - connect \A { \data_r0_l__o_ok \data_r0_l__o } - connect \B { \o_ok \alu_div0_o } - connect \S $73 - connect \Y $72 - end - process $group_61 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - assign { \data_r0__o_ok \data_r0__o } $72 + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $76 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $76 - end - process $group_63 - assign \data_r0_l__o$next \data_r0_l__o - assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $76 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_div0_o } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0_l__o_ok$next 1'0 - end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init - update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0_l__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0_l__o \data_r0_l__o$next - update \data_r0_l__o_ok \data_r0_l__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 5 $78 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $79 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $81 - parameter \WIDTH 5 - connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a } - connect \B { \cr_a_ok \alu_div0_cr_a } - connect \S $79 - connect \Y $78 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - process $group_65 - assign \data_r1__cr_a 4'0000 - assign \data_r1__cr_a_ok 1'0 - assign { \data_r1__cr_a_ok \data_r1__cr_a } $78 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $82 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $83 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $82 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - process $group_67 - assign \data_r1_l__cr_a$next \data_r1_l__cr_a - assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $82 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_div0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1_l__cr_a_ok$next 1'0 - end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init - update \data_r1_l__cr_a 4'0000 - update \data_r1_l__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r1_l__cr_a \data_r1_l__cr_a$next - update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 2 \data_r2__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r2__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 3 $84 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $85 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $87 - parameter \WIDTH 3 - connect \A { \data_r2_l__xer_ov_ok \data_r2_l__xer_ov } - connect \B { \xer_ov_ok \alu_div0_xer_ov } - connect \S $85 - connect \Y $84 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - process $group_69 - assign \data_r2__xer_ov 2'00 - assign \data_r2__xer_ov_ok 1'0 - assign { \data_r2__xer_ov_ok \data_r2__xer_ov } $84 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $88 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $89 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $88 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - process $group_71 - assign \data_r2_l__xer_ov$next \data_r2_l__xer_ov - assign \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $88 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov$next } { \xer_ov_ok \alu_div0_xer_ov } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2_l__xer_ov_ok$next 1'0 - end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init - update \data_r2_l__xer_ov 2'00 - update \data_r2_l__xer_ov_ok 1'0 - sync posedge \coresync_clk - update \data_r2_l__xer_ov \data_r2_l__xer_ov$next - update \data_r2_l__xer_ov_ok \data_r2_l__xer_ov_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r3__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $90 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $91 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $93 - parameter \WIDTH 2 - connect \A { \data_r3_l__xer_so_ok \data_r3_l__xer_so } - connect \B { \xer_so_ok \alu_div0_xer_so } - connect \S $91 - connect \Y $90 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - process $group_73 - assign \data_r3__xer_so 1'0 - assign \data_r3__xer_so_ok 1'0 - assign { \data_r3__xer_so_ok \data_r3__xer_so } $90 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $94 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $95 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $94 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - process $group_75 - assign \data_r3_l__xer_so$next \data_r3_l__xer_so - assign \data_r3_l__xer_so_ok$next \data_r3_l__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $94 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \alu_div0_xer_so } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r3_l__xer_so_ok$next 1'0 - end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init - update \data_r3_l__xer_so 1'0 - update \data_r3_l__xer_so_ok 1'0 - sync posedge \coresync_clk - update \data_r3_l__xer_so \data_r3_l__xer_so$next - update \data_r3_l__xer_so_ok \data_r3_l__xer_so_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $97 + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_22.core.trial0" +module \trial0$175 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r0__o_ok - connect \B \cu_busy_o - connect \Y $96 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $99 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r1__cr_a_ok - connect \B \cu_busy_o - connect \Y $98 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $101 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r2__xer_ov_ok - connect \B \cu_busy_o - connect \Y $100 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $103 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r3__xer_so_ok - connect \B \cu_busy_o - connect \Y $102 - end - process $group_77 - assign \cu_wrmask_o 4'0000 - assign \cu_wrmask_o { $102 $100 $98 $96 } - sync init - end - process $group_78 - assign \alu_div0_logical_op__insn_type 7'0000000 - assign \alu_div0_logical_op__fn_unit 11'00000000000 - assign \alu_div0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_div0_logical_op__imm_data__imm_ok 1'0 - assign \alu_div0_logical_op__rc__rc 1'0 - assign \alu_div0_logical_op__rc__rc_ok 1'0 - assign \alu_div0_logical_op__oe__oe 1'0 - assign \alu_div0_logical_op__oe__oe_ok 1'0 - assign \alu_div0_logical_op__invert_a 1'0 - assign \alu_div0_logical_op__zero_a 1'0 - assign \alu_div0_logical_op__input_carry 2'00 - assign \alu_div0_logical_op__invert_out 1'0 - assign \alu_div0_logical_op__write_cr0 1'0 - assign \alu_div0_logical_op__output_carry 1'0 - assign \alu_div0_logical_op__is_32bit 1'0 - assign \alu_div0_logical_op__is_signed 1'0 - assign \alu_div0_logical_op__data_len 4'0000 - assign \alu_div0_logical_op__insn 32'00000000000000000000000000000000 - assign { \alu_div0_logical_op__insn \alu_div0_logical_op__data_len \alu_div0_logical_op__is_signed \alu_div0_logical_op__is_32bit \alu_div0_logical_op__output_carry \alu_div0_logical_op__write_cr0 \alu_div0_logical_op__invert_out \alu_div0_logical_op__input_carry \alu_div0_logical_op__zero_a \alu_div0_logical_op__invert_a { \alu_div0_logical_op__oe__oe_ok \alu_div0_logical_op__oe__oe } { \alu_div0_logical_op__rc__rc_ok \alu_div0_logical_op__rc__rc } { \alu_div0_logical_op__imm_data__imm_ok \alu_div0_logical_op__imm_data__imm } \alu_div0_logical_op__fn_unit \alu_div0_logical_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } - sync init + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101001 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 $104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - cell $mux $105 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \oper_r__zero_a - connect \Y $104 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_96 - assign \src_sel 1'0 - assign \src_sel $104 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 64 $106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $107 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \oper_r__zero_a - connect \Y $106 - end - process $group_97 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $106 - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_22.core.trial1" +module \trial1$176 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 1 \src_sel$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - cell $mux $110 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \oper_r__imm_data__imm_ok - connect \Y $109 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_98 - assign \src_sel$108 1'0 - assign \src_sel$108 $109 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165" - wire width 64 \src_or_imm$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 64 $112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $113 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \oper_r__imm_data__imm - connect \S \oper_r__imm_data__imm_ok - connect \Y $112 - end - process $group_99 - assign \src_or_imm$111 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$111 $112 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $114 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $115 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $114 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101001 + connect \Y $8 end - process $group_100 - assign \alu_div0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_div0_ra $114 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_101 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \src_r0$next \src_or_imm + assign \trial_compare_rhs $7 [191:0] end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $116 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $117 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$111 - connect \S \src_sel$108 - connect \Y $116 - end - process $group_102 - assign \alu_div0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_div0_rb $116 sync init end - process $group_103 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel$108 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_22.core.pe" +module \pe$177 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \src_r1$next \src_or_imm$111 + assign \o 1'1 end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $118 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $119 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $118 - end - process $group_104 - assign \alu_div0_xer_so$1 1'0 - assign \alu_div0_xer_so$1 $118 - sync init - end - process $group_105 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \src_r2$next \src3_i + assign \o 1'0 end - sync init - update \src_r2 1'0 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - process $group_106 - assign \alu_div0_p_valid_i 1'0 - assign \alu_div0_p_valid_i \alui_l_q_alui sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - wire width 1 $120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - cell $and $121 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_div0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $120 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_107 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $120 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end + process $group_1 + assign \n 1'0 + assign \n $1 sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next end - process $group_108 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_22.core" +module \core$174 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$175 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$176 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - process $group_109 - assign \alu_div0_n_ready_i 1'0 - assign \alu_div0_n_ready_i \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$177 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - wire width 1 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - cell $and $123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $122 + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init end - process $group_110 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $122 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next end - process $group_111 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - process $group_112 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $124 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - wire width 1 $126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - cell $not $127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \oper_r__zero_a - connect \Y $126 + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - wire width 1 $128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - cell $not $129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \oper_r__imm_data__imm_ok - connect \Y $128 + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $124 - connect \B { 1'1 $128 $126 } - connect \Y $130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $not $133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $132 + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $130 - connect \B $132 - connect \Y $134 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init end - process $group_113 - assign \cu_rd__rel_o 3'000 - assign \cu_rd__rel_o $134 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $136 + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $138 + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $141 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $140 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $142 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 4 $144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \req_l_q_req - connect \B { $136 $138 $140 $142 } - connect \Y $144 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 4 $146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $147 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $144 - connect \B \cu_wrmask_o - connect \Y $146 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - process $group_114 - assign \cu_wr__rel_o 4'0000 - assign \cu_wr__rel_o $146 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $149 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $148 - end - process $group_115 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $148 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end - sync init + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $151 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $150 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_116 - assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $150 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $153 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $152 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_117 - assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $152 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest3_o { \data_r2__xer_ov_ok \data_r2__xer_ov } [1:0] - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $155 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $154 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_118 - assign \dest4_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $154 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0] - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.p" -module \p$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.n" -module \n$88 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.p" -module \p$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'101001 + connect \Y $30 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.n" -module \n$90 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input" -module \input$91 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_22" +module \core_calculate_stage_22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -100876,7 +89407,7 @@ module \input$91 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -100890,41 +89421,73 @@ module \input$91 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \mul_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \mul_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \mul_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \mul_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__zero_a + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__invert_out + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \mul_op__write_cr0 + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \mul_op__is_32bit + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \mul_op__is_signed + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 15 \mul_op__insn + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 16 \ra + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \rb + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 18 \xer_so + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 19 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -100999,7 +89562,7 @@ module \input$91 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 20 \mul_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -101013,143 +89576,865 @@ module \input$91 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 21 \mul_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 22 \mul_op__imm_data__imm$4 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 23 \mul_op__imm_data__imm_ok$5 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__rc__rc$6 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \mul_op__rc__rc_ok$7 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \mul_op__oe__oe$8 + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \mul_op__oe__oe_ok$9 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \mul_op__invert_a$10 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \mul_op__zero_a$11 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \mul_op__invert_out$12 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \mul_op__write_cr0$13 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \mul_op__is_32bit$14 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \mul_op__is_signed$15 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 34 \mul_op__insn$16 + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 35 \ra$17 + wire width 64 output 52 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 36 \rb$18 + wire width 64 output 53 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 37 \xer_so$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24" - wire width 64 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24" - cell $not $21 + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$174 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_23.core.trial0" +module \trial0$179 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end process $group_0 - assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23" - switch { \mul_op__invert_a } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23" + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \a $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25" - case - assign \a \ra + assign \dr_times_trial_bits $3 end sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101000 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 process $group_1 - assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$17 \a + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - process $group_2 - assign \xer_so$19 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47" - switch { \mul_op__oe__oe_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47" +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_23.core.trial1" +module \trial1$180 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \xer_so$19 \xer_so + assign \dr_times_trial_bits $3 end sync init end - process $group_3 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1101000 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - process $group_4 - assign \mul_op__insn_type$2 7'0000000 - assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5 1'0 - assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__rc_ok$7 1'0 - assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__oe_ok$9 1'0 - assign \mul_op__invert_a$10 1'0 - assign \mul_op__zero_a$11 1'0 - assign \mul_op__invert_out$12 1'0 - assign \mul_op__write_cr0$13 1'0 - assign \mul_op__is_32bit$14 1'0 - assign \mul_op__is_signed$15 1'0 - assign \mul_op__insn$16 32'00000000000000000000000000000000 - assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_23.core.pe" +module \pe$181 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end sync init end - process $group_19 - assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$18 \rb + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.mul1" -module \mul1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_23.core" +module \core$178 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$179 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$180 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$181 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'101000 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5.core_calculate_stage_23" +module \core_calculate_stage_23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" attribute \enum_value_0011100 "OP_DCBZ" attribute \enum_value_0011101 "OP_DIV" attribute \enum_value_0011110 "OP_DIVE" @@ -101195,7 +90480,7 @@ module \mul1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -101209,41 +90494,73 @@ module \mul1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \mul_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \mul_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \mul_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \mul_op__invert_a + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__zero_a + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__invert_out + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \mul_op__write_cr0 + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \mul_op__is_32bit + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \mul_op__is_signed + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 15 \mul_op__insn + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 16 \ra + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \rb + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 18 \xer_so + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 19 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -101318,7 +90635,7 @@ module \mul1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 20 \mul_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -101332,343 +90649,411 @@ module \mul1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 21 \mul_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 22 \mul_op__imm_data__imm$4 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 23 \mul_op__imm_data__imm_ok$5 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__rc__rc$6 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \mul_op__rc__rc_ok$7 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \mul_op__oe__oe$8 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \mul_op__oe__oe_ok$9 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \mul_op__invert_a$10 + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \mul_op__zero_a$11 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \mul_op__invert_out$12 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \mul_op__write_cr0$13 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \mul_op__is_32bit$14 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \mul_op__is_signed$15 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 34 \mul_op__insn$16 + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 35 \ra$17 + wire width 64 output 52 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 36 \rb$18 + wire width 64 output 53 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 37 \xer_so$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 output 38 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 output 39 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30" - wire width 1 \is_32bit + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$178 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end process $group_0 - assign \is_32bit 1'0 - assign \is_32bit \mul_op__is_32bit + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" - wire width 1 \sign_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $21 - parameter \WIDTH 1 - connect \A \ra [63] - connect \B \ra [31] - connect \S \mul_op__is_32bit - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \B \mul_op__is_signed - connect \Y $22 - end process $group_1 - assign \sign_a 1'0 - assign \sign_a $22 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" - wire width 1 \sign_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $25 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \mul_op__is_32bit - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \B \mul_op__is_signed - connect \Y $26 - end - process $group_2 - assign \sign_b 1'0 - assign \sign_b $26 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" - wire width 1 \sign32_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ra [31] - connect \B \mul_op__is_signed - connect \Y $28 - end - process $group_3 - assign \sign32_a 1'0 - assign \sign32_a $28 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" - wire width 1 \sign32_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rb [31] - connect \B \mul_op__is_signed - connect \Y $30 - end - process $group_4 - assign \sign32_b 1'0 - assign \sign32_b $30 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sign_a - connect \B \sign_b - connect \Y $32 - end - process $group_5 - assign \neg_res 1'0 - assign \neg_res $32 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sign32_a - connect \B \sign32_b - connect \Y $34 - end - process $group_6 - assign \neg_res32 1'0 - assign \neg_res32 $34 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50" - wire width 64 \abs_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - wire width 65 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - wire width 65 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $37 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 65 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $39 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - wire width 65 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $42 - parameter \WIDTH 65 - connect \A $39 - connect \B $37 - connect \S \sign_a - connect \Y $41 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - connect $36 $41 - process $group_7 - assign \abs_a 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \abs_a $36 [63:0] + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51" - wire width 64 \abs_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - wire width 65 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - wire width 65 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $44 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 65 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $46 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - wire width 65 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $49 - parameter \WIDTH 65 - connect \A $46 - connect \B $44 - connect \S \sign_b - connect \Y $48 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init end - connect $43 $48 - process $group_8 - assign \abs_b 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \abs_b $43 [63:0] + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - wire width 32 $50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $51 - parameter \WIDTH 32 - connect \A \abs_a [63:32] - connect \B 32'00000000000000000000000000000000 - connect \S \is_32bit - connect \Y $50 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_9 - assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$17 [31:0] \abs_a [31:0] - assign \ra$17 [63:32] $50 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - wire width 32 $52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $53 - parameter \WIDTH 32 - connect \A \abs_b [63:32] - connect \B 32'00000000000000000000000000000000 - connect \S \is_32bit - connect \Y $52 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - process $group_10 - assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$18 [31:0] \abs_b [31:0] - assign \rb$18 [63:32] $52 + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init end - process $group_11 - assign \xer_so$19 1'0 - assign \xer_so$19 \xer_so + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end - process $group_12 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 sync init end - process $group_13 - assign \mul_op__insn_type$2 7'0000000 - assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5 1'0 - assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__rc_ok$7 1'0 - assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__oe_ok$9 1'0 - assign \mul_op__invert_a$10 1'0 - assign \mul_op__zero_a$11 1'0 - assign \mul_op__invert_out$12 1'0 - assign \mul_op__write_cr0$13 1'0 - assign \mul_op__is_32bit$14 1'0 - assign \mul_op__is_signed$15 1'0 - assign \mul_op__insn$16 32'00000000000000000000000000000000 - assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1" -module \mul_pipe1 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_5" +module \pipe_middle_5 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 2 \n_valid_o + wire width 1 output 37 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 3 \n_ready_i + wire width 1 input 38 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid + wire width 2 output 39 \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next + wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -101743,9 +91128,9 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \mul_op__insn_type + wire width 7 output 40 \logical_op__insn_type$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$next + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -101759,87 +91144,143 @@ module \mul_pipe1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 6 \mul_op__fn_unit + wire width 11 output 41 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$next + wire width 11 \logical_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \mul_op__imm_data__imm + wire width 64 output 42 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$next + wire width 64 \logical_op__imm_data__imm$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \mul_op__imm_data__imm_ok + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$next + wire width 1 \logical_op__imm_data__imm_ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 9 \mul_op__rc__rc + wire width 1 output 44 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$next + wire width 1 \logical_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \mul_op__rc__rc_ok + wire width 1 output 45 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$next + wire width 1 \logical_op__rc__rc_ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 11 \mul_op__oe__oe + wire width 1 output 46 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$next + wire width 1 \logical_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \mul_op__oe__oe_ok + wire width 1 output 47 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$next + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 13 \mul_op__invert_a + wire width 2 output 50 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_a$next + wire width 2 \logical_op__input_carry$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 14 \mul_op__zero_a + wire width 1 output 51 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__zero_a$next + wire width 1 \logical_op__invert_out$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 15 \mul_op__invert_out + wire width 1 output 52 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_out$next + wire width 1 \logical_op__write_cr0$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 16 \mul_op__write_cr0 + wire width 1 output 53 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$next + wire width 1 \logical_op__output_carry$15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 17 \mul_op__is_32bit + wire width 1 output 54 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$next + wire width 1 \logical_op__is_32bit$16$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 18 \mul_op__is_signed + wire width 1 output 55 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$next + wire width 1 \logical_op__is_signed$17$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \mul_op__insn + wire width 4 output 56 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$next + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 20 \ra + wire width 64 output 58 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next + wire width 64 \ra$20$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 21 \rb + wire width 64 output 59 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next + wire width 64 \rb$21$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 22 \xer_so + wire width 1 output 60 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 output 23 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \neg_res$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 output 24 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \neg_res32$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 25 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 26 \p_ready_o + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$164 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$165 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 27 \muxid$1 + wire width 2 \core_calculate_stage_20_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -101914,7 +91355,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 28 \mul_op__insn_type$2 + wire width 7 \core_calculate_stage_20_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -101928,49 +91369,73 @@ module \mul_pipe1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 29 \mul_op__fn_unit$3 + wire width 11 \core_calculate_stage_20_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_20_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_20_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_20_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 30 \mul_op__imm_data__imm$4 + wire width 1 \core_calculate_stage_20_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 31 \mul_op__imm_data__imm_ok$5 + wire width 1 \core_calculate_stage_20_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 32 \mul_op__rc__rc$6 + wire width 1 \core_calculate_stage_20_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 33 \mul_op__rc__rc_ok$7 + wire width 1 \core_calculate_stage_20_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 34 \mul_op__oe__oe$8 + wire width 1 \core_calculate_stage_20_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 35 \mul_op__oe__oe_ok$9 + wire width 2 \core_calculate_stage_20_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 36 \mul_op__invert_a$10 + wire width 1 \core_calculate_stage_20_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 37 \mul_op__zero_a$11 + wire width 1 \core_calculate_stage_20_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 38 \mul_op__invert_out$12 + wire width 1 \core_calculate_stage_20_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 39 \mul_op__write_cr0$13 + wire width 1 \core_calculate_stage_20_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 40 \mul_op__is_32bit$14 + wire width 1 \core_calculate_stage_20_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 41 \mul_op__is_signed$15 + wire width 4 \core_calculate_stage_20_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 42 \mul_op__insn$16 + wire width 32 \core_calculate_stage_20_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 43 \ra$17 + wire width 64 \core_calculate_stage_20_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 44 \rb$18 + wire width 64 \core_calculate_stage_20_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 45 \xer_so$19 - cell \p$89 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$90 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end + wire width 1 \core_calculate_stage_20_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_20_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_20_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_20_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_20_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_20_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_20_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_20_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_20_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_20_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_20_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_20_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid + wire width 2 \core_calculate_stage_20_muxid$34 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -102045,7 +91510,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_mul_op__insn_type + wire width 7 \core_calculate_stage_20_logical_op__insn_type$35 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -102059,41 +91524,141 @@ module \mul_pipe1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_mul_op__fn_unit + wire width 11 \core_calculate_stage_20_logical_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_mul_op__imm_data__imm + wire width 64 \core_calculate_stage_20_logical_op__imm_data__imm$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_20_logical_op__imm_data__imm_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__rc__rc + wire width 1 \core_calculate_stage_20_logical_op__rc__rc$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__rc__rc_ok + wire width 1 \core_calculate_stage_20_logical_op__rc__rc_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__oe__oe + wire width 1 \core_calculate_stage_20_logical_op__oe__oe$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__oe__oe_ok + wire width 1 \core_calculate_stage_20_logical_op__oe__oe_ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__invert_a + wire width 1 \core_calculate_stage_20_logical_op__invert_in$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__zero_a + wire width 1 \core_calculate_stage_20_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__invert_out + wire width 2 \core_calculate_stage_20_logical_op__input_carry$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__write_cr0 + wire width 1 \core_calculate_stage_20_logical_op__invert_out$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__is_32bit + wire width 1 \core_calculate_stage_20_logical_op__write_cr0$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__is_signed + wire width 1 \core_calculate_stage_20_logical_op__output_carry$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_mul_op__insn + wire width 1 \core_calculate_stage_20_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_20_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_20_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_20_logical_op__insn$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra + wire width 64 \core_calculate_stage_20_ra$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb + wire width 64 \core_calculate_stage_20_rb$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \input_xer_so + wire width 1 \core_calculate_stage_20_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_20_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_20_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_20_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_20_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_20_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_20_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_20_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_20_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_20_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_20_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_20_compare_rhs$66 + cell \core_calculate_stage_20 \core_calculate_stage_20 + connect \muxid \core_calculate_stage_20_muxid + connect \logical_op__insn_type \core_calculate_stage_20_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_20_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_20_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_20_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_20_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_20_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_20_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_20_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_20_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_20_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_20_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_20_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_20_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_20_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_20_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_20_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_20_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_20_logical_op__insn + connect \ra \core_calculate_stage_20_ra + connect \rb \core_calculate_stage_20_rb + connect \xer_so \core_calculate_stage_20_xer_so + connect \divisor_neg \core_calculate_stage_20_divisor_neg + connect \dividend_neg \core_calculate_stage_20_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_20_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_20_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_20_div_by_zero + connect \divisor_radicand \core_calculate_stage_20_divisor_radicand + connect \operation \core_calculate_stage_20_operation + connect \quotient_root \core_calculate_stage_20_quotient_root + connect \root_times_radicand \core_calculate_stage_20_root_times_radicand + connect \compare_lhs \core_calculate_stage_20_compare_lhs + connect \compare_rhs \core_calculate_stage_20_compare_rhs + connect \muxid$1 \core_calculate_stage_20_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_20_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_20_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_20_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_20_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_20_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_20_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_20_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_20_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_20_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_20_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_20_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_20_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_20_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_20_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_20_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_20_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_20_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_20_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_20_ra$53 + connect \rb$21 \core_calculate_stage_20_rb$54 + connect \xer_so$22 \core_calculate_stage_20_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_20_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_20_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_20_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_20_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_20_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_20_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_20_operation$62 + connect \quotient_root$30 \core_calculate_stage_20_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_20_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_20_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_20_compare_rhs$66 + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$20 + wire width 2 \core_calculate_stage_21_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -102168,7 +91733,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_mul_op__insn_type$21 + wire width 7 \core_calculate_stage_21_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -102182,81 +91747,73 @@ module \mul_pipe1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_mul_op__fn_unit$22 + wire width 11 \core_calculate_stage_21_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_21_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_21_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_21_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_mul_op__imm_data__imm$23 + wire width 1 \core_calculate_stage_21_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__imm_data__imm_ok$24 + wire width 1 \core_calculate_stage_21_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__rc__rc$25 + wire width 1 \core_calculate_stage_21_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__rc__rc_ok$26 + wire width 1 \core_calculate_stage_21_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__oe__oe$27 + wire width 1 \core_calculate_stage_21_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__oe__oe_ok$28 + wire width 2 \core_calculate_stage_21_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__invert_a$29 + wire width 1 \core_calculate_stage_21_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__zero_a$30 + wire width 1 \core_calculate_stage_21_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__invert_out$31 + wire width 1 \core_calculate_stage_21_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__write_cr0$32 + wire width 1 \core_calculate_stage_21_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__is_32bit$33 + wire width 1 \core_calculate_stage_21_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_mul_op__is_signed$34 + wire width 4 \core_calculate_stage_21_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_mul_op__insn$35 + wire width 32 \core_calculate_stage_21_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$36 + wire width 64 \core_calculate_stage_21_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$37 + wire width 64 \core_calculate_stage_21_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \input_xer_so$38 - cell \input$91 \input - connect \muxid \input_muxid - connect \mul_op__insn_type \input_mul_op__insn_type - connect \mul_op__fn_unit \input_mul_op__fn_unit - connect \mul_op__imm_data__imm \input_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm_ok - connect \mul_op__rc__rc \input_mul_op__rc__rc - connect \mul_op__rc__rc_ok \input_mul_op__rc__rc_ok - connect \mul_op__oe__oe \input_mul_op__oe__oe - connect \mul_op__oe__oe_ok \input_mul_op__oe__oe_ok - connect \mul_op__invert_a \input_mul_op__invert_a - connect \mul_op__zero_a \input_mul_op__zero_a - connect \mul_op__invert_out \input_mul_op__invert_out - connect \mul_op__write_cr0 \input_mul_op__write_cr0 - connect \mul_op__is_32bit \input_mul_op__is_32bit - connect \mul_op__is_signed \input_mul_op__is_signed - connect \mul_op__insn \input_mul_op__insn - connect \ra \input_ra - connect \rb \input_rb - connect \xer_so \input_xer_so - connect \muxid$1 \input_muxid$20 - connect \mul_op__insn_type$2 \input_mul_op__insn_type$21 - connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$22 - connect \mul_op__imm_data__imm$4 \input_mul_op__imm_data__imm$23 - connect \mul_op__imm_data__imm_ok$5 \input_mul_op__imm_data__imm_ok$24 - connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$25 - connect \mul_op__rc__rc_ok$7 \input_mul_op__rc__rc_ok$26 - connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$27 - connect \mul_op__oe__oe_ok$9 \input_mul_op__oe__oe_ok$28 - connect \mul_op__invert_a$10 \input_mul_op__invert_a$29 - connect \mul_op__zero_a$11 \input_mul_op__zero_a$30 - connect \mul_op__invert_out$12 \input_mul_op__invert_out$31 - connect \mul_op__write_cr0$13 \input_mul_op__write_cr0$32 - connect \mul_op__is_32bit$14 \input_mul_op__is_32bit$33 - connect \mul_op__is_signed$15 \input_mul_op__is_signed$34 - connect \mul_op__insn$16 \input_mul_op__insn$35 - connect \ra$17 \input_ra$36 - connect \rb$18 \input_rb$37 - connect \xer_so$19 \input_xer_so$38 - end + wire width 1 \core_calculate_stage_21_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_21_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_21_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_21_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_21_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_21_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_21_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_21_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_21_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_21_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_21_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_21_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul1_muxid + wire width 2 \core_calculate_stage_21_muxid$67 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -102331,7 +91888,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul1_mul_op__insn_type + wire width 7 \core_calculate_stage_21_logical_op__insn_type$68 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -102345,41 +91902,141 @@ module \mul_pipe1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul1_mul_op__fn_unit + wire width 11 \core_calculate_stage_21_logical_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul1_mul_op__imm_data__imm + wire width 64 \core_calculate_stage_21_logical_op__imm_data__imm$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_21_logical_op__imm_data__imm_ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__rc__rc + wire width 1 \core_calculate_stage_21_logical_op__rc__rc$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__rc__rc_ok + wire width 1 \core_calculate_stage_21_logical_op__rc__rc_ok$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__oe__oe + wire width 1 \core_calculate_stage_21_logical_op__oe__oe$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__oe__oe_ok + wire width 1 \core_calculate_stage_21_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_21_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_21_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__invert_a + wire width 2 \core_calculate_stage_21_logical_op__input_carry$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__zero_a + wire width 1 \core_calculate_stage_21_logical_op__invert_out$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__invert_out + wire width 1 \core_calculate_stage_21_logical_op__write_cr0$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__write_cr0 + wire width 1 \core_calculate_stage_21_logical_op__output_carry$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__is_32bit + wire width 1 \core_calculate_stage_21_logical_op__is_32bit$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__is_signed + wire width 1 \core_calculate_stage_21_logical_op__is_signed$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul1_mul_op__insn + wire width 4 \core_calculate_stage_21_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_21_logical_op__insn$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul1_ra + wire width 64 \core_calculate_stage_21_ra$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul1_rb + wire width 64 \core_calculate_stage_21_rb$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul1_xer_so + wire width 1 \core_calculate_stage_21_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_21_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_21_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_21_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_21_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_21_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_21_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_21_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_21_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_21_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_21_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_21_compare_rhs$99 + cell \core_calculate_stage_21 \core_calculate_stage_21 + connect \muxid \core_calculate_stage_21_muxid + connect \logical_op__insn_type \core_calculate_stage_21_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_21_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_21_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_21_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_21_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_21_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_21_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_21_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_21_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_21_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_21_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_21_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_21_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_21_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_21_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_21_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_21_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_21_logical_op__insn + connect \ra \core_calculate_stage_21_ra + connect \rb \core_calculate_stage_21_rb + connect \xer_so \core_calculate_stage_21_xer_so + connect \divisor_neg \core_calculate_stage_21_divisor_neg + connect \dividend_neg \core_calculate_stage_21_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_21_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_21_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_21_div_by_zero + connect \divisor_radicand \core_calculate_stage_21_divisor_radicand + connect \operation \core_calculate_stage_21_operation + connect \quotient_root \core_calculate_stage_21_quotient_root + connect \root_times_radicand \core_calculate_stage_21_root_times_radicand + connect \compare_lhs \core_calculate_stage_21_compare_lhs + connect \compare_rhs \core_calculate_stage_21_compare_rhs + connect \muxid$1 \core_calculate_stage_21_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_21_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_21_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_21_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_21_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_21_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_21_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_21_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_21_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_21_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_21_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_21_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_21_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_21_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_21_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_21_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_21_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_21_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_21_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_21_ra$86 + connect \rb$21 \core_calculate_stage_21_rb$87 + connect \xer_so$22 \core_calculate_stage_21_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_21_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_21_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_21_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_21_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_21_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_21_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_21_operation$95 + connect \quotient_root$30 \core_calculate_stage_21_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_21_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_21_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_21_compare_rhs$99 + end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul1_muxid$39 + wire width 2 \core_calculate_stage_22_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -102454,7 +92111,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul1_mul_op__insn_type$40 + wire width 7 \core_calculate_stage_22_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -102468,204 +92125,73 @@ module \mul_pipe1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul1_mul_op__fn_unit$41 + wire width 11 \core_calculate_stage_22_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul1_mul_op__imm_data__imm$42 + wire width 64 \core_calculate_stage_22_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__imm_data__imm_ok$43 + wire width 1 \core_calculate_stage_22_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__rc__rc$44 + wire width 1 \core_calculate_stage_22_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__rc__rc_ok$45 + wire width 1 \core_calculate_stage_22_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__oe__oe$46 + wire width 1 \core_calculate_stage_22_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__oe__oe_ok$47 + wire width 1 \core_calculate_stage_22_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__invert_a$48 + wire width 1 \core_calculate_stage_22_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__zero_a$49 + wire width 1 \core_calculate_stage_22_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__invert_out$50 + wire width 2 \core_calculate_stage_22_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__write_cr0$51 + wire width 1 \core_calculate_stage_22_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__is_32bit$52 + wire width 1 \core_calculate_stage_22_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__is_signed$53 + wire width 1 \core_calculate_stage_22_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul1_mul_op__insn$54 + wire width 1 \core_calculate_stage_22_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_22_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_22_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_22_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul1_ra$55 + wire width 64 \core_calculate_stage_22_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul1_rb$56 + wire width 64 \core_calculate_stage_22_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul1_xer_so$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \mul1_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \mul1_neg_res32 - cell \mul1 \mul1 - connect \muxid \mul1_muxid - connect \mul_op__insn_type \mul1_mul_op__insn_type - connect \mul_op__fn_unit \mul1_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul1_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm_ok - connect \mul_op__rc__rc \mul1_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul1_mul_op__rc__rc_ok - connect \mul_op__oe__oe \mul1_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul1_mul_op__oe__oe_ok - connect \mul_op__invert_a \mul1_mul_op__invert_a - connect \mul_op__zero_a \mul1_mul_op__zero_a - connect \mul_op__invert_out \mul1_mul_op__invert_out - connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 - connect \mul_op__is_32bit \mul1_mul_op__is_32bit - connect \mul_op__is_signed \mul1_mul_op__is_signed - connect \mul_op__insn \mul1_mul_op__insn - connect \ra \mul1_ra - connect \rb \mul1_rb - connect \xer_so \mul1_xer_so - connect \muxid$1 \mul1_muxid$39 - connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$40 - connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$41 - connect \mul_op__imm_data__imm$4 \mul1_mul_op__imm_data__imm$42 - connect \mul_op__imm_data__imm_ok$5 \mul1_mul_op__imm_data__imm_ok$43 - connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$44 - connect \mul_op__rc__rc_ok$7 \mul1_mul_op__rc__rc_ok$45 - connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$46 - connect \mul_op__oe__oe_ok$9 \mul1_mul_op__oe__oe_ok$47 - connect \mul_op__invert_a$10 \mul1_mul_op__invert_a$48 - connect \mul_op__zero_a$11 \mul1_mul_op__zero_a$49 - connect \mul_op__invert_out$12 \mul1_mul_op__invert_out$50 - connect \mul_op__write_cr0$13 \mul1_mul_op__write_cr0$51 - connect \mul_op__is_32bit$14 \mul1_mul_op__is_32bit$52 - connect \mul_op__is_signed$15 \mul1_mul_op__is_signed$53 - connect \mul_op__insn$16 \mul1_mul_op__insn$54 - connect \ra$17 \mul1_ra$55 - connect \rb$18 \mul1_rb$56 - connect \xer_so$19 \mul1_xer_so$57 - connect \neg_res \mul1_neg_res - connect \neg_res32 \mul1_neg_res32 - end - process $group_0 - assign \input_muxid 2'00 - assign \input_muxid \muxid$1 - sync init - end - process $group_1 - assign \input_mul_op__insn_type 7'0000000 - assign \input_mul_op__fn_unit 11'00000000000 - assign \input_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_mul_op__imm_data__imm_ok 1'0 - assign \input_mul_op__rc__rc 1'0 - assign \input_mul_op__rc__rc_ok 1'0 - assign \input_mul_op__oe__oe 1'0 - assign \input_mul_op__oe__oe_ok 1'0 - assign \input_mul_op__invert_a 1'0 - assign \input_mul_op__zero_a 1'0 - assign \input_mul_op__invert_out 1'0 - assign \input_mul_op__write_cr0 1'0 - assign \input_mul_op__is_32bit 1'0 - assign \input_mul_op__is_signed 1'0 - assign \input_mul_op__insn 32'00000000000000000000000000000000 - assign { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__invert_out \input_mul_op__zero_a \input_mul_op__invert_a { \input_mul_op__oe__oe_ok \input_mul_op__oe__oe } { \input_mul_op__rc__rc_ok \input_mul_op__rc__rc } { \input_mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm } \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } - sync init - end - process $group_16 - assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_ra \ra$17 - sync init - end - process $group_17 - assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_rb \rb$18 - sync init - end - process $group_18 - assign \input_xer_so 1'0 - assign \input_xer_so \xer_so$19 - sync init - end - process $group_19 - assign \mul1_muxid 2'00 - assign \mul1_muxid \input_muxid$20 - sync init - end - process $group_20 - assign \mul1_mul_op__insn_type 7'0000000 - assign \mul1_mul_op__fn_unit 11'00000000000 - assign \mul1_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul1_mul_op__imm_data__imm_ok 1'0 - assign \mul1_mul_op__rc__rc 1'0 - assign \mul1_mul_op__rc__rc_ok 1'0 - assign \mul1_mul_op__oe__oe 1'0 - assign \mul1_mul_op__oe__oe_ok 1'0 - assign \mul1_mul_op__invert_a 1'0 - assign \mul1_mul_op__zero_a 1'0 - assign \mul1_mul_op__invert_out 1'0 - assign \mul1_mul_op__write_cr0 1'0 - assign \mul1_mul_op__is_32bit 1'0 - assign \mul1_mul_op__is_signed 1'0 - assign \mul1_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__invert_out \mul1_mul_op__zero_a \mul1_mul_op__invert_a { \mul1_mul_op__oe__oe_ok \mul1_mul_op__oe__oe } { \mul1_mul_op__rc__rc_ok \mul1_mul_op__rc__rc } { \mul1_mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm } \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$35 \input_mul_op__is_signed$34 \input_mul_op__is_32bit$33 \input_mul_op__write_cr0$32 \input_mul_op__invert_out$31 \input_mul_op__zero_a$30 \input_mul_op__invert_a$29 { \input_mul_op__oe__oe_ok$28 \input_mul_op__oe__oe$27 } { \input_mul_op__rc__rc_ok$26 \input_mul_op__rc__rc$25 } { \input_mul_op__imm_data__imm_ok$24 \input_mul_op__imm_data__imm$23 } \input_mul_op__fn_unit$22 \input_mul_op__insn_type$21 } - sync init - end - process $group_35 - assign \mul1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul1_ra \input_ra$36 - sync init - end - process $group_36 - assign \mul1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul1_rb \input_rb$37 - sync init - end - process $group_37 - assign \mul1_xer_so 1'0 - assign \mul1_xer_so \input_xer_so$38 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$58 - process $group_38 - assign \p_valid_i$58 1'0 - assign \p_valid_i$58 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_39 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$58 - connect \B \p_ready_o - connect \Y $59 - end - process $group_40 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $59 - sync init - end + wire width 1 \core_calculate_stage_22_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_22_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_22_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_22_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_22_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_22_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_22_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_22_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_22_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_22_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_22_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_22_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$61 - process $group_41 - assign \muxid$61 2'00 - assign \muxid$61 \mul1_muxid$39 - sync init - end + wire width 2 \core_calculate_stage_22_muxid$100 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -102740,7 +92266,7 @@ module \mul_pipe1 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$62 + wire width 7 \core_calculate_stage_22_logical_op__insn_type$101 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -102754,348 +92280,141 @@ module \mul_pipe1 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$63 + wire width 11 \core_calculate_stage_22_logical_op__fn_unit$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$64 + wire width 64 \core_calculate_stage_22_logical_op__imm_data__imm$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$65 + wire width 1 \core_calculate_stage_22_logical_op__imm_data__imm_ok$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$66 + wire width 1 \core_calculate_stage_22_logical_op__rc__rc$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$67 + wire width 1 \core_calculate_stage_22_logical_op__rc__rc_ok$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$68 + wire width 1 \core_calculate_stage_22_logical_op__oe__oe$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$69 + wire width 1 \core_calculate_stage_22_logical_op__oe__oe_ok$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_a$70 + wire width 1 \core_calculate_stage_22_logical_op__invert_in$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__zero_a$71 + wire width 1 \core_calculate_stage_22_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_out$72 + wire width 2 \core_calculate_stage_22_logical_op__input_carry$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$73 + wire width 1 \core_calculate_stage_22_logical_op__invert_out$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$74 + wire width 1 \core_calculate_stage_22_logical_op__write_cr0$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$75 + wire width 1 \core_calculate_stage_22_logical_op__output_carry$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$76 - process $group_42 - assign \mul_op__insn_type$62 7'0000000 - assign \mul_op__fn_unit$63 11'00000000000 - assign \mul_op__imm_data__imm$64 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$65 1'0 - assign \mul_op__rc__rc$66 1'0 - assign \mul_op__rc__rc_ok$67 1'0 - assign \mul_op__oe__oe$68 1'0 - assign \mul_op__oe__oe_ok$69 1'0 - assign \mul_op__invert_a$70 1'0 - assign \mul_op__zero_a$71 1'0 - assign \mul_op__invert_out$72 1'0 - assign \mul_op__write_cr0$73 1'0 - assign \mul_op__is_32bit$74 1'0 - assign \mul_op__is_signed$75 1'0 - assign \mul_op__insn$76 32'00000000000000000000000000000000 - assign { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 } { \mul1_mul_op__insn$54 \mul1_mul_op__is_signed$53 \mul1_mul_op__is_32bit$52 \mul1_mul_op__write_cr0$51 \mul1_mul_op__invert_out$50 \mul1_mul_op__zero_a$49 \mul1_mul_op__invert_a$48 { \mul1_mul_op__oe__oe_ok$47 \mul1_mul_op__oe__oe$46 } { \mul1_mul_op__rc__rc_ok$45 \mul1_mul_op__rc__rc$44 } { \mul1_mul_op__imm_data__imm_ok$43 \mul1_mul_op__imm_data__imm$42 } \mul1_mul_op__fn_unit$41 \mul1_mul_op__insn_type$40 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$77 - process $group_57 - assign \ra$77 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$77 \mul1_ra$55 - sync init - end + wire width 1 \core_calculate_stage_22_logical_op__is_32bit$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_22_logical_op__is_signed$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_22_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_22_logical_op__insn$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$78 - process $group_58 - assign \rb$78 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$78 \mul1_rb$56 - sync init - end + wire width 64 \core_calculate_stage_22_ra$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$79 - process $group_59 - assign \xer_so$79 1'0 - assign \xer_so$79 \mul1_xer_so$57 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \neg_res$80 - process $group_60 - assign \neg_res$80 1'0 - assign \neg_res$80 \mul1_neg_res - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \neg_res32$81 - process $group_61 - assign \neg_res32$81 1'0 - assign \neg_res32$81 \mul1_neg_res32 - sync init + wire width 64 \core_calculate_stage_22_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_22_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_22_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_22_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_22_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_22_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_22_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_22_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_22_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_22_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_22_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_22_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_22_compare_rhs$132 + cell \core_calculate_stage_22 \core_calculate_stage_22 + connect \muxid \core_calculate_stage_22_muxid + connect \logical_op__insn_type \core_calculate_stage_22_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_22_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_22_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_22_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_22_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_22_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_22_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_22_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_22_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_22_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_22_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_22_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_22_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_22_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_22_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_22_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_22_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_22_logical_op__insn + connect \ra \core_calculate_stage_22_ra + connect \rb \core_calculate_stage_22_rb + connect \xer_so \core_calculate_stage_22_xer_so + connect \divisor_neg \core_calculate_stage_22_divisor_neg + connect \dividend_neg \core_calculate_stage_22_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_22_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_22_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_22_div_by_zero + connect \divisor_radicand \core_calculate_stage_22_divisor_radicand + connect \operation \core_calculate_stage_22_operation + connect \quotient_root \core_calculate_stage_22_quotient_root + connect \root_times_radicand \core_calculate_stage_22_root_times_radicand + connect \compare_lhs \core_calculate_stage_22_compare_lhs + connect \compare_rhs \core_calculate_stage_22_compare_rhs + connect \muxid$1 \core_calculate_stage_22_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_22_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_22_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_22_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_22_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_22_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_22_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_22_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_22_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_22_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_22_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_22_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_22_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_22_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_22_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_22_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_22_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_22_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_22_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_22_ra$119 + connect \rb$21 \core_calculate_stage_22_rb$120 + connect \xer_so$22 \core_calculate_stage_22_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_22_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_22_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_22_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_22_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_22_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_22_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_22_operation$128 + connect \quotient_root$30 \core_calculate_stage_22_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_22_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_22_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_22_compare_rhs$132 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_62 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_63 - assign \muxid$next \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$next \muxid$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$next \muxid$61 - end - sync init - update \muxid 2'00 - sync posedge \coresync_clk - update \muxid \muxid$next - end - process $group_64 - assign \mul_op__insn_type$next \mul_op__insn_type - assign \mul_op__fn_unit$next \mul_op__fn_unit - assign \mul_op__imm_data__imm$next \mul_op__imm_data__imm - assign \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm_ok - assign \mul_op__rc__rc$next \mul_op__rc__rc - assign \mul_op__rc__rc_ok$next \mul_op__rc__rc_ok - assign \mul_op__oe__oe$next \mul_op__oe__oe - assign \mul_op__oe__oe_ok$next \mul_op__oe__oe_ok - assign \mul_op__invert_a$next \mul_op__invert_a - assign \mul_op__zero_a$next \mul_op__zero_a - assign \mul_op__invert_out$next \mul_op__invert_out - assign \mul_op__write_cr0$next \mul_op__write_cr0 - assign \mul_op__is_32bit$next \mul_op__is_32bit - assign \mul_op__is_signed$next \mul_op__is_signed - assign \mul_op__insn$next \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next \mul_op__invert_out$next \mul_op__zero_a$next \mul_op__invert_a$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next \mul_op__invert_out$next \mul_op__zero_a$next \mul_op__invert_a$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \mul_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$next 1'0 - assign \mul_op__rc__rc$next 1'0 - assign \mul_op__rc__rc_ok$next 1'0 - assign \mul_op__oe__oe$next 1'0 - assign \mul_op__oe__oe_ok$next 1'0 - end - sync init - update \mul_op__insn_type 7'0000000 - update \mul_op__fn_unit 11'00000000000 - update \mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \mul_op__imm_data__imm_ok 1'0 - update \mul_op__rc__rc 1'0 - update \mul_op__rc__rc_ok 1'0 - update \mul_op__oe__oe 1'0 - update \mul_op__oe__oe_ok 1'0 - update \mul_op__invert_a 1'0 - update \mul_op__zero_a 1'0 - update \mul_op__invert_out 1'0 - update \mul_op__write_cr0 1'0 - update \mul_op__is_32bit 1'0 - update \mul_op__is_signed 1'0 - update \mul_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \mul_op__insn_type \mul_op__insn_type$next - update \mul_op__fn_unit \mul_op__fn_unit$next - update \mul_op__imm_data__imm \mul_op__imm_data__imm$next - update \mul_op__imm_data__imm_ok \mul_op__imm_data__imm_ok$next - update \mul_op__rc__rc \mul_op__rc__rc$next - update \mul_op__rc__rc_ok \mul_op__rc__rc_ok$next - update \mul_op__oe__oe \mul_op__oe__oe$next - update \mul_op__oe__oe_ok \mul_op__oe__oe_ok$next - update \mul_op__invert_a \mul_op__invert_a$next - update \mul_op__zero_a \mul_op__zero_a$next - update \mul_op__invert_out \mul_op__invert_out$next - update \mul_op__write_cr0 \mul_op__write_cr0$next - update \mul_op__is_32bit \mul_op__is_32bit$next - update \mul_op__is_signed \mul_op__is_signed$next - update \mul_op__insn \mul_op__insn$next - end - process $group_79 - assign \ra$next \ra - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$next \ra$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$next \ra$77 - end - sync init - update \ra 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra \ra$next - end - process $group_80 - assign \rb$next \rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$next \rb$78 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$next \rb$78 - end - sync init - update \rb 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb \rb$next - end - process $group_81 - assign \xer_so$next \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$next \xer_so$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$next \xer_so$79 - end - sync init - update \xer_so 1'0 - sync posedge \coresync_clk - update \xer_so \xer_so$next - end - process $group_82 - assign \neg_res$next \neg_res - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \neg_res$next \neg_res$80 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \neg_res$next \neg_res$80 - end - sync init - update \neg_res 1'0 - sync posedge \coresync_clk - update \neg_res \neg_res$next - end - process $group_83 - assign \neg_res32$next \neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \neg_res32$next \neg_res32$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \neg_res32$next \neg_res32$81 - end - sync init - update \neg_res32 1'0 - sync posedge \coresync_clk - update \neg_res32 \neg_res32$next - end - process $group_84 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_85 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p" -module \p$92 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.n" -module \n$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.mul2" -module \mul2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid + wire width 2 \core_calculate_stage_23_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -103170,7 +92489,7 @@ module \mul2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type + wire width 7 \core_calculate_stage_23_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -103184,45 +92503,73 @@ module \mul2 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \mul_op__fn_unit + wire width 11 \core_calculate_stage_23_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__imm + wire width 64 \core_calculate_stage_23_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_23_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \mul_op__rc__rc + wire width 1 \core_calculate_stage_23_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__rc_ok + wire width 1 \core_calculate_stage_23_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \mul_op__oe__oe + wire width 1 \core_calculate_stage_23_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__oe_ok + wire width 1 \core_calculate_stage_23_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_23_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_23_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \mul_op__invert_a + wire width 2 \core_calculate_stage_23_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__zero_a + wire width 1 \core_calculate_stage_23_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__invert_out + wire width 1 \core_calculate_stage_23_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \mul_op__write_cr0 + wire width 1 \core_calculate_stage_23_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \mul_op__is_32bit + wire width 1 \core_calculate_stage_23_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \mul_op__is_signed + wire width 1 \core_calculate_stage_23_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 15 \mul_op__insn + wire width 4 \core_calculate_stage_23_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_23_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 16 \ra + wire width 64 \core_calculate_stage_23_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \rb + wire width 64 \core_calculate_stage_23_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 18 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 input 19 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 input 20 \neg_res32 + wire width 1 \core_calculate_stage_23_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_23_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_23_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_23_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_23_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_23_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_23_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_23_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_23_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_23_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_23_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_23_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 + wire width 2 \core_calculate_stage_23_muxid$133 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -103297,7 +92644,7 @@ module \mul2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \mul_op__insn_type$2 + wire width 7 \core_calculate_stage_23_logical_op__insn_type$134 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -103311,426 +92658,568 @@ module \mul2 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 23 \mul_op__fn_unit$3 + wire width 11 \core_calculate_stage_23_logical_op__fn_unit$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \mul_op__imm_data__imm$4 + wire width 64 \core_calculate_stage_23_logical_op__imm_data__imm$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \mul_op__imm_data__imm_ok$5 + wire width 1 \core_calculate_stage_23_logical_op__imm_data__imm_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \mul_op__rc__rc$6 + wire width 1 \core_calculate_stage_23_logical_op__rc__rc$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \mul_op__rc__rc_ok$7 + wire width 1 \core_calculate_stage_23_logical_op__rc__rc_ok$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \mul_op__oe__oe$8 + wire width 1 \core_calculate_stage_23_logical_op__oe__oe$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \mul_op__oe__oe_ok$9 + wire width 1 \core_calculate_stage_23_logical_op__oe__oe_ok$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \mul_op__invert_a$10 + wire width 1 \core_calculate_stage_23_logical_op__invert_in$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \mul_op__zero_a$11 + wire width 1 \core_calculate_stage_23_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \mul_op__invert_out$12 + wire width 2 \core_calculate_stage_23_logical_op__input_carry$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \mul_op__write_cr0$13 + wire width 1 \core_calculate_stage_23_logical_op__invert_out$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \mul_op__is_32bit$14 + wire width 1 \core_calculate_stage_23_logical_op__write_cr0$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \mul_op__is_signed$15 + wire width 1 \core_calculate_stage_23_logical_op__output_carry$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 36 \mul_op__insn$16 + wire width 1 \core_calculate_stage_23_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_23_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_23_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_23_logical_op__insn$151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 output 37 \o + wire width 64 \core_calculate_stage_23_ra$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 38 \xer_so$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 output 39 \neg_res$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 output 40 \neg_res32$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - wire width 129 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - wire width 128 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 128 - connect \A \ra - connect \B \rb - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \Y_WIDTH 129 - connect \A $21 - connect \Y $20 + wire width 64 \core_calculate_stage_23_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_23_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_23_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_23_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_23_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_23_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_23_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_23_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_23_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_23_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_23_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_23_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_23_compare_rhs$165 + cell \core_calculate_stage_23 \core_calculate_stage_23 + connect \muxid \core_calculate_stage_23_muxid + connect \logical_op__insn_type \core_calculate_stage_23_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_23_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_23_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_23_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_23_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_23_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_23_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_23_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_23_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_23_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_23_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_23_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_23_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_23_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_23_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_23_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_23_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_23_logical_op__insn + connect \ra \core_calculate_stage_23_ra + connect \rb \core_calculate_stage_23_rb + connect \xer_so \core_calculate_stage_23_xer_so + connect \divisor_neg \core_calculate_stage_23_divisor_neg + connect \dividend_neg \core_calculate_stage_23_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_23_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_23_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_23_div_by_zero + connect \divisor_radicand \core_calculate_stage_23_divisor_radicand + connect \operation \core_calculate_stage_23_operation + connect \quotient_root \core_calculate_stage_23_quotient_root + connect \root_times_radicand \core_calculate_stage_23_root_times_radicand + connect \compare_lhs \core_calculate_stage_23_compare_lhs + connect \compare_rhs \core_calculate_stage_23_compare_rhs + connect \muxid$1 \core_calculate_stage_23_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_23_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_23_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_23_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_23_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_23_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_23_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_23_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_23_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_23_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_23_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_23_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_23_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_23_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_23_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_23_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_23_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_23_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_23_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_23_ra$152 + connect \rb$21 \core_calculate_stage_23_rb$153 + connect \xer_so$22 \core_calculate_stage_23_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_23_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_23_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_23_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_23_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_23_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_23_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_23_operation$161 + connect \quotient_root$30 \core_calculate_stage_23_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_23_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_23_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_23_compare_rhs$165 end process $group_0 - assign \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \o $20 + assign \core_calculate_stage_20_muxid 2'00 + assign \core_calculate_stage_20_muxid \muxid sync init end process $group_1 - assign \neg_res$18 1'0 - assign \neg_res$18 \neg_res + assign \core_calculate_stage_20_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_20_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_20_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_20_logical_op__rc__rc 1'0 + assign \core_calculate_stage_20_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_20_logical_op__oe__oe 1'0 + assign \core_calculate_stage_20_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_20_logical_op__invert_in 1'0 + assign \core_calculate_stage_20_logical_op__zero_a 1'0 + assign \core_calculate_stage_20_logical_op__input_carry 2'00 + assign \core_calculate_stage_20_logical_op__invert_out 1'0 + assign \core_calculate_stage_20_logical_op__write_cr0 1'0 + assign \core_calculate_stage_20_logical_op__output_carry 1'0 + assign \core_calculate_stage_20_logical_op__is_32bit 1'0 + assign \core_calculate_stage_20_logical_op__is_signed 1'0 + assign \core_calculate_stage_20_logical_op__data_len 4'0000 + assign \core_calculate_stage_20_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_20_logical_op__insn \core_calculate_stage_20_logical_op__data_len \core_calculate_stage_20_logical_op__is_signed \core_calculate_stage_20_logical_op__is_32bit \core_calculate_stage_20_logical_op__output_carry \core_calculate_stage_20_logical_op__write_cr0 \core_calculate_stage_20_logical_op__invert_out \core_calculate_stage_20_logical_op__input_carry \core_calculate_stage_20_logical_op__zero_a \core_calculate_stage_20_logical_op__invert_in { \core_calculate_stage_20_logical_op__oe__oe_ok \core_calculate_stage_20_logical_op__oe__oe } { \core_calculate_stage_20_logical_op__rc__rc_ok \core_calculate_stage_20_logical_op__rc__rc } { \core_calculate_stage_20_logical_op__imm_data__imm_ok \core_calculate_stage_20_logical_op__imm_data__imm } \core_calculate_stage_20_logical_op__fn_unit \core_calculate_stage_20_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - process $group_2 - assign \neg_res32$19 1'0 - assign \neg_res32$19 \neg_res32 + process $group_19 + assign \core_calculate_stage_20_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_ra \ra sync init end - process $group_3 - assign \xer_so$17 1'0 - assign \xer_so$17 \xer_so + process $group_20 + assign \core_calculate_stage_20_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_rb \rb sync init end - process $group_4 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + process $group_21 + assign \core_calculate_stage_20_xer_so 1'0 + assign \core_calculate_stage_20_xer_so \xer_so sync init end - process $group_5 - assign \mul_op__insn_type$2 7'0000000 - assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5 1'0 - assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__rc_ok$7 1'0 - assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__oe_ok$9 1'0 - assign \mul_op__invert_a$10 1'0 - assign \mul_op__zero_a$11 1'0 - assign \mul_op__invert_out$12 1'0 - assign \mul_op__write_cr0$13 1'0 - assign \mul_op__is_32bit$14 1'0 - assign \mul_op__is_signed$15 1'0 - assign \mul_op__insn$16 32'00000000000000000000000000000000 - assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + process $group_22 + assign \core_calculate_stage_20_divisor_neg 1'0 + assign \core_calculate_stage_20_divisor_neg \divisor_neg sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2" -module \mul_pipe2 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \mul_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \mul_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \mul_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \mul_op__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \mul_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \mul_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 19 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 21 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 22 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 input 23 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 input 24 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 25 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 26 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 27 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 28 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$2$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 29 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 30 \mul_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \mul_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \mul_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \mul_op__oe__oe_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \mul_op__invert_a$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_a$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \mul_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__zero_a$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \mul_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_out$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \mul_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \mul_op__is_32bit$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \mul_op__is_signed$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 42 \mul_op__insn$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 output 43 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 44 \xer_so$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 output 45 \neg_res$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 \neg_res$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 output 46 \neg_res32$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \neg_res32$19$next - cell \p$92 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o + process $group_23 + assign \core_calculate_stage_20_dividend_neg 1'0 + assign \core_calculate_stage_20_dividend_neg \dividend_neg + sync init end - cell \n$93 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + process $group_24 + assign \core_calculate_stage_20_dive_abs_ov32 1'0 + assign \core_calculate_stage_20_dive_abs_ov32 \dive_abs_ov32 + sync init + end + process $group_25 + assign \core_calculate_stage_20_dive_abs_ov64 1'0 + assign \core_calculate_stage_20_dive_abs_ov64 \dive_abs_ov64 + sync init + end + process $group_26 + assign \core_calculate_stage_20_div_by_zero 1'0 + assign \core_calculate_stage_20_div_by_zero \div_by_zero + sync init + end + process $group_27 + assign \core_calculate_stage_20_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_calculate_stage_20_operation 2'00 + assign \core_calculate_stage_20_operation \operation + sync init + end + process $group_29 + assign \core_calculate_stage_20_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_calculate_stage_20_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_calculate_stage_20_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_calculate_stage_20_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \core_calculate_stage_21_muxid 2'00 + assign \core_calculate_stage_21_muxid \core_calculate_stage_20_muxid$34 + sync init + end + process $group_34 + assign \core_calculate_stage_21_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_21_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_21_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_21_logical_op__rc__rc 1'0 + assign \core_calculate_stage_21_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_21_logical_op__oe__oe 1'0 + assign \core_calculate_stage_21_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_21_logical_op__invert_in 1'0 + assign \core_calculate_stage_21_logical_op__zero_a 1'0 + assign \core_calculate_stage_21_logical_op__input_carry 2'00 + assign \core_calculate_stage_21_logical_op__invert_out 1'0 + assign \core_calculate_stage_21_logical_op__write_cr0 1'0 + assign \core_calculate_stage_21_logical_op__output_carry 1'0 + assign \core_calculate_stage_21_logical_op__is_32bit 1'0 + assign \core_calculate_stage_21_logical_op__is_signed 1'0 + assign \core_calculate_stage_21_logical_op__data_len 4'0000 + assign \core_calculate_stage_21_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_21_logical_op__insn \core_calculate_stage_21_logical_op__data_len \core_calculate_stage_21_logical_op__is_signed \core_calculate_stage_21_logical_op__is_32bit \core_calculate_stage_21_logical_op__output_carry \core_calculate_stage_21_logical_op__write_cr0 \core_calculate_stage_21_logical_op__invert_out \core_calculate_stage_21_logical_op__input_carry \core_calculate_stage_21_logical_op__zero_a \core_calculate_stage_21_logical_op__invert_in { \core_calculate_stage_21_logical_op__oe__oe_ok \core_calculate_stage_21_logical_op__oe__oe } { \core_calculate_stage_21_logical_op__rc__rc_ok \core_calculate_stage_21_logical_op__rc__rc } { \core_calculate_stage_21_logical_op__imm_data__imm_ok \core_calculate_stage_21_logical_op__imm_data__imm } \core_calculate_stage_21_logical_op__fn_unit \core_calculate_stage_21_logical_op__insn_type } { \core_calculate_stage_20_logical_op__insn$52 \core_calculate_stage_20_logical_op__data_len$51 \core_calculate_stage_20_logical_op__is_signed$50 \core_calculate_stage_20_logical_op__is_32bit$49 \core_calculate_stage_20_logical_op__output_carry$48 \core_calculate_stage_20_logical_op__write_cr0$47 \core_calculate_stage_20_logical_op__invert_out$46 \core_calculate_stage_20_logical_op__input_carry$45 \core_calculate_stage_20_logical_op__zero_a$44 \core_calculate_stage_20_logical_op__invert_in$43 { \core_calculate_stage_20_logical_op__oe__oe_ok$42 \core_calculate_stage_20_logical_op__oe__oe$41 } { \core_calculate_stage_20_logical_op__rc__rc_ok$40 \core_calculate_stage_20_logical_op__rc__rc$39 } { \core_calculate_stage_20_logical_op__imm_data__imm_ok$38 \core_calculate_stage_20_logical_op__imm_data__imm$37 } \core_calculate_stage_20_logical_op__fn_unit$36 \core_calculate_stage_20_logical_op__insn_type$35 } + sync init + end + process $group_52 + assign \core_calculate_stage_21_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_ra \core_calculate_stage_20_ra$53 + sync init + end + process $group_53 + assign \core_calculate_stage_21_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_rb \core_calculate_stage_20_rb$54 + sync init + end + process $group_54 + assign \core_calculate_stage_21_xer_so 1'0 + assign \core_calculate_stage_21_xer_so \core_calculate_stage_20_xer_so$55 + sync init + end + process $group_55 + assign \core_calculate_stage_21_divisor_neg 1'0 + assign \core_calculate_stage_21_divisor_neg \core_calculate_stage_20_divisor_neg$56 + sync init + end + process $group_56 + assign \core_calculate_stage_21_dividend_neg 1'0 + assign \core_calculate_stage_21_dividend_neg \core_calculate_stage_20_dividend_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_21_dive_abs_ov32 1'0 + assign \core_calculate_stage_21_dive_abs_ov32 \core_calculate_stage_20_dive_abs_ov32$58 + sync init + end + process $group_58 + assign \core_calculate_stage_21_dive_abs_ov64 1'0 + assign \core_calculate_stage_21_dive_abs_ov64 \core_calculate_stage_20_dive_abs_ov64$59 + sync init + end + process $group_59 + assign \core_calculate_stage_21_div_by_zero 1'0 + assign \core_calculate_stage_21_div_by_zero \core_calculate_stage_20_div_by_zero$60 + sync init + end + process $group_60 + assign \core_calculate_stage_21_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_divisor_radicand \core_calculate_stage_20_divisor_radicand$61 + sync init + end + process $group_61 + assign \core_calculate_stage_21_operation 2'00 + assign \core_calculate_stage_21_operation \core_calculate_stage_20_operation$62 + sync init + end + process $group_62 + assign \core_calculate_stage_21_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_quotient_root \core_calculate_stage_20_quotient_root$63 + sync init + end + process $group_63 + assign \core_calculate_stage_21_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_root_times_radicand \core_calculate_stage_20_root_times_radicand$64 + sync init + end + process $group_64 + assign \core_calculate_stage_21_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_compare_lhs \core_calculate_stage_20_compare_lhs$65 + sync init + end + process $group_65 + assign \core_calculate_stage_21_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_compare_rhs \core_calculate_stage_20_compare_rhs$66 + sync init + end + process $group_66 + assign \core_calculate_stage_22_muxid 2'00 + assign \core_calculate_stage_22_muxid \core_calculate_stage_21_muxid$67 + sync init + end + process $group_67 + assign \core_calculate_stage_22_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_22_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_22_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_22_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_22_logical_op__rc__rc 1'0 + assign \core_calculate_stage_22_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_22_logical_op__oe__oe 1'0 + assign \core_calculate_stage_22_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_22_logical_op__invert_in 1'0 + assign \core_calculate_stage_22_logical_op__zero_a 1'0 + assign \core_calculate_stage_22_logical_op__input_carry 2'00 + assign \core_calculate_stage_22_logical_op__invert_out 1'0 + assign \core_calculate_stage_22_logical_op__write_cr0 1'0 + assign \core_calculate_stage_22_logical_op__output_carry 1'0 + assign \core_calculate_stage_22_logical_op__is_32bit 1'0 + assign \core_calculate_stage_22_logical_op__is_signed 1'0 + assign \core_calculate_stage_22_logical_op__data_len 4'0000 + assign \core_calculate_stage_22_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_22_logical_op__insn \core_calculate_stage_22_logical_op__data_len \core_calculate_stage_22_logical_op__is_signed \core_calculate_stage_22_logical_op__is_32bit \core_calculate_stage_22_logical_op__output_carry \core_calculate_stage_22_logical_op__write_cr0 \core_calculate_stage_22_logical_op__invert_out \core_calculate_stage_22_logical_op__input_carry \core_calculate_stage_22_logical_op__zero_a \core_calculate_stage_22_logical_op__invert_in { \core_calculate_stage_22_logical_op__oe__oe_ok \core_calculate_stage_22_logical_op__oe__oe } { \core_calculate_stage_22_logical_op__rc__rc_ok \core_calculate_stage_22_logical_op__rc__rc } { \core_calculate_stage_22_logical_op__imm_data__imm_ok \core_calculate_stage_22_logical_op__imm_data__imm } \core_calculate_stage_22_logical_op__fn_unit \core_calculate_stage_22_logical_op__insn_type } { \core_calculate_stage_21_logical_op__insn$85 \core_calculate_stage_21_logical_op__data_len$84 \core_calculate_stage_21_logical_op__is_signed$83 \core_calculate_stage_21_logical_op__is_32bit$82 \core_calculate_stage_21_logical_op__output_carry$81 \core_calculate_stage_21_logical_op__write_cr0$80 \core_calculate_stage_21_logical_op__invert_out$79 \core_calculate_stage_21_logical_op__input_carry$78 \core_calculate_stage_21_logical_op__zero_a$77 \core_calculate_stage_21_logical_op__invert_in$76 { \core_calculate_stage_21_logical_op__oe__oe_ok$75 \core_calculate_stage_21_logical_op__oe__oe$74 } { \core_calculate_stage_21_logical_op__rc__rc_ok$73 \core_calculate_stage_21_logical_op__rc__rc$72 } { \core_calculate_stage_21_logical_op__imm_data__imm_ok$71 \core_calculate_stage_21_logical_op__imm_data__imm$70 } \core_calculate_stage_21_logical_op__fn_unit$69 \core_calculate_stage_21_logical_op__insn_type$68 } + sync init + end + process $group_85 + assign \core_calculate_stage_22_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_22_ra \core_calculate_stage_21_ra$86 + sync init + end + process $group_86 + assign \core_calculate_stage_22_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_22_rb \core_calculate_stage_21_rb$87 + sync init + end + process $group_87 + assign \core_calculate_stage_22_xer_so 1'0 + assign \core_calculate_stage_22_xer_so \core_calculate_stage_21_xer_so$88 + sync init + end + process $group_88 + assign \core_calculate_stage_22_divisor_neg 1'0 + assign \core_calculate_stage_22_divisor_neg \core_calculate_stage_21_divisor_neg$89 + sync init + end + process $group_89 + assign \core_calculate_stage_22_dividend_neg 1'0 + assign \core_calculate_stage_22_dividend_neg \core_calculate_stage_21_dividend_neg$90 + sync init + end + process $group_90 + assign \core_calculate_stage_22_dive_abs_ov32 1'0 + assign \core_calculate_stage_22_dive_abs_ov32 \core_calculate_stage_21_dive_abs_ov32$91 + sync init + end + process $group_91 + assign \core_calculate_stage_22_dive_abs_ov64 1'0 + assign \core_calculate_stage_22_dive_abs_ov64 \core_calculate_stage_21_dive_abs_ov64$92 + sync init + end + process $group_92 + assign \core_calculate_stage_22_div_by_zero 1'0 + assign \core_calculate_stage_22_div_by_zero \core_calculate_stage_21_div_by_zero$93 + sync init + end + process $group_93 + assign \core_calculate_stage_22_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_22_divisor_radicand \core_calculate_stage_21_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_22_operation 2'00 + assign \core_calculate_stage_22_operation \core_calculate_stage_21_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_22_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_22_quotient_root \core_calculate_stage_21_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_22_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_22_root_times_radicand \core_calculate_stage_21_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_22_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_22_compare_lhs \core_calculate_stage_21_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_22_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_22_compare_rhs \core_calculate_stage_21_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_23_muxid 2'00 + assign \core_calculate_stage_23_muxid \core_calculate_stage_22_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_23_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_23_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_23_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_23_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_23_logical_op__rc__rc 1'0 + assign \core_calculate_stage_23_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_23_logical_op__oe__oe 1'0 + assign \core_calculate_stage_23_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_23_logical_op__invert_in 1'0 + assign \core_calculate_stage_23_logical_op__zero_a 1'0 + assign \core_calculate_stage_23_logical_op__input_carry 2'00 + assign \core_calculate_stage_23_logical_op__invert_out 1'0 + assign \core_calculate_stage_23_logical_op__write_cr0 1'0 + assign \core_calculate_stage_23_logical_op__output_carry 1'0 + assign \core_calculate_stage_23_logical_op__is_32bit 1'0 + assign \core_calculate_stage_23_logical_op__is_signed 1'0 + assign \core_calculate_stage_23_logical_op__data_len 4'0000 + assign \core_calculate_stage_23_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_23_logical_op__insn \core_calculate_stage_23_logical_op__data_len \core_calculate_stage_23_logical_op__is_signed \core_calculate_stage_23_logical_op__is_32bit \core_calculate_stage_23_logical_op__output_carry \core_calculate_stage_23_logical_op__write_cr0 \core_calculate_stage_23_logical_op__invert_out \core_calculate_stage_23_logical_op__input_carry \core_calculate_stage_23_logical_op__zero_a \core_calculate_stage_23_logical_op__invert_in { \core_calculate_stage_23_logical_op__oe__oe_ok \core_calculate_stage_23_logical_op__oe__oe } { \core_calculate_stage_23_logical_op__rc__rc_ok \core_calculate_stage_23_logical_op__rc__rc } { \core_calculate_stage_23_logical_op__imm_data__imm_ok \core_calculate_stage_23_logical_op__imm_data__imm } \core_calculate_stage_23_logical_op__fn_unit \core_calculate_stage_23_logical_op__insn_type } { \core_calculate_stage_22_logical_op__insn$118 \core_calculate_stage_22_logical_op__data_len$117 \core_calculate_stage_22_logical_op__is_signed$116 \core_calculate_stage_22_logical_op__is_32bit$115 \core_calculate_stage_22_logical_op__output_carry$114 \core_calculate_stage_22_logical_op__write_cr0$113 \core_calculate_stage_22_logical_op__invert_out$112 \core_calculate_stage_22_logical_op__input_carry$111 \core_calculate_stage_22_logical_op__zero_a$110 \core_calculate_stage_22_logical_op__invert_in$109 { \core_calculate_stage_22_logical_op__oe__oe_ok$108 \core_calculate_stage_22_logical_op__oe__oe$107 } { \core_calculate_stage_22_logical_op__rc__rc_ok$106 \core_calculate_stage_22_logical_op__rc__rc$105 } { \core_calculate_stage_22_logical_op__imm_data__imm_ok$104 \core_calculate_stage_22_logical_op__imm_data__imm$103 } \core_calculate_stage_22_logical_op__fn_unit$102 \core_calculate_stage_22_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_23_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_23_ra \core_calculate_stage_22_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_23_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_23_rb \core_calculate_stage_22_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_23_xer_so 1'0 + assign \core_calculate_stage_23_xer_so \core_calculate_stage_22_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_23_divisor_neg 1'0 + assign \core_calculate_stage_23_divisor_neg \core_calculate_stage_22_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_23_dividend_neg 1'0 + assign \core_calculate_stage_23_dividend_neg \core_calculate_stage_22_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_23_dive_abs_ov32 1'0 + assign \core_calculate_stage_23_dive_abs_ov32 \core_calculate_stage_22_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_23_dive_abs_ov64 1'0 + assign \core_calculate_stage_23_dive_abs_ov64 \core_calculate_stage_22_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_23_div_by_zero 1'0 + assign \core_calculate_stage_23_div_by_zero \core_calculate_stage_22_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_23_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_23_divisor_radicand \core_calculate_stage_22_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_23_operation 2'00 + assign \core_calculate_stage_23_operation \core_calculate_stage_22_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_23_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_23_quotient_root \core_calculate_stage_22_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_23_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_23_root_times_radicand \core_calculate_stage_22_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_23_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_23_compare_lhs \core_calculate_stage_22_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_23_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_23_compare_rhs \core_calculate_stage_22_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 + end + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 + sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul2_muxid + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_23_muxid$133 + sync init + end attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -103805,7 +93294,7 @@ module \mul_pipe2 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul2_mul_op__insn_type + wire width 7 \logical_op__insn_type$170 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -103819,468 +93308,168 @@ module \mul_pipe2 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul2_mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul2_mul_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__write_cr0 + wire width 11 \logical_op__fn_unit$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul2_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul2_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul2_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \mul2_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \mul2_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul2_muxid$20 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" + wire width 64 \logical_op__imm_data__imm$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul2_mul_op__insn_type$21 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" + wire width 1 \logical_op__imm_data__imm_ok$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul2_mul_op__fn_unit$22 + wire width 1 \logical_op__rc__rc$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul2_mul_op__imm_data__imm$23 + wire width 1 \logical_op__rc__rc_ok$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__imm_data__imm_ok$24 + wire width 1 \logical_op__oe__oe$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__rc__rc$25 + wire width 1 \logical_op__oe__oe_ok$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__rc__rc_ok$26 + wire width 1 \logical_op__invert_in$178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__oe__oe$27 + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__oe__oe_ok$28 + wire width 2 \logical_op__input_carry$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__invert_a$29 + wire width 1 \logical_op__invert_out$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__zero_a$30 + wire width 1 \logical_op__write_cr0$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__invert_out$31 + wire width 1 \logical_op__output_carry$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__write_cr0$32 + wire width 1 \logical_op__is_32bit$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__is_32bit$33 + wire width 1 \logical_op__is_signed$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__is_signed$34 + wire width 4 \logical_op__data_len$186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul2_mul_op__insn$35 + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_23_logical_op__insn$151 \core_calculate_stage_23_logical_op__data_len$150 \core_calculate_stage_23_logical_op__is_signed$149 \core_calculate_stage_23_logical_op__is_32bit$148 \core_calculate_stage_23_logical_op__output_carry$147 \core_calculate_stage_23_logical_op__write_cr0$146 \core_calculate_stage_23_logical_op__invert_out$145 \core_calculate_stage_23_logical_op__input_carry$144 \core_calculate_stage_23_logical_op__zero_a$143 \core_calculate_stage_23_logical_op__invert_in$142 { \core_calculate_stage_23_logical_op__oe__oe_ok$141 \core_calculate_stage_23_logical_op__oe__oe$140 } { \core_calculate_stage_23_logical_op__rc__rc_ok$139 \core_calculate_stage_23_logical_op__rc__rc$138 } { \core_calculate_stage_23_logical_op__imm_data__imm_ok$137 \core_calculate_stage_23_logical_op__imm_data__imm$136 } \core_calculate_stage_23_logical_op__fn_unit$135 \core_calculate_stage_23_logical_op__insn_type$134 } + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul2_o + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_23_ra$152 + sync init + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul2_xer_so$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 \mul2_neg_res$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \mul2_neg_res32$38 - cell \mul2 \mul2 - connect \muxid \mul2_muxid - connect \mul_op__insn_type \mul2_mul_op__insn_type - connect \mul_op__fn_unit \mul2_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul2_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm_ok - connect \mul_op__rc__rc \mul2_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul2_mul_op__rc__rc_ok - connect \mul_op__oe__oe \mul2_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul2_mul_op__oe__oe_ok - connect \mul_op__invert_a \mul2_mul_op__invert_a - connect \mul_op__zero_a \mul2_mul_op__zero_a - connect \mul_op__invert_out \mul2_mul_op__invert_out - connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 - connect \mul_op__is_32bit \mul2_mul_op__is_32bit - connect \mul_op__is_signed \mul2_mul_op__is_signed - connect \mul_op__insn \mul2_mul_op__insn - connect \ra \mul2_ra - connect \rb \mul2_rb - connect \xer_so \mul2_xer_so - connect \neg_res \mul2_neg_res - connect \neg_res32 \mul2_neg_res32 - connect \muxid$1 \mul2_muxid$20 - connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$21 - connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$22 - connect \mul_op__imm_data__imm$4 \mul2_mul_op__imm_data__imm$23 - connect \mul_op__imm_data__imm_ok$5 \mul2_mul_op__imm_data__imm_ok$24 - connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$25 - connect \mul_op__rc__rc_ok$7 \mul2_mul_op__rc__rc_ok$26 - connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$27 - connect \mul_op__oe__oe_ok$9 \mul2_mul_op__oe__oe_ok$28 - connect \mul_op__invert_a$10 \mul2_mul_op__invert_a$29 - connect \mul_op__zero_a$11 \mul2_mul_op__zero_a$30 - connect \mul_op__invert_out$12 \mul2_mul_op__invert_out$31 - connect \mul_op__write_cr0$13 \mul2_mul_op__write_cr0$32 - connect \mul_op__is_32bit$14 \mul2_mul_op__is_32bit$33 - connect \mul_op__is_signed$15 \mul2_mul_op__is_signed$34 - connect \mul_op__insn$16 \mul2_mul_op__insn$35 - connect \o \mul2_o - connect \xer_so$17 \mul2_xer_so$36 - connect \neg_res$18 \mul2_neg_res$37 - connect \neg_res32$19 \mul2_neg_res32$38 + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_23_rb$153 + sync init end - process $group_0 - assign \mul2_muxid 2'00 - assign \mul2_muxid \muxid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_23_xer_so$154 sync init end - process $group_1 - assign \mul2_mul_op__insn_type 7'0000000 - assign \mul2_mul_op__fn_unit 11'00000000000 - assign \mul2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul2_mul_op__imm_data__imm_ok 1'0 - assign \mul2_mul_op__rc__rc 1'0 - assign \mul2_mul_op__rc__rc_ok 1'0 - assign \mul2_mul_op__oe__oe 1'0 - assign \mul2_mul_op__oe__oe_ok 1'0 - assign \mul2_mul_op__invert_a 1'0 - assign \mul2_mul_op__zero_a 1'0 - assign \mul2_mul_op__invert_out 1'0 - assign \mul2_mul_op__write_cr0 1'0 - assign \mul2_mul_op__is_32bit 1'0 - assign \mul2_mul_op__is_signed 1'0 - assign \mul2_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__invert_out \mul2_mul_op__zero_a \mul2_mul_op__invert_a { \mul2_mul_op__oe__oe_ok \mul2_mul_op__oe__oe } { \mul2_mul_op__rc__rc_ok \mul2_mul_op__rc__rc } { \mul2_mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm } \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_23_divisor_neg$155 sync init end - process $group_16 - assign \mul2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul2_ra \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_23_dividend_neg$156 sync init end - process $group_17 - assign \mul2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul2_rb \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_23_dive_abs_ov32$157 sync init end - process $group_18 - assign \mul2_xer_so 1'0 - assign \mul2_xer_so \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_23_dive_abs_ov64$158 sync init end - process $group_19 - assign \mul2_neg_res 1'0 - assign \mul2_neg_res \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_23_div_by_zero$159 sync init end - process $group_20 - assign \mul2_neg_res32 1'0 - assign \mul2_neg_res32 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_23_divisor_radicand$160 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$39 - process $group_21 - assign \p_valid_i$39 1'0 - assign \p_valid_i$39 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_23_operation$161 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_22 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_23_quotient_root$162 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$39 - connect \B \p_ready_o - connect \Y $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_23_root_times_radicand$163 + sync init end - process $group_23 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_23_compare_lhs$164 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$42 - process $group_24 - assign \muxid$42 2'00 - assign \muxid$42 \mul2_muxid$20 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$43 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__zero_a$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_out$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$57 - process $group_25 - assign \mul_op__insn_type$43 7'0000000 - assign \mul_op__fn_unit$44 11'00000000000 - assign \mul_op__imm_data__imm$45 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$46 1'0 - assign \mul_op__rc__rc$47 1'0 - assign \mul_op__rc__rc_ok$48 1'0 - assign \mul_op__oe__oe$49 1'0 - assign \mul_op__oe__oe_ok$50 1'0 - assign \mul_op__invert_a$51 1'0 - assign \mul_op__zero_a$52 1'0 - assign \mul_op__invert_out$53 1'0 - assign \mul_op__write_cr0$54 1'0 - assign \mul_op__is_32bit$55 1'0 - assign \mul_op__is_signed$56 1'0 - assign \mul_op__insn$57 32'00000000000000000000000000000000 - assign { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 } { \mul2_mul_op__insn$35 \mul2_mul_op__is_signed$34 \mul2_mul_op__is_32bit$33 \mul2_mul_op__write_cr0$32 \mul2_mul_op__invert_out$31 \mul2_mul_op__zero_a$30 \mul2_mul_op__invert_a$29 { \mul2_mul_op__oe__oe_ok$28 \mul2_mul_op__oe__oe$27 } { \mul2_mul_op__rc__rc_ok$26 \mul2_mul_op__rc__rc$25 } { \mul2_mul_op__imm_data__imm_ok$24 \mul2_mul_op__imm_data__imm$23 } \mul2_mul_op__fn_unit$22 \mul2_mul_op__insn_type$21 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \o$58 - process $group_40 - assign \o$58 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \o$58 \mul2_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$59 - process $group_41 - assign \xer_so$59 1'0 - assign \xer_so$59 \mul2_xer_so$36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 \neg_res$60 - process $group_42 - assign \neg_res$60 1'0 - assign \neg_res$60 \mul2_neg_res$37 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \neg_res32$61 - process $group_43 - assign \neg_res32$61 1'0 - assign \neg_res32$61 \mul2_neg_res32$38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_23_compare_rhs$165 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy$next - process $group_44 + process $group_168 assign \r_busy$next \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } @@ -104301,168 +93490,337 @@ module \mul_pipe2 sync posedge \coresync_clk update \r_busy \r_busy$next end - process $group_45 + process $group_169 assign \muxid$1$next \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$1$next \muxid$42 + assign \muxid$1$next \muxid$169 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$1$next \muxid$42 + assign \muxid$1$next \muxid$169 end sync init update \muxid$1 2'00 sync posedge \coresync_clk update \muxid$1 \muxid$1$next end - process $group_46 - assign \mul_op__insn_type$2$next \mul_op__insn_type$2 - assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3 - assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4 - assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5 - assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6 - assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7 - assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8 - assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9 - assign \mul_op__invert_a$10$next \mul_op__invert_a$10 - assign \mul_op__zero_a$11$next \mul_op__zero_a$11 - assign \mul_op__invert_out$12$next \mul_op__invert_out$12 - assign \mul_op__write_cr0$13$next \mul_op__write_cr0$13 - assign \mul_op__is_32bit$14$next \mul_op__is_32bit$14 - assign \mul_op__is_signed$15$next \mul_op__is_signed$15 - assign \mul_op__insn$16$next \mul_op__insn$16 + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 } + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 } + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5$next 1'0 - assign \mul_op__rc__rc$6$next 1'0 - assign \mul_op__rc__rc_ok$7$next 1'0 - assign \mul_op__oe__oe$8$next 1'0 - assign \mul_op__oe__oe_ok$9$next 1'0 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 end sync init - update \mul_op__insn_type$2 7'0000000 - update \mul_op__fn_unit$3 11'00000000000 - update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \mul_op__imm_data__imm_ok$5 1'0 - update \mul_op__rc__rc$6 1'0 - update \mul_op__rc__rc_ok$7 1'0 - update \mul_op__oe__oe$8 1'0 - update \mul_op__oe__oe_ok$9 1'0 - update \mul_op__invert_a$10 1'0 - update \mul_op__zero_a$11 1'0 - update \mul_op__invert_out$12 1'0 - update \mul_op__write_cr0$13 1'0 - update \mul_op__is_32bit$14 1'0 - update \mul_op__is_signed$15 1'0 - update \mul_op__insn$16 32'00000000000000000000000000000000 + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 sync posedge \coresync_clk - update \mul_op__insn_type$2 \mul_op__insn_type$2$next - update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next - update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next - update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next - update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next - update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next - update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next - update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next - update \mul_op__invert_a$10 \mul_op__invert_a$10$next - update \mul_op__zero_a$11 \mul_op__zero_a$11$next - update \mul_op__invert_out$12 \mul_op__invert_out$12$next - update \mul_op__write_cr0$13 \mul_op__write_cr0$13$next - update \mul_op__is_32bit$14 \mul_op__is_32bit$14$next - update \mul_op__is_signed$15 \mul_op__is_signed$15$next - update \mul_op__insn$16 \mul_op__insn$16$next + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next end - process $group_61 - assign \o$next \o + process $group_188 + assign \ra$20$next \ra$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \o$next \o$58 + assign \ra$20$next \ra$188 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \o$next \o$58 + assign \ra$20$next \ra$188 end sync init - update \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \o \o$next + update \ra$20 \ra$20$next end - process $group_62 - assign \xer_so$17$next \xer_so$17 + process $group_189 + assign \rb$21$next \rb$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \xer_so$17$next \xer_so$59 + assign \rb$21$next \rb$189 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \xer_so$17$next \xer_so$59 + assign \rb$21$next \rb$189 end sync init - update \xer_so$17 1'0 + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \xer_so$17 \xer_so$17$next + update \rb$21 \rb$21$next end - process $group_63 - assign \neg_res$18$next \neg_res$18 + process $group_190 + assign \xer_so$22$next \xer_so$22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \neg_res$18$next \neg_res$60 + assign \xer_so$22$next \xer_so$190 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \neg_res$18$next \neg_res$60 + assign \xer_so$22$next \xer_so$190 end sync init - update \neg_res$18 1'0 + update \xer_so$22 1'0 sync posedge \coresync_clk - update \neg_res$18 \neg_res$18$next + update \xer_so$22 \xer_so$22$next end - process $group_64 - assign \neg_res32$19$next \neg_res32$19 + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \neg_res32$19$next \neg_res32$61 + assign \divisor_neg$23$next \divisor_neg$191 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \neg_res32$19$next \neg_res32$61 + assign \divisor_neg$23$next \divisor_neg$191 end sync init - update \neg_res32$19 1'0 + update \divisor_neg$23 1'0 sync posedge \coresync_clk - update \neg_res32$19 \neg_res32$19$next + update \divisor_neg$23 \divisor_neg$23$next end - process $group_65 + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 assign \n_valid_o 1'0 assign \n_valid_o \r_busy sync init end - process $group_66 + process $group_203 assign \p_ready_o 1'0 assign \p_ready_o \n_i_rdy_data sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.p" -module \p$94 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.p" +module \p$182 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" @@ -104489,8 +93847,8 @@ module \p$94 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n" -module \n$95 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.n" +module \n$183 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" @@ -104517,8 +93875,602 @@ module \n$95 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3" -module \mul3 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_24.core.trial0" +module \trial0$185 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_24.core.trial1" +module \trial1$186 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_24.core.pe" +module \pe$187 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_24.core" +module \core$184 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$185 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$186 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$187 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'100111 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_24" +module \core_calculate_stage_24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -104595,7 +94547,7 @@ module \mul3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -104609,41 +94561,73 @@ module \mul3 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \mul_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \mul_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \mul_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \mul_op__invert_a + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__zero_a + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__invert_out + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \mul_op__write_cr0 + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \mul_op__is_32bit + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \mul_op__is_signed + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 15 \mul_op__insn + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 input 16 \o + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 17 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 input 18 \neg_res + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 19 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -104718,7 +94702,7 @@ module \mul3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 20 \mul_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -104732,297 +94716,834 @@ module \mul3 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 21 \mul_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 22 \mul_op__imm_data__imm$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 23 \mul_op__imm_data__imm_ok$5 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__rc__rc$6 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \mul_op__rc__rc_ok$7 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \mul_op__oe__oe$8 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \mul_op__oe__oe_ok$9 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \mul_op__invert_a$10 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \mul_op__zero_a$11 + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \mul_op__invert_out$12 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \mul_op__write_cr0$13 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \mul_op__is_32bit$14 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \mul_op__is_signed$15 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 34 \mul_op__insn$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 35 \o$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 36 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 37 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 38 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 39 \xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" - wire width 1 \is_32bit + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$184 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end process $group_0 - assign \is_32bit 1'0 - assign \is_32bit \mul_op__is_32bit + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" - wire width 129 \mul_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 130 - connect \A \o - connect \Y $20 + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 130 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 130 - connect \A \o - connect \Y $22 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $25 - parameter \WIDTH 130 - connect \A $22 - connect \B $20 - connect \S \neg_res - connect \Y $24 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - connect $19 $24 - process $group_1 - assign \mul_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \mul_o $19 [128:0] + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - wire width 1 $verilog_initial_trigger - process $group_2 - assign \o_ok 1'0 - assign \o_ok 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init - update $verilog_initial_trigger 1'0 end - process $group_3 - assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" - switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" - attribute \nmigen.decoding "OP_MUL_H32/52" - case 7'0110100 - assign \o$17 { \mul_o [63:32] \mul_o [63:32] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" - attribute \nmigen.decoding "OP_MUL_H64/51" - case 7'0110011 - assign \o$17 \mul_o [127:64] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" - attribute \nmigen.decoding "" - case - assign \o$17 \mul_o [63:0] - end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:58" - wire width 1 \mul_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" - cell $reduce_bool $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 33 - parameter \Y_WIDTH 1 - connect \A \mul_o [63:31] - connect \Y $26 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" - cell $reduce_and $30 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_25.core.trial0" +module \trial0$189 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 33 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \mul_o [63:31] - connect \Y $29 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" - cell $not $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $29 - connect \Y $28 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" - cell $and $33 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $26 - connect \B $28 - connect \Y $32 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" - cell $reduce_bool $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 parameter \A_WIDTH 65 - parameter \Y_WIDTH 1 - connect \A \mul_o [127:63] - connect \Y $34 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100110 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" - cell $reduce_and $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 1 - connect \A \mul_o [127:63] - connect \Y $37 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" - cell $not $39 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_25.core.trial1" +module \trial1$190 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $37 - connect \Y $36 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" - cell $and $41 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $34 - connect \B $36 - connect \Y $40 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_4 - assign \mul_ov 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" - switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" - attribute \nmigen.decoding "OP_MUL_H32/52" - case 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" - attribute \nmigen.decoding "OP_MUL_H64/51" - case 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59" - switch { \is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59" - case 1'1 - assign \mul_ov $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:64" - case - assign \mul_ov $40 - end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 end sync init end - process $group_5 - assign \xer_ov 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" - switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" - attribute \nmigen.decoding "OP_MUL_H32/52" - case 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" - attribute \nmigen.decoding "OP_MUL_H64/51" - case 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" - attribute \nmigen.decoding "" - case - assign \xer_ov { \mul_ov \mul_ov } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100110 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] end sync init end - process $group_6 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" - switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" - attribute \nmigen.decoding "OP_MUL_H32/52" - case 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" - attribute \nmigen.decoding "OP_MUL_H64/51" - case 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" - attribute \nmigen.decoding "" - case - assign \xer_ov_ok 1'1 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_25.core.pe" +module \pe$191 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_25.core" +module \core$188 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$189 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$190 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$191 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end process $group_7 - assign \xer_so$18 1'0 - assign \xer_so$18 \xer_so + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger process $group_8 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end process $group_9 - assign \mul_op__insn_type$2 7'0000000 - assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5 1'0 - assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__rc_ok$7 1'0 - assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__oe_ok$9 1'0 - assign \mul_op__invert_a$10 1'0 - assign \mul_op__zero_a$11 1'0 - assign \mul_op__invert_out$12 1'0 - assign \mul_op__write_cr0$13 1'0 - assign \mul_op__is_32bit$14 1'0 - assign \mul_op__is_signed$15 1'0 - assign \mul_op__insn$16 32'00000000000000000000000000000000 - assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'100110 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output" -module \output$96 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_25" +module \core_calculate_stage_25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -105099,7 +95620,7 @@ module \output$96 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -105113,45 +95634,73 @@ module \output$96 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \mul_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \mul_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \mul_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \mul_op__invert_a + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__zero_a + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__invert_out + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \mul_op__write_cr0 + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \mul_op__is_32bit + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \mul_op__is_signed + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 15 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 16 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 17 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 18 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 19 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 20 \xer_so + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -105226,7 +95775,7 @@ module \output$96 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \mul_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -105240,409 +95789,836 @@ module \output$96 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 23 \mul_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \mul_op__imm_data__imm$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \mul_op__imm_data__imm_ok$5 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \mul_op__rc__rc$6 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \mul_op__rc__rc_ok$7 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \mul_op__oe__oe$8 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \mul_op__oe__oe_ok$9 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \mul_op__invert_a$10 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \mul_op__zero_a$11 + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \mul_op__invert_out$12 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \mul_op__write_cr0$13 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \mul_op__is_32bit$14 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \mul_op__is_signed$15 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 36 \mul_op__insn$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 37 \o$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 38 \o_ok$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 39 \cr_a$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 40 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 41 \xer_ov$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 42 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 43 \xer_so$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 44 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 65 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - wire width 64 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $not $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $24 + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$188 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" - cell $pos $26 + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_26.core.trial0" +module \trial0$193 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A $24 - connect \Y $23 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 65 - connect \A \o - connect \Y $27 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end process $group_0 - assign \o$22 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" - switch { \mul_op__invert_out } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \o$22 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - case - assign \o$22 $27 + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" - wire width 64 \target - process $group_1 - assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$22 [63:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" - wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \mul_op__insn_type - connect \B 7'0001010 - connect \Y $29 - end - process $group_2 - assign \is_cmp 1'0 - assign \is_cmp $29 - sync init + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" - wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \mul_op__insn_type - connect \B 7'0001100 - connect \Y $31 - end - process $group_3 - assign \is_cmpeqb 1'0 - assign \is_cmpeqb $31 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" - wire width 1 \msb_test - process $group_4 - assign \msb_test 1'0 - assign \msb_test \target [63] - sync init + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $33 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_5 - assign \is_nzero 1'0 - assign \is_nzero $33 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" - wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $36 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_26.core.trial1" +module \trial1$194 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $35 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $35 - connect \Y $37 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_6 - assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_positive $37 + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $39 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $42 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $39 - connect \Y $41 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100101 + connect \Y $8 end - process $group_7 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \is_negative $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_negative \msb_test + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - cell $not $44 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_26.core.pe" +module \pe$195 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $43 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_26.core" +module \core$192 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$193 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$194 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$195 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger process $group_8 - assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - case 1'1 - assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - case - assign \cr0 { \is_negative \is_positive $43 \xer_so$21 } - end + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end process $group_9 - assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$17 \o$22 [63:0] + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 process $group_10 - assign \o_ok$18 1'0 - assign \o_ok$18 \o_ok + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 process $group_11 - assign \cr_a$19 4'0000 - assign \cr_a$19 \cr0 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init end process $group_12 - assign \cr_a_ok 1'0 - assign \cr_a_ok \mul_op__write_cr0 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end process $group_13 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end process $group_14 - assign \mul_op__insn_type$2 7'0000000 - assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5 1'0 - assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__rc_ok$7 1'0 - assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__oe_ok$9 1'0 - assign \mul_op__invert_a$10 1'0 - assign \mul_op__zero_a$11 1'0 - assign \mul_op__invert_out$12 1'0 - assign \mul_op__write_cr0$13 1'0 - assign \mul_op__is_32bit$14 1'0 - assign \mul_op__is_signed$15 1'0 - assign \mul_op__insn$16 32'00000000000000000000000000000000 - assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" - wire width 1 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - cell $and $46 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \mul_op__oe__oe - connect \B \mul_op__oe__oe_ok - connect \Y $45 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_29 - assign \oe 1'0 - assign \oe $45 + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" - wire width 1 \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" - cell $or $48 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $47 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_30 - assign \so 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \so $47 - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - process $group_31 - assign \xer_so$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_so$21 \so - end - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_32 - assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_so_ok 1'1 - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - process $group_33 - assign \xer_ov$20 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_ov$20 \xer_ov - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - process $group_34 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - case 1'1 - assign \xer_ov_ok 1'1 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'100101 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3" -module \mul_pipe3 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_26" +module \core_calculate_stage_26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -105717,7 +96693,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \mul_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -105731,49 +96707,73 @@ module \mul_pipe3 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \mul_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \mul_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \mul_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \mul_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \mul_op__invert_a + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \mul_op__zero_a + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \mul_op__invert_out + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \mul_op__write_cr0 + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \mul_op__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \mul_op__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 19 \mul_op__insn + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 input 20 \o + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 input 22 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 input 23 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 24 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 25 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 26 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -105848,9 +96848,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 27 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$2$next + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -105864,165 +96862,898 @@ module \mul_pipe3 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 28 \mul_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 29 \mul_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \mul_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \mul_op__rc__rc_ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$8$next + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \mul_op__oe__oe_ok$9 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \mul_op__invert_a$10 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_a$10$next + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \mul_op__zero_a$11 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__zero_a$11$next + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \mul_op__invert_out$12 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_out$12$next + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \mul_op__write_cr0$13 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$13$next + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \mul_op__is_32bit$14 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$14$next + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \mul_op__is_signed$15 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$15$next + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \mul_op__insn$16 + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 42 \o$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 43 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 44 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 45 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 46 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 48 \xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$next - cell \p$94 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$192 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - cell \n$95 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul3_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_27.core.trial0" +module \trial0$197 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100100 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_27.core.trial1" +module \trial1$198 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100100 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_27.core.pe" +module \pe$199 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_27.core" +module \core$196 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$197 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$198 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$199 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'100100 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6.core_calculate_stage_27" +module \core_calculate_stage_27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" attribute \enum_value_0111101 "OP_SHR" attribute \enum_value_0111110 "OP_SYNC" attribute \enum_value_0111111 "OP_TRAP" @@ -106035,7 +97766,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul3_mul_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -106049,41 +97780,73 @@ module \mul_pipe3 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul3_mul_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul3_mul_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__zero_a + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__invert_out + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__write_cr0 + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__is_32bit + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__is_signed + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul3_mul_op__insn + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul3_o + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 \mul3_neg_res + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul3_muxid$19 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -106158,7 +97921,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul3_mul_op__insn_type$20 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -106172,87 +97935,250 @@ module \mul_pipe3 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul3_mul_op__fn_unit$21 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul3_mul_op__imm_data__imm$22 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__imm_data__imm_ok$23 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__rc__rc$24 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__rc__rc_ok$25 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__oe__oe$26 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__oe__oe_ok$27 + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__invert_a$28 + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__zero_a$29 + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__invert_out$30 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__write_cr0$31 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__is_32bit$32 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul3_mul_op__is_signed$33 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul3_mul_op__insn$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \mul3_o$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul3_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \mul3_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul3_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul3_xer_so$36 - cell \mul3 \mul3 - connect \muxid \mul3_muxid - connect \mul_op__insn_type \mul3_mul_op__insn_type - connect \mul_op__fn_unit \mul3_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul3_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm_ok - connect \mul_op__rc__rc \mul3_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul3_mul_op__rc__rc_ok - connect \mul_op__oe__oe \mul3_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul3_mul_op__oe__oe_ok - connect \mul_op__invert_a \mul3_mul_op__invert_a - connect \mul_op__zero_a \mul3_mul_op__zero_a - connect \mul_op__invert_out \mul3_mul_op__invert_out - connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 - connect \mul_op__is_32bit \mul3_mul_op__is_32bit - connect \mul_op__is_signed \mul3_mul_op__is_signed - connect \mul_op__insn \mul3_mul_op__insn - connect \o \mul3_o - connect \xer_so \mul3_xer_so - connect \neg_res \mul3_neg_res - connect \muxid$1 \mul3_muxid$19 - connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$20 - connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$21 - connect \mul_op__imm_data__imm$4 \mul3_mul_op__imm_data__imm$22 - connect \mul_op__imm_data__imm_ok$5 \mul3_mul_op__imm_data__imm_ok$23 - connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$24 - connect \mul_op__rc__rc_ok$7 \mul3_mul_op__rc__rc_ok$25 - connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$26 - connect \mul_op__oe__oe_ok$9 \mul3_mul_op__oe__oe_ok$27 - connect \mul_op__invert_a$10 \mul3_mul_op__invert_a$28 - connect \mul_op__zero_a$11 \mul3_mul_op__zero_a$29 - connect \mul_op__invert_out$12 \mul3_mul_op__invert_out$30 - connect \mul_op__write_cr0$13 \mul3_mul_op__write_cr0$31 - connect \mul_op__is_32bit$14 \mul3_mul_op__is_32bit$32 - connect \mul_op__is_signed$15 \mul3_mul_op__is_signed$33 - connect \mul_op__insn$16 \mul3_mul_op__insn$34 - connect \o$17 \mul3_o$35 - connect \o_ok \mul3_o_ok - connect \xer_ov \mul3_xer_ov - connect \xer_ov_ok \mul3_xer_ov_ok - connect \xer_so$18 \mul3_xer_so$36 + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$196 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_6" +module \pipe_middle_6 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid + wire width 2 input 4 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -106327,7 +98253,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_mul_op__insn_type + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -106341,45 +98267,79 @@ module \mul_pipe3 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_mul_op__fn_unit + wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_mul_op__imm_data__imm + wire width 64 input 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__imm_data__imm_ok + wire width 1 input 8 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__rc__rc + wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__rc__rc_ok + wire width 1 input 10 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__oe__oe + wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__oe__oe_ok + wire width 1 input 12 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__invert_a + wire width 1 input 13 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__zero_a + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__invert_out + wire width 2 input 15 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__write_cr0 + wire width 1 input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__is_32bit + wire width 1 input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__is_signed + wire width 1 input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$37 + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -106454,7 +98414,9 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_mul_op__insn_type$38 + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -106468,243 +98430,143 @@ module \mul_pipe3 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_mul_op__fn_unit$39 + wire width 11 output 41 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_mul_op__imm_data__imm$40 + wire width 11 \logical_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__imm_data__imm_ok$41 + wire width 64 output 42 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__rc__rc$42 + wire width 64 \logical_op__imm_data__imm$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__rc__rc_ok$43 + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__oe__oe$44 + wire width 1 \logical_op__imm_data__imm_ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__oe__oe_ok$45 + wire width 1 output 44 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__invert_a$46 + wire width 1 \logical_op__rc__rc$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__zero_a$47 + wire width 1 output 45 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__invert_out$48 + wire width 1 \logical_op__rc__rc_ok$7$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__write_cr0$49 + wire width 1 output 46 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__is_32bit$50 + wire width 1 \logical_op__oe__oe$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_mul_op__is_signed$51 + wire width 1 output 47 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_mul_op__insn$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so_ok - cell \output$96 \output - connect \muxid \output_muxid - connect \mul_op__insn_type \output_mul_op__insn_type - connect \mul_op__fn_unit \output_mul_op__fn_unit - connect \mul_op__imm_data__imm \output_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm_ok - connect \mul_op__rc__rc \output_mul_op__rc__rc - connect \mul_op__rc__rc_ok \output_mul_op__rc__rc_ok - connect \mul_op__oe__oe \output_mul_op__oe__oe - connect \mul_op__oe__oe_ok \output_mul_op__oe__oe_ok - connect \mul_op__invert_a \output_mul_op__invert_a - connect \mul_op__zero_a \output_mul_op__zero_a - connect \mul_op__invert_out \output_mul_op__invert_out - connect \mul_op__write_cr0 \output_mul_op__write_cr0 - connect \mul_op__is_32bit \output_mul_op__is_32bit - connect \mul_op__is_signed \output_mul_op__is_signed - connect \mul_op__insn \output_mul_op__insn - connect \o \output_o - connect \o_ok \output_o_ok - connect \cr_a \output_cr_a - connect \xer_ov \output_xer_ov - connect \xer_so \output_xer_so - connect \muxid$1 \output_muxid$37 - connect \mul_op__insn_type$2 \output_mul_op__insn_type$38 - connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$39 - connect \mul_op__imm_data__imm$4 \output_mul_op__imm_data__imm$40 - connect \mul_op__imm_data__imm_ok$5 \output_mul_op__imm_data__imm_ok$41 - connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$42 - connect \mul_op__rc__rc_ok$7 \output_mul_op__rc__rc_ok$43 - connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$44 - connect \mul_op__oe__oe_ok$9 \output_mul_op__oe__oe_ok$45 - connect \mul_op__invert_a$10 \output_mul_op__invert_a$46 - connect \mul_op__zero_a$11 \output_mul_op__zero_a$47 - connect \mul_op__invert_out$12 \output_mul_op__invert_out$48 - connect \mul_op__write_cr0$13 \output_mul_op__write_cr0$49 - connect \mul_op__is_32bit$14 \output_mul_op__is_32bit$50 - connect \mul_op__is_signed$15 \output_mul_op__is_signed$51 - connect \mul_op__insn$16 \output_mul_op__insn$52 - connect \o$17 \output_o$53 - connect \o_ok$18 \output_o_ok$54 - connect \cr_a$19 \output_cr_a$55 - connect \cr_a_ok \output_cr_a_ok - connect \xer_ov$20 \output_xer_ov$56 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so$21 \output_xer_so$57 - connect \xer_so_ok \output_xer_so_ok - end - process $group_0 - assign \mul3_muxid 2'00 - assign \mul3_muxid \muxid - sync init - end - process $group_1 - assign \mul3_mul_op__insn_type 7'0000000 - assign \mul3_mul_op__fn_unit 11'00000000000 - assign \mul3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul3_mul_op__imm_data__imm_ok 1'0 - assign \mul3_mul_op__rc__rc 1'0 - assign \mul3_mul_op__rc__rc_ok 1'0 - assign \mul3_mul_op__oe__oe 1'0 - assign \mul3_mul_op__oe__oe_ok 1'0 - assign \mul3_mul_op__invert_a 1'0 - assign \mul3_mul_op__zero_a 1'0 - assign \mul3_mul_op__invert_out 1'0 - assign \mul3_mul_op__write_cr0 1'0 - assign \mul3_mul_op__is_32bit 1'0 - assign \mul3_mul_op__is_signed 1'0 - assign \mul3_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__invert_out \mul3_mul_op__zero_a \mul3_mul_op__invert_a { \mul3_mul_op__oe__oe_ok \mul3_mul_op__oe__oe } { \mul3_mul_op__rc__rc_ok \mul3_mul_op__rc__rc } { \mul3_mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm } \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } - sync init - end - process $group_16 - assign \mul3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \mul3_o \o - sync init - end - process $group_17 - assign \mul3_xer_so 1'0 - assign \mul3_xer_so \xer_so - sync init - end - process $group_18 - assign \mul3_neg_res 1'0 - assign \mul3_neg_res \neg_res - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \neg_res32$58 - process $group_19 - assign \neg_res32$58 1'0 - assign \neg_res32$58 \neg_res32 - sync init - end - process $group_20 - assign \output_muxid 2'00 - assign \output_muxid \mul3_muxid$19 - sync init - end - process $group_21 - assign \output_mul_op__insn_type 7'0000000 - assign \output_mul_op__fn_unit 11'00000000000 - assign \output_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_mul_op__imm_data__imm_ok 1'0 - assign \output_mul_op__rc__rc 1'0 - assign \output_mul_op__rc__rc_ok 1'0 - assign \output_mul_op__oe__oe 1'0 - assign \output_mul_op__oe__oe_ok 1'0 - assign \output_mul_op__invert_a 1'0 - assign \output_mul_op__zero_a 1'0 - assign \output_mul_op__invert_out 1'0 - assign \output_mul_op__write_cr0 1'0 - assign \output_mul_op__is_32bit 1'0 - assign \output_mul_op__is_signed 1'0 - assign \output_mul_op__insn 32'00000000000000000000000000000000 - assign { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__invert_out \output_mul_op__zero_a \output_mul_op__invert_a { \output_mul_op__oe__oe_ok \output_mul_op__oe__oe } { \output_mul_op__rc__rc_ok \output_mul_op__rc__rc } { \output_mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm } \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$34 \mul3_mul_op__is_signed$33 \mul3_mul_op__is_32bit$32 \mul3_mul_op__write_cr0$31 \mul3_mul_op__invert_out$30 \mul3_mul_op__zero_a$29 \mul3_mul_op__invert_a$28 { \mul3_mul_op__oe__oe_ok$27 \mul3_mul_op__oe__oe$26 } { \mul3_mul_op__rc__rc_ok$25 \mul3_mul_op__rc__rc$24 } { \mul3_mul_op__imm_data__imm_ok$23 \mul3_mul_op__imm_data__imm$22 } \mul3_mul_op__fn_unit$21 \mul3_mul_op__insn_type$20 } - sync init - end - process $group_36 - assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_o_ok 1'0 - assign { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$35 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$61 - process $group_38 - assign \output_cr_a 4'0000 - assign \cr_a_ok$59 1'0 - assign { \cr_a_ok$59 \output_cr_a } { \cr_a_ok$61 \cr_a$60 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$62 - process $group_40 - assign \output_xer_ov 2'00 - assign \xer_ov_ok$62 1'0 - assign { \xer_ov_ok$62 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$64 - process $group_42 - assign \output_xer_so 1'0 - assign \xer_so_ok$63 1'0 - assign { \xer_so_ok$63 \output_xer_so } { \xer_so_ok$64 \mul3_xer_so$36 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$65 - process $group_44 - assign \p_valid_i$65 1'0 - assign \p_valid_i$65 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_45 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$65 - connect \B \p_ready_o - connect \Y $66 + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$182 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_46 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $66 - sync init + cell \n$183 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$68 - process $group_47 - assign \muxid$68 2'00 - assign \muxid$68 \output_muxid$37 - sync init - end + wire width 2 \core_calculate_stage_24_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -106779,7 +98641,7 @@ module \mul_pipe3 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$69 + wire width 7 \core_calculate_stage_24_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -106793,338 +98655,73 @@ module \mul_pipe3 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$70 + wire width 11 \core_calculate_stage_24_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$71 + wire width 64 \core_calculate_stage_24_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$72 + wire width 1 \core_calculate_stage_24_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$73 + wire width 1 \core_calculate_stage_24_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$74 + wire width 1 \core_calculate_stage_24_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$75 + wire width 1 \core_calculate_stage_24_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$76 + wire width 1 \core_calculate_stage_24_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_a$77 + wire width 1 \core_calculate_stage_24_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__zero_a$78 + wire width 1 \core_calculate_stage_24_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_out$79 + wire width 2 \core_calculate_stage_24_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$80 + wire width 1 \core_calculate_stage_24_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$81 + wire width 1 \core_calculate_stage_24_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$82 + wire width 1 \core_calculate_stage_24_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$83 - process $group_48 - assign \mul_op__insn_type$69 7'0000000 - assign \mul_op__fn_unit$70 11'00000000000 - assign \mul_op__imm_data__imm$71 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$72 1'0 - assign \mul_op__rc__rc$73 1'0 - assign \mul_op__rc__rc_ok$74 1'0 - assign \mul_op__oe__oe$75 1'0 - assign \mul_op__oe__oe_ok$76 1'0 - assign \mul_op__invert_a$77 1'0 - assign \mul_op__zero_a$78 1'0 - assign \mul_op__invert_out$79 1'0 - assign \mul_op__write_cr0$80 1'0 - assign \mul_op__is_32bit$81 1'0 - assign \mul_op__is_signed$82 1'0 - assign \mul_op__insn$83 32'00000000000000000000000000000000 - assign { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 } { \output_mul_op__insn$52 \output_mul_op__is_signed$51 \output_mul_op__is_32bit$50 \output_mul_op__write_cr0$49 \output_mul_op__invert_out$48 \output_mul_op__zero_a$47 \output_mul_op__invert_a$46 { \output_mul_op__oe__oe_ok$45 \output_mul_op__oe__oe$44 } { \output_mul_op__rc__rc_ok$43 \output_mul_op__rc__rc$42 } { \output_mul_op__imm_data__imm_ok$41 \output_mul_op__imm_data__imm$40 } \output_mul_op__fn_unit$39 \output_mul_op__insn_type$38 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$85 - process $group_63 - assign \o$84 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$85 1'0 - assign { \o_ok$85 \o$84 } { \output_o_ok$54 \output_o$53 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$87 - process $group_65 - assign \cr_a$86 4'0000 - assign \cr_a_ok$87 1'0 - assign { \cr_a_ok$87 \cr_a$86 } { \output_cr_a_ok \output_cr_a$55 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$89 - process $group_67 - assign \xer_ov$88 2'00 - assign \xer_ov_ok$89 1'0 - assign { \xer_ov_ok$89 \xer_ov$88 } { \output_xer_ov_ok \output_xer_ov$56 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$91 - process $group_69 - assign \xer_so$90 1'0 - assign \xer_so_ok$91 1'0 - assign { \xer_so_ok$91 \xer_so$90 } { \output_xer_so_ok \output_xer_so$57 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_71 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_72 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$68 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$68 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_73 - assign \mul_op__insn_type$2$next \mul_op__insn_type$2 - assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3 - assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4 - assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5 - assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6 - assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7 - assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8 - assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9 - assign \mul_op__invert_a$10$next \mul_op__invert_a$10 - assign \mul_op__zero_a$11$next \mul_op__zero_a$11 - assign \mul_op__invert_out$12$next \mul_op__invert_out$12 - assign \mul_op__write_cr0$13$next \mul_op__write_cr0$13 - assign \mul_op__is_32bit$14$next \mul_op__is_32bit$14 - assign \mul_op__is_signed$15$next \mul_op__is_signed$15 - assign \mul_op__insn$16$next \mul_op__insn$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$5$next 1'0 - assign \mul_op__rc__rc$6$next 1'0 - assign \mul_op__rc__rc_ok$7$next 1'0 - assign \mul_op__oe__oe$8$next 1'0 - assign \mul_op__oe__oe_ok$9$next 1'0 - end - sync init - update \mul_op__insn_type$2 7'0000000 - update \mul_op__fn_unit$3 11'00000000000 - update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \mul_op__imm_data__imm_ok$5 1'0 - update \mul_op__rc__rc$6 1'0 - update \mul_op__rc__rc_ok$7 1'0 - update \mul_op__oe__oe$8 1'0 - update \mul_op__oe__oe_ok$9 1'0 - update \mul_op__invert_a$10 1'0 - update \mul_op__zero_a$11 1'0 - update \mul_op__invert_out$12 1'0 - update \mul_op__write_cr0$13 1'0 - update \mul_op__is_32bit$14 1'0 - update \mul_op__is_signed$15 1'0 - update \mul_op__insn$16 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \mul_op__insn_type$2 \mul_op__insn_type$2$next - update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next - update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next - update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next - update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next - update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next - update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next - update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next - update \mul_op__invert_a$10 \mul_op__invert_a$10$next - update \mul_op__zero_a$11 \mul_op__zero_a$11$next - update \mul_op__invert_out$12 \mul_op__invert_out$12$next - update \mul_op__write_cr0$13 \mul_op__write_cr0$13$next - update \mul_op__is_32bit$14 \mul_op__is_32bit$14$next - update \mul_op__is_signed$15 \mul_op__is_signed$15$next - update \mul_op__insn$16 \mul_op__insn$16$next - end - process $group_88 - assign \o$17$next \o$17 - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$17$next } { \o_ok$85 \o$84 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$17$next } { \o_ok$85 \o$84 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o$17 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o$17 \o$17$next - update \o_ok \o_ok$next - end - process $group_90 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$87 \cr_a$86 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$87 \cr_a$86 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next - end - process $group_92 - assign \xer_ov$next \xer_ov - assign \xer_ov_ok$next \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$89 \xer_ov$88 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$89 \xer_ov$88 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ov_ok$next 1'0 - end - sync init - update \xer_ov 2'00 - update \xer_ov_ok 1'0 - sync posedge \coresync_clk - update \xer_ov \xer_ov$next - update \xer_ov_ok \xer_ov_ok$next - end - process $group_94 - assign \xer_so$18$next \xer_so$18 - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$18$next } { \xer_so_ok$91 \xer_so$90 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$18$next } { \xer_so_ok$91 \xer_so$90 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so$18 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so$18 \xer_so$18$next - update \xer_so_ok \xer_so_ok$next - end - process $group_96 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_97 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \cr_a$60 4'0000 - connect \cr_a_ok$61 1'0 - connect \xer_so_ok$64 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0" -module \alu_mul0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \xer_so_ok - attribute \src "simple/issuer.py:89" - wire width 1 input 5 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 7 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 8 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 9 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 10 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 11 \xer_so + wire width 1 \core_calculate_stage_24_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_24_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_24_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_24_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_24_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_24_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_24_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_24_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_24_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_24_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_24_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_24_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_24_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_24_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_24_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_24_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_24_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_24_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_24_muxid$34 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -107199,7 +98796,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 12 \mul_op__insn_type + wire width 7 \core_calculate_stage_24_logical_op__insn_type$35 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -107213,57 +98810,141 @@ module \alu_mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 13 \mul_op__fn_unit + wire width 11 \core_calculate_stage_24_logical_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_24_logical_op__imm_data__imm$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_24_logical_op__imm_data__imm_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 14 \mul_op__imm_data__imm + wire width 1 \core_calculate_stage_24_logical_op__rc__rc$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \mul_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_24_logical_op__rc__rc_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \mul_op__rc__rc + wire width 1 \core_calculate_stage_24_logical_op__oe__oe$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \mul_op__rc__rc_ok + wire width 1 \core_calculate_stage_24_logical_op__oe__oe_ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \mul_op__oe__oe + wire width 1 \core_calculate_stage_24_logical_op__invert_in$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \mul_op__oe__oe_ok + wire width 1 \core_calculate_stage_24_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_24_logical_op__input_carry$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \mul_op__invert_a + wire width 1 \core_calculate_stage_24_logical_op__invert_out$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 21 \mul_op__zero_a + wire width 1 \core_calculate_stage_24_logical_op__write_cr0$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 22 \mul_op__invert_out + wire width 1 \core_calculate_stage_24_logical_op__output_carry$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 23 \mul_op__write_cr0 + wire width 1 \core_calculate_stage_24_logical_op__is_32bit$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 24 \mul_op__is_32bit + wire width 1 \core_calculate_stage_24_logical_op__is_signed$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 25 \mul_op__is_signed + wire width 4 \core_calculate_stage_24_logical_op__data_len$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 26 \mul_op__insn + wire width 32 \core_calculate_stage_24_logical_op__insn$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 27 \ra + wire width 64 \core_calculate_stage_24_ra$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 28 \rb + wire width 64 \core_calculate_stage_24_rb$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 29 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 30 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 31 \p_ready_o - cell \p$87 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$88 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + wire width 1 \core_calculate_stage_24_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_24_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_24_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_24_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_24_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_24_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_24_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_24_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_24_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_24_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_24_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_24_compare_rhs$66 + cell \core_calculate_stage_24 \core_calculate_stage_24 + connect \muxid \core_calculate_stage_24_muxid + connect \logical_op__insn_type \core_calculate_stage_24_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_24_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_24_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_24_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_24_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_24_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_24_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_24_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_24_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_24_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_24_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_24_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_24_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_24_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_24_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_24_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_24_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_24_logical_op__insn + connect \ra \core_calculate_stage_24_ra + connect \rb \core_calculate_stage_24_rb + connect \xer_so \core_calculate_stage_24_xer_so + connect \divisor_neg \core_calculate_stage_24_divisor_neg + connect \dividend_neg \core_calculate_stage_24_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_24_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_24_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_24_div_by_zero + connect \divisor_radicand \core_calculate_stage_24_divisor_radicand + connect \operation \core_calculate_stage_24_operation + connect \quotient_root \core_calculate_stage_24_quotient_root + connect \root_times_radicand \core_calculate_stage_24_root_times_radicand + connect \compare_lhs \core_calculate_stage_24_compare_lhs + connect \compare_rhs \core_calculate_stage_24_compare_rhs + connect \muxid$1 \core_calculate_stage_24_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_24_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_24_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_24_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_24_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_24_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_24_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_24_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_24_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_24_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_24_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_24_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_24_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_24_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_24_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_24_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_24_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_24_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_24_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_24_ra$53 + connect \rb$21 \core_calculate_stage_24_rb$54 + connect \xer_so$22 \core_calculate_stage_24_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_24_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_24_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_24_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_24_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_24_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_24_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_24_operation$62 + connect \quotient_root$30 \core_calculate_stage_24_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_24_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_24_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_24_compare_rhs$66 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \mul_pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \mul_pipe1_n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe1_muxid + wire width 2 \core_calculate_stage_25_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -107338,7 +99019,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe1_mul_op__insn_type + wire width 7 \core_calculate_stage_25_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -107352,49 +99033,73 @@ module \alu_mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe1_mul_op__fn_unit + wire width 11 \core_calculate_stage_25_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe1_mul_op__imm_data__imm + wire width 64 \core_calculate_stage_25_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_25_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__rc__rc + wire width 1 \core_calculate_stage_25_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__rc__rc_ok + wire width 1 \core_calculate_stage_25_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__oe__oe + wire width 1 \core_calculate_stage_25_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__oe__oe_ok + wire width 1 \core_calculate_stage_25_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_25_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_25_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__invert_a + wire width 2 \core_calculate_stage_25_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__zero_a + wire width 1 \core_calculate_stage_25_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__invert_out + wire width 1 \core_calculate_stage_25_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__write_cr0 + wire width 1 \core_calculate_stage_25_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__is_32bit + wire width 1 \core_calculate_stage_25_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__is_signed + wire width 1 \core_calculate_stage_25_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe1_mul_op__insn + wire width 4 \core_calculate_stage_25_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_25_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_ra + wire width 64 \core_calculate_stage_25_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_rb + wire width 64 \core_calculate_stage_25_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul_pipe1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \mul_pipe1_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \mul_pipe1_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \mul_pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \mul_pipe1_p_ready_o + wire width 1 \core_calculate_stage_25_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_25_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_25_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_25_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_25_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_25_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_25_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_25_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_25_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_25_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_25_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_25_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe1_muxid$2 + wire width 2 \core_calculate_stage_25_muxid$67 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -107469,7 +99174,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe1_mul_op__insn_type$3 + wire width 7 \core_calculate_stage_25_logical_op__insn_type$68 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -107483,93 +99188,141 @@ module \alu_mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe1_mul_op__fn_unit$4 + wire width 11 \core_calculate_stage_25_logical_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe1_mul_op__imm_data__imm$5 + wire width 64 \core_calculate_stage_25_logical_op__imm_data__imm$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok$6 + wire width 1 \core_calculate_stage_25_logical_op__imm_data__imm_ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__rc__rc$7 + wire width 1 \core_calculate_stage_25_logical_op__rc__rc$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__rc__rc_ok$8 + wire width 1 \core_calculate_stage_25_logical_op__rc__rc_ok$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__oe__oe$9 + wire width 1 \core_calculate_stage_25_logical_op__oe__oe$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__oe__oe_ok$10 + wire width 1 \core_calculate_stage_25_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_25_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_25_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_25_logical_op__input_carry$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__invert_a$11 + wire width 1 \core_calculate_stage_25_logical_op__invert_out$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__zero_a$12 + wire width 1 \core_calculate_stage_25_logical_op__write_cr0$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__invert_out$13 + wire width 1 \core_calculate_stage_25_logical_op__output_carry$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__write_cr0$14 + wire width 1 \core_calculate_stage_25_logical_op__is_32bit$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__is_32bit$15 + wire width 1 \core_calculate_stage_25_logical_op__is_signed$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__is_signed$16 + wire width 4 \core_calculate_stage_25_logical_op__data_len$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe1_mul_op__insn$17 + wire width 32 \core_calculate_stage_25_logical_op__insn$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_ra$18 + wire width 64 \core_calculate_stage_25_ra$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_rb$19 + wire width 64 \core_calculate_stage_25_rb$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul_pipe1_xer_so$20 - cell \mul_pipe1 \mul_pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \n_valid_o \mul_pipe1_n_valid_o - connect \n_ready_i \mul_pipe1_n_ready_i - connect \muxid \mul_pipe1_muxid - connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type - connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul_pipe1_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm_ok - connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc_ok - connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe_ok - connect \mul_op__invert_a \mul_pipe1_mul_op__invert_a - connect \mul_op__zero_a \mul_pipe1_mul_op__zero_a - connect \mul_op__invert_out \mul_pipe1_mul_op__invert_out - connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 - connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit - connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed - connect \mul_op__insn \mul_pipe1_mul_op__insn - connect \ra \mul_pipe1_ra - connect \rb \mul_pipe1_rb - connect \xer_so \mul_pipe1_xer_so - connect \neg_res \mul_pipe1_neg_res - connect \neg_res32 \mul_pipe1_neg_res32 - connect \p_valid_i \mul_pipe1_p_valid_i - connect \p_ready_o \mul_pipe1_p_ready_o - connect \muxid$1 \mul_pipe1_muxid$2 - connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 - connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 - connect \mul_op__imm_data__imm$4 \mul_pipe1_mul_op__imm_data__imm$5 - connect \mul_op__imm_data__imm_ok$5 \mul_pipe1_mul_op__imm_data__imm_ok$6 - connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 - connect \mul_op__rc__rc_ok$7 \mul_pipe1_mul_op__rc__rc_ok$8 - connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 - connect \mul_op__oe__oe_ok$9 \mul_pipe1_mul_op__oe__oe_ok$10 - connect \mul_op__invert_a$10 \mul_pipe1_mul_op__invert_a$11 - connect \mul_op__zero_a$11 \mul_pipe1_mul_op__zero_a$12 - connect \mul_op__invert_out$12 \mul_pipe1_mul_op__invert_out$13 - connect \mul_op__write_cr0$13 \mul_pipe1_mul_op__write_cr0$14 - connect \mul_op__is_32bit$14 \mul_pipe1_mul_op__is_32bit$15 - connect \mul_op__is_signed$15 \mul_pipe1_mul_op__is_signed$16 - connect \mul_op__insn$16 \mul_pipe1_mul_op__insn$17 - connect \ra$17 \mul_pipe1_ra$18 - connect \rb$18 \mul_pipe1_rb$19 - connect \xer_so$19 \mul_pipe1_xer_so$20 + wire width 1 \core_calculate_stage_25_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_25_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_25_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_25_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_25_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_25_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_25_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_25_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_25_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_25_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_25_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_25_compare_rhs$99 + cell \core_calculate_stage_25 \core_calculate_stage_25 + connect \muxid \core_calculate_stage_25_muxid + connect \logical_op__insn_type \core_calculate_stage_25_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_25_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_25_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_25_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_25_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_25_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_25_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_25_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_25_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_25_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_25_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_25_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_25_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_25_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_25_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_25_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_25_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_25_logical_op__insn + connect \ra \core_calculate_stage_25_ra + connect \rb \core_calculate_stage_25_rb + connect \xer_so \core_calculate_stage_25_xer_so + connect \divisor_neg \core_calculate_stage_25_divisor_neg + connect \dividend_neg \core_calculate_stage_25_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_25_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_25_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_25_div_by_zero + connect \divisor_radicand \core_calculate_stage_25_divisor_radicand + connect \operation \core_calculate_stage_25_operation + connect \quotient_root \core_calculate_stage_25_quotient_root + connect \root_times_radicand \core_calculate_stage_25_root_times_radicand + connect \compare_lhs \core_calculate_stage_25_compare_lhs + connect \compare_rhs \core_calculate_stage_25_compare_rhs + connect \muxid$1 \core_calculate_stage_25_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_25_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_25_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_25_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_25_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_25_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_25_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_25_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_25_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_25_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_25_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_25_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_25_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_25_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_25_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_25_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_25_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_25_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_25_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_25_ra$86 + connect \rb$21 \core_calculate_stage_25_rb$87 + connect \xer_so$22 \core_calculate_stage_25_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_25_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_25_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_25_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_25_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_25_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_25_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_25_operation$95 + connect \quotient_root$30 \core_calculate_stage_25_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_25_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_25_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_25_compare_rhs$99 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \mul_pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \mul_pipe2_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe2_muxid + wire width 2 \core_calculate_stage_26_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -107644,7 +99397,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe2_mul_op__insn_type + wire width 7 \core_calculate_stage_26_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -107658,49 +99411,73 @@ module \alu_mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe2_mul_op__fn_unit + wire width 11 \core_calculate_stage_26_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe2_mul_op__imm_data__imm + wire width 64 \core_calculate_stage_26_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_26_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__rc__rc + wire width 1 \core_calculate_stage_26_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__rc__rc_ok + wire width 1 \core_calculate_stage_26_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__oe__oe + wire width 1 \core_calculate_stage_26_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__oe__oe_ok + wire width 1 \core_calculate_stage_26_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__invert_a + wire width 1 \core_calculate_stage_26_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__zero_a + wire width 1 \core_calculate_stage_26_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__invert_out + wire width 2 \core_calculate_stage_26_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__write_cr0 + wire width 1 \core_calculate_stage_26_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__is_32bit + wire width 1 \core_calculate_stage_26_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__is_signed + wire width 1 \core_calculate_stage_26_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe2_mul_op__insn + wire width 1 \core_calculate_stage_26_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_26_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_26_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_26_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe2_ra + wire width 64 \core_calculate_stage_26_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe2_rb + wire width 64 \core_calculate_stage_26_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul_pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \mul_pipe2_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \mul_pipe2_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \mul_pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \mul_pipe2_n_ready_i + wire width 1 \core_calculate_stage_26_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_26_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_26_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_26_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_26_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_26_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_26_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_26_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_26_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_26_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_26_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_26_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe2_muxid$21 + wire width 2 \core_calculate_stage_26_muxid$100 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -107775,7 +99552,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe2_mul_op__insn_type$22 + wire width 7 \core_calculate_stage_26_logical_op__insn_type$101 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -107789,96 +99566,141 @@ module \alu_mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe2_mul_op__fn_unit$23 + wire width 11 \core_calculate_stage_26_logical_op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_26_logical_op__imm_data__imm$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe2_mul_op__imm_data__imm$24 + wire width 1 \core_calculate_stage_26_logical_op__imm_data__imm_ok$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok$25 + wire width 1 \core_calculate_stage_26_logical_op__rc__rc$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__rc__rc$26 + wire width 1 \core_calculate_stage_26_logical_op__rc__rc_ok$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__rc__rc_ok$27 + wire width 1 \core_calculate_stage_26_logical_op__oe__oe$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__oe__oe$28 + wire width 1 \core_calculate_stage_26_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_26_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_26_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__oe__oe_ok$29 + wire width 2 \core_calculate_stage_26_logical_op__input_carry$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__invert_a$30 + wire width 1 \core_calculate_stage_26_logical_op__invert_out$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__zero_a$31 + wire width 1 \core_calculate_stage_26_logical_op__write_cr0$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__invert_out$32 + wire width 1 \core_calculate_stage_26_logical_op__output_carry$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__write_cr0$33 + wire width 1 \core_calculate_stage_26_logical_op__is_32bit$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__is_32bit$34 + wire width 1 \core_calculate_stage_26_logical_op__is_signed$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__is_signed$35 + wire width 4 \core_calculate_stage_26_logical_op__data_len$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe2_mul_op__insn$36 + wire width 32 \core_calculate_stage_26_logical_op__insn$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul_pipe2_o + wire width 64 \core_calculate_stage_26_ra$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul_pipe2_xer_so$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 \mul_pipe2_neg_res$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \mul_pipe2_neg_res32$39 - cell \mul_pipe2 \mul_pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \mul_pipe2_p_valid_i - connect \p_ready_o \mul_pipe2_p_ready_o - connect \muxid \mul_pipe2_muxid - connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type - connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul_pipe2_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm_ok - connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc_ok - connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe_ok - connect \mul_op__invert_a \mul_pipe2_mul_op__invert_a - connect \mul_op__zero_a \mul_pipe2_mul_op__zero_a - connect \mul_op__invert_out \mul_pipe2_mul_op__invert_out - connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 - connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit - connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed - connect \mul_op__insn \mul_pipe2_mul_op__insn - connect \ra \mul_pipe2_ra - connect \rb \mul_pipe2_rb - connect \xer_so \mul_pipe2_xer_so - connect \neg_res \mul_pipe2_neg_res - connect \neg_res32 \mul_pipe2_neg_res32 - connect \n_valid_o \mul_pipe2_n_valid_o - connect \n_ready_i \mul_pipe2_n_ready_i - connect \muxid$1 \mul_pipe2_muxid$21 - connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$22 - connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$23 - connect \mul_op__imm_data__imm$4 \mul_pipe2_mul_op__imm_data__imm$24 - connect \mul_op__imm_data__imm_ok$5 \mul_pipe2_mul_op__imm_data__imm_ok$25 - connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$26 - connect \mul_op__rc__rc_ok$7 \mul_pipe2_mul_op__rc__rc_ok$27 - connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$28 - connect \mul_op__oe__oe_ok$9 \mul_pipe2_mul_op__oe__oe_ok$29 - connect \mul_op__invert_a$10 \mul_pipe2_mul_op__invert_a$30 - connect \mul_op__zero_a$11 \mul_pipe2_mul_op__zero_a$31 - connect \mul_op__invert_out$12 \mul_pipe2_mul_op__invert_out$32 - connect \mul_op__write_cr0$13 \mul_pipe2_mul_op__write_cr0$33 - connect \mul_op__is_32bit$14 \mul_pipe2_mul_op__is_32bit$34 - connect \mul_op__is_signed$15 \mul_pipe2_mul_op__is_signed$35 - connect \mul_op__insn$16 \mul_pipe2_mul_op__insn$36 - connect \o \mul_pipe2_o - connect \xer_so$17 \mul_pipe2_xer_so$37 - connect \neg_res$18 \mul_pipe2_neg_res$38 - connect \neg_res32$19 \mul_pipe2_neg_res32$39 + wire width 64 \core_calculate_stage_26_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_26_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_26_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_26_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_26_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_26_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_26_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_26_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_26_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_26_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_26_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_26_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_26_compare_rhs$132 + cell \core_calculate_stage_26 \core_calculate_stage_26 + connect \muxid \core_calculate_stage_26_muxid + connect \logical_op__insn_type \core_calculate_stage_26_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_26_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_26_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_26_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_26_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_26_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_26_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_26_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_26_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_26_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_26_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_26_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_26_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_26_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_26_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_26_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_26_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_26_logical_op__insn + connect \ra \core_calculate_stage_26_ra + connect \rb \core_calculate_stage_26_rb + connect \xer_so \core_calculate_stage_26_xer_so + connect \divisor_neg \core_calculate_stage_26_divisor_neg + connect \dividend_neg \core_calculate_stage_26_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_26_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_26_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_26_div_by_zero + connect \divisor_radicand \core_calculate_stage_26_divisor_radicand + connect \operation \core_calculate_stage_26_operation + connect \quotient_root \core_calculate_stage_26_quotient_root + connect \root_times_radicand \core_calculate_stage_26_root_times_radicand + connect \compare_lhs \core_calculate_stage_26_compare_lhs + connect \compare_rhs \core_calculate_stage_26_compare_rhs + connect \muxid$1 \core_calculate_stage_26_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_26_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_26_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_26_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_26_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_26_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_26_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_26_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_26_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_26_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_26_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_26_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_26_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_26_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_26_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_26_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_26_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_26_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_26_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_26_ra$119 + connect \rb$21 \core_calculate_stage_26_rb$120 + connect \xer_so$22 \core_calculate_stage_26_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_26_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_26_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_26_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_26_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_26_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_26_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_26_operation$128 + connect \quotient_root$30 \core_calculate_stage_26_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_26_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_26_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_26_compare_rhs$132 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \mul_pipe3_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \mul_pipe3_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe3_muxid + wire width 2 \core_calculate_stage_27_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -107953,7 +99775,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe3_mul_op__insn_type + wire width 7 \core_calculate_stage_27_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -107967,47 +99789,73 @@ module \alu_mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe3_mul_op__fn_unit + wire width 11 \core_calculate_stage_27_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe3_mul_op__imm_data__imm + wire width 64 \core_calculate_stage_27_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_27_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__rc__rc + wire width 1 \core_calculate_stage_27_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__rc__rc_ok + wire width 1 \core_calculate_stage_27_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__oe__oe + wire width 1 \core_calculate_stage_27_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__oe__oe_ok + wire width 1 \core_calculate_stage_27_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_27_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_27_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__invert_a + wire width 2 \core_calculate_stage_27_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__zero_a + wire width 1 \core_calculate_stage_27_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__invert_out + wire width 1 \core_calculate_stage_27_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__write_cr0 + wire width 1 \core_calculate_stage_27_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__is_32bit + wire width 1 \core_calculate_stage_27_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__is_signed + wire width 1 \core_calculate_stage_27_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe3_mul_op__insn + wire width 4 \core_calculate_stage_27_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_27_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul_pipe3_o + wire width 64 \core_calculate_stage_27_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul_pipe3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 \mul_pipe3_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \mul_pipe3_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \mul_pipe3_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \mul_pipe3_n_ready_i + wire width 64 \core_calculate_stage_27_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_27_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_27_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_27_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_27_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_27_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_27_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_27_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_27_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_27_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_27_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_27_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_27_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe3_muxid$40 + wire width 2 \core_calculate_stage_27_muxid$133 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -108082,7 +99930,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe3_mul_op__insn_type$41 + wire width 7 \core_calculate_stage_27_logical_op__insn_type$134 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -108096,280 +99944,566 @@ module \alu_mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe3_mul_op__fn_unit$42 + wire width 11 \core_calculate_stage_27_logical_op__fn_unit$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe3_mul_op__imm_data__imm$43 + wire width 64 \core_calculate_stage_27_logical_op__imm_data__imm$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok$44 + wire width 1 \core_calculate_stage_27_logical_op__imm_data__imm_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__rc__rc$45 + wire width 1 \core_calculate_stage_27_logical_op__rc__rc$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__rc__rc_ok$46 + wire width 1 \core_calculate_stage_27_logical_op__rc__rc_ok$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__oe__oe$47 + wire width 1 \core_calculate_stage_27_logical_op__oe__oe$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__oe__oe_ok$48 + wire width 1 \core_calculate_stage_27_logical_op__oe__oe_ok$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__invert_a$49 + wire width 1 \core_calculate_stage_27_logical_op__invert_in$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__zero_a$50 + wire width 1 \core_calculate_stage_27_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__invert_out$51 + wire width 2 \core_calculate_stage_27_logical_op__input_carry$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__write_cr0$52 + wire width 1 \core_calculate_stage_27_logical_op__invert_out$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__is_32bit$53 + wire width 1 \core_calculate_stage_27_logical_op__write_cr0$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__is_signed$54 + wire width 1 \core_calculate_stage_27_logical_op__output_carry$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe3_mul_op__insn$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \mul_pipe3_o$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul_pipe3_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \mul_pipe3_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul_pipe3_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \mul_pipe3_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul_pipe3_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul_pipe3_xer_so$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul_pipe3_xer_so_ok - cell \mul_pipe3 \mul_pipe3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \mul_pipe3_p_valid_i - connect \p_ready_o \mul_pipe3_p_ready_o - connect \muxid \mul_pipe3_muxid - connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type - connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit - connect \mul_op__imm_data__imm \mul_pipe3_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm_ok - connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc - connect \mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc_ok - connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe - connect \mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe_ok - connect \mul_op__invert_a \mul_pipe3_mul_op__invert_a - connect \mul_op__zero_a \mul_pipe3_mul_op__zero_a - connect \mul_op__invert_out \mul_pipe3_mul_op__invert_out - connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 - connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit - connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed - connect \mul_op__insn \mul_pipe3_mul_op__insn - connect \o \mul_pipe3_o - connect \xer_so \mul_pipe3_xer_so - connect \neg_res \mul_pipe3_neg_res - connect \neg_res32 \mul_pipe3_neg_res32 - connect \n_valid_o \mul_pipe3_n_valid_o - connect \n_ready_i \mul_pipe3_n_ready_i - connect \muxid$1 \mul_pipe3_muxid$40 - connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$41 - connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$42 - connect \mul_op__imm_data__imm$4 \mul_pipe3_mul_op__imm_data__imm$43 - connect \mul_op__imm_data__imm_ok$5 \mul_pipe3_mul_op__imm_data__imm_ok$44 - connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$45 - connect \mul_op__rc__rc_ok$7 \mul_pipe3_mul_op__rc__rc_ok$46 - connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$47 - connect \mul_op__oe__oe_ok$9 \mul_pipe3_mul_op__oe__oe_ok$48 - connect \mul_op__invert_a$10 \mul_pipe3_mul_op__invert_a$49 - connect \mul_op__zero_a$11 \mul_pipe3_mul_op__zero_a$50 - connect \mul_op__invert_out$12 \mul_pipe3_mul_op__invert_out$51 - connect \mul_op__write_cr0$13 \mul_pipe3_mul_op__write_cr0$52 - connect \mul_op__is_32bit$14 \mul_pipe3_mul_op__is_32bit$53 - connect \mul_op__is_signed$15 \mul_pipe3_mul_op__is_signed$54 - connect \mul_op__insn$16 \mul_pipe3_mul_op__insn$55 - connect \o$17 \mul_pipe3_o$56 - connect \o_ok \mul_pipe3_o_ok - connect \cr_a \mul_pipe3_cr_a - connect \cr_a_ok \mul_pipe3_cr_a_ok - connect \xer_ov \mul_pipe3_xer_ov - connect \xer_ov_ok \mul_pipe3_xer_ov_ok - connect \xer_so$18 \mul_pipe3_xer_so$57 - connect \xer_so_ok \mul_pipe3_xer_so_ok + wire width 1 \core_calculate_stage_27_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_27_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_27_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_27_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_27_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_27_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_27_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_27_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_27_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_27_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_27_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_27_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_27_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_27_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_27_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_27_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_27_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_27_compare_rhs$165 + cell \core_calculate_stage_27 \core_calculate_stage_27 + connect \muxid \core_calculate_stage_27_muxid + connect \logical_op__insn_type \core_calculate_stage_27_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_27_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_27_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_27_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_27_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_27_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_27_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_27_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_27_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_27_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_27_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_27_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_27_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_27_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_27_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_27_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_27_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_27_logical_op__insn + connect \ra \core_calculate_stage_27_ra + connect \rb \core_calculate_stage_27_rb + connect \xer_so \core_calculate_stage_27_xer_so + connect \divisor_neg \core_calculate_stage_27_divisor_neg + connect \dividend_neg \core_calculate_stage_27_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_27_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_27_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_27_div_by_zero + connect \divisor_radicand \core_calculate_stage_27_divisor_radicand + connect \operation \core_calculate_stage_27_operation + connect \quotient_root \core_calculate_stage_27_quotient_root + connect \root_times_radicand \core_calculate_stage_27_root_times_radicand + connect \compare_lhs \core_calculate_stage_27_compare_lhs + connect \compare_rhs \core_calculate_stage_27_compare_rhs + connect \muxid$1 \core_calculate_stage_27_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_27_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_27_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_27_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_27_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_27_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_27_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_27_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_27_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_27_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_27_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_27_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_27_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_27_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_27_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_27_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_27_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_27_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_27_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_27_ra$152 + connect \rb$21 \core_calculate_stage_27_rb$153 + connect \xer_so$22 \core_calculate_stage_27_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_27_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_27_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_27_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_27_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_27_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_27_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_27_operation$161 + connect \quotient_root$30 \core_calculate_stage_27_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_27_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_27_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_27_compare_rhs$165 end process $group_0 - assign \mul_pipe2_p_valid_i 1'0 - assign \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o + assign \core_calculate_stage_24_muxid 2'00 + assign \core_calculate_stage_24_muxid \muxid sync init end process $group_1 - assign \mul_pipe1_n_ready_i 1'0 - assign \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o - sync init - end - process $group_2 - assign \mul_pipe2_muxid 2'00 - assign \mul_pipe2_muxid \mul_pipe1_muxid - sync init - end - process $group_3 - assign \mul_pipe2_mul_op__insn_type 7'0000000 - assign \mul_pipe2_mul_op__fn_unit 11'00000000000 - assign \mul_pipe2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe2_mul_op__imm_data__imm_ok 1'0 - assign \mul_pipe2_mul_op__rc__rc 1'0 - assign \mul_pipe2_mul_op__rc__rc_ok 1'0 - assign \mul_pipe2_mul_op__oe__oe 1'0 - assign \mul_pipe2_mul_op__oe__oe_ok 1'0 - assign \mul_pipe2_mul_op__invert_a 1'0 - assign \mul_pipe2_mul_op__zero_a 1'0 - assign \mul_pipe2_mul_op__invert_out 1'0 - assign \mul_pipe2_mul_op__write_cr0 1'0 - assign \mul_pipe2_mul_op__is_32bit 1'0 - assign \mul_pipe2_mul_op__is_signed 1'0 - assign \mul_pipe2_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__invert_out \mul_pipe2_mul_op__zero_a \mul_pipe2_mul_op__invert_a { \mul_pipe2_mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe } { \mul_pipe2_mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc } { \mul_pipe2_mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm } \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__invert_out \mul_pipe1_mul_op__zero_a \mul_pipe1_mul_op__invert_a { \mul_pipe1_mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe } { \mul_pipe1_mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc } { \mul_pipe1_mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm } \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } - sync init - end - process $group_18 - assign \mul_pipe2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe2_ra \mul_pipe1_ra + assign \core_calculate_stage_24_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_24_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_24_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_24_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_24_logical_op__rc__rc 1'0 + assign \core_calculate_stage_24_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_24_logical_op__oe__oe 1'0 + assign \core_calculate_stage_24_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_24_logical_op__invert_in 1'0 + assign \core_calculate_stage_24_logical_op__zero_a 1'0 + assign \core_calculate_stage_24_logical_op__input_carry 2'00 + assign \core_calculate_stage_24_logical_op__invert_out 1'0 + assign \core_calculate_stage_24_logical_op__write_cr0 1'0 + assign \core_calculate_stage_24_logical_op__output_carry 1'0 + assign \core_calculate_stage_24_logical_op__is_32bit 1'0 + assign \core_calculate_stage_24_logical_op__is_signed 1'0 + assign \core_calculate_stage_24_logical_op__data_len 4'0000 + assign \core_calculate_stage_24_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_24_logical_op__insn \core_calculate_stage_24_logical_op__data_len \core_calculate_stage_24_logical_op__is_signed \core_calculate_stage_24_logical_op__is_32bit \core_calculate_stage_24_logical_op__output_carry \core_calculate_stage_24_logical_op__write_cr0 \core_calculate_stage_24_logical_op__invert_out \core_calculate_stage_24_logical_op__input_carry \core_calculate_stage_24_logical_op__zero_a \core_calculate_stage_24_logical_op__invert_in { \core_calculate_stage_24_logical_op__oe__oe_ok \core_calculate_stage_24_logical_op__oe__oe } { \core_calculate_stage_24_logical_op__rc__rc_ok \core_calculate_stage_24_logical_op__rc__rc } { \core_calculate_stage_24_logical_op__imm_data__imm_ok \core_calculate_stage_24_logical_op__imm_data__imm } \core_calculate_stage_24_logical_op__fn_unit \core_calculate_stage_24_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end process $group_19 - assign \mul_pipe2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe2_rb \mul_pipe1_rb + assign \core_calculate_stage_24_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_24_ra \ra sync init end process $group_20 - assign \mul_pipe2_xer_so 1'0 - assign \mul_pipe2_xer_so \mul_pipe1_xer_so + assign \core_calculate_stage_24_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_24_rb \rb sync init end process $group_21 - assign \mul_pipe2_neg_res 1'0 - assign \mul_pipe2_neg_res \mul_pipe1_neg_res + assign \core_calculate_stage_24_xer_so 1'0 + assign \core_calculate_stage_24_xer_so \xer_so sync init end process $group_22 - assign \mul_pipe2_neg_res32 1'0 - assign \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 + assign \core_calculate_stage_24_divisor_neg 1'0 + assign \core_calculate_stage_24_divisor_neg \divisor_neg sync init end process $group_23 - assign \mul_pipe3_p_valid_i 1'0 - assign \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o + assign \core_calculate_stage_24_dividend_neg 1'0 + assign \core_calculate_stage_24_dividend_neg \dividend_neg sync init end process $group_24 - assign \mul_pipe2_n_ready_i 1'0 - assign \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o + assign \core_calculate_stage_24_dive_abs_ov32 1'0 + assign \core_calculate_stage_24_dive_abs_ov32 \dive_abs_ov32 sync init end process $group_25 - assign \mul_pipe3_muxid 2'00 - assign \mul_pipe3_muxid \mul_pipe2_muxid$21 + assign \core_calculate_stage_24_dive_abs_ov64 1'0 + assign \core_calculate_stage_24_dive_abs_ov64 \dive_abs_ov64 sync init end process $group_26 - assign \mul_pipe3_mul_op__insn_type 7'0000000 - assign \mul_pipe3_mul_op__fn_unit 11'00000000000 - assign \mul_pipe3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe3_mul_op__imm_data__imm_ok 1'0 - assign \mul_pipe3_mul_op__rc__rc 1'0 - assign \mul_pipe3_mul_op__rc__rc_ok 1'0 - assign \mul_pipe3_mul_op__oe__oe 1'0 - assign \mul_pipe3_mul_op__oe__oe_ok 1'0 - assign \mul_pipe3_mul_op__invert_a 1'0 - assign \mul_pipe3_mul_op__zero_a 1'0 - assign \mul_pipe3_mul_op__invert_out 1'0 - assign \mul_pipe3_mul_op__write_cr0 1'0 - assign \mul_pipe3_mul_op__is_32bit 1'0 - assign \mul_pipe3_mul_op__is_signed 1'0 - assign \mul_pipe3_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__invert_out \mul_pipe3_mul_op__zero_a \mul_pipe3_mul_op__invert_a { \mul_pipe3_mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe } { \mul_pipe3_mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc } { \mul_pipe3_mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm } \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$36 \mul_pipe2_mul_op__is_signed$35 \mul_pipe2_mul_op__is_32bit$34 \mul_pipe2_mul_op__write_cr0$33 \mul_pipe2_mul_op__invert_out$32 \mul_pipe2_mul_op__zero_a$31 \mul_pipe2_mul_op__invert_a$30 { \mul_pipe2_mul_op__oe__oe_ok$29 \mul_pipe2_mul_op__oe__oe$28 } { \mul_pipe2_mul_op__rc__rc_ok$27 \mul_pipe2_mul_op__rc__rc$26 } { \mul_pipe2_mul_op__imm_data__imm_ok$25 \mul_pipe2_mul_op__imm_data__imm$24 } \mul_pipe2_mul_op__fn_unit$23 \mul_pipe2_mul_op__insn_type$22 } + assign \core_calculate_stage_24_div_by_zero 1'0 + assign \core_calculate_stage_24_div_by_zero \div_by_zero sync init end - process $group_41 - assign \mul_pipe3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe3_o \mul_pipe2_o + process $group_27 + assign \core_calculate_stage_24_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_24_divisor_radicand \divisor_radicand sync init end - process $group_42 - assign \mul_pipe3_xer_so 1'0 - assign \mul_pipe3_xer_so \mul_pipe2_xer_so$37 + process $group_28 + assign \core_calculate_stage_24_operation 2'00 + assign \core_calculate_stage_24_operation \operation sync init end - process $group_43 - assign \mul_pipe3_neg_res 1'0 - assign \mul_pipe3_neg_res \mul_pipe2_neg_res$38 + process $group_29 + assign \core_calculate_stage_24_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_24_quotient_root \quotient_root sync init end - process $group_44 - assign \mul_pipe3_neg_res32 1'0 - assign \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$39 + process $group_30 + assign \core_calculate_stage_24_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_24_root_times_radicand \root_times_radicand sync init end - process $group_45 - assign \mul_pipe1_p_valid_i 1'0 - assign \mul_pipe1_p_valid_i \p_valid_i + process $group_31 + assign \core_calculate_stage_24_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_24_compare_lhs \compare_lhs sync init end - process $group_46 - assign \p_ready_o 1'0 - assign \p_ready_o \mul_pipe1_p_ready_o + process $group_32 + assign \core_calculate_stage_24_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_24_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_47 - assign \mul_pipe1_muxid$2 2'00 - assign \mul_pipe1_muxid$2 \muxid + process $group_33 + assign \core_calculate_stage_25_muxid 2'00 + assign \core_calculate_stage_25_muxid \core_calculate_stage_24_muxid$34 sync init end - process $group_48 - assign \mul_pipe1_mul_op__insn_type$3 7'0000000 - assign \mul_pipe1_mul_op__fn_unit$4 11'00000000000 - assign \mul_pipe1_mul_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe1_mul_op__imm_data__imm_ok$6 1'0 - assign \mul_pipe1_mul_op__rc__rc$7 1'0 - assign \mul_pipe1_mul_op__rc__rc_ok$8 1'0 - assign \mul_pipe1_mul_op__oe__oe$9 1'0 - assign \mul_pipe1_mul_op__oe__oe_ok$10 1'0 - assign \mul_pipe1_mul_op__invert_a$11 1'0 - assign \mul_pipe1_mul_op__zero_a$12 1'0 - assign \mul_pipe1_mul_op__invert_out$13 1'0 - assign \mul_pipe1_mul_op__write_cr0$14 1'0 - assign \mul_pipe1_mul_op__is_32bit$15 1'0 - assign \mul_pipe1_mul_op__is_signed$16 1'0 - assign \mul_pipe1_mul_op__insn$17 32'00000000000000000000000000000000 - assign { \mul_pipe1_mul_op__insn$17 \mul_pipe1_mul_op__is_signed$16 \mul_pipe1_mul_op__is_32bit$15 \mul_pipe1_mul_op__write_cr0$14 \mul_pipe1_mul_op__invert_out$13 \mul_pipe1_mul_op__zero_a$12 \mul_pipe1_mul_op__invert_a$11 { \mul_pipe1_mul_op__oe__oe_ok$10 \mul_pipe1_mul_op__oe__oe$9 } { \mul_pipe1_mul_op__rc__rc_ok$8 \mul_pipe1_mul_op__rc__rc$7 } { \mul_pipe1_mul_op__imm_data__imm_ok$6 \mul_pipe1_mul_op__imm_data__imm$5 } \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + process $group_34 + assign \core_calculate_stage_25_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_25_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_25_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_25_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_25_logical_op__rc__rc 1'0 + assign \core_calculate_stage_25_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_25_logical_op__oe__oe 1'0 + assign \core_calculate_stage_25_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_25_logical_op__invert_in 1'0 + assign \core_calculate_stage_25_logical_op__zero_a 1'0 + assign \core_calculate_stage_25_logical_op__input_carry 2'00 + assign \core_calculate_stage_25_logical_op__invert_out 1'0 + assign \core_calculate_stage_25_logical_op__write_cr0 1'0 + assign \core_calculate_stage_25_logical_op__output_carry 1'0 + assign \core_calculate_stage_25_logical_op__is_32bit 1'0 + assign \core_calculate_stage_25_logical_op__is_signed 1'0 + assign \core_calculate_stage_25_logical_op__data_len 4'0000 + assign \core_calculate_stage_25_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_25_logical_op__insn \core_calculate_stage_25_logical_op__data_len \core_calculate_stage_25_logical_op__is_signed \core_calculate_stage_25_logical_op__is_32bit \core_calculate_stage_25_logical_op__output_carry \core_calculate_stage_25_logical_op__write_cr0 \core_calculate_stage_25_logical_op__invert_out \core_calculate_stage_25_logical_op__input_carry \core_calculate_stage_25_logical_op__zero_a \core_calculate_stage_25_logical_op__invert_in { \core_calculate_stage_25_logical_op__oe__oe_ok \core_calculate_stage_25_logical_op__oe__oe } { \core_calculate_stage_25_logical_op__rc__rc_ok \core_calculate_stage_25_logical_op__rc__rc } { \core_calculate_stage_25_logical_op__imm_data__imm_ok \core_calculate_stage_25_logical_op__imm_data__imm } \core_calculate_stage_25_logical_op__fn_unit \core_calculate_stage_25_logical_op__insn_type } { \core_calculate_stage_24_logical_op__insn$52 \core_calculate_stage_24_logical_op__data_len$51 \core_calculate_stage_24_logical_op__is_signed$50 \core_calculate_stage_24_logical_op__is_32bit$49 \core_calculate_stage_24_logical_op__output_carry$48 \core_calculate_stage_24_logical_op__write_cr0$47 \core_calculate_stage_24_logical_op__invert_out$46 \core_calculate_stage_24_logical_op__input_carry$45 \core_calculate_stage_24_logical_op__zero_a$44 \core_calculate_stage_24_logical_op__invert_in$43 { \core_calculate_stage_24_logical_op__oe__oe_ok$42 \core_calculate_stage_24_logical_op__oe__oe$41 } { \core_calculate_stage_24_logical_op__rc__rc_ok$40 \core_calculate_stage_24_logical_op__rc__rc$39 } { \core_calculate_stage_24_logical_op__imm_data__imm_ok$38 \core_calculate_stage_24_logical_op__imm_data__imm$37 } \core_calculate_stage_24_logical_op__fn_unit$36 \core_calculate_stage_24_logical_op__insn_type$35 } + sync init + end + process $group_52 + assign \core_calculate_stage_25_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_25_ra \core_calculate_stage_24_ra$53 + sync init + end + process $group_53 + assign \core_calculate_stage_25_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_25_rb \core_calculate_stage_24_rb$54 + sync init + end + process $group_54 + assign \core_calculate_stage_25_xer_so 1'0 + assign \core_calculate_stage_25_xer_so \core_calculate_stage_24_xer_so$55 + sync init + end + process $group_55 + assign \core_calculate_stage_25_divisor_neg 1'0 + assign \core_calculate_stage_25_divisor_neg \core_calculate_stage_24_divisor_neg$56 + sync init + end + process $group_56 + assign \core_calculate_stage_25_dividend_neg 1'0 + assign \core_calculate_stage_25_dividend_neg \core_calculate_stage_24_dividend_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_25_dive_abs_ov32 1'0 + assign \core_calculate_stage_25_dive_abs_ov32 \core_calculate_stage_24_dive_abs_ov32$58 + sync init + end + process $group_58 + assign \core_calculate_stage_25_dive_abs_ov64 1'0 + assign \core_calculate_stage_25_dive_abs_ov64 \core_calculate_stage_24_dive_abs_ov64$59 + sync init + end + process $group_59 + assign \core_calculate_stage_25_div_by_zero 1'0 + assign \core_calculate_stage_25_div_by_zero \core_calculate_stage_24_div_by_zero$60 + sync init + end + process $group_60 + assign \core_calculate_stage_25_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_25_divisor_radicand \core_calculate_stage_24_divisor_radicand$61 + sync init + end + process $group_61 + assign \core_calculate_stage_25_operation 2'00 + assign \core_calculate_stage_25_operation \core_calculate_stage_24_operation$62 + sync init + end + process $group_62 + assign \core_calculate_stage_25_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_25_quotient_root \core_calculate_stage_24_quotient_root$63 sync init end process $group_63 - assign \mul_pipe1_ra$18 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe1_ra$18 \ra + assign \core_calculate_stage_25_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_25_root_times_radicand \core_calculate_stage_24_root_times_radicand$64 sync init end process $group_64 - assign \mul_pipe1_rb$19 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe1_rb$19 \rb + assign \core_calculate_stage_25_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_25_compare_lhs \core_calculate_stage_24_compare_lhs$65 sync init end process $group_65 - assign \mul_pipe1_xer_so$20 1'0 - assign \mul_pipe1_xer_so$20 \xer_so$1 + assign \core_calculate_stage_25_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_25_compare_rhs \core_calculate_stage_24_compare_rhs$66 sync init end process $group_66 - assign \n_valid_o 1'0 - assign \n_valid_o \mul_pipe3_n_valid_o + assign \core_calculate_stage_26_muxid 2'00 + assign \core_calculate_stage_26_muxid \core_calculate_stage_25_muxid$67 sync init end process $group_67 - assign \mul_pipe3_n_ready_i 1'0 - assign \mul_pipe3_n_ready_i \n_ready_i + assign \core_calculate_stage_26_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_26_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_26_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_26_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_26_logical_op__rc__rc 1'0 + assign \core_calculate_stage_26_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_26_logical_op__oe__oe 1'0 + assign \core_calculate_stage_26_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_26_logical_op__invert_in 1'0 + assign \core_calculate_stage_26_logical_op__zero_a 1'0 + assign \core_calculate_stage_26_logical_op__input_carry 2'00 + assign \core_calculate_stage_26_logical_op__invert_out 1'0 + assign \core_calculate_stage_26_logical_op__write_cr0 1'0 + assign \core_calculate_stage_26_logical_op__output_carry 1'0 + assign \core_calculate_stage_26_logical_op__is_32bit 1'0 + assign \core_calculate_stage_26_logical_op__is_signed 1'0 + assign \core_calculate_stage_26_logical_op__data_len 4'0000 + assign \core_calculate_stage_26_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_26_logical_op__insn \core_calculate_stage_26_logical_op__data_len \core_calculate_stage_26_logical_op__is_signed \core_calculate_stage_26_logical_op__is_32bit \core_calculate_stage_26_logical_op__output_carry \core_calculate_stage_26_logical_op__write_cr0 \core_calculate_stage_26_logical_op__invert_out \core_calculate_stage_26_logical_op__input_carry \core_calculate_stage_26_logical_op__zero_a \core_calculate_stage_26_logical_op__invert_in { \core_calculate_stage_26_logical_op__oe__oe_ok \core_calculate_stage_26_logical_op__oe__oe } { \core_calculate_stage_26_logical_op__rc__rc_ok \core_calculate_stage_26_logical_op__rc__rc } { \core_calculate_stage_26_logical_op__imm_data__imm_ok \core_calculate_stage_26_logical_op__imm_data__imm } \core_calculate_stage_26_logical_op__fn_unit \core_calculate_stage_26_logical_op__insn_type } { \core_calculate_stage_25_logical_op__insn$85 \core_calculate_stage_25_logical_op__data_len$84 \core_calculate_stage_25_logical_op__is_signed$83 \core_calculate_stage_25_logical_op__is_32bit$82 \core_calculate_stage_25_logical_op__output_carry$81 \core_calculate_stage_25_logical_op__write_cr0$80 \core_calculate_stage_25_logical_op__invert_out$79 \core_calculate_stage_25_logical_op__input_carry$78 \core_calculate_stage_25_logical_op__zero_a$77 \core_calculate_stage_25_logical_op__invert_in$76 { \core_calculate_stage_25_logical_op__oe__oe_ok$75 \core_calculate_stage_25_logical_op__oe__oe$74 } { \core_calculate_stage_25_logical_op__rc__rc_ok$73 \core_calculate_stage_25_logical_op__rc__rc$72 } { \core_calculate_stage_25_logical_op__imm_data__imm_ok$71 \core_calculate_stage_25_logical_op__imm_data__imm$70 } \core_calculate_stage_25_logical_op__fn_unit$69 \core_calculate_stage_25_logical_op__insn_type$68 } + sync init + end + process $group_85 + assign \core_calculate_stage_26_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_26_ra \core_calculate_stage_25_ra$86 + sync init + end + process $group_86 + assign \core_calculate_stage_26_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_26_rb \core_calculate_stage_25_rb$87 + sync init + end + process $group_87 + assign \core_calculate_stage_26_xer_so 1'0 + assign \core_calculate_stage_26_xer_so \core_calculate_stage_25_xer_so$88 + sync init + end + process $group_88 + assign \core_calculate_stage_26_divisor_neg 1'0 + assign \core_calculate_stage_26_divisor_neg \core_calculate_stage_25_divisor_neg$89 + sync init + end + process $group_89 + assign \core_calculate_stage_26_dividend_neg 1'0 + assign \core_calculate_stage_26_dividend_neg \core_calculate_stage_25_dividend_neg$90 + sync init + end + process $group_90 + assign \core_calculate_stage_26_dive_abs_ov32 1'0 + assign \core_calculate_stage_26_dive_abs_ov32 \core_calculate_stage_25_dive_abs_ov32$91 + sync init + end + process $group_91 + assign \core_calculate_stage_26_dive_abs_ov64 1'0 + assign \core_calculate_stage_26_dive_abs_ov64 \core_calculate_stage_25_dive_abs_ov64$92 + sync init + end + process $group_92 + assign \core_calculate_stage_26_div_by_zero 1'0 + assign \core_calculate_stage_26_div_by_zero \core_calculate_stage_25_div_by_zero$93 + sync init + end + process $group_93 + assign \core_calculate_stage_26_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_26_divisor_radicand \core_calculate_stage_25_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_26_operation 2'00 + assign \core_calculate_stage_26_operation \core_calculate_stage_25_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_26_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_26_quotient_root \core_calculate_stage_25_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_26_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_26_root_times_radicand \core_calculate_stage_25_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_26_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_26_compare_lhs \core_calculate_stage_25_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_26_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_26_compare_rhs \core_calculate_stage_25_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_27_muxid 2'00 + assign \core_calculate_stage_27_muxid \core_calculate_stage_26_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_27_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_27_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_27_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_27_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_27_logical_op__rc__rc 1'0 + assign \core_calculate_stage_27_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_27_logical_op__oe__oe 1'0 + assign \core_calculate_stage_27_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_27_logical_op__invert_in 1'0 + assign \core_calculate_stage_27_logical_op__zero_a 1'0 + assign \core_calculate_stage_27_logical_op__input_carry 2'00 + assign \core_calculate_stage_27_logical_op__invert_out 1'0 + assign \core_calculate_stage_27_logical_op__write_cr0 1'0 + assign \core_calculate_stage_27_logical_op__output_carry 1'0 + assign \core_calculate_stage_27_logical_op__is_32bit 1'0 + assign \core_calculate_stage_27_logical_op__is_signed 1'0 + assign \core_calculate_stage_27_logical_op__data_len 4'0000 + assign \core_calculate_stage_27_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_27_logical_op__insn \core_calculate_stage_27_logical_op__data_len \core_calculate_stage_27_logical_op__is_signed \core_calculate_stage_27_logical_op__is_32bit \core_calculate_stage_27_logical_op__output_carry \core_calculate_stage_27_logical_op__write_cr0 \core_calculate_stage_27_logical_op__invert_out \core_calculate_stage_27_logical_op__input_carry \core_calculate_stage_27_logical_op__zero_a \core_calculate_stage_27_logical_op__invert_in { \core_calculate_stage_27_logical_op__oe__oe_ok \core_calculate_stage_27_logical_op__oe__oe } { \core_calculate_stage_27_logical_op__rc__rc_ok \core_calculate_stage_27_logical_op__rc__rc } { \core_calculate_stage_27_logical_op__imm_data__imm_ok \core_calculate_stage_27_logical_op__imm_data__imm } \core_calculate_stage_27_logical_op__fn_unit \core_calculate_stage_27_logical_op__insn_type } { \core_calculate_stage_26_logical_op__insn$118 \core_calculate_stage_26_logical_op__data_len$117 \core_calculate_stage_26_logical_op__is_signed$116 \core_calculate_stage_26_logical_op__is_32bit$115 \core_calculate_stage_26_logical_op__output_carry$114 \core_calculate_stage_26_logical_op__write_cr0$113 \core_calculate_stage_26_logical_op__invert_out$112 \core_calculate_stage_26_logical_op__input_carry$111 \core_calculate_stage_26_logical_op__zero_a$110 \core_calculate_stage_26_logical_op__invert_in$109 { \core_calculate_stage_26_logical_op__oe__oe_ok$108 \core_calculate_stage_26_logical_op__oe__oe$107 } { \core_calculate_stage_26_logical_op__rc__rc_ok$106 \core_calculate_stage_26_logical_op__rc__rc$105 } { \core_calculate_stage_26_logical_op__imm_data__imm_ok$104 \core_calculate_stage_26_logical_op__imm_data__imm$103 } \core_calculate_stage_26_logical_op__fn_unit$102 \core_calculate_stage_26_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_27_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_27_ra \core_calculate_stage_26_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_27_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_27_rb \core_calculate_stage_26_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_27_xer_so 1'0 + assign \core_calculate_stage_27_xer_so \core_calculate_stage_26_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_27_divisor_neg 1'0 + assign \core_calculate_stage_27_divisor_neg \core_calculate_stage_26_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_27_dividend_neg 1'0 + assign \core_calculate_stage_27_dividend_neg \core_calculate_stage_26_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_27_dive_abs_ov32 1'0 + assign \core_calculate_stage_27_dive_abs_ov32 \core_calculate_stage_26_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_27_dive_abs_ov64 1'0 + assign \core_calculate_stage_27_dive_abs_ov64 \core_calculate_stage_26_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_27_div_by_zero 1'0 + assign \core_calculate_stage_27_div_by_zero \core_calculate_stage_26_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_27_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_27_divisor_radicand \core_calculate_stage_26_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_27_operation 2'00 + assign \core_calculate_stage_27_operation \core_calculate_stage_26_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_27_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_27_quotient_root \core_calculate_stage_26_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_27_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_27_root_times_radicand \core_calculate_stage_26_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_27_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_27_compare_lhs \core_calculate_stage_26_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_27_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_27_compare_rhs \core_calculate_stage_26_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 + end + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$58 - process $group_68 - assign \muxid$58 2'00 - assign \muxid$58 \mul_pipe3_muxid$40 + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_27_muxid$133 sync init end attribute \enum_base_type "MicrOp" @@ -108446,7 +100580,7 @@ module \alu_mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$59 + wire width 7 \logical_op__insn_type$170 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -108460,1098 +100594,1171 @@ module \alu_mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$60 + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__imm$61 + wire width 1 \logical_op__rc__rc$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__imm_ok$62 + wire width 1 \logical_op__rc__rc_ok$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$63 + wire width 1 \logical_op__oe__oe$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc_ok$64 + wire width 1 \logical_op__oe__oe_ok$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$65 + wire width 1 \logical_op__invert_in$178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe_ok$66 + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_a$67 + wire width 2 \logical_op__input_carry$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__zero_a$68 + wire width 1 \logical_op__invert_out$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__invert_out$69 + wire width 1 \logical_op__write_cr0$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$70 + wire width 1 \logical_op__output_carry$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$71 + wire width 1 \logical_op__is_32bit$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$72 + wire width 1 \logical_op__is_signed$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$73 - process $group_69 - assign \mul_op__insn_type$59 7'0000000 - assign \mul_op__fn_unit$60 11'00000000000 - assign \mul_op__imm_data__imm$61 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__imm_ok$62 1'0 - assign \mul_op__rc__rc$63 1'0 - assign \mul_op__rc__rc_ok$64 1'0 - assign \mul_op__oe__oe$65 1'0 - assign \mul_op__oe__oe_ok$66 1'0 - assign \mul_op__invert_a$67 1'0 - assign \mul_op__zero_a$68 1'0 - assign \mul_op__invert_out$69 1'0 - assign \mul_op__write_cr0$70 1'0 - assign \mul_op__is_32bit$71 1'0 - assign \mul_op__is_signed$72 1'0 - assign \mul_op__insn$73 32'00000000000000000000000000000000 - assign { \mul_op__insn$73 \mul_op__is_signed$72 \mul_op__is_32bit$71 \mul_op__write_cr0$70 \mul_op__invert_out$69 \mul_op__zero_a$68 \mul_op__invert_a$67 { \mul_op__oe__oe_ok$66 \mul_op__oe__oe$65 } { \mul_op__rc__rc_ok$64 \mul_op__rc__rc$63 } { \mul_op__imm_data__imm_ok$62 \mul_op__imm_data__imm$61 } \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \mul_pipe3_mul_op__insn$55 \mul_pipe3_mul_op__is_signed$54 \mul_pipe3_mul_op__is_32bit$53 \mul_pipe3_mul_op__write_cr0$52 \mul_pipe3_mul_op__invert_out$51 \mul_pipe3_mul_op__zero_a$50 \mul_pipe3_mul_op__invert_a$49 { \mul_pipe3_mul_op__oe__oe_ok$48 \mul_pipe3_mul_op__oe__oe$47 } { \mul_pipe3_mul_op__rc__rc_ok$46 \mul_pipe3_mul_op__rc__rc$45 } { \mul_pipe3_mul_op__imm_data__imm_ok$44 \mul_pipe3_mul_op__imm_data__imm$43 } \mul_pipe3_mul_op__fn_unit$42 \mul_pipe3_mul_op__insn_type$41 } + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_27_logical_op__insn$151 \core_calculate_stage_27_logical_op__data_len$150 \core_calculate_stage_27_logical_op__is_signed$149 \core_calculate_stage_27_logical_op__is_32bit$148 \core_calculate_stage_27_logical_op__output_carry$147 \core_calculate_stage_27_logical_op__write_cr0$146 \core_calculate_stage_27_logical_op__invert_out$145 \core_calculate_stage_27_logical_op__input_carry$144 \core_calculate_stage_27_logical_op__zero_a$143 \core_calculate_stage_27_logical_op__invert_in$142 { \core_calculate_stage_27_logical_op__oe__oe_ok$141 \core_calculate_stage_27_logical_op__oe__oe$140 } { \core_calculate_stage_27_logical_op__rc__rc_ok$139 \core_calculate_stage_27_logical_op__rc__rc$138 } { \core_calculate_stage_27_logical_op__imm_data__imm_ok$137 \core_calculate_stage_27_logical_op__imm_data__imm$136 } \core_calculate_stage_27_logical_op__fn_unit$135 \core_calculate_stage_27_logical_op__insn_type$134 } sync init end - process $group_84 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$56 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_27_ra$152 sync init end - process $group_86 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_27_rb$153 sync init end - process $group_88 - assign \xer_ov 2'00 - assign \xer_ov_ok 1'0 - assign { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_27_xer_so$154 sync init end - process $group_90 - assign \xer_so 1'0 - assign \xer_so_ok 1'0 - assign { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$57 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_27_divisor_neg$155 sync init end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l" -module \src_l$97 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_27_dividend_neg$156 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_27_dive_abs_ov32$157 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_src - connect \Y $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_27_dive_abs_ov64$158 + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_27_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_27_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_27_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_27_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_27_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_27_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_27_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \q_int$next 3'000 + assign \r_busy$next 1'0 end sync init - update \q_int 3'000 + update \r_busy 1'0 sync posedge \coresync_clk - update \q_int \q_int$next + update \r_busy \r_busy$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $7 + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_src - connect \Y $11 + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next end - process $group_1 - assign \q_src 3'000 - assign \q_src $11 + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $13 + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next end - process $group_2 - assign \qn_src 3'000 - assign \qn_src $13 + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $15 + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next end - process $group_3 - assign \qlq_src 3'000 - assign \qlq_src $15 + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l" -module \opc_l$98 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.p" +module \p$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.n" +module \n$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + assign \trigger 1'0 + assign \trigger $1 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_28.core.trial0" +module \trial0$203 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100011 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l" -module \req_l$99 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_28.core.trial1" +module \trial1$204 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $1 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $3 - connect \B \s_req - connect \Y $5 - end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \q_int$next 4'0000 + assign \dr_times_trial_bits $3 end sync init - update \q_int 4'0000 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $7 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $7 - connect \Y $9 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100011 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $9 - connect \B \s_req - connect \Y $11 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end + connect $7 $10 process $group_1 - assign \q_req 4'0000 - assign \q_req $11 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 4'0000 - assign \qn_req $13 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_28.core.pe" +module \pe$205 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_3 - assign \qlq_req 4'0000 - assign \qlq_req $15 + process $group_1 + assign \n 1'0 + assign \n $1 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l" -module \rst_l$100 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_28.core" +module \core$202 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$203 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$204 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$205 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 end process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 + assign \operation$2 2'00 + assign \operation$2 \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l" -module \rok_l$101 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l" -module \alui_l$102 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 - end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l" -module \alu_l$103 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 - end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 - sync init + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'100011 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0" -module \mul0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_28" +module \core_calculate_stage_28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -109626,7 +101833,7 @@ module \mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_mul0__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -109640,83 +101847,73 @@ module \mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_mul0__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_mul0__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_mul0__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \oper_i_alu_mul0__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_mul0__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \oper_i_alu_mul0__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_mul0__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \oper_i_alu_mul0__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \oper_i_alu_mul0__zero_a + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \oper_i_alu_mul0__invert_out + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_alu_mul0__write_cr0 + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \oper_i_alu_mul0__is_32bit + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_alu_mul0__is_signed + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 15 \oper_i_alu_mul0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 16 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 17 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 input 18 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 19 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 20 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 21 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 22 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 1 input 23 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 25 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 26 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 27 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 28 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 29 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 30 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 31 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 32 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 output 33 \dest4_o - attribute \src "simple/issuer.py:89" - wire width 1 input 34 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_mul0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_mul0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_mul0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_mul0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_mul0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \alu_mul0_xer_so + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -109791,7 +101988,7 @@ module \mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_mul0_mul_op__insn_type + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -109805,826 +102002,836 @@ module \mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_mul0_mul_op__fn_unit + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_mul0_mul_op__imm_data__imm + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__imm_data__imm_ok + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__rc__rc + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__rc__rc_ok + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__oe__oe + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__oe__oe_ok + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__invert_a + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__zero_a + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__invert_out + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__write_cr0 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__is_32bit + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__is_signed + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_mul0_mul_op__insn + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_mul0_ra + wire width 64 output 52 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_mul0_rb + wire width 64 output 53 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \alu_mul0_xer_so$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_mul0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_mul0_p_ready_o - cell \alu_mul0 \alu_mul0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \cr_a_ok \cr_a_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_mul0_n_valid_o - connect \n_ready_i \alu_mul0_n_ready_i - connect \o \alu_mul0_o - connect \cr_a \alu_mul0_cr_a - connect \xer_ov \alu_mul0_xer_ov - connect \xer_so \alu_mul0_xer_so - connect \mul_op__insn_type \alu_mul0_mul_op__insn_type - connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit - connect \mul_op__imm_data__imm \alu_mul0_mul_op__imm_data__imm - connect \mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm_ok - connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc - connect \mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc_ok - connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe - connect \mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe_ok - connect \mul_op__invert_a \alu_mul0_mul_op__invert_a - connect \mul_op__zero_a \alu_mul0_mul_op__zero_a - connect \mul_op__invert_out \alu_mul0_mul_op__invert_out - connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 - connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit - connect \mul_op__is_signed \alu_mul0_mul_op__is_signed - connect \mul_op__insn \alu_mul0_mul_op__insn - connect \ra \alu_mul0_ra - connect \rb \alu_mul0_rb - connect \xer_so$1 \alu_mul0_xer_so$1 - connect \p_valid_i \alu_mul0_p_valid_i - connect \p_ready_o \alu_mul0_p_ready_o + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$202 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - cell \src_l$97 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$98 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \req_l_r_req$next - cell \req_l$99 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - cell \rst_l$100 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$101 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$102 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$103 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - cell $and $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $2 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $5 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $5 - connect \B \cu_rd__go_i - connect \Y $7 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $reduce_and $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $7 - connect \Y $4 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $2 - connect \B $4 - connect \Y $10 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $10 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $12 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $and $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $12 - connect \Y $14 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_2 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse $14 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_done - process $group_3 - assign \alu_done 1'0 - assign \alu_done \alu_mul0_n_valid_o + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly$next - process $group_4 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $and $19 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_29.core.trial0" +module \trial0$207 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $16 - connect \Y $18 - end - process $group_5 - assign \alu_pulse 1'0 - assign \alu_pulse $18 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" - wire width 4 \alu_pulsem - process $group_6 - assign \alu_pulsem 4'0000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - sync init + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 4 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 4 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 4 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - cell $and $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $20 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_7 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $20 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \prev_wr_go$next 4'0000 + assign \dr_times_trial_bits $3 end sync init - update \prev_wr_go 4'0000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 4 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wrmask_o - connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 4 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__rel_o - connect \B $24 - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $reduce_bool $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $26 - connect \Y $23 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $23 - connect \Y $22 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100010 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $22 - connect \Y $30 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_8 - assign \cu_done_o 1'0 - assign \cu_done_o $30 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $35 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_29.core.trial1" +module \trial1$208 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $34 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $or $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \B $34 - connect \Y $36 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_9 - assign \wr_any 1'0 - assign \wr_any $36 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $not $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_mul0_n_ready_i - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $and $41 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $38 - connect \Y $40 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 4 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $43 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $42 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100010 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $eq $45 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $42 - connect \B 1'0 - connect \Y $44 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $40 - connect \B $44 - connect \Y $46 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $eq $49 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_29.core.pe" +module \pe$209 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o + connect \A \i connect \B 1'0 - connect \Y $48 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $51 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_29.core" +module \core$206 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$207 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$208 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$209 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A $48 - connect \B \alu_mul0_n_ready_i - connect \Y $50 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $53 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $50 - connect \B \alu_mul0_n_valid_o - connect \Y $52 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $55 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $52 - connect \B \cu_busy_o - connect \Y $54 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_10 - assign \req_done 1'0 - assign \req_done $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - switch { $54 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \req_done 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $57 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $56 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_11 - assign \reset 1'0 - assign \reset $56 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - wire width 1 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - cell $or $59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $58 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_12 - assign \rst_r 1'0 - assign \rst_r $58 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 4 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - wire width 4 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - cell $or $61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $60 - end - process $group_13 - assign \reset_w 4'0000 - assign \reset_w $60 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - wire width 3 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - cell $or $63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $62 - end - process $group_14 - assign \reset_r 3'000 - assign \reset_r $62 - sync init - end - process $group_15 - assign \rok_l_s_rdok 1'0 - assign \rok_l_s_rdok \cu_issue_i - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - cell $and $65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_mul0_n_valid_o - connect \B \cu_busy_o - connect \Y $64 - end - process $group_16 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $64 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_17 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \all_rd - sync init - end - process $group_18 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \rst_r - sync init - end - process $group_19 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end process $group_20 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_21 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 3'000 - end + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init - update \src_l_s_src 3'000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_22 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 3'111 - end - sync init - update \src_l_r_src 3'111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - wire width 4 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - cell $and $67 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $66 - end - process $group_23 - assign \req_l_s_req 4'0000 - assign \req_l_s_req $66 - sync init + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'100010 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - wire width 4 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - cell $or $69 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $68 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_24 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $68 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 4'1111 - end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init - update \req_l_r_req 4'1111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_29" +module \core_calculate_stage_29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -110699,7 +102906,7 @@ module \mul0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -110713,1149 +102920,989 @@ module \mul0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__zero_a + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__invert_out + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__write_cr0 + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_signed + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_out - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_out$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 125 $70 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $71 - parameter \WIDTH 125 - connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__write_cr0 \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } - connect \B { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__invert_a { \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } - connect \S \cu_issue_i - connect \Y $70 + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$206 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end process $group_25 - assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 11'00000000000 - assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__imm_data__imm_ok 1'0 - assign \oper_r__rc__rc 1'0 - assign \oper_r__rc__rc_ok 1'0 - assign \oper_r__oe__oe 1'0 - assign \oper_r__oe__oe_ok 1'0 - assign \oper_r__invert_a 1'0 - assign \oper_r__zero_a 1'0 - assign \oper_r__invert_out 1'0 - assign \oper_r__write_cr0 1'0 - assign \oper_r__is_32bit 1'0 - assign \oper_r__is_signed 1'0 - assign \oper_r__insn 32'00000000000000000000000000000000 - assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $70 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - process $group_40 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__rc__rc$next \oper_l__rc__rc - assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok - assign \oper_l__oe__oe$next \oper_l__oe__oe - assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok - assign \oper_l__invert_a$next \oper_l__invert_a - assign \oper_l__zero_a$next \oper_l__zero_a - assign \oper_l__invert_out$next \oper_l__invert_out - assign \oper_l__write_cr0$next \oper_l__write_cr0 - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__insn$next \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__invert_a { \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - assign \oper_l__rc__rc$next 1'0 - assign \oper_l__rc__rc_ok$next 1'0 - assign \oper_l__oe__oe$next 1'0 - assign \oper_l__oe__oe_ok$next 1'0 - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 11'00000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__rc__rc 1'0 - update \oper_l__rc__rc_ok 1'0 - update \oper_l__oe__oe 1'0 - update \oper_l__oe__oe_ok 1'0 - update \oper_l__invert_a 1'0 - update \oper_l__zero_a 1'0 - update \oper_l__invert_out 1'0 - update \oper_l__write_cr0 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__rc__rc \oper_l__rc__rc$next - update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next - update \oper_l__oe__oe \oper_l__oe__oe$next - update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next - update \oper_l__invert_a \oper_l__invert_a$next - update \oper_l__zero_a \oper_l__zero_a$next - update \oper_l__invert_out \oper_l__invert_out$next - update \oper_l__write_cr0 \oper_l__write_cr0$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__insn \oper_l__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $72 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $73 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $75 - parameter \WIDTH 65 - connect \A { \data_r0_l__o_ok \data_r0_l__o } - connect \B { \o_ok \alu_mul0_o } - connect \S $73 - connect \Y $72 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - process $group_55 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - assign { \data_r0__o_ok \data_r0__o } $72 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $76 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $76 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - process $group_57 - assign \data_r0_l__o$next \data_r0_l__o - assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $76 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_mul0_o } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0_l__o_ok$next 1'0 - end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init - update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0_l__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0_l__o \data_r0_l__o$next - update \data_r0_l__o_ok \data_r0_l__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 5 $78 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $79 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $81 - parameter \WIDTH 5 - connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a } - connect \B { \cr_a_ok \alu_mul0_cr_a } - connect \S $79 - connect \Y $78 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_59 - assign \data_r1__cr_a 4'0000 - assign \data_r1__cr_a_ok 1'0 - assign { \data_r1__cr_a_ok \data_r1__cr_a } $78 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $82 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $83 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $82 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - process $group_61 - assign \data_r1_l__cr_a$next \data_r1_l__cr_a - assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $82 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_mul0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1_l__cr_a_ok$next 1'0 - end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init - update \data_r1_l__cr_a 4'0000 - update \data_r1_l__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r1_l__cr_a \data_r1_l__cr_a$next - update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 2 \data_r2__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r2__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 3 $84 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $85 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $87 - parameter \WIDTH 3 - connect \A { \data_r2_l__xer_ov_ok \data_r2_l__xer_ov } - connect \B { \xer_ov_ok \alu_mul0_xer_ov } - connect \S $85 - connect \Y $84 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init end - process $group_63 - assign \data_r2__xer_ov 2'00 - assign \data_r2__xer_ov_ok 1'0 - assign { \data_r2__xer_ov_ok \data_r2__xer_ov } $84 + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $88 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $89 + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_30.core.trial0" +module \trial0$211 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $88 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - process $group_65 - assign \data_r2_l__xer_ov$next \data_r2_l__xer_ov - assign \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $88 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov$next } { \xer_ov_ok \alu_mul0_xer_ov } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \data_r2_l__xer_ov_ok$next 1'0 + assign \dr_times_trial_bits $3 end sync init - update \data_r2_l__xer_ov 2'00 - update \data_r2_l__xer_ov_ok 1'0 - sync posedge \coresync_clk - update \data_r2_l__xer_ov \data_r2_l__xer_ov$next - update \data_r2_l__xer_ov_ok \data_r2_l__xer_ov_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r3__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r3_l__xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $90 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $91 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $93 - parameter \WIDTH 2 - connect \A { \data_r3_l__xer_so_ok \data_r3_l__xer_so } - connect \B { \xer_so_ok \alu_mul0_xer_so } - connect \S $91 - connect \Y $90 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_67 - assign \data_r3__xer_so 1'0 - assign \data_r3__xer_so_ok 1'0 - assign { \data_r3__xer_so_ok \data_r3__xer_so } $90 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100001 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $94 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $94 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_69 - assign \data_r3_l__xer_so$next \data_r3_l__xer_so - assign \data_r3_l__xer_so_ok$next \data_r3_l__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $94 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \alu_mul0_xer_so } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \data_r3_l__xer_so_ok$next 1'0 + assign \trial_compare_rhs $7 [191:0] end sync init - update \data_r3_l__xer_so 1'0 - update \data_r3_l__xer_so_ok 1'0 - sync posedge \coresync_clk - update \data_r3_l__xer_so \data_r3_l__xer_so$next - update \data_r3_l__xer_so_ok \data_r3_l__xer_so_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $97 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_30.core.trial1" +module \trial1$212 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r0__o_ok - connect \B \cu_busy_o - connect \Y $96 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $99 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r1__cr_a_ok - connect \B \cu_busy_o - connect \Y $98 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $101 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r2__xer_ov_ok - connect \B \cu_busy_o - connect \Y $100 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $103 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r3__xer_so_ok - connect \B \cu_busy_o - connect \Y $102 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100001 + connect \Y $8 end - process $group_71 - assign \cu_wrmask_o 4'0000 - assign \cu_wrmask_o { $102 $100 $98 $96 } - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_72 - assign \alu_mul0_mul_op__insn_type 7'0000000 - assign \alu_mul0_mul_op__fn_unit 11'00000000000 - assign \alu_mul0_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_mul0_mul_op__imm_data__imm_ok 1'0 - assign \alu_mul0_mul_op__rc__rc 1'0 - assign \alu_mul0_mul_op__rc__rc_ok 1'0 - assign \alu_mul0_mul_op__oe__oe 1'0 - assign \alu_mul0_mul_op__oe__oe_ok 1'0 - assign \alu_mul0_mul_op__invert_a 1'0 - assign \alu_mul0_mul_op__zero_a 1'0 - assign \alu_mul0_mul_op__invert_out 1'0 - assign \alu_mul0_mul_op__write_cr0 1'0 - assign \alu_mul0_mul_op__is_32bit 1'0 - assign \alu_mul0_mul_op__is_signed 1'0 - assign \alu_mul0_mul_op__insn 32'00000000000000000000000000000000 - assign { \alu_mul0_mul_op__insn \alu_mul0_mul_op__is_signed \alu_mul0_mul_op__is_32bit \alu_mul0_mul_op__write_cr0 \alu_mul0_mul_op__invert_out \alu_mul0_mul_op__zero_a \alu_mul0_mul_op__invert_a { \alu_mul0_mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe } { \alu_mul0_mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc } { \alu_mul0_mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm } \alu_mul0_mul_op__fn_unit \alu_mul0_mul_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 $104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - cell $mux $105 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \oper_r__zero_a - connect \Y $104 - end - process $group_87 - assign \src_sel 1'0 - assign \src_sel $104 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_30.core.pe" +module \pe$213 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 64 $106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $107 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \oper_r__zero_a - connect \Y $106 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_88 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $106 + process $group_1 + assign \n 1'0 + assign \n $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 1 \src_sel$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - cell $mux $110 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \oper_r__imm_data__imm_ok - connect \Y $109 - end - process $group_89 - assign \src_sel$108 1'0 - assign \src_sel$108 $109 - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_30.core" +module \core$210 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$211 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$212 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165" - wire width 64 \src_or_imm$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 64 $112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $113 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \oper_r__imm_data__imm - connect \S \oper_r__imm_data__imm_ok - connect \Y $112 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$213 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end - process $group_90 - assign \src_or_imm$111 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$111 $112 + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $114 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $115 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $114 - end - process $group_91 - assign \alu_mul0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_mul0_ra $114 + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation sync init end - process $group_92 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src_or_imm - end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $116 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $117 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$111 - connect \S \src_sel$108 - connect \Y $116 end - process $group_93 - assign \alu_mul0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_mul0_rb $116 + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - process $group_94 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel$108 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src_or_imm$111 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $118 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $119 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $118 end - process $group_95 - assign \alu_mul0_xer_so$1 1'0 - assign \alu_mul0_xer_so$1 $118 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end - process $group_96 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init - update \src_r2 1'0 - sync posedge \coresync_clk - update \src_r2 \src_r2$next end - process $group_97 - assign \alu_mul0_p_valid_i 1'0 - assign \alu_mul0_p_valid_i \alui_l_q_alui + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - wire width 1 $120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - cell $and $121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_mul0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $120 - end - process $group_98 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $120 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next + update $verilog_initial_trigger 1'0 end - process $group_99 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end - process $group_100 - assign \alu_mul0_n_ready_i 1'0 - assign \alu_mul0_n_ready_i \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - wire width 1 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - cell $and $123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_mul0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $122 - end - process $group_101 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $122 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next end - process $group_102 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end - process $group_103 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $125 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $124 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - wire width 1 $126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - cell $not $127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \oper_r__zero_a - connect \Y $126 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - wire width 1 $128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - cell $not $129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \oper_r__imm_data__imm_ok - connect \Y $128 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $124 - connect \B { 1'1 $128 $126 } - connect \Y $130 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $not $133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $132 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 3 $134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $130 - connect \B $132 - connect \Y $134 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - process $group_104 - assign \cu_rd__rel_o 3'000 - assign \cu_rd__rel_o $134 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $136 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $139 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $138 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $140 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $143 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $142 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 4 $144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \req_l_q_req - connect \B { $136 $138 $140 $142 } - connect \Y $144 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 4 $146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $144 - connect \B \cu_wrmask_o - connect \Y $146 - end - process $group_105 - assign \cu_wr__rel_o 4'0000 - assign \cu_wr__rel_o $146 - sync init + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $149 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $148 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_106 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $148 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $151 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $150 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_107 - assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $150 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $153 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $152 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_108 - assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $152 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest3_o { \data_r2__xer_ov_ok \data_r2__xer_ov } [1:0] - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $155 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $154 - end - process $group_109 - assign \dest4_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $154 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0] - end - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p" -module \p$104 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n" -module \n$105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.p" -module \p$107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init + parameter \B_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \next_bits + connect \B 6'100001 + connect \Y $30 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.n" -module \n$108 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.input" -module \input$109 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_30" +module \core_calculate_stage_30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -111932,7 +103979,7 @@ module \input$109 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \sr_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -111946,47 +103993,73 @@ module \input$109 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \sr_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \sr_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \sr_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \sr_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \sr_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \sr_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \sr_op__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \sr_op__output_carry + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \sr_op__input_cr + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \sr_op__output_cr + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \sr_op__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \sr_op__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \ra + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \rb + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \rc + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 20 \xer_ca + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -112061,7 +104134,7 @@ module \input$109 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \sr_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -112075,907 +104148,834 @@ module \input$109 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 23 \sr_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \sr_op__imm_data__imm$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \sr_op__imm_data__imm_ok$5 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \sr_op__rc__rc$6 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \sr_op__rc__rc_ok$7 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \sr_op__oe__oe$8 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \sr_op__oe__oe_ok$9 + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 31 \sr_op__input_carry$10 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \sr_op__output_carry$11 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \sr_op__input_cr$12 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \sr_op__output_cr$13 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \sr_op__is_32bit$14 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \sr_op__is_signed$15 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 37 \sr_op__insn$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 38 \ra$17 + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 39 \rb$18 + wire width 64 output 52 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 40 \rc$19 + wire width 64 output 53 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 output 41 \xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$210 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end process $group_0 - assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \a \ra + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end process $group_1 - assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$17 \a - sync init - end - process $group_2 - assign \xer_ca$20 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36" - switch \sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37" - attribute \nmigen.decoding "ZERO/0" - case 2'00 - assign \xer_ca$20 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \xer_ca$20 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" - attribute \nmigen.decoding "CA/2" - case 2'10 - assign \xer_ca$20 \xer_ca - end - sync init - end - process $group_3 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - process $group_4 - assign \sr_op__insn_type$2 7'0000000 - assign \sr_op__fn_unit$3 11'00000000000 - assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$5 1'0 - assign \sr_op__rc__rc$6 1'0 - assign \sr_op__rc__rc_ok$7 1'0 - assign \sr_op__oe__oe$8 1'0 - assign \sr_op__oe__oe_ok$9 1'0 - assign { } 0'0 - assign \sr_op__input_carry$10 2'00 - assign \sr_op__output_carry$11 1'0 - assign \sr_op__input_cr$12 1'0 - assign \sr_op__output_cr$13 1'0 - assign \sr_op__is_32bit$14 1'0 - assign \sr_op__is_signed$15 1'0 - assign \sr_op__insn$16 32'00000000000000000000000000000000 - assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init end process $group_20 - assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$18 \rb + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end process $group_21 - assign \rc$19 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rc$19 \rc + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator.rotl" -module \rotl - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" - wire width 64 input 0 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" - wire width 6 input 1 \b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" - wire width 64 output 2 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - wire width 8 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 8 - connect \A 7'1000000 - connect \B \b - connect \Y $2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" - cell $shift $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A { \a \a } - connect \B $2 - connect \Y $1 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - process $group_0 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o $1 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator" -module \rotator - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47" - wire width 5 input 0 \me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48" - wire width 5 input 1 \mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" - wire width 1 input 2 \mb_extra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52" - wire width 64 input 3 \rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - wire width 64 input 4 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" - wire width 7 input 5 \shift - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" - wire width 1 input 6 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" - wire width 1 input 7 \arith - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" - wire width 1 input 8 \right_shift - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" - wire width 1 input 9 \clear_left - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" - wire width 1 input 10 \clear_right - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" - wire width 1 input 11 \sign_ext_rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" - wire width 64 output 12 \result_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" - wire width 1 output 13 \carry_out_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" - wire width 64 \rotl_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" - wire width 6 \rotl_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" - wire width 64 \rotl_o - cell \rotl \rotl - connect \a \rotl_a - connect \b \rotl_b - connect \o \rotl_o + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:78" - wire width 32 \hi32 - process $group_0 - assign \hi32 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82" - switch { \sign_ext_rs \is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82" - case 2'-1 - assign \hi32 \rs [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:84" - case 2'1- - assign \hi32 { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:87" - case - assign \hi32 \rs [63:32] - end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79" - wire width 64 \repl32 - process $group_1 - assign \repl32 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \repl32 { \hi32 \rs [31:0] } + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:91" - wire width 6 \shift_signed - process $group_2 - assign \shift_signed 6'000000 - assign \shift_signed \shift [5:0] + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:70" - wire width 6 \rot_count - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96" - wire width 7 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96" - wire width 7 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96" - cell $neg $3 - parameter \A_SIGNED 1 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \shift_signed - connect \Y $2 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - connect $1 $2 - process $group_3 - assign \rot_count 6'000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:95" - switch { \right_shift } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:95" - case 1'1 - assign \rot_count $1 [5:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:97" - case - assign \rot_count \shift [5:0] - end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - process $group_4 - assign \rotl_a 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rotl_a \repl32 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - process $group_5 - assign \rotl_b 6'000000 - assign \rotl_b \rot_count + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:71" - wire width 64 \rot - process $group_6 - assign \rot 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rot \rotl_o + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:72" - wire width 7 \sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \Y $4 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107" - cell $and $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift [6] - connect \B $4 - connect \Y $6 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - process $group_7 - assign \sh 7'0000000 - assign \sh { $6 \shift [5:0] } + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73" - wire width 7 \mb$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48" - wire width 7 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 7 - connect \A \mb - connect \Y $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123" - cell $not $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sh [5] - connect \Y $11 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init end - process $group_8 - assign \mb$8 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:113" - switch { \right_shift \clear_left } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:113" - case 2'-1 - assign \mb$8 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:115" - switch { \is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:115" - case 1'1 - assign \mb$8 [6:5] 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:117" - case - assign \mb$8 [6:5] { 1'0 \mb_extra } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:119" - case 2'1- - assign \mb$8 \sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122" - switch { \is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122" - case 1'1 - assign \mb$8 [6:5] { \sh [5] $11 } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:124" - case - assign \mb$8 { 1'0 \is_32bit 5'00000 } - end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74" - wire width 7 \me$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128" - cell $and $15 + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_31.core.trial0" +module \trial0$215 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \clear_right - connect \B \is_32bit - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_left - connect \Y $16 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_right - connect \B $16 - connect \Y $18 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:136" - wire width 6 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:136" - cell $not $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \sh [5:0] - connect \Y $20 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_9 - assign \me$13 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128" - switch { $18 $14 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128" - case 2'-1 - assign \me$13 { 2'01 \me } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - case 2'1- - assign \me$13 { 1'0 \mb_extra \mb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - case - assign \me$13 { \sh [6] $20 } + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14" - wire width 64 \right_mask - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15" - cell $le $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \mb$8 - connect \B 7'1000000 - connect \Y $22 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16" - wire width 257 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16" - wire width 8 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16" - cell $sub $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A 7'1000000 - connect \B \mb$8 - connect \Y $25 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100000 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16" - wire width 256 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16" - cell $sshl $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 256 - connect \A 1'1 - connect \B $25 - connect \Y $27 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16" - wire width 257 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16" - cell $sub $30 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_31.core.trial1" +module \trial1$216 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 256 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 257 - connect \A $27 + parameter \Y_WIDTH 1 + connect \A \operation connect \B 1'1 - connect \Y $29 + connect \Y $1 end - connect $24 $29 - process $group_10 - assign \right_mask 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \right_mask $24 [63:0] + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75" - wire width 64 \mr - process $group_11 - assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mr \right_mask - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21" - wire width 64 \left_mask - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22" - wire width 257 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22" - wire width 257 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22" - wire width 8 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22" - cell $sub $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A 6'111111 - connect \B \me$13 - connect \Y $33 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1100000 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22" - wire width 256 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22" - cell $sshl $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 256 - connect \A 1'1 - connect \B $33 - connect \Y $35 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_31.core.pe" +module \pe$217 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22" - wire width 257 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22" - cell $sub $38 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 256 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 257 - connect \A $35 - connect \B 1'1 - connect \Y $37 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22" - cell $not $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 257 - parameter \Y_WIDTH 257 - connect \A $37 - connect \Y $32 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init end - connect $31 $32 - process $group_12 - assign \left_mask 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \left_mask $31 [63:0] +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_31.core" +module \core$214 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$215 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$216 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$217 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76" - wire width 64 \ml - process $group_13 - assign \ml 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ml \left_mask + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77" - wire width 2 \output_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147" - cell $not $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_right - connect \Y $40 + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147" - cell $and $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_left - connect \B $40 - connect \Y $42 + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147" - cell $or $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $42 - connect \B \right_shift - connect \Y $44 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:148" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:148" - cell $and $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \arith - connect \B \repl32 [63] - connect \Y $46 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150" - cell $gt $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \mb$8 [5:0] - connect \B \me$13 [5:0] - connect \Y $48 + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150" - cell $and $51 + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \clear_right - connect \B $48 - connect \Y $50 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end process $group_14 - assign \output_mode 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147" - switch { $44 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147" - case 1'1 - assign \output_mode { 1'1 $46 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:149" - case - assign \output_mode { 1'0 $50 } - end + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - wire width 64 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - cell $and $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \B \ml - connect \Y $52 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - wire width 64 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - cell $and $55 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rot - connect \B $52 - connect \Y $54 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - wire width 64 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - wire width 64 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - cell $and $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \B \ml - connect \Y $57 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - cell $not $59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $57 - connect \Y $56 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - wire width 64 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - cell $and $61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B $56 - connect \Y $60 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - wire width 64 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156" - cell $or $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $54 - connect \B $60 - connect \Y $62 + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - wire width 64 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - cell $or $65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \B \ml - connect \Y $64 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - wire width 64 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - cell $and $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rot - connect \B $64 - connect \Y $66 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - wire width 64 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - wire width 64 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - cell $or $70 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \B \ml - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - cell $not $71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $69 - connect \Y $68 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - wire width 64 $72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - cell $and $73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B $68 - connect \Y $72 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - wire width 64 $74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158" - cell $or $75 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $66 - connect \B $72 - connect \Y $74 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:160" - wire width 64 $76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:160" - cell $and $77 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rot - connect \B \mr - connect \Y $76 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - wire width 64 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $not $79 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \Y $78 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - wire width 64 $80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $or $81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rot - connect \B $78 - connect \Y $80 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_15 - assign \result_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154" - switch \output_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155" - case 2'00 - assign \result_o $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157" - case 2'01 - assign \result_o $74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159" - case 2'10 - assign \result_o $76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - case 2'11 - assign \result_o $80 - end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - wire width 1 $82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - wire width 64 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $not $84 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 parameter \Y_WIDTH 64 - connect \A \ml - connect \Y $83 + connect \A \next_bits + connect \B 6'100000 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - wire width 64 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $86 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \rs - connect \B $83 - connect \Y $85 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $reduce_bool $87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A $85 - connect \Y $82 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_16 - assign \carry_out_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154" - switch \output_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155" - case 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - case 2'11 - assign \carry_out_o $82 - end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main" -module \main$110 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7.core_calculate_stage_31" +module \core_calculate_stage_31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" @@ -113052,7 +105052,7 @@ module \main$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \sr_op__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -113066,45 +105066,73 @@ module \main$110 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \sr_op__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \sr_op__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \sr_op__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \sr_op__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \sr_op__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \sr_op__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \sr_op__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \sr_op__output_carry + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \sr_op__input_cr + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \sr_op__output_cr + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \sr_op__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \sr_op__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \sr_op__insn + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \ra + wire width 64 input 19 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \rb + wire width 64 input 20 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \rc + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 20 \muxid$1 + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -113179,7 +105207,7 @@ module \main$110 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 21 \sr_op__insn_type$2 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -113193,263 +105221,250 @@ module \main$110 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 22 \sr_op__fn_unit$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 23 \sr_op__imm_data__imm$4 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \sr_op__imm_data__imm_ok$5 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \sr_op__rc__rc$6 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \sr_op__rc__rc_ok$7 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \sr_op__oe__oe$8 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \sr_op__oe__oe_ok$9 + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 30 \sr_op__input_carry$10 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \sr_op__output_carry$11 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \sr_op__input_cr$12 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \sr_op__output_cr$13 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \sr_op__is_32bit$14 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \sr_op__is_signed$15 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 36 \sr_op__insn$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 37 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 38 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 39 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47" - wire width 5 \rotator_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48" - wire width 5 \rotator_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" - wire width 1 \rotator_mb_extra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52" - wire width 64 \rotator_rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - wire width 64 \rotator_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" - wire width 7 \rotator_shift - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" - wire width 1 \rotator_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" - wire width 1 \rotator_arith - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" - wire width 1 \rotator_right_shift - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" - wire width 1 \rotator_clear_left - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" - wire width 1 \rotator_clear_right - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" - wire width 1 \rotator_sign_ext_rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" - wire width 64 \rotator_result_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" - wire width 1 \rotator_carry_out_o - cell \rotator \rotator - connect \me \rotator_me - connect \mb \rotator_mb - connect \mb_extra \rotator_mb_extra - connect \rs \rotator_rs - connect \ra \rotator_ra - connect \shift \rotator_shift - connect \is_32bit \rotator_is_32bit - connect \arith \rotator_arith - connect \right_shift \rotator_right_shift - connect \clear_left \rotator_clear_left - connect \clear_right \rotator_clear_right - connect \sign_ext_rs \rotator_sign_ext_rs - connect \result_o \rotator_result_o - connect \carry_out_o \rotator_carry_out_o + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$214 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:42" - wire width 5 \mb process $group_0 - assign \mb 5'00000 - assign \mb { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] } + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:43" - wire width 5 \me process $group_1 - assign \me 5'00000 - assign \me { \sr_op__insn [5] \sr_op__insn [4] \sr_op__insn [3] \sr_op__insn [2] \sr_op__insn [1] } + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:44" - wire width 1 \mb_extra - process $group_2 - assign \mb_extra 1'0 - assign \mb_extra { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] \sr_op__insn [5] } [0] + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init end - process $group_3 - assign \rotator_me 5'00000 - assign \rotator_me \me + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end - process $group_4 - assign \rotator_mb 5'00000 - assign \rotator_mb \mb + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - process $group_5 - assign \rotator_mb_extra 1'0 - assign \rotator_mb_extra \mb_extra + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - process $group_6 - assign \rotator_rs 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rotator_rs \rc + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - process $group_7 - assign \rotator_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rotator_ra \ra + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init end - process $group_8 - assign \rotator_shift 7'0000000 - assign \rotator_shift \rb [6:0] + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - process $group_9 - assign \rotator_is_32bit 1'0 - assign \rotator_is_32bit \sr_op__is_32bit + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - process $group_10 - assign \rotator_arith 1'0 - assign \rotator_arith \sr_op__is_signed + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - process $group_11 - assign \o_ok 1'0 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66" - switch \sr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67" - attribute \nmigen.decoding "OP_SHL/60" - case 7'0111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68" - attribute \nmigen.decoding "OP_SHR/61" - case 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" - attribute \nmigen.decoding "OP_RLC/56" - case 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" - attribute \nmigen.decoding "OP_RLCL/57" - case 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71" - attribute \nmigen.decoding "OP_RLCR/58" - case 7'0111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72" - attribute \nmigen.decoding "OP_EXTSWSLI/32" - case 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73" - attribute \nmigen.decoding "" - case - assign \o_ok 1'0 - end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:65" - wire width 4 \mode - process $group_12 - assign \mode 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66" - switch \sr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67" - attribute \nmigen.decoding "OP_SHL/60" - case 7'0111100 - assign \mode 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68" - attribute \nmigen.decoding "OP_SHR/61" - case 7'0111101 - assign \mode 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" - attribute \nmigen.decoding "OP_RLC/56" - case 7'0111000 - assign \mode 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" - attribute \nmigen.decoding "OP_RLCL/57" - case 7'0111001 - assign \mode 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71" - attribute \nmigen.decoding "OP_RLCR/58" - case 7'0111010 - assign \mode 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72" - attribute \nmigen.decoding "OP_EXTSWSLI/32" - case 7'0100000 - assign \mode 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73" - attribute \nmigen.decoding "" - case - end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - process $group_13 - assign \rotator_right_shift 1'0 - assign \rotator_clear_left 1'0 - assign \rotator_clear_right 1'0 - assign \rotator_sign_ext_rs 1'0 - assign { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - process $group_17 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o \rotator_result_o + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs sync init end - process $group_18 - assign \xer_ca 2'00 - assign \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - process $group_19 - assign \muxid$1 2'00 - assign \muxid$1 \muxid + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - process $group_20 - assign \sr_op__insn_type$2 7'0000000 - assign \sr_op__fn_unit$3 11'00000000000 - assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$5 1'0 - assign \sr_op__rc__rc$6 1'0 - assign \sr_op__rc__rc_ok$7 1'0 - assign \sr_op__oe__oe$8 1'0 - assign \sr_op__oe__oe_ok$9 1'0 - assign { } 0'0 - assign \sr_op__input_carry$10 2'00 - assign \sr_op__output_carry$11 1'0 - assign \sr_op__input_cr$12 1'0 - assign \sr_op__output_cr$13 1'0 - assign \sr_op__is_32bit$14 1'0 - assign \sr_op__is_signed$15 1'0 - assign \sr_op__insn$16 32'00000000000000000000000000000000 - assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.output" -module \output$111 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_7" +module \pipe_middle_7 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid + wire width 2 input 4 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -113524,7 +105539,7 @@ module \output$111 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \sr_op__insn_type + wire width 7 input 5 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -113538,47 +105553,79 @@ module \output$111 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \sr_op__fn_unit + wire width 11 input 6 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__imm + wire width 64 input 7 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \sr_op__imm_data__imm_ok + wire width 1 input 8 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \sr_op__rc__rc + wire width 1 input 9 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \sr_op__rc__rc_ok + wire width 1 input 10 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \sr_op__oe__oe + wire width 1 input 11 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \sr_op__oe__oe_ok + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \sr_op__input_carry + wire width 2 input 15 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \sr_op__output_carry + wire width 1 input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \sr_op__input_cr + wire width 1 input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \sr_op__output_cr + wire width 1 input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \sr_op__is_32bit + wire width 1 input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \sr_op__is_signed + wire width 1 input 20 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 18 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 19 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 20 \xer_ca + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 21 \muxid$1 + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -113653,7 +105700,9 @@ module \output$111 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 22 \sr_op__insn_type$2 + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -113667,317 +105716,143 @@ module \output$111 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 23 \sr_op__fn_unit$3 + wire width 11 output 41 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 24 \sr_op__imm_data__imm$4 + wire width 11 \logical_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \sr_op__imm_data__imm_ok$5 + wire width 64 output 42 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \sr_op__rc__rc$6 + wire width 64 \logical_op__imm_data__imm$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \sr_op__rc__rc_ok$7 + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \sr_op__oe__oe$8 + wire width 1 \logical_op__imm_data__imm_ok$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \sr_op__oe__oe_ok$9 + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 31 \sr_op__input_carry$10 + wire width 2 output 50 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \sr_op__output_carry$11 + wire width 2 \logical_op__input_carry$12$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \sr_op__input_cr$12 + wire width 1 output 51 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \sr_op__output_cr$13 + wire width 1 \logical_op__invert_out$13$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \sr_op__is_32bit$14 + wire width 1 output 52 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \sr_op__is_signed$15 + wire width 1 \logical_op__write_cr0$14$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 37 \sr_op__insn$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 38 \o$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 39 \o_ok$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 40 \cr_a$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 41 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 42 \xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 43 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" - wire width 65 \o$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $22 - end - process $group_0 - assign \o$21 65'00000000000000000000000000000000000000000000000000000000000000000 - assign \o$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" - wire width 64 \target - process $group_1 - assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$21 [63:0] - sync init - end - process $group_2 - assign \xer_ca$20 2'00 - assign \xer_ca$20 \xer_ca - sync init - end - process $group_3 - assign \xer_ca_ok 1'0 - assign \xer_ca_ok \sr_op__output_carry - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" - wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" - cell $eq $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \sr_op__insn_type - connect \B 7'0001010 - connect \Y $24 - end - process $group_4 - assign \is_cmp 1'0 - assign \is_cmp $24 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" - wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" - cell $eq $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \sr_op__insn_type - connect \B 7'0001100 - connect \Y $26 - end - process $group_5 - assign \is_cmpeqb 1'0 - assign \is_cmpeqb $26 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" - wire width 1 \msb_test - process $group_6 - assign \msb_test 1'0 - assign \msb_test \target [63] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $28 - end - process $group_7 - assign \is_nzero 1'0 - assign \is_nzero $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" - wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $not $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $and $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $30 - connect \Y $32 - end - process $group_8 - assign \is_positive 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_positive \msb_test - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_positive $32 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" - wire width 1 \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $not $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" - cell $and $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $34 - connect \Y $36 - end - process $group_9 - assign \is_negative 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - switch { \is_cmp } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" - case 1'1 - assign \is_negative $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" - case - assign \is_negative \msb_test - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" - cell $not $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $38 - end - process $group_10 - assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - switch { \is_cmpeqb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" - case 1'1 - assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - case - assign \cr0 { \is_negative \is_positive $38 1'0 } - end - sync init - end - process $group_11 - assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$17 \o$21 [63:0] - sync init - end - process $group_12 - assign \o_ok$18 1'0 - assign \o_ok$18 \o_ok - sync init - end - process $group_13 - assign \cr_a$19 4'0000 - assign \cr_a$19 \cr0 - sync init - end + wire width 1 output 53 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 $40 + wire width 1 \logical_op__output_carry$15$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 0 - parameter \Y_WIDTH 1 - connect \A { } - connect \Y $40 - end - process $group_14 - assign \cr_a_ok 1'0 - assign \cr_a_ok $40 - sync init - end - process $group_15 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$200 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_16 - assign \sr_op__insn_type$2 7'0000000 - assign \sr_op__fn_unit$3 11'00000000000 - assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$5 1'0 - assign \sr_op__rc__rc$6 1'0 - assign \sr_op__rc__rc_ok$7 1'0 - assign \sr_op__oe__oe$8 1'0 - assign \sr_op__oe__oe_ok$9 1'0 - assign { } 0'0 - assign \sr_op__input_carry$10 2'00 - assign \sr_op__output_carry$11 1'0 - assign \sr_op__input_cr$12 1'0 - assign \sr_op__output_cr$13 1'0 - assign \sr_op__is_32bit$14 1'0 - assign \sr_op__is_signed$15 1'0 - assign \sr_op__insn$16 32'00000000000000000000000000000000 - assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } - sync init + cell \n$201 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe" -module \pipe$106 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid + wire width 2 \core_calculate_stage_28_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -114052,7 +105927,7 @@ module \pipe$106 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \sr_op__insn_type + wire width 7 \core_calculate_stage_28_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -114066,53 +105941,73 @@ module \pipe$106 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \sr_op__fn_unit + wire width 11 \core_calculate_stage_28_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \sr_op__imm_data__imm + wire width 64 \core_calculate_stage_28_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \sr_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_28_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \sr_op__rc__rc + wire width 1 \core_calculate_stage_28_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \sr_op__rc__rc_ok + wire width 1 \core_calculate_stage_28_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \sr_op__oe__oe + wire width 1 \core_calculate_stage_28_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \sr_op__oe__oe_ok + wire width 1 \core_calculate_stage_28_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_28_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_28_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 14 \sr_op__input_carry + wire width 2 \core_calculate_stage_28_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \sr_op__output_carry + wire width 1 \core_calculate_stage_28_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \sr_op__input_cr + wire width 1 \core_calculate_stage_28_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \sr_op__output_cr + wire width 1 \core_calculate_stage_28_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \sr_op__is_32bit + wire width 1 \core_calculate_stage_28_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \sr_op__is_signed + wire width 1 \core_calculate_stage_28_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 20 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 21 \ra + wire width 4 \core_calculate_stage_28_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_28_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 22 \rb + wire width 64 \core_calculate_stage_28_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \rc + wire width 64 \core_calculate_stage_28_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 24 \xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 25 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 26 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 27 \muxid$1 + wire width 1 \core_calculate_stage_28_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_28_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_28_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_28_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_28_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_28_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_28_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_28_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_28_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_28_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_28_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_28_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next + wire width 2 \core_calculate_stage_28_muxid$34 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -114187,9 +106082,7 @@ module \pipe$106 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 28 \sr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$2$next + wire width 7 \core_calculate_stage_28_logical_op__insn_type$35 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -114203,99 +106096,141 @@ module \pipe$106 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 29 \sr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \sr_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 30 \sr_op__imm_data__imm$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__imm$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \sr_op__imm_data__imm_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__imm_ok$5$next + wire width 11 \core_calculate_stage_28_logical_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \sr_op__rc__rc$6 + wire width 64 \core_calculate_stage_28_logical_op__imm_data__imm$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc$6$next + wire width 1 \core_calculate_stage_28_logical_op__imm_data__imm_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \sr_op__rc__rc_ok$7 + wire width 1 \core_calculate_stage_28_logical_op__rc__rc$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc_ok$7$next + wire width 1 \core_calculate_stage_28_logical_op__rc__rc_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \sr_op__oe__oe$8 + wire width 1 \core_calculate_stage_28_logical_op__oe__oe$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe$8$next + wire width 1 \core_calculate_stage_28_logical_op__oe__oe_ok$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \sr_op__oe__oe_ok$9 + wire width 1 \core_calculate_stage_28_logical_op__invert_in$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe_ok$9$next + wire width 1 \core_calculate_stage_28_logical_op__zero_a$44 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 37 \sr_op__input_carry$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \sr_op__output_carry$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_carry$11$next + wire width 2 \core_calculate_stage_28_logical_op__input_carry$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \sr_op__input_cr$12 + wire width 1 \core_calculate_stage_28_logical_op__invert_out$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__input_cr$12$next + wire width 1 \core_calculate_stage_28_logical_op__write_cr0$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \sr_op__output_cr$13 + wire width 1 \core_calculate_stage_28_logical_op__output_carry$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_cr$13$next + wire width 1 \core_calculate_stage_28_logical_op__is_32bit$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \sr_op__is_32bit$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_32bit$14$next + wire width 1 \core_calculate_stage_28_logical_op__is_signed$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \sr_op__is_signed$15 + wire width 4 \core_calculate_stage_28_logical_op__data_len$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_signed$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 43 \sr_op__insn$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 44 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 45 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 46 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ca$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$next - cell \p$107 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$108 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + wire width 32 \core_calculate_stage_28_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_28_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_28_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_28_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_28_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_28_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_28_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_28_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_28_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_28_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_28_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_28_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_28_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_28_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_28_compare_rhs$66 + cell \core_calculate_stage_28 \core_calculate_stage_28 + connect \muxid \core_calculate_stage_28_muxid + connect \logical_op__insn_type \core_calculate_stage_28_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_28_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_28_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_28_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_28_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_28_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_28_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_28_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_28_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_28_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_28_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_28_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_28_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_28_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_28_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_28_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_28_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_28_logical_op__insn + connect \ra \core_calculate_stage_28_ra + connect \rb \core_calculate_stage_28_rb + connect \xer_so \core_calculate_stage_28_xer_so + connect \divisor_neg \core_calculate_stage_28_divisor_neg + connect \dividend_neg \core_calculate_stage_28_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_28_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_28_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_28_div_by_zero + connect \divisor_radicand \core_calculate_stage_28_divisor_radicand + connect \operation \core_calculate_stage_28_operation + connect \quotient_root \core_calculate_stage_28_quotient_root + connect \root_times_radicand \core_calculate_stage_28_root_times_radicand + connect \compare_lhs \core_calculate_stage_28_compare_lhs + connect \compare_rhs \core_calculate_stage_28_compare_rhs + connect \muxid$1 \core_calculate_stage_28_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_28_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_28_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_28_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_28_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_28_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_28_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_28_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_28_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_28_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_28_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_28_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_28_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_28_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_28_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_28_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_28_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_28_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_28_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_28_ra$53 + connect \rb$21 \core_calculate_stage_28_rb$54 + connect \xer_so$22 \core_calculate_stage_28_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_28_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_28_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_28_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_28_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_28_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_28_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_28_operation$62 + connect \quotient_root$30 \core_calculate_stage_28_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_28_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_28_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_28_compare_rhs$66 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid + wire width 2 \core_calculate_stage_29_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -114370,7 +106305,7 @@ module \pipe$106 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_sr_op__insn_type + wire width 7 \core_calculate_stage_29_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -114384,47 +106319,73 @@ module \pipe$106 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_sr_op__fn_unit + wire width 11 \core_calculate_stage_29_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__imm + wire width 64 \core_calculate_stage_29_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_29_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__rc__rc + wire width 1 \core_calculate_stage_29_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__rc__rc_ok + wire width 1 \core_calculate_stage_29_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__oe__oe + wire width 1 \core_calculate_stage_29_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__oe__oe_ok + wire width 1 \core_calculate_stage_29_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_29_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_29_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry + wire width 2 \core_calculate_stage_29_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__output_carry + wire width 1 \core_calculate_stage_29_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__input_cr + wire width 1 \core_calculate_stage_29_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__output_cr + wire width 1 \core_calculate_stage_29_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__is_32bit + wire width 1 \core_calculate_stage_29_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__is_signed + wire width 1 \core_calculate_stage_29_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_sr_op__insn + wire width 4 \core_calculate_stage_29_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_29_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra + wire width 64 \core_calculate_stage_29_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb + wire width 64 \core_calculate_stage_29_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca + wire width 1 \core_calculate_stage_29_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_29_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_29_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_29_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_29_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_29_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_29_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_29_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_29_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_29_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_29_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_29_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$18 + wire width 2 \core_calculate_stage_29_muxid$67 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -114499,7 +106460,7 @@ module \pipe$106 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_sr_op__insn_type$19 + wire width 7 \core_calculate_stage_29_logical_op__insn_type$68 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -114513,89 +106474,141 @@ module \pipe$106 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \input_sr_op__fn_unit$20 + wire width 11 \core_calculate_stage_29_logical_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_sr_op__imm_data__imm$21 + wire width 64 \core_calculate_stage_29_logical_op__imm_data__imm$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__imm_data__imm_ok$22 + wire width 1 \core_calculate_stage_29_logical_op__imm_data__imm_ok$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__rc__rc$23 + wire width 1 \core_calculate_stage_29_logical_op__rc__rc$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__rc__rc_ok$24 + wire width 1 \core_calculate_stage_29_logical_op__rc__rc_ok$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__oe__oe$25 + wire width 1 \core_calculate_stage_29_logical_op__oe__oe$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__oe__oe_ok$26 + wire width 1 \core_calculate_stage_29_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_29_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_29_logical_op__zero_a$77 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_sr_op__input_carry$27 + wire width 2 \core_calculate_stage_29_logical_op__input_carry$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__output_carry$28 + wire width 1 \core_calculate_stage_29_logical_op__invert_out$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__input_cr$29 + wire width 1 \core_calculate_stage_29_logical_op__write_cr0$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__output_cr$30 + wire width 1 \core_calculate_stage_29_logical_op__output_carry$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__is_32bit$31 + wire width 1 \core_calculate_stage_29_logical_op__is_32bit$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \input_sr_op__is_signed$32 + wire width 1 \core_calculate_stage_29_logical_op__is_signed$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_sr_op__insn$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$34 + wire width 4 \core_calculate_stage_29_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_29_logical_op__insn$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$35 + wire width 64 \core_calculate_stage_29_ra$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rc$36 + wire width 64 \core_calculate_stage_29_rb$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$37 - cell \input$109 \input - connect \muxid \input_muxid - connect \sr_op__insn_type \input_sr_op__insn_type - connect \sr_op__fn_unit \input_sr_op__fn_unit - connect \sr_op__imm_data__imm \input_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm_ok - connect \sr_op__rc__rc \input_sr_op__rc__rc - connect \sr_op__rc__rc_ok \input_sr_op__rc__rc_ok - connect \sr_op__oe__oe \input_sr_op__oe__oe - connect \sr_op__oe__oe_ok \input_sr_op__oe__oe_ok - connect \sr_op__input_carry \input_sr_op__input_carry - connect \sr_op__output_carry \input_sr_op__output_carry - connect \sr_op__input_cr \input_sr_op__input_cr - connect \sr_op__output_cr \input_sr_op__output_cr - connect \sr_op__is_32bit \input_sr_op__is_32bit - connect \sr_op__is_signed \input_sr_op__is_signed - connect \sr_op__insn \input_sr_op__insn - connect \ra \input_ra - connect \rb \input_rb - connect \rc \input_rc - connect \xer_ca \input_xer_ca - connect \muxid$1 \input_muxid$18 - connect \sr_op__insn_type$2 \input_sr_op__insn_type$19 - connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$20 - connect \sr_op__imm_data__imm$4 \input_sr_op__imm_data__imm$21 - connect \sr_op__imm_data__imm_ok$5 \input_sr_op__imm_data__imm_ok$22 - connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$23 - connect \sr_op__rc__rc_ok$7 \input_sr_op__rc__rc_ok$24 - connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$25 - connect \sr_op__oe__oe_ok$9 \input_sr_op__oe__oe_ok$26 - connect \sr_op__input_carry$10 \input_sr_op__input_carry$27 - connect \sr_op__output_carry$11 \input_sr_op__output_carry$28 - connect \sr_op__input_cr$12 \input_sr_op__input_cr$29 - connect \sr_op__output_cr$13 \input_sr_op__output_cr$30 - connect \sr_op__is_32bit$14 \input_sr_op__is_32bit$31 - connect \sr_op__is_signed$15 \input_sr_op__is_signed$32 - connect \sr_op__insn$16 \input_sr_op__insn$33 - connect \ra$17 \input_ra$34 - connect \rb$18 \input_rb$35 - connect \rc$19 \input_rc$36 - connect \xer_ca$20 \input_xer_ca$37 + wire width 1 \core_calculate_stage_29_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_29_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_29_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_29_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_29_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_29_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_29_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_29_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_29_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_29_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_29_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_29_compare_rhs$99 + cell \core_calculate_stage_29 \core_calculate_stage_29 + connect \muxid \core_calculate_stage_29_muxid + connect \logical_op__insn_type \core_calculate_stage_29_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_29_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_29_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_29_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_29_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_29_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_29_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_29_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_29_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_29_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_29_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_29_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_29_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_29_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_29_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_29_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_29_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_29_logical_op__insn + connect \ra \core_calculate_stage_29_ra + connect \rb \core_calculate_stage_29_rb + connect \xer_so \core_calculate_stage_29_xer_so + connect \divisor_neg \core_calculate_stage_29_divisor_neg + connect \dividend_neg \core_calculate_stage_29_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_29_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_29_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_29_div_by_zero + connect \divisor_radicand \core_calculate_stage_29_divisor_radicand + connect \operation \core_calculate_stage_29_operation + connect \quotient_root \core_calculate_stage_29_quotient_root + connect \root_times_radicand \core_calculate_stage_29_root_times_radicand + connect \compare_lhs \core_calculate_stage_29_compare_lhs + connect \compare_rhs \core_calculate_stage_29_compare_rhs + connect \muxid$1 \core_calculate_stage_29_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_29_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_29_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_29_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_29_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_29_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_29_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_29_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_29_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_29_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_29_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_29_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_29_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_29_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_29_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_29_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_29_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_29_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_29_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_29_ra$86 + connect \rb$21 \core_calculate_stage_29_rb$87 + connect \xer_so$22 \core_calculate_stage_29_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_29_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_29_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_29_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_29_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_29_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_29_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_29_operation$95 + connect \quotient_root$30 \core_calculate_stage_29_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_29_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_29_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_29_compare_rhs$99 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid + wire width 2 \core_calculate_stage_30_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -114670,7 +106683,7 @@ module \pipe$106 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_sr_op__insn_type + wire width 7 \core_calculate_stage_30_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -114684,45 +106697,73 @@ module \pipe$106 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_sr_op__fn_unit + wire width 11 \core_calculate_stage_30_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_sr_op__imm_data__imm + wire width 64 \core_calculate_stage_30_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_30_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__rc__rc + wire width 1 \core_calculate_stage_30_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__rc__rc_ok + wire width 1 \core_calculate_stage_30_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__oe__oe + wire width 1 \core_calculate_stage_30_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__oe__oe_ok + wire width 1 \core_calculate_stage_30_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_30_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_30_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_sr_op__input_carry + wire width 2 \core_calculate_stage_30_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__output_carry + wire width 1 \core_calculate_stage_30_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__input_cr + wire width 1 \core_calculate_stage_30_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__output_cr + wire width 1 \core_calculate_stage_30_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__is_32bit + wire width 1 \core_calculate_stage_30_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__is_signed + wire width 1 \core_calculate_stage_30_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_sr_op__insn + wire width 4 \core_calculate_stage_30_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_30_logical_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra + wire width 64 \core_calculate_stage_30_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb + wire width 64 \core_calculate_stage_30_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rc + wire width 1 \core_calculate_stage_30_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_30_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_30_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_30_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_30_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_30_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_30_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_30_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_30_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_30_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_30_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_30_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$38 + wire width 2 \core_calculate_stage_30_muxid$100 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -114797,7 +106838,7 @@ module \pipe$106 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_sr_op__insn_type$39 + wire width 7 \core_calculate_stage_30_logical_op__insn_type$101 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -114811,85 +106852,141 @@ module \pipe$106 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_sr_op__fn_unit$40 + wire width 11 \core_calculate_stage_30_logical_op__fn_unit$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_sr_op__imm_data__imm$41 + wire width 64 \core_calculate_stage_30_logical_op__imm_data__imm$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__imm_data__imm_ok$42 + wire width 1 \core_calculate_stage_30_logical_op__imm_data__imm_ok$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__rc__rc$43 + wire width 1 \core_calculate_stage_30_logical_op__rc__rc$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__rc__rc_ok$44 + wire width 1 \core_calculate_stage_30_logical_op__rc__rc_ok$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__oe__oe$45 + wire width 1 \core_calculate_stage_30_logical_op__oe__oe$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__oe__oe_ok$46 + wire width 1 \core_calculate_stage_30_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_30_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_30_logical_op__zero_a$110 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_sr_op__input_carry$47 + wire width 2 \core_calculate_stage_30_logical_op__input_carry$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__output_carry$48 + wire width 1 \core_calculate_stage_30_logical_op__invert_out$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__input_cr$49 + wire width 1 \core_calculate_stage_30_logical_op__write_cr0$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__output_cr$50 + wire width 1 \core_calculate_stage_30_logical_op__output_carry$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__is_32bit$51 + wire width 1 \core_calculate_stage_30_logical_op__is_32bit$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_sr_op__is_signed$52 + wire width 1 \core_calculate_stage_30_logical_op__is_signed$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_sr_op__insn$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \main_xer_ca - cell \main$110 \main - connect \muxid \main_muxid - connect \sr_op__insn_type \main_sr_op__insn_type - connect \sr_op__fn_unit \main_sr_op__fn_unit - connect \sr_op__imm_data__imm \main_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm_ok - connect \sr_op__rc__rc \main_sr_op__rc__rc - connect \sr_op__rc__rc_ok \main_sr_op__rc__rc_ok - connect \sr_op__oe__oe \main_sr_op__oe__oe - connect \sr_op__oe__oe_ok \main_sr_op__oe__oe_ok - connect \sr_op__input_carry \main_sr_op__input_carry - connect \sr_op__output_carry \main_sr_op__output_carry - connect \sr_op__input_cr \main_sr_op__input_cr - connect \sr_op__output_cr \main_sr_op__output_cr - connect \sr_op__is_32bit \main_sr_op__is_32bit - connect \sr_op__is_signed \main_sr_op__is_signed - connect \sr_op__insn \main_sr_op__insn - connect \ra \main_ra - connect \rb \main_rb - connect \rc \main_rc - connect \muxid$1 \main_muxid$38 - connect \sr_op__insn_type$2 \main_sr_op__insn_type$39 - connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$40 - connect \sr_op__imm_data__imm$4 \main_sr_op__imm_data__imm$41 - connect \sr_op__imm_data__imm_ok$5 \main_sr_op__imm_data__imm_ok$42 - connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$43 - connect \sr_op__rc__rc_ok$7 \main_sr_op__rc__rc_ok$44 - connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$45 - connect \sr_op__oe__oe_ok$9 \main_sr_op__oe__oe_ok$46 - connect \sr_op__input_carry$10 \main_sr_op__input_carry$47 - connect \sr_op__output_carry$11 \main_sr_op__output_carry$48 - connect \sr_op__input_cr$12 \main_sr_op__input_cr$49 - connect \sr_op__output_cr$13 \main_sr_op__output_cr$50 - connect \sr_op__is_32bit$14 \main_sr_op__is_32bit$51 - connect \sr_op__is_signed$15 \main_sr_op__is_signed$52 - connect \sr_op__insn$16 \main_sr_op__insn$53 - connect \o \main_o - connect \o_ok \main_o_ok - connect \xer_ca \main_xer_ca + wire width 4 \core_calculate_stage_30_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_30_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_30_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_30_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_30_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_30_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_30_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_30_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_30_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_30_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_30_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_30_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_30_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_30_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_30_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_30_compare_rhs$132 + cell \core_calculate_stage_30 \core_calculate_stage_30 + connect \muxid \core_calculate_stage_30_muxid + connect \logical_op__insn_type \core_calculate_stage_30_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_30_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_30_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_30_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_30_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_30_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_30_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_30_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_30_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_30_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_30_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_30_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_30_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_30_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_30_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_30_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_30_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_30_logical_op__insn + connect \ra \core_calculate_stage_30_ra + connect \rb \core_calculate_stage_30_rb + connect \xer_so \core_calculate_stage_30_xer_so + connect \divisor_neg \core_calculate_stage_30_divisor_neg + connect \dividend_neg \core_calculate_stage_30_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_30_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_30_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_30_div_by_zero + connect \divisor_radicand \core_calculate_stage_30_divisor_radicand + connect \operation \core_calculate_stage_30_operation + connect \quotient_root \core_calculate_stage_30_quotient_root + connect \root_times_radicand \core_calculate_stage_30_root_times_radicand + connect \compare_lhs \core_calculate_stage_30_compare_lhs + connect \compare_rhs \core_calculate_stage_30_compare_rhs + connect \muxid$1 \core_calculate_stage_30_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_30_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_30_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_30_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_30_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_30_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_30_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_30_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_30_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_30_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_30_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_30_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_30_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_30_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_30_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_30_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_30_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_30_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_30_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_30_ra$119 + connect \rb$21 \core_calculate_stage_30_rb$120 + connect \xer_so$22 \core_calculate_stage_30_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_30_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_30_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_30_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_30_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_30_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_30_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_30_operation$128 + connect \quotient_root$30 \core_calculate_stage_30_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_30_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_30_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_30_compare_rhs$132 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid + wire width 2 \core_calculate_stage_31_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -114964,7 +107061,7 @@ module \pipe$106 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type + wire width 7 \core_calculate_stage_31_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -114978,47 +107075,73 @@ module \pipe$106 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_sr_op__fn_unit + wire width 11 \core_calculate_stage_31_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__imm + wire width 64 \core_calculate_stage_31_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__imm_data__imm_ok + wire width 1 \core_calculate_stage_31_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__rc__rc + wire width 1 \core_calculate_stage_31_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__rc__rc_ok + wire width 1 \core_calculate_stage_31_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__oe__oe + wire width 1 \core_calculate_stage_31_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__oe__oe_ok + wire width 1 \core_calculate_stage_31_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_31_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_31_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry + wire width 2 \core_calculate_stage_31_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__output_carry + wire width 1 \core_calculate_stage_31_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__input_cr + wire width 1 \core_calculate_stage_31_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__output_cr + wire width 1 \core_calculate_stage_31_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__is_32bit + wire width 1 \core_calculate_stage_31_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__is_signed + wire width 1 \core_calculate_stage_31_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca + wire width 4 \core_calculate_stage_31_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_31_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_31_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_31_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_31_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_31_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_31_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_31_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_31_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_31_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_31_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_31_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_31_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_31_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_31_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_31_compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$54 + wire width 2 \core_calculate_stage_31_muxid$133 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -115093,7 +107216,7 @@ module \pipe$106 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type$55 + wire width 7 \core_calculate_stage_31_logical_op__insn_type$134 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -115107,248 +107230,537 @@ module \pipe$106 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \output_sr_op__fn_unit$56 + wire width 11 \core_calculate_stage_31_logical_op__fn_unit$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_31_logical_op__imm_data__imm$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__imm$57 + wire width 1 \core_calculate_stage_31_logical_op__imm_data__imm_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__imm_data__imm_ok$58 + wire width 1 \core_calculate_stage_31_logical_op__rc__rc$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__rc__rc$59 + wire width 1 \core_calculate_stage_31_logical_op__rc__rc_ok$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__rc__rc_ok$60 + wire width 1 \core_calculate_stage_31_logical_op__oe__oe$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__oe__oe$61 + wire width 1 \core_calculate_stage_31_logical_op__oe__oe_ok$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__oe__oe_ok$62 + wire width 1 \core_calculate_stage_31_logical_op__invert_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_31_logical_op__zero_a$143 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry$63 + wire width 2 \core_calculate_stage_31_logical_op__input_carry$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__output_carry$64 + wire width 1 \core_calculate_stage_31_logical_op__invert_out$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__input_cr$65 + wire width 1 \core_calculate_stage_31_logical_op__write_cr0$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__output_cr$66 + wire width 1 \core_calculate_stage_31_logical_op__output_carry$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__is_32bit$67 + wire width 1 \core_calculate_stage_31_logical_op__is_32bit$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_sr_op__is_signed$68 + wire width 1 \core_calculate_stage_31_logical_op__is_signed$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_ca_ok - cell \output$111 \output - connect \muxid \output_muxid - connect \sr_op__insn_type \output_sr_op__insn_type - connect \sr_op__fn_unit \output_sr_op__fn_unit - connect \sr_op__imm_data__imm \output_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm_ok - connect \sr_op__rc__rc \output_sr_op__rc__rc - connect \sr_op__rc__rc_ok \output_sr_op__rc__rc_ok - connect \sr_op__oe__oe \output_sr_op__oe__oe - connect \sr_op__oe__oe_ok \output_sr_op__oe__oe_ok - connect \sr_op__input_carry \output_sr_op__input_carry - connect \sr_op__output_carry \output_sr_op__output_carry - connect \sr_op__input_cr \output_sr_op__input_cr - connect \sr_op__output_cr \output_sr_op__output_cr - connect \sr_op__is_32bit \output_sr_op__is_32bit - connect \sr_op__is_signed \output_sr_op__is_signed - connect \sr_op__insn \output_sr_op__insn - connect \o \output_o - connect \o_ok \output_o_ok - connect \cr_a \output_cr_a - connect \xer_ca \output_xer_ca - connect \muxid$1 \output_muxid$54 - connect \sr_op__insn_type$2 \output_sr_op__insn_type$55 - connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$56 - connect \sr_op__imm_data__imm$4 \output_sr_op__imm_data__imm$57 - connect \sr_op__imm_data__imm_ok$5 \output_sr_op__imm_data__imm_ok$58 - connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$59 - connect \sr_op__rc__rc_ok$7 \output_sr_op__rc__rc_ok$60 - connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$61 - connect \sr_op__oe__oe_ok$9 \output_sr_op__oe__oe_ok$62 - connect \sr_op__input_carry$10 \output_sr_op__input_carry$63 - connect \sr_op__output_carry$11 \output_sr_op__output_carry$64 - connect \sr_op__input_cr$12 \output_sr_op__input_cr$65 - connect \sr_op__output_cr$13 \output_sr_op__output_cr$66 - connect \sr_op__is_32bit$14 \output_sr_op__is_32bit$67 - connect \sr_op__is_signed$15 \output_sr_op__is_signed$68 - connect \sr_op__insn$16 \output_sr_op__insn$69 - connect \o$17 \output_o$70 - connect \o_ok$18 \output_o_ok$71 - connect \cr_a$19 \output_cr_a$72 - connect \cr_a_ok \output_cr_a_ok - connect \xer_ca$20 \output_xer_ca$73 - connect \xer_ca_ok \output_xer_ca_ok + wire width 4 \core_calculate_stage_31_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_31_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_31_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_31_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_31_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_31_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_31_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_31_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_31_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_31_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_31_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_31_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_31_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_31_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_31_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_31_compare_rhs$165 + cell \core_calculate_stage_31 \core_calculate_stage_31 + connect \muxid \core_calculate_stage_31_muxid + connect \logical_op__insn_type \core_calculate_stage_31_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_31_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_31_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_31_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_31_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_31_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_31_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_31_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_31_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_31_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_31_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_31_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_31_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_31_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_31_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_31_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_31_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_31_logical_op__insn + connect \ra \core_calculate_stage_31_ra + connect \rb \core_calculate_stage_31_rb + connect \xer_so \core_calculate_stage_31_xer_so + connect \divisor_neg \core_calculate_stage_31_divisor_neg + connect \dividend_neg \core_calculate_stage_31_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_31_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_31_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_31_div_by_zero + connect \divisor_radicand \core_calculate_stage_31_divisor_radicand + connect \operation \core_calculate_stage_31_operation + connect \quotient_root \core_calculate_stage_31_quotient_root + connect \root_times_radicand \core_calculate_stage_31_root_times_radicand + connect \compare_lhs \core_calculate_stage_31_compare_lhs + connect \compare_rhs \core_calculate_stage_31_compare_rhs + connect \muxid$1 \core_calculate_stage_31_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_31_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_31_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_31_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_31_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_31_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_31_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_31_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_31_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_31_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_31_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_31_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_31_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_31_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_31_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_31_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_31_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_31_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_31_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_31_ra$152 + connect \rb$21 \core_calculate_stage_31_rb$153 + connect \xer_so$22 \core_calculate_stage_31_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_31_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_31_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_31_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_31_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_31_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_31_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_31_operation$161 + connect \quotient_root$30 \core_calculate_stage_31_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_31_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_31_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_31_compare_rhs$165 end process $group_0 - assign \input_muxid 2'00 - assign \input_muxid \muxid + assign \core_calculate_stage_28_muxid 2'00 + assign \core_calculate_stage_28_muxid \muxid sync init end process $group_1 - assign \input_sr_op__insn_type 7'0000000 - assign \input_sr_op__fn_unit 11'00000000000 - assign \input_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_sr_op__imm_data__imm_ok 1'0 - assign \input_sr_op__rc__rc 1'0 - assign \input_sr_op__rc__rc_ok 1'0 - assign \input_sr_op__oe__oe 1'0 - assign \input_sr_op__oe__oe_ok 1'0 - assign { } 0'0 - assign \input_sr_op__input_carry 2'00 - assign \input_sr_op__output_carry 1'0 - assign \input_sr_op__input_cr 1'0 - assign \input_sr_op__output_cr 1'0 - assign \input_sr_op__is_32bit 1'0 - assign \input_sr_op__is_signed 1'0 - assign \input_sr_op__insn 32'00000000000000000000000000000000 - assign { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry { } { \input_sr_op__oe__oe_ok \input_sr_op__oe__oe } { \input_sr_op__rc__rc_ok \input_sr_op__rc__rc } { \input_sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm } \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } - sync init - end - process $group_17 - assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_ra \ra - sync init - end - process $group_18 - assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_rb \rb + assign \core_calculate_stage_28_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_28_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_28_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_28_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_28_logical_op__rc__rc 1'0 + assign \core_calculate_stage_28_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_28_logical_op__oe__oe 1'0 + assign \core_calculate_stage_28_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_28_logical_op__invert_in 1'0 + assign \core_calculate_stage_28_logical_op__zero_a 1'0 + assign \core_calculate_stage_28_logical_op__input_carry 2'00 + assign \core_calculate_stage_28_logical_op__invert_out 1'0 + assign \core_calculate_stage_28_logical_op__write_cr0 1'0 + assign \core_calculate_stage_28_logical_op__output_carry 1'0 + assign \core_calculate_stage_28_logical_op__is_32bit 1'0 + assign \core_calculate_stage_28_logical_op__is_signed 1'0 + assign \core_calculate_stage_28_logical_op__data_len 4'0000 + assign \core_calculate_stage_28_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_28_logical_op__insn \core_calculate_stage_28_logical_op__data_len \core_calculate_stage_28_logical_op__is_signed \core_calculate_stage_28_logical_op__is_32bit \core_calculate_stage_28_logical_op__output_carry \core_calculate_stage_28_logical_op__write_cr0 \core_calculate_stage_28_logical_op__invert_out \core_calculate_stage_28_logical_op__input_carry \core_calculate_stage_28_logical_op__zero_a \core_calculate_stage_28_logical_op__invert_in { \core_calculate_stage_28_logical_op__oe__oe_ok \core_calculate_stage_28_logical_op__oe__oe } { \core_calculate_stage_28_logical_op__rc__rc_ok \core_calculate_stage_28_logical_op__rc__rc } { \core_calculate_stage_28_logical_op__imm_data__imm_ok \core_calculate_stage_28_logical_op__imm_data__imm } \core_calculate_stage_28_logical_op__fn_unit \core_calculate_stage_28_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end process $group_19 - assign \input_rc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_rc \rc + assign \core_calculate_stage_28_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_28_ra \ra sync init end process $group_20 - assign \input_xer_ca 2'00 - assign \input_xer_ca \xer_ca + assign \core_calculate_stage_28_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_28_rb \rb sync init end process $group_21 - assign \main_muxid 2'00 - assign \main_muxid \input_muxid$18 + assign \core_calculate_stage_28_xer_so 1'0 + assign \core_calculate_stage_28_xer_so \xer_so sync init end process $group_22 - assign \main_sr_op__insn_type 7'0000000 - assign \main_sr_op__fn_unit 11'00000000000 - assign \main_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_sr_op__imm_data__imm_ok 1'0 - assign \main_sr_op__rc__rc 1'0 - assign \main_sr_op__rc__rc_ok 1'0 - assign \main_sr_op__oe__oe 1'0 - assign \main_sr_op__oe__oe_ok 1'0 - assign { } 0'0 - assign \main_sr_op__input_carry 2'00 - assign \main_sr_op__output_carry 1'0 - assign \main_sr_op__input_cr 1'0 - assign \main_sr_op__output_cr 1'0 - assign \main_sr_op__is_32bit 1'0 - assign \main_sr_op__is_signed 1'0 - assign \main_sr_op__insn 32'00000000000000000000000000000000 - assign { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry { } { \main_sr_op__oe__oe_ok \main_sr_op__oe__oe } { \main_sr_op__rc__rc_ok \main_sr_op__rc__rc } { \main_sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm } \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$33 \input_sr_op__is_signed$32 \input_sr_op__is_32bit$31 \input_sr_op__output_cr$30 \input_sr_op__input_cr$29 \input_sr_op__output_carry$28 \input_sr_op__input_carry$27 { } { \input_sr_op__oe__oe_ok$26 \input_sr_op__oe__oe$25 } { \input_sr_op__rc__rc_ok$24 \input_sr_op__rc__rc$23 } { \input_sr_op__imm_data__imm_ok$22 \input_sr_op__imm_data__imm$21 } \input_sr_op__fn_unit$20 \input_sr_op__insn_type$19 } + assign \core_calculate_stage_28_divisor_neg 1'0 + assign \core_calculate_stage_28_divisor_neg \divisor_neg sync init end - process $group_38 - assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \input_ra$34 + process $group_23 + assign \core_calculate_stage_28_dividend_neg 1'0 + assign \core_calculate_stage_28_dividend_neg \dividend_neg sync init end - process $group_39 - assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \input_rb$35 + process $group_24 + assign \core_calculate_stage_28_dive_abs_ov32 1'0 + assign \core_calculate_stage_28_dive_abs_ov32 \dive_abs_ov32 sync init end - process $group_40 - assign \main_rc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rc \input_rc$36 + process $group_25 + assign \core_calculate_stage_28_dive_abs_ov64 1'0 + assign \core_calculate_stage_28_dive_abs_ov64 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \xer_ca$74 - process $group_41 - assign \xer_ca$74 2'00 - assign \xer_ca$74 \input_xer_ca$37 + process $group_26 + assign \core_calculate_stage_28_div_by_zero 1'0 + assign \core_calculate_stage_28_div_by_zero \div_by_zero sync init end - process $group_42 - assign \output_muxid 2'00 - assign \output_muxid \main_muxid$38 + process $group_27 + assign \core_calculate_stage_28_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_28_divisor_radicand \divisor_radicand sync init end - process $group_43 - assign \output_sr_op__insn_type 7'0000000 - assign \output_sr_op__fn_unit 11'00000000000 - assign \output_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_sr_op__imm_data__imm_ok 1'0 - assign \output_sr_op__rc__rc 1'0 - assign \output_sr_op__rc__rc_ok 1'0 - assign \output_sr_op__oe__oe 1'0 - assign \output_sr_op__oe__oe_ok 1'0 - assign { } 0'0 - assign \output_sr_op__input_carry 2'00 - assign \output_sr_op__output_carry 1'0 - assign \output_sr_op__input_cr 1'0 - assign \output_sr_op__output_cr 1'0 - assign \output_sr_op__is_32bit 1'0 - assign \output_sr_op__is_signed 1'0 - assign \output_sr_op__insn 32'00000000000000000000000000000000 - assign { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry { } { \output_sr_op__oe__oe_ok \output_sr_op__oe__oe } { \output_sr_op__rc__rc_ok \output_sr_op__rc__rc } { \output_sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm } \output_sr_op__fn_unit \output_sr_op__insn_type } { \main_sr_op__insn$53 \main_sr_op__is_signed$52 \main_sr_op__is_32bit$51 \main_sr_op__output_cr$50 \main_sr_op__input_cr$49 \main_sr_op__output_carry$48 \main_sr_op__input_carry$47 { } { \main_sr_op__oe__oe_ok$46 \main_sr_op__oe__oe$45 } { \main_sr_op__rc__rc_ok$44 \main_sr_op__rc__rc$43 } { \main_sr_op__imm_data__imm_ok$42 \main_sr_op__imm_data__imm$41 } \main_sr_op__fn_unit$40 \main_sr_op__insn_type$39 } + process $group_28 + assign \core_calculate_stage_28_operation 2'00 + assign \core_calculate_stage_28_operation \operation + sync init + end + process $group_29 + assign \core_calculate_stage_28_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_28_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_calculate_stage_28_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_28_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_calculate_stage_28_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_28_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_calculate_stage_28_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_28_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \core_calculate_stage_29_muxid 2'00 + assign \core_calculate_stage_29_muxid \core_calculate_stage_28_muxid$34 + sync init + end + process $group_34 + assign \core_calculate_stage_29_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_29_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_29_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_29_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_29_logical_op__rc__rc 1'0 + assign \core_calculate_stage_29_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_29_logical_op__oe__oe 1'0 + assign \core_calculate_stage_29_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_29_logical_op__invert_in 1'0 + assign \core_calculate_stage_29_logical_op__zero_a 1'0 + assign \core_calculate_stage_29_logical_op__input_carry 2'00 + assign \core_calculate_stage_29_logical_op__invert_out 1'0 + assign \core_calculate_stage_29_logical_op__write_cr0 1'0 + assign \core_calculate_stage_29_logical_op__output_carry 1'0 + assign \core_calculate_stage_29_logical_op__is_32bit 1'0 + assign \core_calculate_stage_29_logical_op__is_signed 1'0 + assign \core_calculate_stage_29_logical_op__data_len 4'0000 + assign \core_calculate_stage_29_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_29_logical_op__insn \core_calculate_stage_29_logical_op__data_len \core_calculate_stage_29_logical_op__is_signed \core_calculate_stage_29_logical_op__is_32bit \core_calculate_stage_29_logical_op__output_carry \core_calculate_stage_29_logical_op__write_cr0 \core_calculate_stage_29_logical_op__invert_out \core_calculate_stage_29_logical_op__input_carry \core_calculate_stage_29_logical_op__zero_a \core_calculate_stage_29_logical_op__invert_in { \core_calculate_stage_29_logical_op__oe__oe_ok \core_calculate_stage_29_logical_op__oe__oe } { \core_calculate_stage_29_logical_op__rc__rc_ok \core_calculate_stage_29_logical_op__rc__rc } { \core_calculate_stage_29_logical_op__imm_data__imm_ok \core_calculate_stage_29_logical_op__imm_data__imm } \core_calculate_stage_29_logical_op__fn_unit \core_calculate_stage_29_logical_op__insn_type } { \core_calculate_stage_28_logical_op__insn$52 \core_calculate_stage_28_logical_op__data_len$51 \core_calculate_stage_28_logical_op__is_signed$50 \core_calculate_stage_28_logical_op__is_32bit$49 \core_calculate_stage_28_logical_op__output_carry$48 \core_calculate_stage_28_logical_op__write_cr0$47 \core_calculate_stage_28_logical_op__invert_out$46 \core_calculate_stage_28_logical_op__input_carry$45 \core_calculate_stage_28_logical_op__zero_a$44 \core_calculate_stage_28_logical_op__invert_in$43 { \core_calculate_stage_28_logical_op__oe__oe_ok$42 \core_calculate_stage_28_logical_op__oe__oe$41 } { \core_calculate_stage_28_logical_op__rc__rc_ok$40 \core_calculate_stage_28_logical_op__rc__rc$39 } { \core_calculate_stage_28_logical_op__imm_data__imm_ok$38 \core_calculate_stage_28_logical_op__imm_data__imm$37 } \core_calculate_stage_28_logical_op__fn_unit$36 \core_calculate_stage_28_logical_op__insn_type$35 } + sync init + end + process $group_52 + assign \core_calculate_stage_29_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_29_ra \core_calculate_stage_28_ra$53 + sync init + end + process $group_53 + assign \core_calculate_stage_29_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_29_rb \core_calculate_stage_28_rb$54 + sync init + end + process $group_54 + assign \core_calculate_stage_29_xer_so 1'0 + assign \core_calculate_stage_29_xer_so \core_calculate_stage_28_xer_so$55 + sync init + end + process $group_55 + assign \core_calculate_stage_29_divisor_neg 1'0 + assign \core_calculate_stage_29_divisor_neg \core_calculate_stage_28_divisor_neg$56 + sync init + end + process $group_56 + assign \core_calculate_stage_29_dividend_neg 1'0 + assign \core_calculate_stage_29_dividend_neg \core_calculate_stage_28_dividend_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_29_dive_abs_ov32 1'0 + assign \core_calculate_stage_29_dive_abs_ov32 \core_calculate_stage_28_dive_abs_ov32$58 + sync init + end + process $group_58 + assign \core_calculate_stage_29_dive_abs_ov64 1'0 + assign \core_calculate_stage_29_dive_abs_ov64 \core_calculate_stage_28_dive_abs_ov64$59 sync init end process $group_59 - assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_o_ok 1'0 - assign { \output_o_ok \output_o } { \main_o_ok \main_o } + assign \core_calculate_stage_29_div_by_zero 1'0 + assign \core_calculate_stage_29_div_by_zero \core_calculate_stage_28_div_by_zero$60 + sync init + end + process $group_60 + assign \core_calculate_stage_29_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_29_divisor_radicand \core_calculate_stage_28_divisor_radicand$61 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$77 process $group_61 - assign \output_cr_a 4'0000 - assign \cr_a_ok$75 1'0 - assign { \cr_a_ok$75 \output_cr_a } { \cr_a_ok$77 \cr_a$76 } + assign \core_calculate_stage_29_operation 2'00 + assign \core_calculate_stage_29_operation \core_calculate_stage_28_operation$62 + sync init + end + process $group_62 + assign \core_calculate_stage_29_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_29_quotient_root \core_calculate_stage_28_quotient_root$63 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$79 process $group_63 - assign \output_xer_ca 2'00 - assign \xer_ca_ok$78 1'0 - assign { \xer_ca_ok$78 \output_xer_ca } { \xer_ca_ok$79 \main_xer_ca } + assign \core_calculate_stage_29_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_29_root_times_radicand \core_calculate_stage_28_root_times_radicand$64 + sync init + end + process $group_64 + assign \core_calculate_stage_29_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_29_compare_lhs \core_calculate_stage_28_compare_lhs$65 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$80 process $group_65 - assign \p_valid_i$80 1'0 - assign \p_valid_i$80 \p_valid_i + assign \core_calculate_stage_29_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_29_compare_rhs \core_calculate_stage_28_compare_rhs$66 + sync init + end + process $group_66 + assign \core_calculate_stage_30_muxid 2'00 + assign \core_calculate_stage_30_muxid \core_calculate_stage_29_muxid$67 + sync init + end + process $group_67 + assign \core_calculate_stage_30_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_30_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_30_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_30_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_30_logical_op__rc__rc 1'0 + assign \core_calculate_stage_30_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_30_logical_op__oe__oe 1'0 + assign \core_calculate_stage_30_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_30_logical_op__invert_in 1'0 + assign \core_calculate_stage_30_logical_op__zero_a 1'0 + assign \core_calculate_stage_30_logical_op__input_carry 2'00 + assign \core_calculate_stage_30_logical_op__invert_out 1'0 + assign \core_calculate_stage_30_logical_op__write_cr0 1'0 + assign \core_calculate_stage_30_logical_op__output_carry 1'0 + assign \core_calculate_stage_30_logical_op__is_32bit 1'0 + assign \core_calculate_stage_30_logical_op__is_signed 1'0 + assign \core_calculate_stage_30_logical_op__data_len 4'0000 + assign \core_calculate_stage_30_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_30_logical_op__insn \core_calculate_stage_30_logical_op__data_len \core_calculate_stage_30_logical_op__is_signed \core_calculate_stage_30_logical_op__is_32bit \core_calculate_stage_30_logical_op__output_carry \core_calculate_stage_30_logical_op__write_cr0 \core_calculate_stage_30_logical_op__invert_out \core_calculate_stage_30_logical_op__input_carry \core_calculate_stage_30_logical_op__zero_a \core_calculate_stage_30_logical_op__invert_in { \core_calculate_stage_30_logical_op__oe__oe_ok \core_calculate_stage_30_logical_op__oe__oe } { \core_calculate_stage_30_logical_op__rc__rc_ok \core_calculate_stage_30_logical_op__rc__rc } { \core_calculate_stage_30_logical_op__imm_data__imm_ok \core_calculate_stage_30_logical_op__imm_data__imm } \core_calculate_stage_30_logical_op__fn_unit \core_calculate_stage_30_logical_op__insn_type } { \core_calculate_stage_29_logical_op__insn$85 \core_calculate_stage_29_logical_op__data_len$84 \core_calculate_stage_29_logical_op__is_signed$83 \core_calculate_stage_29_logical_op__is_32bit$82 \core_calculate_stage_29_logical_op__output_carry$81 \core_calculate_stage_29_logical_op__write_cr0$80 \core_calculate_stage_29_logical_op__invert_out$79 \core_calculate_stage_29_logical_op__input_carry$78 \core_calculate_stage_29_logical_op__zero_a$77 \core_calculate_stage_29_logical_op__invert_in$76 { \core_calculate_stage_29_logical_op__oe__oe_ok$75 \core_calculate_stage_29_logical_op__oe__oe$74 } { \core_calculate_stage_29_logical_op__rc__rc_ok$73 \core_calculate_stage_29_logical_op__rc__rc$72 } { \core_calculate_stage_29_logical_op__imm_data__imm_ok$71 \core_calculate_stage_29_logical_op__imm_data__imm$70 } \core_calculate_stage_29_logical_op__fn_unit$69 \core_calculate_stage_29_logical_op__insn_type$68 } + sync init + end + process $group_85 + assign \core_calculate_stage_30_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_30_ra \core_calculate_stage_29_ra$86 + sync init + end + process $group_86 + assign \core_calculate_stage_30_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_30_rb \core_calculate_stage_29_rb$87 + sync init + end + process $group_87 + assign \core_calculate_stage_30_xer_so 1'0 + assign \core_calculate_stage_30_xer_so \core_calculate_stage_29_xer_so$88 + sync init + end + process $group_88 + assign \core_calculate_stage_30_divisor_neg 1'0 + assign \core_calculate_stage_30_divisor_neg \core_calculate_stage_29_divisor_neg$89 + sync init + end + process $group_89 + assign \core_calculate_stage_30_dividend_neg 1'0 + assign \core_calculate_stage_30_dividend_neg \core_calculate_stage_29_dividend_neg$90 + sync init + end + process $group_90 + assign \core_calculate_stage_30_dive_abs_ov32 1'0 + assign \core_calculate_stage_30_dive_abs_ov32 \core_calculate_stage_29_dive_abs_ov32$91 + sync init + end + process $group_91 + assign \core_calculate_stage_30_dive_abs_ov64 1'0 + assign \core_calculate_stage_30_dive_abs_ov64 \core_calculate_stage_29_dive_abs_ov64$92 + sync init + end + process $group_92 + assign \core_calculate_stage_30_div_by_zero 1'0 + assign \core_calculate_stage_30_div_by_zero \core_calculate_stage_29_div_by_zero$93 + sync init + end + process $group_93 + assign \core_calculate_stage_30_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_30_divisor_radicand \core_calculate_stage_29_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_30_operation 2'00 + assign \core_calculate_stage_30_operation \core_calculate_stage_29_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_30_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_30_quotient_root \core_calculate_stage_29_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_30_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_30_root_times_radicand \core_calculate_stage_29_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_30_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_30_compare_lhs \core_calculate_stage_29_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_30_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_30_compare_rhs \core_calculate_stage_29_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_31_muxid 2'00 + assign \core_calculate_stage_31_muxid \core_calculate_stage_30_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_31_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_31_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_31_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_31_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_31_logical_op__rc__rc 1'0 + assign \core_calculate_stage_31_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_31_logical_op__oe__oe 1'0 + assign \core_calculate_stage_31_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_31_logical_op__invert_in 1'0 + assign \core_calculate_stage_31_logical_op__zero_a 1'0 + assign \core_calculate_stage_31_logical_op__input_carry 2'00 + assign \core_calculate_stage_31_logical_op__invert_out 1'0 + assign \core_calculate_stage_31_logical_op__write_cr0 1'0 + assign \core_calculate_stage_31_logical_op__output_carry 1'0 + assign \core_calculate_stage_31_logical_op__is_32bit 1'0 + assign \core_calculate_stage_31_logical_op__is_signed 1'0 + assign \core_calculate_stage_31_logical_op__data_len 4'0000 + assign \core_calculate_stage_31_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_31_logical_op__insn \core_calculate_stage_31_logical_op__data_len \core_calculate_stage_31_logical_op__is_signed \core_calculate_stage_31_logical_op__is_32bit \core_calculate_stage_31_logical_op__output_carry \core_calculate_stage_31_logical_op__write_cr0 \core_calculate_stage_31_logical_op__invert_out \core_calculate_stage_31_logical_op__input_carry \core_calculate_stage_31_logical_op__zero_a \core_calculate_stage_31_logical_op__invert_in { \core_calculate_stage_31_logical_op__oe__oe_ok \core_calculate_stage_31_logical_op__oe__oe } { \core_calculate_stage_31_logical_op__rc__rc_ok \core_calculate_stage_31_logical_op__rc__rc } { \core_calculate_stage_31_logical_op__imm_data__imm_ok \core_calculate_stage_31_logical_op__imm_data__imm } \core_calculate_stage_31_logical_op__fn_unit \core_calculate_stage_31_logical_op__insn_type } { \core_calculate_stage_30_logical_op__insn$118 \core_calculate_stage_30_logical_op__data_len$117 \core_calculate_stage_30_logical_op__is_signed$116 \core_calculate_stage_30_logical_op__is_32bit$115 \core_calculate_stage_30_logical_op__output_carry$114 \core_calculate_stage_30_logical_op__write_cr0$113 \core_calculate_stage_30_logical_op__invert_out$112 \core_calculate_stage_30_logical_op__input_carry$111 \core_calculate_stage_30_logical_op__zero_a$110 \core_calculate_stage_30_logical_op__invert_in$109 { \core_calculate_stage_30_logical_op__oe__oe_ok$108 \core_calculate_stage_30_logical_op__oe__oe$107 } { \core_calculate_stage_30_logical_op__rc__rc_ok$106 \core_calculate_stage_30_logical_op__rc__rc$105 } { \core_calculate_stage_30_logical_op__imm_data__imm_ok$104 \core_calculate_stage_30_logical_op__imm_data__imm$103 } \core_calculate_stage_30_logical_op__fn_unit$102 \core_calculate_stage_30_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_31_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_31_ra \core_calculate_stage_30_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_31_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_31_rb \core_calculate_stage_30_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_31_xer_so 1'0 + assign \core_calculate_stage_31_xer_so \core_calculate_stage_30_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_31_divisor_neg 1'0 + assign \core_calculate_stage_31_divisor_neg \core_calculate_stage_30_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_31_dividend_neg 1'0 + assign \core_calculate_stage_31_dividend_neg \core_calculate_stage_30_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_31_dive_abs_ov32 1'0 + assign \core_calculate_stage_31_dive_abs_ov32 \core_calculate_stage_30_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_31_dive_abs_ov64 1'0 + assign \core_calculate_stage_31_dive_abs_ov64 \core_calculate_stage_30_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_31_div_by_zero 1'0 + assign \core_calculate_stage_31_div_by_zero \core_calculate_stage_30_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_31_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_31_divisor_radicand \core_calculate_stage_30_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_31_operation 2'00 + assign \core_calculate_stage_31_operation \core_calculate_stage_30_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_31_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_31_quotient_root \core_calculate_stage_30_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_31_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_31_root_times_radicand \core_calculate_stage_30_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_31_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_31_compare_lhs \core_calculate_stage_30_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_31_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_31_compare_rhs \core_calculate_stage_30_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" wire width 1 \n_i_rdy_data - process $group_66 + process $group_133 assign \n_i_rdy_data 1'0 assign \n_i_rdy_data \n_ready_i sync init @@ -115356,28 +107768,28 @@ module \pipe$106 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire width 1 \p_valid_i_p_ready_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $81 + wire width 1 $167 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $82 + cell $and $168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$80 + connect \A \p_valid_i$166 connect \B \p_ready_o - connect \Y $81 + connect \Y $167 end - process $group_67 + process $group_134 assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $81 + assign \p_valid_i_p_ready_o $167 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$83 - process $group_68 - assign \muxid$83 2'00 - assign \muxid$83 \output_muxid$54 + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_31_muxid$133 sync init end attribute \enum_base_type "MicrOp" @@ -115454,7 +107866,7 @@ module \pipe$106 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$84 + wire width 7 \logical_op__insn_type$170 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -115468,92 +107880,168 @@ module \pipe$106 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \sr_op__fn_unit$85 + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__imm$86 + wire width 1 \logical_op__imm_data__imm_ok$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__imm_ok$87 + wire width 1 \logical_op__rc__rc$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc$88 + wire width 1 \logical_op__rc__rc_ok$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc_ok$89 + wire width 1 \logical_op__oe__oe$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe$90 + wire width 1 \logical_op__oe__oe_ok$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe_ok$91 + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$92 + wire width 2 \logical_op__input_carry$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_carry$93 + wire width 1 \logical_op__invert_out$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__input_cr$94 + wire width 1 \logical_op__write_cr0$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_cr$95 + wire width 1 \logical_op__output_carry$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_32bit$96 + wire width 1 \logical_op__is_32bit$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_signed$97 + wire width 1 \logical_op__is_signed$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$98 - process $group_69 - assign \sr_op__insn_type$84 7'0000000 - assign \sr_op__fn_unit$85 11'00000000000 - assign \sr_op__imm_data__imm$86 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$87 1'0 - assign \sr_op__rc__rc$88 1'0 - assign \sr_op__rc__rc_ok$89 1'0 - assign \sr_op__oe__oe$90 1'0 - assign \sr_op__oe__oe_ok$91 1'0 - assign { } 0'0 - assign \sr_op__input_carry$92 2'00 - assign \sr_op__output_carry$93 1'0 - assign \sr_op__input_cr$94 1'0 - assign \sr_op__output_cr$95 1'0 - assign \sr_op__is_32bit$96 1'0 - assign \sr_op__is_signed$97 1'0 - assign \sr_op__insn$98 32'00000000000000000000000000000000 - assign { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 } { \output_sr_op__insn$69 \output_sr_op__is_signed$68 \output_sr_op__is_32bit$67 \output_sr_op__output_cr$66 \output_sr_op__input_cr$65 \output_sr_op__output_carry$64 \output_sr_op__input_carry$63 { } { \output_sr_op__oe__oe_ok$62 \output_sr_op__oe__oe$61 } { \output_sr_op__rc__rc_ok$60 \output_sr_op__rc__rc$59 } { \output_sr_op__imm_data__imm_ok$58 \output_sr_op__imm_data__imm$57 } \output_sr_op__fn_unit$56 \output_sr_op__insn_type$55 } + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_31_logical_op__insn$151 \core_calculate_stage_31_logical_op__data_len$150 \core_calculate_stage_31_logical_op__is_signed$149 \core_calculate_stage_31_logical_op__is_32bit$148 \core_calculate_stage_31_logical_op__output_carry$147 \core_calculate_stage_31_logical_op__write_cr0$146 \core_calculate_stage_31_logical_op__invert_out$145 \core_calculate_stage_31_logical_op__input_carry$144 \core_calculate_stage_31_logical_op__zero_a$143 \core_calculate_stage_31_logical_op__invert_in$142 { \core_calculate_stage_31_logical_op__oe__oe_ok$141 \core_calculate_stage_31_logical_op__oe__oe$140 } { \core_calculate_stage_31_logical_op__rc__rc_ok$139 \core_calculate_stage_31_logical_op__rc__rc$138 } { \core_calculate_stage_31_logical_op__imm_data__imm_ok$137 \core_calculate_stage_31_logical_op__imm_data__imm$136 } \core_calculate_stage_31_logical_op__fn_unit$135 \core_calculate_stage_31_logical_op__insn_type$134 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$100 - process $group_85 - assign \o$99 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$100 1'0 - assign { \o_ok$100 \o$99 } { \output_o_ok$71 \output_o$70 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_31_ra$152 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$102 - process $group_87 - assign \cr_a$101 4'0000 - assign \cr_a_ok$102 1'0 - assign { \cr_a_ok$102 \cr_a$101 } { \output_cr_a_ok \output_cr_a$72 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_31_rb$153 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$104 - process $group_89 - assign \xer_ca$103 2'00 - assign \xer_ca_ok$104 1'0 - assign { \xer_ca_ok$104 \xer_ca$103 } { \output_xer_ca_ok \output_xer_ca$73 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_31_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_31_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_31_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_31_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_31_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_31_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_31_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_31_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_31_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_31_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_31_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_31_compare_rhs$165 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" wire width 1 \r_busy$next - process $group_91 + process $group_168 assign \r_busy$next \r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } @@ -115574,488 +108062,997 @@ module \pipe$106 sync posedge \coresync_clk update \r_busy \r_busy$next end - process $group_92 + process $group_169 assign \muxid$1$next \muxid$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign \muxid$1$next \muxid$83 + assign \muxid$1$next \muxid$169 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign \muxid$1$next \muxid$83 + assign \muxid$1$next \muxid$169 end sync init update \muxid$1 2'00 sync posedge \coresync_clk update \muxid$1 \muxid$1$next end - process $group_93 - assign \sr_op__insn_type$2$next \sr_op__insn_type$2 - assign \sr_op__fn_unit$3$next \sr_op__fn_unit$3 - assign \sr_op__imm_data__imm$4$next \sr_op__imm_data__imm$4 - assign \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm_ok$5 - assign \sr_op__rc__rc$6$next \sr_op__rc__rc$6 - assign \sr_op__rc__rc_ok$7$next \sr_op__rc__rc_ok$7 - assign \sr_op__oe__oe$8$next \sr_op__oe__oe$8 - assign \sr_op__oe__oe_ok$9$next \sr_op__oe__oe_ok$9 - assign { } { } - assign \sr_op__input_carry$10$next \sr_op__input_carry$10 - assign \sr_op__output_carry$11$next \sr_op__output_carry$11 - assign \sr_op__input_cr$12$next \sr_op__input_cr$12 - assign \sr_op__output_cr$13$next \sr_op__output_cr$13 - assign \sr_op__is_32bit$14$next \sr_op__is_32bit$14 - assign \sr_op__is_signed$15$next \sr_op__is_signed$15 - assign \sr_op__insn$16$next \sr_op__insn$16 + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 } + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 } + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \sr_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$5$next 1'0 - assign \sr_op__rc__rc$6$next 1'0 - assign \sr_op__rc__rc_ok$7$next 1'0 - assign \sr_op__oe__oe$8$next 1'0 - assign \sr_op__oe__oe_ok$9$next 1'0 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 end sync init - update \sr_op__insn_type$2 7'0000000 - update \sr_op__fn_unit$3 11'00000000000 - update \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \sr_op__imm_data__imm_ok$5 1'0 - update \sr_op__rc__rc$6 1'0 - update \sr_op__rc__rc_ok$7 1'0 - update \sr_op__oe__oe$8 1'0 - update \sr_op__oe__oe_ok$9 1'0 - update { } 0'0 - update \sr_op__input_carry$10 2'00 - update \sr_op__output_carry$11 1'0 - update \sr_op__input_cr$12 1'0 - update \sr_op__output_cr$13 1'0 - update \sr_op__is_32bit$14 1'0 - update \sr_op__is_signed$15 1'0 - update \sr_op__insn$16 32'00000000000000000000000000000000 + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 sync posedge \coresync_clk - update \sr_op__insn_type$2 \sr_op__insn_type$2$next - update \sr_op__fn_unit$3 \sr_op__fn_unit$3$next - update \sr_op__imm_data__imm$4 \sr_op__imm_data__imm$4$next - update \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm_ok$5$next - update \sr_op__rc__rc$6 \sr_op__rc__rc$6$next - update \sr_op__rc__rc_ok$7 \sr_op__rc__rc_ok$7$next - update \sr_op__oe__oe$8 \sr_op__oe__oe$8$next - update \sr_op__oe__oe_ok$9 \sr_op__oe__oe_ok$9$next - update { } { } - update \sr_op__input_carry$10 \sr_op__input_carry$10$next - update \sr_op__output_carry$11 \sr_op__output_carry$11$next - update \sr_op__input_cr$12 \sr_op__input_cr$12$next - update \sr_op__output_cr$13 \sr_op__output_cr$13$next - update \sr_op__is_32bit$14 \sr_op__is_32bit$14$next - update \sr_op__is_signed$15 \sr_op__is_signed$15$next - update \sr_op__insn$16 \sr_op__insn$16$next + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next end - process $group_109 - assign \o$next \o - assign \o_ok$next \o_ok + process $group_188 + assign \ra$20$next \ra$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$100 \o$99 } + assign \ra$20$next \ra$188 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \o_ok$next \o$next } { \o_ok$100 \o$99 } + assign \ra$20$next \ra$188 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 end sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next + update \rb$21 \rb$21$next end - process $group_111 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok + process $group_190 + assign \xer_so$22$next \xer_so$22 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$102 \cr_a$101 } + assign \xer_so$22$next \xer_so$190 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$102 \cr_a$101 } + assign \xer_so$22$next \xer_so$190 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 end sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 + update \divisor_neg$23 1'0 sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next + update \divisor_neg$23 \divisor_neg$23$next end - process $group_113 - assign \xer_ca$17$next \xer_ca$17 - assign \xer_ca_ok$next \xer_ca_ok + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \xer_ca_ok$next \xer_ca$17$next } { \xer_ca_ok$104 \xer_ca$103 } + assign \dividend_neg$24$next \dividend_neg$192 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \xer_ca_ok$next \xer_ca$17$next } { \xer_ca_ok$104 \xer_ca$103 } + assign \dividend_neg$24$next \dividend_neg$192 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ca_ok$next 1'0 + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 end sync init - update \xer_ca$17 2'00 - update \xer_ca_ok 1'0 + update \dive_abs_ov32$25 1'0 sync posedge \coresync_clk - update \xer_ca$17 \xer_ca$17$next - update \xer_ca_ok \xer_ca_ok$next + update \dive_abs_ov32$25 \dive_abs_ov32$25$next end - process $group_115 + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 assign \n_valid_o 1'0 assign \n_valid_o \r_busy sync init end - process $group_116 + process $group_203 assign \p_ready_o 1'0 assign \p_ready_o \n_i_rdy_data sync init end - connect \cr_a$76 4'0000 - connect \cr_a_ok$77 1'0 - connect \xer_ca_ok$79 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0" -module \alu_shift_rot0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ca_ok - attribute \src "simple/issuer.py:89" - wire width 1 input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 7 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 8 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 9 \xer_ca - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 10 \sr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 11 \sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 12 \sr_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \sr_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \sr_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \sr_op__oe__oe_ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 19 \sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 21 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 22 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 23 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 24 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 25 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 26 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 27 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 28 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 29 \xer_ca$1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.p" +module \p$218 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 30 \p_valid_i + wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 31 \p_ready_o - cell \p$104 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 end - cell \n$105 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_sr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_sr_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__oe__oe_ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe_xer_ca +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.n" +module \n$219 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_n_valid_o + wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_32.core.trial0" +module \trial0$221 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_32.core.trial1" +module \trial1$222 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_32.core.pe" +module \pe$223 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_32.core" +module \core$220 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$221 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$222 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$223 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'11111 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_32" +module \core_calculate_stage_32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" attribute \enum_value_0000111 "OP_BC" attribute \enum_value_0001000 "OP_BCREG" attribute \enum_value_0001001 "OP_BPERM" @@ -116122,7 +109119,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_sr_op__insn_type$3 + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -116136,173 +109133,73 @@ module \alu_shift_rot0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_sr_op__fn_unit$4 + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_sr_op__imm_data__imm$5 + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__imm_data__imm_ok$6 + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__rc__rc$7 + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__rc__rc_ok$8 + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__oe__oe$9 + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__oe__oe_ok$10 + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_sr_op__input_carry$11 + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__output_carry$12 + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__input_cr$13 + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__output_cr$14 + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__is_32bit$15 + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_sr_op__is_signed$16 + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_sr_op__insn$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_xer_ca$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_ca_ok - cell \pipe$106 \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_p_valid_i - connect \p_ready_o \pipe_p_ready_o - connect \muxid \pipe_muxid - connect \sr_op__insn_type \pipe_sr_op__insn_type - connect \sr_op__fn_unit \pipe_sr_op__fn_unit - connect \sr_op__imm_data__imm \pipe_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \pipe_sr_op__imm_data__imm_ok - connect \sr_op__rc__rc \pipe_sr_op__rc__rc - connect \sr_op__rc__rc_ok \pipe_sr_op__rc__rc_ok - connect \sr_op__oe__oe \pipe_sr_op__oe__oe - connect \sr_op__oe__oe_ok \pipe_sr_op__oe__oe_ok - connect \sr_op__input_carry \pipe_sr_op__input_carry - connect \sr_op__output_carry \pipe_sr_op__output_carry - connect \sr_op__input_cr \pipe_sr_op__input_cr - connect \sr_op__output_cr \pipe_sr_op__output_cr - connect \sr_op__is_32bit \pipe_sr_op__is_32bit - connect \sr_op__is_signed \pipe_sr_op__is_signed - connect \sr_op__insn \pipe_sr_op__insn - connect \ra \pipe_ra - connect \rb \pipe_rb - connect \rc \pipe_rc - connect \xer_ca \pipe_xer_ca - connect \n_valid_o \pipe_n_valid_o - connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$2 - connect \sr_op__insn_type$2 \pipe_sr_op__insn_type$3 - connect \sr_op__fn_unit$3 \pipe_sr_op__fn_unit$4 - connect \sr_op__imm_data__imm$4 \pipe_sr_op__imm_data__imm$5 - connect \sr_op__imm_data__imm_ok$5 \pipe_sr_op__imm_data__imm_ok$6 - connect \sr_op__rc__rc$6 \pipe_sr_op__rc__rc$7 - connect \sr_op__rc__rc_ok$7 \pipe_sr_op__rc__rc_ok$8 - connect \sr_op__oe__oe$8 \pipe_sr_op__oe__oe$9 - connect \sr_op__oe__oe_ok$9 \pipe_sr_op__oe__oe_ok$10 - connect \sr_op__input_carry$10 \pipe_sr_op__input_carry$11 - connect \sr_op__output_carry$11 \pipe_sr_op__output_carry$12 - connect \sr_op__input_cr$12 \pipe_sr_op__input_cr$13 - connect \sr_op__output_cr$13 \pipe_sr_op__output_cr$14 - connect \sr_op__is_32bit$14 \pipe_sr_op__is_32bit$15 - connect \sr_op__is_signed$15 \pipe_sr_op__is_signed$16 - connect \sr_op__insn$16 \pipe_sr_op__insn$17 - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \cr_a \pipe_cr_a - connect \cr_a_ok \pipe_cr_a_ok - connect \xer_ca$17 \pipe_xer_ca$18 - connect \xer_ca_ok \pipe_xer_ca_ok - end - process $group_0 - assign \pipe_p_valid_i 1'0 - assign \pipe_p_valid_i \p_valid_i - sync init - end - process $group_1 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_2 - assign \pipe_muxid 2'00 - assign \pipe_muxid \muxid - sync init - end - process $group_3 - assign \pipe_sr_op__insn_type 7'0000000 - assign \pipe_sr_op__fn_unit 11'00000000000 - assign \pipe_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_sr_op__imm_data__imm_ok 1'0 - assign \pipe_sr_op__rc__rc 1'0 - assign \pipe_sr_op__rc__rc_ok 1'0 - assign \pipe_sr_op__oe__oe 1'0 - assign \pipe_sr_op__oe__oe_ok 1'0 - assign { } 0'0 - assign \pipe_sr_op__input_carry 2'00 - assign \pipe_sr_op__output_carry 1'0 - assign \pipe_sr_op__input_cr 1'0 - assign \pipe_sr_op__output_cr 1'0 - assign \pipe_sr_op__is_32bit 1'0 - assign \pipe_sr_op__is_signed 1'0 - assign \pipe_sr_op__insn 32'00000000000000000000000000000000 - assign { \pipe_sr_op__insn \pipe_sr_op__is_signed \pipe_sr_op__is_32bit \pipe_sr_op__output_cr \pipe_sr_op__input_cr \pipe_sr_op__output_carry \pipe_sr_op__input_carry { } { \pipe_sr_op__oe__oe_ok \pipe_sr_op__oe__oe } { \pipe_sr_op__rc__rc_ok \pipe_sr_op__rc__rc } { \pipe_sr_op__imm_data__imm_ok \pipe_sr_op__imm_data__imm } \pipe_sr_op__fn_unit \pipe_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } - sync init - end - process $group_19 - assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_ra \ra - sync init - end - process $group_20 - assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_rb \rb - sync init - end - process $group_21 - assign \pipe_rc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_rc \rc - sync init - end - process $group_22 - assign \pipe_xer_ca 2'00 - assign \pipe_xer_ca \xer_ca$1 - sync init - end - process $group_23 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_n_valid_o - sync init - end - process $group_24 - assign \pipe_n_ready_i 1'0 - assign \pipe_n_ready_i \n_ready_i - sync init - end + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$19 - process $group_25 - assign \muxid$19 2'00 - assign \muxid$19 \pipe_muxid$2 - sync init - end + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -116377,7 +109274,7 @@ module \alu_shift_rot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$20 + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -116391,1097 +109288,836 @@ module \alu_shift_rot0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \sr_op__fn_unit$21 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__imm$22 + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__imm_ok$23 + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc$24 + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc_ok$25 + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe$26 + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe_ok$27 + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$28 + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_carry$29 + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__input_cr$30 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_cr$31 + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_32bit$32 + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_signed$33 + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$34 + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$220 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end process $group_26 - assign \sr_op__insn_type$20 7'0000000 - assign \sr_op__fn_unit$21 11'00000000000 - assign \sr_op__imm_data__imm$22 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__imm_ok$23 1'0 - assign \sr_op__rc__rc$24 1'0 - assign \sr_op__rc__rc_ok$25 1'0 - assign \sr_op__oe__oe$26 1'0 - assign \sr_op__oe__oe_ok$27 1'0 - assign { } 0'0 - assign \sr_op__input_carry$28 2'00 - assign \sr_op__output_carry$29 1'0 - assign \sr_op__input_cr$30 1'0 - assign \sr_op__output_cr$31 1'0 - assign \sr_op__is_32bit$32 1'0 - assign \sr_op__is_signed$33 1'0 - assign \sr_op__insn$34 32'00000000000000000000000000000000 - assign { \sr_op__insn$34 \sr_op__is_signed$33 \sr_op__is_32bit$32 \sr_op__output_cr$31 \sr_op__input_cr$30 \sr_op__output_carry$29 \sr_op__input_carry$28 { } { \sr_op__oe__oe_ok$27 \sr_op__oe__oe$26 } { \sr_op__rc__rc_ok$25 \sr_op__rc__rc$24 } { \sr_op__imm_data__imm_ok$23 \sr_op__imm_data__imm$22 } \sr_op__fn_unit$21 \sr_op__insn_type$20 } { \pipe_sr_op__insn$17 \pipe_sr_op__is_signed$16 \pipe_sr_op__is_32bit$15 \pipe_sr_op__output_cr$14 \pipe_sr_op__input_cr$13 \pipe_sr_op__output_carry$12 \pipe_sr_op__input_carry$11 { } { \pipe_sr_op__oe__oe_ok$10 \pipe_sr_op__oe__oe$9 } { \pipe_sr_op__rc__rc_ok$8 \pipe_sr_op__rc__rc$7 } { \pipe_sr_op__imm_data__imm_ok$6 \pipe_sr_op__imm_data__imm$5 } \pipe_sr_op__fn_unit$4 \pipe_sr_op__insn_type$3 } + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - process $group_42 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_o_ok \pipe_o } + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - process $group_44 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a } + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - process $group_46 - assign \xer_ca 2'00 - assign \xer_ca_ok 1'0 - assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$18 } + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - connect \muxid 2'00 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" -module \src_l$112 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_33.core.trial0" +module \trial0$225 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $1 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $3 - connect \B \s_src - connect \Y $5 - end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \q_int$next 4'0000 + assign \dr_times_trial_bits $3 end sync init - update \q_int 4'0000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $7 - connect \Y $9 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 4'0000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 4'0000 - assign \qn_src $13 - sync init + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011110 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_3 - assign \qlq_src 4'0000 - assign \qlq_src $15 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" -module \opc_l$113 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_33.core.trial1" +module \trial1$226 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r_opc + connect \A \operation + connect \B 1'1 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc + connect \A \operation + connect \B 1'1 connect \Y $5 end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011110 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_33.core.pe" +module \pe$227 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \q_int$next 1'0 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 end sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 + connect \A \i + connect \B 1'0 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_33.core" +module \core$224 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$225 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$226 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$227 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" -module \req_l$114 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $1 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_req - connect \Y $5 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end - sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 3'000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 3'000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 3'000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" -module \rst_l$115 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" -module \rok_l$116 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" -module \alui_l$117 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 - end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 - end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" -module \alu_l$118 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 - end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 - end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 - sync init + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'11110 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0" -module \shiftrot0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_33" +module \core_calculate_stage_33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -117556,7 +110192,7 @@ module \shiftrot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_shift_rot0__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -117570,83 +110206,73 @@ module \shiftrot0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_shift_rot0__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_shift_rot0__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_shift_rot0__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \oper_i_alu_shift_rot0__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_shift_rot0__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \oper_i_alu_shift_rot0__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_shift_rot0__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \oper_i_alu_shift_rot0__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \oper_i_alu_shift_rot0__output_carry + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_alu_shift_rot0__input_cr + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \oper_i_alu_shift_rot0__output_cr + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_alu_shift_rot0__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \oper_i_alu_shift_rot0__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \oper_i_alu_shift_rot0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 17 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 18 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 4 input 19 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 20 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 21 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 22 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 23 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 24 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 2 input 25 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 26 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 27 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 28 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 29 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 30 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 31 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 32 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 33 \dest3_o - attribute \src "simple/issuer.py:89" - wire width 1 input 34 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_shift_rot0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_shift_rot0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_shift_rot0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_shift_rot0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_shift_rot0_xer_ca + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -117721,7 +110347,7 @@ module \shiftrot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_shift_rot0_sr_op__insn_type + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -117735,831 +110361,836 @@ module \shiftrot0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_shift_rot0_sr_op__fn_unit + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_shift_rot0_sr_op__imm_data__imm + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__imm_data__imm_ok + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__rc__rc + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__rc__rc_ok + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__oe__oe + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__oe__oe_ok + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_shift_rot0_sr_op__input_carry + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__output_carry + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__input_cr + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__output_cr + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__is_32bit + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__is_signed + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_shift_rot0_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_ra + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_rb + wire width 64 output 52 \ra$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_rc + wire width 64 output 53 \rb$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_shift_rot0_xer_ca$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_shift_rot0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_shift_rot0_p_ready_o - cell \alu_shift_rot0 \alu_shift_rot0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \cr_a_ok \cr_a_ok - connect \xer_ca_ok \xer_ca_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_shift_rot0_n_valid_o - connect \n_ready_i \alu_shift_rot0_n_ready_i - connect \o \alu_shift_rot0_o - connect \cr_a \alu_shift_rot0_cr_a - connect \xer_ca \alu_shift_rot0_xer_ca - connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type - connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit - connect \sr_op__imm_data__imm \alu_shift_rot0_sr_op__imm_data__imm - connect \sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm_ok - connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc - connect \sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc_ok - connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe - connect \sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe_ok - connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry - connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry - connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr - connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr - connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit - connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed - connect \sr_op__insn \alu_shift_rot0_sr_op__insn - connect \ra \alu_shift_rot0_ra - connect \rb \alu_shift_rot0_rb - connect \rc \alu_shift_rot0_rc - connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 - connect \p_valid_i \alu_shift_rot0_p_valid_i - connect \p_ready_o \alu_shift_rot0_p_ready_o + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$224 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \src_l_q_src - cell \src_l$112 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$113 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req$next - cell \req_l$114 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - cell \rst_l$115 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$116 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$117 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$118 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - cell $and $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $2 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__rel_o - connect \Y $5 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $5 - connect \B \cu_rd__go_i - connect \Y $7 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $reduce_and $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A $7 - connect \Y $4 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $2 - connect \B $4 - connect \Y $10 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $10 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $12 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" - cell $and $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $12 - connect \Y $14 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_2 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse $14 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_done - process $group_3 - assign \alu_done 1'0 - assign \alu_done \alu_shift_rot0_n_valid_o + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 1 \alu_done_dly$next - process $group_4 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 1 \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203" - cell $and $19 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_34.core.trial0" +module \trial0$229 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $16 - connect \Y $18 - end - process $group_5 - assign \alu_pulse 1'0 - assign \alu_pulse $18 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" - wire width 3 \alu_pulsem - process $group_6 - assign \alu_pulsem 3'000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - sync init + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" - wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 3 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - cell $and $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $20 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_7 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $20 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \prev_wr_go$next 3'000 + assign \dr_times_trial_bits $3 end sync init - update \prev_wr_go 3'000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wrmask_o - connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__rel_o - connect \B $24 - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $reduce_bool $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $26 - connect \Y $23 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $not $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $23 - connect \Y $22 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $22 - connect \Y $30 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_8 - assign \cu_done_o 1'0 - assign \cu_done_o $30 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $reduce_bool $35 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_34.core.trial1" +module \trial1$230 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $34 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218" - cell $or $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \B $34 - connect \Y $36 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_9 - assign \wr_any 1'0 - assign \wr_any $36 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $not $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_ready_i - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219" - cell $and $41 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $38 - connect \Y $40 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 3 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $43 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $42 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $eq $45 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $42 - connect \B 1'0 - connect \Y $44 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" - cell $and $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $40 - connect \B $44 - connect \Y $46 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $eq $49 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_34.core.pe" +module \pe$231 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o + connect \A \i connect \B 1'0 - connect \Y $48 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $51 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_34.core" +module \core$228 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$229 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$230 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$231 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A $48 - connect \B \alu_shift_rot0_n_ready_i - connect \Y $50 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $53 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $50 - connect \B \alu_shift_rot0_n_valid_o - connect \Y $52 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - cell $and $55 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $52 - connect \B \cu_busy_o - connect \Y $54 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_10 - assign \req_done 1'0 - assign \req_done $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" - switch { $54 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \req_done 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $57 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $56 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_11 - assign \reset 1'0 - assign \reset $56 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - wire width 1 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234" - cell $or $59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $58 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_12 - assign \rst_r 1'0 - assign \rst_r $58 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - wire width 3 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235" - cell $or $61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $60 - end - process $group_13 - assign \reset_w 3'000 - assign \reset_w $60 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - wire width 4 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236" - cell $or $63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $62 - end - process $group_14 - assign \reset_r 4'0000 - assign \reset_r $62 - sync init - end - process $group_15 - assign \rok_l_s_rdok 1'0 - assign \rok_l_s_rdok \cu_issue_i - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240" - cell $and $65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_valid_o - connect \B \cu_busy_o - connect \Y $64 - end - process $group_16 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $64 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_17 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \all_rd - sync init - end - process $group_18 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \rst_r - sync init - end - process $group_19 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end process $group_20 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_21 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 4'0000 - end - sync init - update \src_l_s_src 4'0000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_22 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 4'1111 - end + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init - update \src_l_r_src 4'1111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - wire width 3 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255" - cell $and $67 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $66 - end - process $group_23 - assign \req_l_s_req 3'000 - assign \req_l_s_req $66 - sync init + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'11101 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - wire width 3 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256" - cell $or $69 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $68 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_24 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $68 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 3'111 - end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init - update \req_l_r_req 3'111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_34" +module \core_calculate_stage_34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -118634,7 +111265,7 @@ module \shiftrot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -118648,2376 +111279,2622 @@ module \shiftrot0 attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__output_carry + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__input_cr + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__output_cr + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_signed + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 11 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__input_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__input_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_carry - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_carry$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__input_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__input_cr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_cr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 126 $70 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $71 - parameter \WIDTH 126 - connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { } { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } - connect \B { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry { } { \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } - connect \S \cu_issue_i - connect \Y $70 + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$228 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end process $group_25 - assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 11'00000000000 - assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__imm_data__imm_ok 1'0 - assign \oper_r__rc__rc 1'0 - assign \oper_r__rc__rc_ok 1'0 - assign \oper_r__oe__oe 1'0 - assign \oper_r__oe__oe_ok 1'0 - assign { } 0'0 - assign \oper_r__input_carry 2'00 - assign \oper_r__output_carry 1'0 - assign \oper_r__input_cr 1'0 - assign \oper_r__output_cr 1'0 - assign \oper_r__is_32bit 1'0 - assign \oper_r__is_signed 1'0 - assign \oper_r__insn 32'00000000000000000000000000000000 - assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $70 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - process $group_41 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__rc__rc$next \oper_l__rc__rc - assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok - assign \oper_l__oe__oe$next \oper_l__oe__oe - assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok - assign { } { } - assign \oper_l__input_carry$next \oper_l__input_carry - assign \oper_l__output_carry$next \oper_l__output_carry - assign \oper_l__input_cr$next \oper_l__input_cr - assign \oper_l__output_cr$next \oper_l__output_cr - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__insn$next \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { } { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry { } { \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - assign \oper_l__rc__rc$next 1'0 - assign \oper_l__rc__rc_ok$next 1'0 - assign \oper_l__oe__oe$next 1'0 - assign \oper_l__oe__oe_ok$next 1'0 - end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 11'00000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__rc__rc 1'0 - update \oper_l__rc__rc_ok 1'0 - update \oper_l__oe__oe 1'0 - update \oper_l__oe__oe_ok 1'0 - update { } 0'0 - update \oper_l__input_carry 2'00 - update \oper_l__output_carry 1'0 - update \oper_l__input_cr 1'0 - update \oper_l__output_cr 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__rc__rc \oper_l__rc__rc$next - update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next - update \oper_l__oe__oe \oper_l__oe__oe$next - update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next - update { } { } - update \oper_l__input_carry \oper_l__input_carry$next - update \oper_l__output_carry \oper_l__output_carry$next - update \oper_l__input_cr \oper_l__input_cr$next - update \oper_l__output_cr \oper_l__output_cr$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__insn \oper_l__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 65 $72 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $73 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $75 - parameter \WIDTH 65 - connect \A { \data_r0_l__o_ok \data_r0_l__o } - connect \B { \o_ok \alu_shift_rot0_o } - connect \S $73 - connect \Y $72 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - process $group_57 - assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__o_ok 1'0 - assign { \data_r0__o_ok \data_r0__o } $72 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $76 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $76 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - process $group_59 - assign \data_r0_l__o$next \data_r0_l__o - assign \data_r0_l__o_ok$next \data_r0_l__o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $76 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_shift_rot0_o } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0_l__o_ok$next 1'0 - end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init - update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0_l__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0_l__o \data_r0_l__o$next - update \data_r0_l__o_ok \data_r0_l__o_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 5 $78 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $79 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $81 - parameter \WIDTH 5 - connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a } - connect \B { \cr_a_ok \alu_shift_rot0_cr_a } - connect \S $79 - connect \Y $78 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_61 - assign \data_r1__cr_a 4'0000 - assign \data_r1__cr_a_ok 1'0 - assign { \data_r1__cr_a_ok \data_r1__cr_a } $78 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $82 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $83 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $82 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - process $group_63 - assign \data_r1_l__cr_a$next \data_r1_l__cr_a - assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $82 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_shift_rot0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1_l__cr_a_ok$next 1'0 - end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init - update \data_r1_l__cr_a 4'0000 - update \data_r1_l__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r1_l__cr_a \data_r1_l__cr_a$next - update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270" - wire width 1 \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 3 $84 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744" - cell $reduce_bool $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $85 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $87 - parameter \WIDTH 3 - connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } - connect \B { \xer_ca_ok \alu_shift_rot0_xer_ca } - connect \S $85 - connect \Y $84 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init end - process $group_65 - assign \data_r2__xer_ca 2'00 - assign \data_r2__xer_ca_ok 1'0 - assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $84 + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $88 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $89 + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_35.core.trial0" +module \trial0$233 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_pulsem - connect \Y $88 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - process $group_67 - assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca - assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { $88 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \alu_shift_rot0_xer_ca } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \data_r2_l__xer_ca_ok$next 1'0 + assign \dr_times_trial_bits $3 end sync init - update \data_r2_l__xer_ca 2'00 - update \data_r2_l__xer_ca_ok 1'0 - sync posedge \coresync_clk - update \data_r2_l__xer_ca \data_r2_l__xer_ca$next - update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \data_r0__o_ok - connect \B \cu_busy_o - connect \Y $90 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r1__cr_a_ok - connect \B \cu_busy_o - connect \Y $92 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011100 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - wire width 1 $94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278" - cell $and $95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_r2__xer_ca_ok - connect \B \cu_busy_o - connect \Y $94 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_69 - assign \cu_wrmask_o 3'000 - assign \cu_wrmask_o { $94 $92 $90 } + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - process $group_70 - assign \alu_shift_rot0_sr_op__insn_type 7'0000000 - assign \alu_shift_rot0_sr_op__fn_unit 11'00000000000 - assign \alu_shift_rot0_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_shift_rot0_sr_op__imm_data__imm_ok 1'0 - assign \alu_shift_rot0_sr_op__rc__rc 1'0 - assign \alu_shift_rot0_sr_op__rc__rc_ok 1'0 - assign \alu_shift_rot0_sr_op__oe__oe 1'0 - assign \alu_shift_rot0_sr_op__oe__oe_ok 1'0 - assign { } 0'0 - assign \alu_shift_rot0_sr_op__input_carry 2'00 - assign \alu_shift_rot0_sr_op__output_carry 1'0 - assign \alu_shift_rot0_sr_op__input_cr 1'0 - assign \alu_shift_rot0_sr_op__output_cr 1'0 - assign \alu_shift_rot0_sr_op__is_32bit 1'0 - assign \alu_shift_rot0_sr_op__is_signed 1'0 - assign \alu_shift_rot0_sr_op__insn 32'00000000000000000000000000000000 - assign { \alu_shift_rot0_sr_op__insn \alu_shift_rot0_sr_op__is_signed \alu_shift_rot0_sr_op__is_32bit \alu_shift_rot0_sr_op__output_cr \alu_shift_rot0_sr_op__input_cr \alu_shift_rot0_sr_op__output_carry \alu_shift_rot0_sr_op__input_carry { } { \alu_shift_rot0_sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe } { \alu_shift_rot0_sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc } { \alu_shift_rot0_sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm } \alu_shift_rot0_sr_op__fn_unit \alu_shift_rot0_sr_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_35.core.trial1" +module \trial1$234 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 $96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - cell $mux $97 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \oper_r__imm_data__imm_ok - connect \Y $96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_86 - assign \src_sel 1'0 - assign \src_sel $96 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 64 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $99 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \oper_r__imm_data__imm - connect \S \oper_r__imm_data__imm_ok - connect \Y $98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_87 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $98 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011100 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $100 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $101 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $100 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_88 - assign \alu_shift_rot0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_shift_rot0_ra $100 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - process $group_89 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_35.core.pe" +module \pe$235 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \src_r0$next \src1_i + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 end sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $102 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $103 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $102 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_90 - assign \alu_shift_rot0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_shift_rot0_rb $102 + process $group_1 + assign \n 1'0 + assign \n $1 sync init end - process $group_91 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src_or_imm - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_35.core" +module \core$232 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$233 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$234 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $104 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $105 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $104 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$235 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end - process $group_92 - assign \alu_shift_rot0_rc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_shift_rot0_rc $104 + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - process $group_93 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation sync init - update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r2 \src_r2$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $106 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $107 - parameter \WIDTH 2 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $106 + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init end - process $group_94 - assign \alu_shift_rot0_xer_ca$1 2'00 - assign \alu_shift_rot0_xer_ca$1 $106 + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - process $group_95 - assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r3$next \src4_i - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init - update \src_r3 2'00 - sync posedge \coresync_clk - update \src_r3 \src_r3$next end - process $group_96 - assign \alu_shift_rot0_p_valid_i 1'0 - assign \alu_shift_rot0_p_valid_i \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - wire width 1 $108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329" - cell $and $109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $108 + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init end - process $group_97 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $108 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next end - process $group_98 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end - process $group_99 - assign \alu_shift_rot0_n_ready_i 1'0 - assign \alu_shift_rot0_n_ready_i \alu_l_q_alu + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - wire width 1 $110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336" - cell $and $111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $110 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init end - process $group_100 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $110 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next end - process $group_101 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end - process $group_102 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $113 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $112 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - wire width 1 $114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172" - cell $not $115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \oper_r__imm_data__imm_ok - connect \Y $114 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $112 - connect \B { 1'1 1'1 $114 1'1 } - connect \Y $116 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $not $119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rdmaskn_i - connect \Y $118 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - wire width 4 $120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" - cell $and $121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $116 - connect \B $118 - connect \Y $120 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init end - process $group_103 - assign \cu_rd__rel_o 4'0000 - assign \cu_rd__rel_o $120 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $123 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $122 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $124 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - wire width 1 $126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352" - cell $and $127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $126 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 3 $128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B { $122 $124 $126 } - connect \Y $128 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - wire width 3 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353" - cell $and $131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $128 - connect \B \cu_wrmask_o - connect \Y $130 - end - process $group_104 - assign \cu_wr__rel_o 3'000 - assign \cu_wr__rel_o $130 - sync init + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $133 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $132 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_105 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $132 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $135 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $134 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_106 - assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $134 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - wire width 1 $136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - cell $and $137 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $136 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_107 - assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - switch { $136 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357" - case 1'1 - assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" -module \opc_l$119 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'11100 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8.core_calculate_stage_35" +module \core_calculate_stage_35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$232 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" -module \src_l$120 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $1 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_src - connect \Y $5 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $7 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_src - connect \Y $11 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - process $group_1 - assign \q_src 3'000 - assign \q_src $11 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $13 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - process $group_2 - assign \qn_src 3'000 - assign \qn_src $13 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $15 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - process $group_3 - assign \qlq_src 3'000 - assign \qlq_src $15 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" -module \alu_l$121 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_8" +module \pipe_middle_8 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 - end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 - end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l" -module \adr_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_adr - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_adr - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_adr - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_adr - connect \Y $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 41 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$218 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_1 - assign \q_adr 1'0 - assign \q_adr $11 - sync init + cell \n$219 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_adr - connect \Y $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_32_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_32_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_32_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_32_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_32_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_32_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_32_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_32_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_32_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_32_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_32_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_32_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_32_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_32_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_32_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_32_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_32_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_32_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_32_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_32_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_32_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_32_muxid$34 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_32_logical_op__insn_type$35 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_32_logical_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_32_logical_op__imm_data__imm$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__imm_data__imm_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__invert_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_32_logical_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__write_cr0$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_32_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_32_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_32_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_32_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_32_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_32_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_32_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_32_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_32_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_32_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_32_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_32_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_32_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_32_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_32_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_32_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_32_compare_rhs$66 + cell \core_calculate_stage_32 \core_calculate_stage_32 + connect \muxid \core_calculate_stage_32_muxid + connect \logical_op__insn_type \core_calculate_stage_32_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_32_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_32_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_32_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_32_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_32_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_32_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_32_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_32_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_32_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_32_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_32_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_32_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_32_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_32_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_32_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_32_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_32_logical_op__insn + connect \ra \core_calculate_stage_32_ra + connect \rb \core_calculate_stage_32_rb + connect \xer_so \core_calculate_stage_32_xer_so + connect \divisor_neg \core_calculate_stage_32_divisor_neg + connect \dividend_neg \core_calculate_stage_32_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_32_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_32_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_32_div_by_zero + connect \divisor_radicand \core_calculate_stage_32_divisor_radicand + connect \operation \core_calculate_stage_32_operation + connect \quotient_root \core_calculate_stage_32_quotient_root + connect \root_times_radicand \core_calculate_stage_32_root_times_radicand + connect \compare_lhs \core_calculate_stage_32_compare_lhs + connect \compare_rhs \core_calculate_stage_32_compare_rhs + connect \muxid$1 \core_calculate_stage_32_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_32_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_32_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_32_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_32_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_32_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_32_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_32_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_32_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_32_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_32_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_32_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_32_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_32_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_32_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_32_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_32_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_32_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_32_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_32_ra$53 + connect \rb$21 \core_calculate_stage_32_rb$54 + connect \xer_so$22 \core_calculate_stage_32_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_32_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_32_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_32_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_32_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_32_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_32_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_32_operation$62 + connect \quotient_root$30 \core_calculate_stage_32_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_32_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_32_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_32_compare_rhs$66 end - process $group_2 - assign \qn_adr 1'0 - assign \qn_adr $13 - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_33_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_33_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_33_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_33_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_33_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_33_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_33_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_33_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_33_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_33_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_33_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_33_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_33_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_33_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_33_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_33_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_33_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_33_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_33_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_33_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_33_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_33_muxid$67 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_33_logical_op__insn_type$68 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_33_logical_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_33_logical_op__imm_data__imm$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__imm_data__imm_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__rc__rc_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_33_logical_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__invert_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__write_cr0$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_33_logical_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_33_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_33_logical_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_33_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_33_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_33_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_33_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_33_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_33_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_33_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_33_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_33_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_33_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_33_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_33_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_33_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_33_compare_rhs$99 + cell \core_calculate_stage_33 \core_calculate_stage_33 + connect \muxid \core_calculate_stage_33_muxid + connect \logical_op__insn_type \core_calculate_stage_33_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_33_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_33_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_33_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_33_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_33_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_33_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_33_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_33_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_33_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_33_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_33_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_33_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_33_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_33_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_33_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_33_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_33_logical_op__insn + connect \ra \core_calculate_stage_33_ra + connect \rb \core_calculate_stage_33_rb + connect \xer_so \core_calculate_stage_33_xer_so + connect \divisor_neg \core_calculate_stage_33_divisor_neg + connect \dividend_neg \core_calculate_stage_33_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_33_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_33_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_33_div_by_zero + connect \divisor_radicand \core_calculate_stage_33_divisor_radicand + connect \operation \core_calculate_stage_33_operation + connect \quotient_root \core_calculate_stage_33_quotient_root + connect \root_times_radicand \core_calculate_stage_33_root_times_radicand + connect \compare_lhs \core_calculate_stage_33_compare_lhs + connect \compare_rhs \core_calculate_stage_33_compare_rhs + connect \muxid$1 \core_calculate_stage_33_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_33_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_33_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_33_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_33_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_33_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_33_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_33_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_33_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_33_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_33_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_33_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_33_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_33_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_33_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_33_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_33_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_33_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_33_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_33_ra$86 + connect \rb$21 \core_calculate_stage_33_rb$87 + connect \xer_so$22 \core_calculate_stage_33_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_33_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_33_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_33_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_33_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_33_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_33_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_33_operation$95 + connect \quotient_root$30 \core_calculate_stage_33_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_33_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_33_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_33_compare_rhs$99 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_adr - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_adr 1'0 - assign \qlq_adr $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l" -module \lod_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 output 4 \qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lod - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_lod - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lod - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_lod - connect \Y $11 - end - process $group_1 - assign \q_lod 1'0 - assign \q_lod $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lod - connect \Y $13 - end - process $group_2 - assign \qn_lod 1'0 - assign \qn_lod $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lod - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_lod 1'0 - assign \qlq_lod $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l" -module \sto_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_sto - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_sto - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_sto - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_sto - connect \Y $11 - end - process $group_1 - assign \q_sto 1'0 - assign \q_sto $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_sto - connect \Y $13 - end - process $group_2 - assign \qn_sto 1'0 - assign \qn_sto $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_sto - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_sto 1'0 - assign \qlq_sto $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l" -module \wri_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_wri - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_wri - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_wri - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_wri - connect \Y $11 - end - process $group_1 - assign \q_wri 1'0 - assign \q_wri $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_wri - connect \Y $13 - end - process $group_2 - assign \qn_wri 1'0 - assign \qn_wri $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_wri - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_wri 1'0 - assign \qlq_wri $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l" -module \upd_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_upd - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_upd - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_upd - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_upd - connect \Y $11 - end - process $group_1 - assign \q_upd 1'0 - assign \q_upd $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_upd - connect \Y $13 - end - process $group_2 - assign \qn_upd 1'0 - assign \qn_upd $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_upd - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_upd 1'0 - assign \qlq_upd $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" -module \rst_l$122 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l" -module \lsd_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lsd - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_lsd - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lsd - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_lsd - connect \Y $11 - end - process $group_1 - assign \q_lsd 1'0 - assign \q_lsd $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lsd - connect \Y $13 - end - process $group_2 - assign \qn_lsd 1'0 - assign \qn_lsd $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lsd - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_lsd 1'0 - assign \qlq_lsd $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0" -module \ldst0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 1 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 input 2 \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 3 \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 input 4 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_34_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -121092,700 +113969,1113 @@ module \ldst0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \oper_i_ldst_ldst0__insn_type + wire width 7 \core_calculate_stage_34_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 6 \oper_i_ldst_ldst0__imm_data__imm + wire width 11 \core_calculate_stage_34_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \oper_i_ldst_ldst0__imm_data__imm_ok + wire width 64 \core_calculate_stage_34_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_ldst_ldst0__zero_a + wire width 1 \core_calculate_stage_34_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \oper_i_ldst_ldst0__rc__rc + wire width 1 \core_calculate_stage_34_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \oper_i_ldst_ldst0__rc__rc_ok + wire width 1 \core_calculate_stage_34_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \oper_i_ldst_ldst0__oe__oe + wire width 1 \core_calculate_stage_34_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_ldst_ldst0__oe__oe_ok + wire width 1 \core_calculate_stage_34_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \oper_i_ldst_ldst0__is_32bit + wire width 1 \core_calculate_stage_34_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_ldst_ldst0__is_signed + wire width 1 \core_calculate_stage_34_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 15 \oper_i_ldst_ldst0__data_len + wire width 2 \core_calculate_stage_34_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \oper_i_ldst_ldst0__byte_reverse + wire width 1 \core_calculate_stage_34_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \oper_i_ldst_ldst0__sign_extend - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" + wire width 1 \core_calculate_stage_34_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 18 \oper_i_ldst_ldst0__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 19 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 20 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 input 21 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 22 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 23 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 24 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 25 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 26 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 27 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 input 28 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 29 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 30 \ea - attribute \src "simple/issuer.py:89" - wire width 1 input 31 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 32 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 33 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 34 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 output 35 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 36 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 input 37 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 input 38 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 39 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 40 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 41 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 42 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$119 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - cell \src_l$120 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - cell \alu_l$121 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_alu \alu_l_s_alu - connect \r_alu \alu_l_r_alu - connect \q_alu \alu_l_q_alu - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \adr_l_s_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \adr_l_r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \adr_l_r_adr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \adr_l_q_adr - cell \adr_l \adr_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_adr \adr_l_s_adr - connect \r_adr \adr_l_r_adr - connect \q_adr \adr_l_q_adr - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \lod_l_s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \lod_l_r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \lod_l_qn_lod - cell \lod_l \lod_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_lod \lod_l_s_lod - connect \r_lod \lod_l_r_lod - connect \qn_lod \lod_l_qn_lod - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \sto_l_s_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \sto_l_r_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \sto_l_r_sto$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \sto_l_q_sto - cell \sto_l \sto_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_sto \sto_l_s_sto - connect \r_sto \sto_l_r_sto - connect \q_sto \sto_l_q_sto - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \wri_l_s_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \wri_l_r_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \wri_l_r_wri$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \wri_l_q_wri - cell \wri_l \wri_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_wri \wri_l_s_wri - connect \r_wri \wri_l_r_wri - connect \q_wri \wri_l_q_wri + wire width 1 \core_calculate_stage_34_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_34_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_34_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_34_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_34_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_34_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_34_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_34_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_34_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_34_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_34_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_34_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_34_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_34_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_34_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_34_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_34_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_34_muxid$100 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_34_logical_op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_34_logical_op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_34_logical_op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__rc__rc$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__rc__rc_ok$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__oe__oe$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_34_logical_op__input_carry$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__invert_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__write_cr0$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__output_carry$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__is_32bit$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_34_logical_op__is_signed$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_34_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_34_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_34_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_34_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_34_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_34_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_34_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_34_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_34_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_34_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_34_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_34_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_34_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_34_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_34_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_34_compare_rhs$132 + cell \core_calculate_stage_34 \core_calculate_stage_34 + connect \muxid \core_calculate_stage_34_muxid + connect \logical_op__insn_type \core_calculate_stage_34_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_34_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_34_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_34_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_34_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_34_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_34_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_34_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_34_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_34_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_34_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_34_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_34_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_34_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_34_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_34_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_34_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_34_logical_op__insn + connect \ra \core_calculate_stage_34_ra + connect \rb \core_calculate_stage_34_rb + connect \xer_so \core_calculate_stage_34_xer_so + connect \divisor_neg \core_calculate_stage_34_divisor_neg + connect \dividend_neg \core_calculate_stage_34_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_34_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_34_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_34_div_by_zero + connect \divisor_radicand \core_calculate_stage_34_divisor_radicand + connect \operation \core_calculate_stage_34_operation + connect \quotient_root \core_calculate_stage_34_quotient_root + connect \root_times_radicand \core_calculate_stage_34_root_times_radicand + connect \compare_lhs \core_calculate_stage_34_compare_lhs + connect \compare_rhs \core_calculate_stage_34_compare_rhs + connect \muxid$1 \core_calculate_stage_34_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_34_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_34_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_34_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_34_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_34_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_34_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_34_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_34_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_34_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_34_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_34_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_34_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_34_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_34_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_34_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_34_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_34_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_34_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_34_ra$119 + connect \rb$21 \core_calculate_stage_34_rb$120 + connect \xer_so$22 \core_calculate_stage_34_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_34_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_34_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_34_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_34_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_34_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_34_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_34_operation$128 + connect \quotient_root$30 \core_calculate_stage_34_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_34_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_34_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_34_compare_rhs$132 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \upd_l_s_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \upd_l_s_upd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \upd_l_r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \upd_l_r_upd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \upd_l_q_upd - cell \upd_l \upd_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_upd \upd_l_s_upd - connect \r_upd \upd_l_r_upd - connect \q_upd \upd_l_q_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_35_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_35_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_35_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_35_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__zero_a + attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_35_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_35_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_35_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_35_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_35_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_35_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_35_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_35_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_35_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_35_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_35_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_35_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_35_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_35_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_35_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_35_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_35_muxid$133 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_35_logical_op__insn_type$134 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_35_logical_op__fn_unit$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_35_logical_op__imm_data__imm$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__imm_data__imm_ok$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__rc__rc$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__rc__rc_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__oe__oe$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__oe__oe_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__invert_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_35_logical_op__input_carry$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__invert_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__write_cr0$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__output_carry$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_35_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_35_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_35_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_35_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_35_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_35_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_35_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_35_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_35_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_35_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_35_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_35_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_35_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_35_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_35_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_35_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_35_compare_rhs$165 + cell \core_calculate_stage_35 \core_calculate_stage_35 + connect \muxid \core_calculate_stage_35_muxid + connect \logical_op__insn_type \core_calculate_stage_35_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_35_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_35_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_35_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_35_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_35_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_35_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_35_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_35_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_35_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_35_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_35_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_35_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_35_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_35_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_35_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_35_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_35_logical_op__insn + connect \ra \core_calculate_stage_35_ra + connect \rb \core_calculate_stage_35_rb + connect \xer_so \core_calculate_stage_35_xer_so + connect \divisor_neg \core_calculate_stage_35_divisor_neg + connect \dividend_neg \core_calculate_stage_35_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_35_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_35_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_35_div_by_zero + connect \divisor_radicand \core_calculate_stage_35_divisor_radicand + connect \operation \core_calculate_stage_35_operation + connect \quotient_root \core_calculate_stage_35_quotient_root + connect \root_times_radicand \core_calculate_stage_35_root_times_radicand + connect \compare_lhs \core_calculate_stage_35_compare_lhs + connect \compare_rhs \core_calculate_stage_35_compare_rhs + connect \muxid$1 \core_calculate_stage_35_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_35_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_35_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_35_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_35_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_35_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_35_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_35_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_35_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_35_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_35_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_35_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_35_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_35_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_35_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_35_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_35_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_35_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_35_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_35_ra$152 + connect \rb$21 \core_calculate_stage_35_rb$153 + connect \xer_so$22 \core_calculate_stage_35_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_35_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_35_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_35_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_35_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_35_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_35_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_35_operation$161 + connect \quotient_root$30 \core_calculate_stage_35_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_35_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_35_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_35_compare_rhs$165 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rst_l_q_rst - cell \rst_l$122 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - connect \q_rst \rst_l_q_rst + process $group_0 + assign \core_calculate_stage_32_muxid 2'00 + assign \core_calculate_stage_32_muxid \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \lsd_l_s_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \lsd_l_r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \lsd_l_r_lsd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \lsd_l_q_lsd - cell \lsd_l \lsd_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_lsd \lsd_l_s_lsd - connect \r_lsd \lsd_l_r_lsd - connect \q_lsd \lsd_l_q_lsd + process $group_1 + assign \core_calculate_stage_32_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_32_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_32_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_32_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_32_logical_op__rc__rc 1'0 + assign \core_calculate_stage_32_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_32_logical_op__oe__oe 1'0 + assign \core_calculate_stage_32_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_32_logical_op__invert_in 1'0 + assign \core_calculate_stage_32_logical_op__zero_a 1'0 + assign \core_calculate_stage_32_logical_op__input_carry 2'00 + assign \core_calculate_stage_32_logical_op__invert_out 1'0 + assign \core_calculate_stage_32_logical_op__write_cr0 1'0 + assign \core_calculate_stage_32_logical_op__output_carry 1'0 + assign \core_calculate_stage_32_logical_op__is_32bit 1'0 + assign \core_calculate_stage_32_logical_op__is_signed 1'0 + assign \core_calculate_stage_32_logical_op__data_len 4'0000 + assign \core_calculate_stage_32_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_32_logical_op__insn \core_calculate_stage_32_logical_op__data_len \core_calculate_stage_32_logical_op__is_signed \core_calculate_stage_32_logical_op__is_32bit \core_calculate_stage_32_logical_op__output_carry \core_calculate_stage_32_logical_op__write_cr0 \core_calculate_stage_32_logical_op__invert_out \core_calculate_stage_32_logical_op__input_carry \core_calculate_stage_32_logical_op__zero_a \core_calculate_stage_32_logical_op__invert_in { \core_calculate_stage_32_logical_op__oe__oe_ok \core_calculate_stage_32_logical_op__oe__oe } { \core_calculate_stage_32_logical_op__rc__rc_ok \core_calculate_stage_32_logical_op__rc__rc } { \core_calculate_stage_32_logical_op__imm_data__imm_ok \core_calculate_stage_32_logical_op__imm_data__imm } \core_calculate_stage_32_logical_op__fn_unit \core_calculate_stage_32_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" - wire width 1 \reset_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" - cell $or $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $1 + process $group_19 + assign \core_calculate_stage_32_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_32_ra \ra + sync init end - process $group_0 - assign \reset_i 1'0 - assign \reset_i $1 + process $group_20 + assign \core_calculate_stage_32_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_32_rb \rb sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:285" - wire width 1 \reset_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" - wire width 1 \wr_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" - cell $or $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_reset - connect \B \cu_go_die_i - connect \Y $3 + process $group_21 + assign \core_calculate_stage_32_xer_so 1'0 + assign \core_calculate_stage_32_xer_so \xer_so + sync init end - process $group_1 - assign \reset_o 1'0 - assign \reset_o $3 + process $group_22 + assign \core_calculate_stage_32_divisor_neg 1'0 + assign \core_calculate_stage_32_divisor_neg \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286" - wire width 1 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_go_die_i - connect \Y $5 + process $group_23 + assign \core_calculate_stage_32_dividend_neg 1'0 + assign \core_calculate_stage_32_dividend_neg \dividend_neg + sync init end - process $group_2 - assign \reset_w 1'0 - assign \reset_w $5 + process $group_24 + assign \core_calculate_stage_32_dive_abs_ov32 1'0 + assign \core_calculate_stage_32_dive_abs_ov32 \dive_abs_ov32 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" - wire width 1 \reset_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_go_die_i - connect \Y $7 + process $group_25 + assign \core_calculate_stage_32_dive_abs_ov64 1'0 + assign \core_calculate_stage_32_dive_abs_ov64 \dive_abs_ov64 + sync init end - process $group_3 - assign \reset_u 1'0 - assign \reset_u $7 + process $group_26 + assign \core_calculate_stage_32_div_by_zero 1'0 + assign \core_calculate_stage_32_div_by_zero \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" - wire width 1 \reset_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__go_i - connect \B \cu_go_die_i - connect \Y $9 + process $group_27 + assign \core_calculate_stage_32_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_32_divisor_radicand \divisor_radicand + sync init end - process $group_4 - assign \reset_s 1'0 - assign \reset_s $9 + process $group_28 + assign \core_calculate_stage_32_operation 2'00 + assign \core_calculate_stage_32_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $11 + process $group_29 + assign \core_calculate_stage_32_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_32_quotient_root \quotient_root + sync init end - process $group_5 - assign \reset_r 3'000 - assign \reset_r $11 + process $group_30 + assign \core_calculate_stage_32_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_32_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" - wire width 1 \reset_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_ad__go_i - connect \B \cu_go_die_i - connect \Y $13 + process $group_31 + assign \core_calculate_stage_32_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_32_compare_lhs \compare_lhs + sync init end - process $group_6 - assign \reset_a 1'0 - assign \reset_a $13 + process $group_32 + assign \core_calculate_stage_32_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_32_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - wire width 1 \p_st_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - wire width 1 \p_st_go$next - process $group_7 - assign \p_st_go$next \p_st_go - assign \p_st_go$next \cu_st__go_i + process $group_33 + assign \core_calculate_stage_33_muxid 2'00 + assign \core_calculate_stage_33_muxid \core_calculate_stage_32_muxid$34 sync init - update \p_st_go 1'0 - sync posedge \coresync_clk - update \p_st_go \p_st_go$next end - process $group_8 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end + process $group_34 + assign \core_calculate_stage_33_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_33_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_33_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_33_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_33_logical_op__rc__rc 1'0 + assign \core_calculate_stage_33_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_33_logical_op__oe__oe 1'0 + assign \core_calculate_stage_33_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_33_logical_op__invert_in 1'0 + assign \core_calculate_stage_33_logical_op__zero_a 1'0 + assign \core_calculate_stage_33_logical_op__input_carry 2'00 + assign \core_calculate_stage_33_logical_op__invert_out 1'0 + assign \core_calculate_stage_33_logical_op__write_cr0 1'0 + assign \core_calculate_stage_33_logical_op__output_carry 1'0 + assign \core_calculate_stage_33_logical_op__is_32bit 1'0 + assign \core_calculate_stage_33_logical_op__is_signed 1'0 + assign \core_calculate_stage_33_logical_op__data_len 4'0000 + assign \core_calculate_stage_33_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_33_logical_op__insn \core_calculate_stage_33_logical_op__data_len \core_calculate_stage_33_logical_op__is_signed \core_calculate_stage_33_logical_op__is_32bit \core_calculate_stage_33_logical_op__output_carry \core_calculate_stage_33_logical_op__write_cr0 \core_calculate_stage_33_logical_op__invert_out \core_calculate_stage_33_logical_op__input_carry \core_calculate_stage_33_logical_op__zero_a \core_calculate_stage_33_logical_op__invert_in { \core_calculate_stage_33_logical_op__oe__oe_ok \core_calculate_stage_33_logical_op__oe__oe } { \core_calculate_stage_33_logical_op__rc__rc_ok \core_calculate_stage_33_logical_op__rc__rc } { \core_calculate_stage_33_logical_op__imm_data__imm_ok \core_calculate_stage_33_logical_op__imm_data__imm } \core_calculate_stage_33_logical_op__fn_unit \core_calculate_stage_33_logical_op__insn_type } { \core_calculate_stage_32_logical_op__insn$52 \core_calculate_stage_32_logical_op__data_len$51 \core_calculate_stage_32_logical_op__is_signed$50 \core_calculate_stage_32_logical_op__is_32bit$49 \core_calculate_stage_32_logical_op__output_carry$48 \core_calculate_stage_32_logical_op__write_cr0$47 \core_calculate_stage_32_logical_op__invert_out$46 \core_calculate_stage_32_logical_op__input_carry$45 \core_calculate_stage_32_logical_op__zero_a$44 \core_calculate_stage_32_logical_op__invert_in$43 { \core_calculate_stage_32_logical_op__oe__oe_ok$42 \core_calculate_stage_32_logical_op__oe__oe$41 } { \core_calculate_stage_32_logical_op__rc__rc_ok$40 \core_calculate_stage_32_logical_op__rc__rc$39 } { \core_calculate_stage_32_logical_op__imm_data__imm_ok$38 \core_calculate_stage_32_logical_op__imm_data__imm$37 } \core_calculate_stage_32_logical_op__fn_unit$36 \core_calculate_stage_32_logical_op__insn_type$35 } sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next end - process $group_9 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \reset_o - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end + process $group_52 + assign \core_calculate_stage_33_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_33_ra \core_calculate_stage_32_ra$53 sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next end - process $group_10 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 3'000 - end + process $group_53 + assign \core_calculate_stage_33_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_33_rb \core_calculate_stage_32_rb$54 sync init - update \src_l_s_src 3'000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next end - process $group_11 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 3'111 - end + process $group_54 + assign \core_calculate_stage_33_xer_so 1'0 + assign \core_calculate_stage_33_xer_so \core_calculate_stage_32_xer_so$55 sync init - update \src_l_r_src 3'111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next end - process $group_12 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \reset_i + process $group_55 + assign \core_calculate_stage_33_divisor_neg 1'0 + assign \core_calculate_stage_33_divisor_neg \core_calculate_stage_32_divisor_neg$56 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269" - wire width 1 \alu_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269" - wire width 1 \alu_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:268" - wire width 1 \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331" - cell $not $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \Y $15 + process $group_56 + assign \core_calculate_stage_33_dividend_neg 1'0 + assign \core_calculate_stage_33_dividend_neg \core_calculate_stage_32_dividend_neg$57 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331" - cell $and $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_ok - connect \B $15 - connect \Y $17 + process $group_57 + assign \core_calculate_stage_33_dive_abs_ov32 1'0 + assign \core_calculate_stage_33_dive_abs_ov32 \core_calculate_stage_32_dive_abs_ov32$58 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" - wire width 1 \rda_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rda_any - connect \Y $19 + process $group_58 + assign \core_calculate_stage_33_dive_abs_ov64 1'0 + assign \core_calculate_stage_33_dive_abs_ov64 \core_calculate_stage_32_dive_abs_ov64$59 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $17 - connect \B $19 - connect \Y $21 + process $group_59 + assign \core_calculate_stage_33_div_by_zero 1'0 + assign \core_calculate_stage_33_div_by_zero \core_calculate_stage_32_div_by_zero$60 + sync init end - process $group_13 - assign \alu_l_r_alu 1'1 - assign \alu_l_r_alu $21 + process $group_60 + assign \core_calculate_stage_33_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_33_divisor_radicand \core_calculate_stage_32_divisor_radicand$61 sync init end - process $group_14 - assign \adr_l_s_adr 1'0 - assign \adr_l_s_adr \reset_i + process $group_61 + assign \core_calculate_stage_33_operation 2'00 + assign \core_calculate_stage_33_operation \core_calculate_stage_32_operation$62 sync init end - process $group_15 - assign \adr_l_r_adr$next \adr_l_r_adr - assign \adr_l_r_adr$next \reset_a - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \adr_l_r_adr$next 1'1 - end + process $group_62 + assign \core_calculate_stage_33_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_33_quotient_root \core_calculate_stage_32_quotient_root$63 sync init - update \adr_l_r_adr 1'1 - sync posedge \coresync_clk - update \adr_l_r_adr \adr_l_r_adr$next end - process $group_16 - assign \lod_l_s_lod 1'0 - assign \lod_l_s_lod \reset_i + process $group_63 + assign \core_calculate_stage_33_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_33_root_times_radicand \core_calculate_stage_32_root_times_radicand$64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" - wire width 1 \ld_ok - process $group_17 - assign \lod_l_r_lod 1'1 - assign \lod_l_r_lod \ld_ok + process $group_64 + assign \core_calculate_stage_33_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_33_compare_lhs \core_calculate_stage_32_compare_lhs$65 sync init end - process $group_18 - assign \wri_l_s_wri 1'0 - assign \wri_l_s_wri \cu_issue_i + process $group_65 + assign \core_calculate_stage_33_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_33_compare_rhs \core_calculate_stage_32_compare_rhs$66 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - wire width 2 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - wire width 2 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $or $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reset_w - connect \B { \cu_done_o \cu_done_o } - connect \Y $24 + process $group_66 + assign \core_calculate_stage_34_muxid 2'00 + assign \core_calculate_stage_34_muxid \core_calculate_stage_33_muxid$67 + sync init end - connect $23 $24 - process $group_19 - assign \wri_l_r_wri$next \wri_l_r_wri - assign \wri_l_r_wri$next $23 [0] - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wri_l_r_wri$next 1'1 - end + process $group_67 + assign \core_calculate_stage_34_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_34_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_34_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_34_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_34_logical_op__rc__rc 1'0 + assign \core_calculate_stage_34_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_34_logical_op__oe__oe 1'0 + assign \core_calculate_stage_34_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_34_logical_op__invert_in 1'0 + assign \core_calculate_stage_34_logical_op__zero_a 1'0 + assign \core_calculate_stage_34_logical_op__input_carry 2'00 + assign \core_calculate_stage_34_logical_op__invert_out 1'0 + assign \core_calculate_stage_34_logical_op__write_cr0 1'0 + assign \core_calculate_stage_34_logical_op__output_carry 1'0 + assign \core_calculate_stage_34_logical_op__is_32bit 1'0 + assign \core_calculate_stage_34_logical_op__is_signed 1'0 + assign \core_calculate_stage_34_logical_op__data_len 4'0000 + assign \core_calculate_stage_34_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_34_logical_op__insn \core_calculate_stage_34_logical_op__data_len \core_calculate_stage_34_logical_op__is_signed \core_calculate_stage_34_logical_op__is_32bit \core_calculate_stage_34_logical_op__output_carry \core_calculate_stage_34_logical_op__write_cr0 \core_calculate_stage_34_logical_op__invert_out \core_calculate_stage_34_logical_op__input_carry \core_calculate_stage_34_logical_op__zero_a \core_calculate_stage_34_logical_op__invert_in { \core_calculate_stage_34_logical_op__oe__oe_ok \core_calculate_stage_34_logical_op__oe__oe } { \core_calculate_stage_34_logical_op__rc__rc_ok \core_calculate_stage_34_logical_op__rc__rc } { \core_calculate_stage_34_logical_op__imm_data__imm_ok \core_calculate_stage_34_logical_op__imm_data__imm } \core_calculate_stage_34_logical_op__fn_unit \core_calculate_stage_34_logical_op__insn_type } { \core_calculate_stage_33_logical_op__insn$85 \core_calculate_stage_33_logical_op__data_len$84 \core_calculate_stage_33_logical_op__is_signed$83 \core_calculate_stage_33_logical_op__is_32bit$82 \core_calculate_stage_33_logical_op__output_carry$81 \core_calculate_stage_33_logical_op__write_cr0$80 \core_calculate_stage_33_logical_op__invert_out$79 \core_calculate_stage_33_logical_op__input_carry$78 \core_calculate_stage_33_logical_op__zero_a$77 \core_calculate_stage_33_logical_op__invert_in$76 { \core_calculate_stage_33_logical_op__oe__oe_ok$75 \core_calculate_stage_33_logical_op__oe__oe$74 } { \core_calculate_stage_33_logical_op__rc__rc_ok$73 \core_calculate_stage_33_logical_op__rc__rc$72 } { \core_calculate_stage_33_logical_op__imm_data__imm_ok$71 \core_calculate_stage_33_logical_op__imm_data__imm$70 } \core_calculate_stage_33_logical_op__fn_unit$69 \core_calculate_stage_33_logical_op__insn_type$68 } sync init - update \wri_l_r_wri 1'1 - sync posedge \coresync_clk - update \wri_l_r_wri \wri_l_r_wri$next end - process $group_20 - assign \upd_l_s_upd$next \upd_l_s_upd - assign \upd_l_s_upd$next \reset_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \upd_l_s_upd$next 1'0 - end + process $group_85 + assign \core_calculate_stage_34_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_34_ra \core_calculate_stage_33_ra$86 sync init - update \upd_l_s_upd 1'0 - sync posedge \coresync_clk - update \upd_l_s_upd \upd_l_s_upd$next end - process $group_21 - assign \upd_l_r_upd$next \upd_l_r_upd - assign \upd_l_r_upd$next \reset_u - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \upd_l_r_upd$next 1'1 - end + process $group_86 + assign \core_calculate_stage_34_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_34_rb \core_calculate_stage_33_rb$87 sync init - update \upd_l_r_upd 1'1 - sync posedge \coresync_clk - update \upd_l_r_upd \upd_l_r_upd$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" - wire width 1 \addr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:265" - wire width 1 \op_is_st - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_ok - connect \B \op_is_st - connect \Y $26 + process $group_87 + assign \core_calculate_stage_34_xer_so 1'0 + assign \core_calculate_stage_34_xer_so \core_calculate_stage_33_xer_so$88 + sync init end - process $group_22 - assign \sto_l_s_sto 1'0 - assign \sto_l_s_sto $26 + process $group_88 + assign \core_calculate_stage_34_divisor_neg 1'0 + assign \core_calculate_stage_34_divisor_neg \core_calculate_stage_33_divisor_neg$89 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:351" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:351" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \reset_s - connect \B \p_st_go - connect \Y $28 + process $group_89 + assign \core_calculate_stage_34_dividend_neg 1'0 + assign \core_calculate_stage_34_dividend_neg \core_calculate_stage_33_dividend_neg$90 + sync init end - process $group_23 - assign \sto_l_r_sto$next \sto_l_r_sto - assign \sto_l_r_sto$next $28 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \sto_l_r_sto$next 1'1 - end + process $group_90 + assign \core_calculate_stage_34_dive_abs_ov32 1'0 + assign \core_calculate_stage_34_dive_abs_ov32 \core_calculate_stage_33_dive_abs_ov32$91 sync init - update \sto_l_r_sto 1'1 - sync posedge \coresync_clk - update \sto_l_r_sto \sto_l_r_sto$next end - process $group_24 - assign \lsd_l_s_lsd 1'0 - assign \lsd_l_s_lsd \cu_issue_i + process $group_91 + assign \core_calculate_stage_34_dive_abs_ov64 1'0 + assign \core_calculate_stage_34_dive_abs_ov64 \core_calculate_stage_33_dive_abs_ov64$92 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355" - cell $or $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \reset_s - connect \B \p_st_go - connect \Y $30 + process $group_92 + assign \core_calculate_stage_34_div_by_zero 1'0 + assign \core_calculate_stage_34_div_by_zero \core_calculate_stage_33_div_by_zero$93 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355" - cell $or $33 + process $group_93 + assign \core_calculate_stage_34_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_34_divisor_radicand \core_calculate_stage_33_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_34_operation 2'00 + assign \core_calculate_stage_34_operation \core_calculate_stage_33_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_34_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_34_quotient_root \core_calculate_stage_33_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_34_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_34_root_times_radicand \core_calculate_stage_33_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_34_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_34_compare_lhs \core_calculate_stage_33_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_34_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_34_compare_rhs \core_calculate_stage_33_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_35_muxid 2'00 + assign \core_calculate_stage_35_muxid \core_calculate_stage_34_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_35_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_35_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_35_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_35_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_35_logical_op__rc__rc 1'0 + assign \core_calculate_stage_35_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_35_logical_op__oe__oe 1'0 + assign \core_calculate_stage_35_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_35_logical_op__invert_in 1'0 + assign \core_calculate_stage_35_logical_op__zero_a 1'0 + assign \core_calculate_stage_35_logical_op__input_carry 2'00 + assign \core_calculate_stage_35_logical_op__invert_out 1'0 + assign \core_calculate_stage_35_logical_op__write_cr0 1'0 + assign \core_calculate_stage_35_logical_op__output_carry 1'0 + assign \core_calculate_stage_35_logical_op__is_32bit 1'0 + assign \core_calculate_stage_35_logical_op__is_signed 1'0 + assign \core_calculate_stage_35_logical_op__data_len 4'0000 + assign \core_calculate_stage_35_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_35_logical_op__insn \core_calculate_stage_35_logical_op__data_len \core_calculate_stage_35_logical_op__is_signed \core_calculate_stage_35_logical_op__is_32bit \core_calculate_stage_35_logical_op__output_carry \core_calculate_stage_35_logical_op__write_cr0 \core_calculate_stage_35_logical_op__invert_out \core_calculate_stage_35_logical_op__input_carry \core_calculate_stage_35_logical_op__zero_a \core_calculate_stage_35_logical_op__invert_in { \core_calculate_stage_35_logical_op__oe__oe_ok \core_calculate_stage_35_logical_op__oe__oe } { \core_calculate_stage_35_logical_op__rc__rc_ok \core_calculate_stage_35_logical_op__rc__rc } { \core_calculate_stage_35_logical_op__imm_data__imm_ok \core_calculate_stage_35_logical_op__imm_data__imm } \core_calculate_stage_35_logical_op__fn_unit \core_calculate_stage_35_logical_op__insn_type } { \core_calculate_stage_34_logical_op__insn$118 \core_calculate_stage_34_logical_op__data_len$117 \core_calculate_stage_34_logical_op__is_signed$116 \core_calculate_stage_34_logical_op__is_32bit$115 \core_calculate_stage_34_logical_op__output_carry$114 \core_calculate_stage_34_logical_op__write_cr0$113 \core_calculate_stage_34_logical_op__invert_out$112 \core_calculate_stage_34_logical_op__input_carry$111 \core_calculate_stage_34_logical_op__zero_a$110 \core_calculate_stage_34_logical_op__invert_in$109 { \core_calculate_stage_34_logical_op__oe__oe_ok$108 \core_calculate_stage_34_logical_op__oe__oe$107 } { \core_calculate_stage_34_logical_op__rc__rc_ok$106 \core_calculate_stage_34_logical_op__rc__rc$105 } { \core_calculate_stage_34_logical_op__imm_data__imm_ok$104 \core_calculate_stage_34_logical_op__imm_data__imm$103 } \core_calculate_stage_34_logical_op__fn_unit$102 \core_calculate_stage_34_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_35_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_35_ra \core_calculate_stage_34_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_35_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_35_rb \core_calculate_stage_34_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_35_xer_so 1'0 + assign \core_calculate_stage_35_xer_so \core_calculate_stage_34_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_35_divisor_neg 1'0 + assign \core_calculate_stage_35_divisor_neg \core_calculate_stage_34_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_35_dividend_neg 1'0 + assign \core_calculate_stage_35_dividend_neg \core_calculate_stage_34_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_35_dive_abs_ov32 1'0 + assign \core_calculate_stage_35_dive_abs_ov32 \core_calculate_stage_34_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_35_dive_abs_ov64 1'0 + assign \core_calculate_stage_35_dive_abs_ov64 \core_calculate_stage_34_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_35_div_by_zero 1'0 + assign \core_calculate_stage_35_div_by_zero \core_calculate_stage_34_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_35_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_35_divisor_radicand \core_calculate_stage_34_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_35_operation 2'00 + assign \core_calculate_stage_35_operation \core_calculate_stage_34_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_35_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_35_quotient_root \core_calculate_stage_34_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_35_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_35_root_times_radicand \core_calculate_stage_34_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_35_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_35_compare_lhs \core_calculate_stage_34_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_35_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_35_compare_rhs \core_calculate_stage_34_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $30 - connect \B \ld_ok - connect \Y $32 - end - process $group_25 - assign \lsd_l_r_lsd$next \lsd_l_r_lsd - assign \lsd_l_r_lsd$next $32 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \lsd_l_r_lsd$next 1'1 - end - sync init - update \lsd_l_r_lsd 1'1 - sync posedge \coresync_clk - update \lsd_l_r_lsd \lsd_l_r_lsd$next + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 end - process $group_26 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \addr_ok + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 sync init end - process $group_27 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_35_muxid$133 sync init end attribute \enum_base_type "MicrOp" @@ -121862,1398 +115152,1185 @@ module \ldst0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__imm + wire width 11 \logical_op__fn_unit$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__imm_ok + wire width 64 \logical_op__imm_data__imm$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__zero_a + wire width 1 \logical_op__imm_data__imm_ok$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc + wire width 1 \logical_op__rc__rc$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc_ok + wire width 1 \logical_op__rc__rc_ok$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe + wire width 1 \logical_op__oe__oe$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe_ok + wire width 1 \logical_op__oe__oe_ok$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit + wire width 1 \logical_op__invert_in$178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_signed + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len + wire width 2 \logical_op__input_carry$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__byte_reverse + wire width 1 \logical_op__invert_out$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__sign_extend - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" + wire width 1 \logical_op__write_cr0$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__ldst_mode - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 7 \oper_l__insn_type$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__data_len$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__byte_reverse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__byte_reverse$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__sign_extend - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__sign_extend$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__ldst_mode - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__ldst_mode$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 87 $34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $35 - parameter \WIDTH 87 - connect \A { \oper_l__ldst_mode \oper_l__sign_extend \oper_l__byte_reverse \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__zero_a { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn_type } - connect \B { \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm } \oper_i_ldst_ldst0__insn_type } - connect \S \cu_issue_i - connect \Y $34 - end - process $group_28 - assign \oper_r__insn_type 7'0000000 - assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__imm_data__imm_ok 1'0 - assign \oper_r__zero_a 1'0 - assign \oper_r__rc__rc 1'0 - assign \oper_r__rc__rc_ok 1'0 - assign \oper_r__oe__oe 1'0 - assign \oper_r__oe__oe_ok 1'0 - assign \oper_r__is_32bit 1'0 - assign \oper_r__is_signed 1'0 - assign \oper_r__data_len 4'0000 - assign \oper_r__byte_reverse 1'0 - assign \oper_r__sign_extend 1'0 - assign \oper_r__ldst_mode 2'00 - assign { \oper_r__ldst_mode \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } $34 + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_35_logical_op__insn$151 \core_calculate_stage_35_logical_op__data_len$150 \core_calculate_stage_35_logical_op__is_signed$149 \core_calculate_stage_35_logical_op__is_32bit$148 \core_calculate_stage_35_logical_op__output_carry$147 \core_calculate_stage_35_logical_op__write_cr0$146 \core_calculate_stage_35_logical_op__invert_out$145 \core_calculate_stage_35_logical_op__input_carry$144 \core_calculate_stage_35_logical_op__zero_a$143 \core_calculate_stage_35_logical_op__invert_in$142 { \core_calculate_stage_35_logical_op__oe__oe_ok$141 \core_calculate_stage_35_logical_op__oe__oe$140 } { \core_calculate_stage_35_logical_op__rc__rc_ok$139 \core_calculate_stage_35_logical_op__rc__rc$138 } { \core_calculate_stage_35_logical_op__imm_data__imm_ok$137 \core_calculate_stage_35_logical_op__imm_data__imm$136 } \core_calculate_stage_35_logical_op__fn_unit$135 \core_calculate_stage_35_logical_op__insn_type$134 } sync init end - process $group_42 - assign \oper_l__insn_type$next \oper_l__insn_type - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__zero_a$next \oper_l__zero_a - assign \oper_l__rc__rc$next \oper_l__rc__rc - assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok - assign \oper_l__oe__oe$next \oper_l__oe__oe - assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__data_len$next \oper_l__data_len - assign \oper_l__byte_reverse$next \oper_l__byte_reverse - assign \oper_l__sign_extend$next \oper_l__sign_extend - assign \oper_l__ldst_mode$next \oper_l__ldst_mode - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign { \oper_l__ldst_mode$next \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__zero_a$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn_type$next } { \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm } \oper_i_ldst_ldst0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - assign \oper_l__rc__rc$next 1'0 - assign \oper_l__rc__rc_ok$next 1'0 - assign \oper_l__oe__oe$next 1'0 - assign \oper_l__oe__oe_ok$next 1'0 - end - sync init - update \oper_l__insn_type 7'0000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__zero_a 1'0 - update \oper_l__rc__rc 1'0 - update \oper_l__rc__rc_ok 1'0 - update \oper_l__oe__oe 1'0 - update \oper_l__oe__oe_ok 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__data_len 4'0000 - update \oper_l__byte_reverse 1'0 - update \oper_l__sign_extend 1'0 - update \oper_l__ldst_mode 2'00 - sync posedge \coresync_clk - update \oper_l__insn_type \oper_l__insn_type$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__zero_a \oper_l__zero_a$next - update \oper_l__rc__rc \oper_l__rc__rc$next - update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next - update \oper_l__oe__oe \oper_l__oe__oe$next - update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__data_len \oper_l__data_len$next - update \oper_l__byte_reverse \oper_l__byte_reverse$next - update \oper_l__sign_extend \oper_l__sign_extend$next - update \oper_l__ldst_mode \oper_l__ldst_mode$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" - wire width 64 \ldd_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279" - wire width 64 \ldd_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ldo_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ldo_r$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $37 - parameter \WIDTH 64 - connect \A \ldo_r - connect \B \ldd_o - connect \S \ld_ok - connect \Y $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_35_ra$152 + sync init end - process $group_56 - assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ldd_r $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_35_rb$153 sync init end - process $group_57 - assign \ldo_r$next \ldo_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \ld_ok } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \ldo_r$next \ldd_o - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_35_xer_so$154 sync init - update \ldo_r 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ldo_r \ldo_r$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0_l$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $38 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $39 - parameter \WIDTH 64 - connect \A \src_r0_l - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_35_divisor_neg$155 + sync init end - process $group_58 - assign \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_r0 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_35_dividend_neg$156 sync init end - process $group_59 - assign \src_r0_l$next \src_r0_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0_l$next \src1_i - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_35_dive_abs_ov32$157 sync init - update \src_r0_l 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0_l \src_r0_l$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1_l$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $41 - parameter \WIDTH 64 - connect \A \src_r1_l - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_35_dive_abs_ov64$158 + sync init end - process $group_60 - assign \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_r1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_35_div_by_zero$159 sync init end - process $group_61 - assign \src_r1_l$next \src_r1_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1_l$next \src2_i - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_35_divisor_radicand$160 sync init - update \src_r1_l 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1_l \src_r1_l$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2_l$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $42 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $43 - parameter \WIDTH 64 - connect \A \src_r2_l - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $42 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_35_operation$161 + sync init end - process $group_62 - assign \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_r2 $42 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_35_quotient_root$162 sync init end - process $group_63 - assign \src_r2_l$next \src_r2_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2_l$next \src3_i - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_35_root_times_radicand$163 sync init - update \src_r2_l 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r2_l \src_r2_l$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" - wire width 64 \addr_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278" - wire width 64 \alu_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278" - wire width 64 \alu_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ea_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ea_r$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $45 - parameter \WIDTH 64 - connect \A \ea_r - connect \B \alu_o - connect \S \alu_l_q_alu - connect \Y $44 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_35_compare_lhs$164 + sync init end - process $group_64 - assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \addr_r $44 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_35_compare_rhs$165 sync init end - process $group_65 - assign \ea_r$next \ea_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \alu_l_q_alu } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst case 1'1 - assign \ea_r$next \alu_o + assign \r_busy$next 1'0 end sync init - update \ea_r 64'0000000000000000000000000000000000000000000000000000000000000000 + update \r_busy 1'0 sync posedge \coresync_clk - update \ea_r \ea_r$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:383" - wire width 64 \src1_or_z - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" - wire width 64 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" - cell $mux $47 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \oper_r__zero_a - connect \Y $46 + update \r_busy \r_busy$next end - process $group_66 - assign \src1_or_z 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_or_z $46 + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:388" - wire width 64 \src2_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:389" - wire width 64 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:389" - cell $mux $49 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \oper_r__imm_data__imm - connect \S \oper_r__imm_data__imm_ok - connect \Y $48 - end - process $group_67 - assign \src2_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_or_imm $48 + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - wire width 65 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - wire width 65 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - cell $add $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \src1_or_z - connect \B \src2_or_imm - connect \Y $51 - end - connect $50 $51 - process $group_68 - assign \alu_o$next \alu_o - assign \alu_o$next $50 [63:0] + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end sync init - update \alu_o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \alu_o \alu_o$next + update \ra$20 \ra$20$next end - process $group_69 - assign \alu_ok$next \alu_ok - assign \alu_ok$next \alu_valid + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end sync init - update \alu_ok 1'0 + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \coresync_clk - update \alu_ok \alu_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396" - cell $eq $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \oper_r__insn_type - connect \B 7'0100110 - connect \Y $53 + update \rb$21 \rb$21$next end - process $group_70 - assign \op_is_st 1'0 - assign \op_is_st $53 + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:264" - wire width 1 \op_is_ld - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:397" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:397" - cell $eq $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \oper_r__insn_type - connect \B 7'0100101 - connect \Y $55 - end - process $group_71 - assign \op_is_ld 1'0 - assign \op_is_ld $55 + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112" - wire width 1 \load_mem_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $and $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \op_is_ld - connect \B \cu_ad__go_i - connect \Y $57 + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next end - process $group_72 - assign \load_mem_o 1'0 - assign \load_mem_o $57 + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" - wire width 1 \stwd_mem_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401" - cell $and $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \op_is_st - connect \B \cu_st__go_i - connect \Y $59 + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next end - process $group_73 - assign \stwd_mem_o 1'0 - assign \stwd_mem_o $59 + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:108" - wire width 1 \ld_o - process $group_74 - assign \ld_o 1'0 - assign \ld_o \op_is_ld + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109" - wire width 1 \st_o - process $group_75 - assign \st_o 1'0 - assign \st_o \op_is_st + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next end - process $group_76 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - wire width 3 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - cell $and $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $61 + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - wire width 2 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - cell $not $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A { \oper_r__imm_data__imm_ok \oper_r__zero_a } - connect \Y $63 + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - wire width 3 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - cell $and $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A $61 - connect \B $63 - connect \Y $65 + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - cell $not $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $67 + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - wire width 3 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416" - cell $and $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $65 - connect \B $67 - connect \Y $69 + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425" - cell $and $72 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.p" +module \p$236 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src_l_q_src [2] - connect \B \cu_busy_o - connect \Y $71 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425" - cell $and $74 + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.n" +module \n$237 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $71 - connect \B \op_is_st - connect \Y $73 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 end - process $group_77 - assign \cu_rd__rel_o 3'000 - assign \cu_rd__rel_o $69 - assign \cu_rd__rel_o [2] $73 + process $group_0 + assign \trigger 1'0 + assign \trigger $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419" - cell $or $76 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_36.core.trial0" +module \trial0$239 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_rd__go_i [0] - connect \B \cu_rd__go_i [1] - connect \Y $75 - end - process $group_78 - assign \rda_any 1'0 - assign \rda_any $75 - sync init + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422" - wire width 1 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422" - cell $or $79 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_rd__rel_o [0] - connect \B \cu_rd__rel_o [1] - connect \Y $78 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422" - cell $not $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $78 - connect \Y $77 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422" - cell $and $82 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $77 - connect \Y $81 - end - process $group_79 - assign \alu_valid 1'0 - assign \alu_valid $81 - sync init + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" - wire width 1 \rd_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $84 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_rd__rel_o [2] - connect \Y $83 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011011 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $86 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \B $83 - connect \Y $85 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_80 - assign \rd_done 1'0 - assign \rd_done $85 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $and $88 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_36.core.trial1" +module \trial1$240 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \B \adr_l_q_adr - connect \Y $87 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $and $90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $87 - connect \B \cu_busy_o - connect \Y $89 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_81 - assign \cu_ad__rel_o 1'0 - assign \cu_ad__rel_o $89 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sto_l_q_sto - connect \B \cu_busy_o - connect \Y $91 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $91 - connect \B \rd_done - connect \Y $93 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011011 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $93 - connect \B \op_is_st - connect \Y $95 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:435" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:435" - cell $and $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $95 - connect \B \cu_shadown_i - connect \Y $97 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init end - process $group_82 - assign \cu_st__rel_o 1'0 - assign \cu_st__rel_o $97 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_36.core.pe" +module \pe$241 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $and $100 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd_done - connect \B \wri_l_q_wri - connect \Y $99 + connect \A \i + connect \B 1'0 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $and $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $99 - connect \B \cu_busy_o - connect \Y $101 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $and $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $101 - connect \B \lod_l_qn_lod - connect \Y $103 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_36.core" +module \core$238 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$239 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$240 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $and $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $103 - connect \B \op_is_ld - connect \Y $105 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$241 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $and $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $105 - connect \B \cu_shadown_i - connect \Y $107 + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \upd_l_q_upd - connect \B \cu_busy_o - connect \Y $109 + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" - cell $eq $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $111 + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $109 - connect \B $111 - connect \Y $113 + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $113 - connect \B \alu_valid - connect \Y $115 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $115 - connect \B \cu_shadown_i - connect \Y $117 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init end - process $group_83 - assign \cu_wr__rel_o 2'00 - assign \cu_wr__rel_o [0] $107 - assign \cu_wr__rel_o [1] $117 + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $or $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__go_i - connect \B \p_st_go - connect \Y $119 + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $or $122 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A $119 - connect \B \cu_wr__go_i [0] - connect \Y $121 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $or $124 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $121 - connect \B \cu_wr__go_i [1] - connect \Y $123 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - process $group_84 - assign \wr_any 1'0 - assign \wr_any $123 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rst_l_q_rst - connect \B \cu_busy_o - connect \Y $125 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $125 - connect \B \cu_shadown_i - connect \Y $127 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $or $131 + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o - connect \B \cu_wr__rel_o [0] - connect \Y $130 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $or $133 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $130 - connect \B \cu_wr__rel_o [1] - connect \Y $132 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $not $134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $132 - connect \Y $129 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $136 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $127 - connect \B $129 - connect \Y $135 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - wire width 1 $137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $or $138 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lod_l_qn_lod - connect \B \op_is_st - connect \Y $137 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - wire width 1 $139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $140 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $135 - connect \B $137 - connect \Y $139 - end - process $group_85 - assign \wr_reset 1'0 - assign \wr_reset $139 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_86 - assign \cu_done_o 1'0 - assign \cu_done_o \wr_reset + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \dest1_o - process $group_87 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o \dest1_o - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'11011 + connect \Y $30 end - process $group_88 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - switch { \cu_wr__go_i [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - case 1'1 - assign \dest1_o \ldd_r - end - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \dest2_o - process $group_89 - assign \ea 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ea \dest2_o + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" - wire width 1 $141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" - cell $eq $142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $141 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - wire width 1 $143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - cell $and $144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $141 - connect \B \cu_wr__go_i [1] - connect \Y $143 - end - process $group_90 - assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - switch { $143 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - case 1'1 - assign \dest2_o \addr_r - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 2 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" - wire width 3 $145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" - wire width 1 $146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398" - cell $eq $147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $146 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" - wire width 3 $148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469" - cell $and $149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \B { $146 \op_is_ld } - connect \Y $148 - end - connect $145 $148 - process $group_91 - assign \cu_wrmask_o 2'00 - assign \cu_wrmask_o $145 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" - wire width 1 $150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" - cell $and $151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \op_is_ld - connect \B \cu_busy_o - connect \Y $150 - end - process $group_92 - assign \ldst_port0_is_ld_i 1'0 - assign \ldst_port0_is_ld_i $150 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - wire width 1 $152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - cell $and $153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \op_is_st - connect \B \cu_busy_o - connect \Y $152 - end - process $group_93 - assign \ldst_port0_is_st_i 1'0 - assign \ldst_port0_is_st_i $152 - sync init - end - process $group_94 - assign \ldst_port0_data_len 4'0000 - assign \ldst_port0_data_len \oper_i_ldst_ldst0__data_len - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" - wire width 96 $154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" - cell $pos $155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 96 - connect \A \addr_r - connect \Y $154 - end - process $group_95 - assign \ldst_port0_addr_i 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \ldst_port0_addr_i $154 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" - wire width 1 $156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" - cell $and $157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_ok - connect \B \lsd_l_q_lsd - connect \Y $156 - end - process $group_96 - assign \ldst_port0_addr_i_ok 1'0 - assign \ldst_port0_addr_i_ok $156 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:106" - wire width 1 \addr_exc_o - process $group_97 - assign \addr_exc_o 1'0 - assign \addr_exc_o \ldst_port0_addr_exc_o - sync init - end - process $group_98 - assign \addr_ok 1'0 - assign \addr_ok \ldst_port0_addr_ok_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" - wire width 64 \lddata_r - process $group_99 - assign \lddata_r 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486" - switch { \oper_i_ldst_ldst0__byte_reverse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:12" - switch \oper_i_ldst_ldst0__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14" - case 4'0001 - assign \lddata_r [7:0] \ldst_port0_ld_data_o [7:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14" - case 4'0010 - assign \lddata_r [7:0] \ldst_port0_ld_data_o [15:8] - assign \lddata_r [15:8] \ldst_port0_ld_data_o [7:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14" - case 4'0100 - assign \lddata_r [7:0] \ldst_port0_ld_data_o [31:24] - assign \lddata_r [15:8] \ldst_port0_ld_data_o [23:16] - assign \lddata_r [23:16] \ldst_port0_ld_data_o [15:8] - assign \lddata_r [31:24] \ldst_port0_ld_data_o [7:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14" - case 4'1000 - assign \lddata_r [7:0] \ldst_port0_ld_data_o [63:56] - assign \lddata_r [15:8] \ldst_port0_ld_data_o [55:48] - assign \lddata_r [23:16] \ldst_port0_ld_data_o [47:40] - assign \lddata_r [31:24] \ldst_port0_ld_data_o [39:32] - assign \lddata_r [39:32] \ldst_port0_ld_data_o [31:24] - assign \lddata_r [47:40] \ldst_port0_ld_data_o [23:16] - assign \lddata_r [55:48] \ldst_port0_ld_data_o [15:8] - assign \lddata_r [63:56] \ldst_port0_ld_data_o [7:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:491" - case - end - sync init - end - process $group_100 - assign \ldd_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486" - switch { \oper_i_ldst_ldst0__byte_reverse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486" - case 1'1 - assign \ldd_o \lddata_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:491" - case - assign \ldd_o \ldst_port0_ld_data_o - end - sync init - end - process $group_101 - assign \ld_ok 1'0 - assign \ld_ok \ldst_port0_ld_data_o_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" - wire width 64 \stdata_r - process $group_102 - assign \stdata_r 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498" - switch { \oper_i_ldst_ldst0__byte_reverse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:12" - switch \oper_i_ldst_ldst0__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14" - case 4'0001 - assign \stdata_r [7:0] \src_r2 [7:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14" - case 4'0010 - assign \stdata_r [7:0] \src_r2 [15:8] - assign \stdata_r [15:8] \src_r2 [7:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14" - case 4'0100 - assign \stdata_r [7:0] \src_r2 [31:24] - assign \stdata_r [15:8] \src_r2 [23:16] - assign \stdata_r [23:16] \src_r2 [15:8] - assign \stdata_r [31:24] \src_r2 [7:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14" - case 4'1000 - assign \stdata_r [7:0] \src_r2 [63:56] - assign \stdata_r [15:8] \src_r2 [55:48] - assign \stdata_r [23:16] \src_r2 [47:40] - assign \stdata_r [31:24] \src_r2 [39:32] - assign \stdata_r [39:32] \src_r2 [31:24] - assign \stdata_r [47:40] \src_r2 [23:16] - assign \stdata_r [55:48] \src_r2 [15:8] - assign \stdata_r [63:56] \src_r2 [7:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:503" - case - end - sync init - end - process $group_103 - assign \ldst_port0_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498" - switch { \oper_i_ldst_ldst0__byte_reverse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498" - case 1'1 - assign \ldst_port0_st_data_i \stdata_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:503" - case - assign \ldst_port0_st_data_i \src_r2 - end - sync init - end - process $group_104 - assign \ldst_port0_st_data_i_ok 1'0 - assign \ldst_port0_st_data_i_ok \cu_st__go_i - sync init - end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus" -module \fus - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 1 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 input 2 \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 3 \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 input 4 \cu_st__go_i +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_36" +module \core_calculate_stage_36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -123328,7 +116405,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \oper_i_alu_alu0__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -123342,49 +116419,73 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \oper_i_alu_alu0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \oper_i_alu_alu0__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_alu0__imm_data__imm_ok + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \oper_i_alu_alu0__rc__rc + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \oper_i_alu_alu0__rc__rc_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \oper_i_alu_alu0__oe__oe + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_alu_alu0__oe__oe_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \oper_i_alu_alu0__invert_a + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_alu_alu0__zero_a + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \oper_i_alu_alu0__invert_out + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \oper_i_alu_alu0__write_cr0 + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 17 \oper_i_alu_alu0__input_carry + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \oper_i_alu_alu0__output_carry + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \oper_i_alu_alu0__is_32bit + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \oper_i_alu_alu0__is_signed + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \oper_i_alu_alu0__data_len + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \oper_i_alu_alu0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 23 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 24 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 4 input 25 \cu_rdmaskn_i + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -123459,7 +116560,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 26 \oper_i_alu_cr0__insn_type + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -123473,233 +116574,836 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 27 \oper_i_alu_cr0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 28 \oper_i_alu_cr0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 29 \oper_i_alu_cr0__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 30 \oper_i_alu_cr0__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 31 \cu_issue_i$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 32 \cu_busy_o$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 6 input 33 \cu_rdmaskn_i$3 + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 34 \oper_i_alu_branch0__cia - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 35 \oper_i_alu_branch0__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 36 \oper_i_alu_branch0__fn_unit + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 37 \oper_i_alu_branch0__insn + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 38 \oper_i_alu_branch0__imm_data__imm + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 39 \oper_i_alu_branch0__imm_data__imm_ok + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 40 \oper_i_alu_branch0__lk + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 41 \oper_i_alu_branch0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 42 \cu_issue_i$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 43 \cu_busy_o$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 input 44 \cu_rdmaskn_i$6 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 45 \oper_i_alu_trap0__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 46 \oper_i_alu_trap0__fn_unit + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 47 \oper_i_alu_trap0__insn + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 48 \oper_i_alu_trap0__msr + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 49 \oper_i_alu_trap0__cia + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 50 \oper_i_alu_trap0__is_32bit + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 input 51 \oper_i_alu_trap0__traptype + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 52 \oper_i_alu_trap0__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 53 \cu_issue_i$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 54 \cu_busy_o$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 4 input 55 \cu_rdmaskn_i$9 + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$238 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_37.core.trial0" +module \trial0$243 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011010 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_37.core.trial1" +module \trial1$244 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011010 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_37.core.pe" +module \pe$245 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_37.core" +module \core$242 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$243 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$244 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$245 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'11010 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_37" +module \core_calculate_stage_37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -123774,7 +117478,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 56 \oper_i_alu_logical0__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -123788,148 +117492,73 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 57 \oper_i_alu_logical0__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 58 \oper_i_alu_logical0__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 59 \oper_i_alu_logical0__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 60 \oper_i_alu_logical0__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 61 \oper_i_alu_logical0__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 62 \oper_i_alu_logical0__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 63 \oper_i_alu_logical0__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 64 \oper_i_alu_logical0__invert_a + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 65 \oper_i_alu_logical0__zero_a + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 66 \oper_i_alu_logical0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 67 \oper_i_alu_logical0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 68 \oper_i_alu_logical0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 69 \oper_i_alu_logical0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 70 \oper_i_alu_logical0__is_32bit + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 71 \oper_i_alu_logical0__is_signed + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 72 \oper_i_alu_logical0__data_len + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 73 \oper_i_alu_logical0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 74 \cu_issue_i$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 75 \cu_busy_o$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 2 input 76 \cu_rdmaskn_i$12 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 77 \oper_i_alu_spr0__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 78 \oper_i_alu_spr0__fn_unit + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 79 \oper_i_alu_spr0__insn + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 80 \oper_i_alu_spr0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 81 \cu_issue_i$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 82 \cu_busy_o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 6 input 83 \cu_rdmaskn_i$15 + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -124004,7 +117633,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 84 \oper_i_alu_div0__insn_type + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -124018,49 +117647,836 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 85 \oper_i_alu_div0__fn_unit + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 86 \oper_i_alu_div0__imm_data__imm + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 87 \oper_i_alu_div0__imm_data__imm_ok + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 88 \oper_i_alu_div0__rc__rc + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 89 \oper_i_alu_div0__rc__rc_ok + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 90 \oper_i_alu_div0__oe__oe + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 91 \oper_i_alu_div0__oe__oe_ok + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 92 \oper_i_alu_div0__invert_a + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 93 \oper_i_alu_div0__zero_a + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 94 \oper_i_alu_div0__input_carry + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 95 \oper_i_alu_div0__invert_out + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 96 \oper_i_alu_div0__write_cr0 + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 97 \oper_i_alu_div0__output_carry + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 98 \oper_i_alu_div0__is_32bit + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 99 \oper_i_alu_div0__is_signed + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 100 \oper_i_alu_div0__data_len + wire width 4 output 50 \logical_op__data_len$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 101 \oper_i_alu_div0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 102 \cu_issue_i$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 103 \cu_busy_o$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 input 104 \cu_rdmaskn_i$18 + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$242 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_38.core.trial0" +module \trial0$247 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011001 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_38.core.trial1" +module \trial1$248 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011001 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_38.core.pe" +module \pe$249 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_38.core" +module \core$246 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$247 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$248 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$249 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'11001 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_38" +module \core_calculate_stage_38 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -124135,7 +118551,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 105 \oper_i_alu_mul0__insn_type + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -124149,39 +118565,73 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 106 \oper_i_alu_mul0__fn_unit + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 107 \oper_i_alu_mul0__imm_data__imm + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 108 \oper_i_alu_mul0__imm_data__imm_ok + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 109 \oper_i_alu_mul0__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 110 \oper_i_alu_mul0__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 111 \oper_i_alu_mul0__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 112 \oper_i_alu_mul0__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 113 \oper_i_alu_mul0__invert_a + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 114 \oper_i_alu_mul0__zero_a + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 115 \oper_i_alu_mul0__invert_out + wire width 1 input 14 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 116 \oper_i_alu_mul0__write_cr0 + wire width 1 input 15 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 117 \oper_i_alu_mul0__is_32bit + wire width 1 input 16 \logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 118 \oper_i_alu_mul0__is_signed + wire width 4 input 17 \logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 119 \oper_i_alu_mul0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 120 \cu_issue_i$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 121 \cu_busy_o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 input 122 \cu_rdmaskn_i$21 + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -124256,7 +118706,7 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 123 \oper_i_alu_shift_rot0__insn_type + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -124270,43 +118720,836 @@ module \fus attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 124 \oper_i_alu_shift_rot0__fn_unit + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 125 \oper_i_alu_shift_rot0__imm_data__imm + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 126 \oper_i_alu_shift_rot0__imm_data__imm_ok + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 127 \oper_i_alu_shift_rot0__rc__rc + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 128 \oper_i_alu_shift_rot0__rc__rc_ok + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 129 \oper_i_alu_shift_rot0__oe__oe + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 130 \oper_i_alu_shift_rot0__oe__oe_ok + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 132 \oper_i_alu_shift_rot0__input_carry + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 133 \oper_i_alu_shift_rot0__output_carry + wire width 1 output 45 \logical_op__invert_out$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 134 \oper_i_alu_shift_rot0__input_cr + wire width 1 output 46 \logical_op__write_cr0$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 135 \oper_i_alu_shift_rot0__output_cr + wire width 1 output 47 \logical_op__output_carry$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 136 \oper_i_alu_shift_rot0__is_32bit + wire width 1 output 48 \logical_op__is_32bit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 137 \oper_i_alu_shift_rot0__is_signed + wire width 1 output 49 \logical_op__is_signed$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 138 \oper_i_alu_shift_rot0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 139 \cu_issue_i$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 140 \cu_busy_o$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 4 input 141 \cu_rdmaskn_i$24 + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$246 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_39.core.trial0" +module \trial0$251 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011000 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_39.core.trial1" +module \trial1$252 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1011000 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_39.core.pe" +module \pe$253 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_39.core" +module \core$250 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$251 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$252 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$253 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'11000 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9.core_calculate_stage_39" +module \core_calculate_stage_39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -124381,3326 +119624,4696 @@ module \fus attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 142 \oper_i_ldst_ldst0__insn_type + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 143 \oper_i_ldst_ldst0__imm_data__imm + wire width 11 input 2 \logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 144 \oper_i_ldst_ldst0__imm_data__imm_ok + wire width 64 input 3 \logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 145 \oper_i_ldst_ldst0__zero_a + wire width 1 input 4 \logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 146 \oper_i_ldst_ldst0__rc__rc + wire width 1 input 5 \logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 147 \oper_i_ldst_ldst0__rc__rc_ok + wire width 1 input 6 \logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 148 \oper_i_ldst_ldst0__oe__oe + wire width 1 input 7 \logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 149 \oper_i_ldst_ldst0__oe__oe_ok + wire width 1 input 8 \logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 150 \oper_i_ldst_ldst0__is_32bit + wire width 1 input 9 \logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 151 \oper_i_ldst_ldst0__is_signed + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 152 \oper_i_ldst_ldst0__data_len + wire width 2 input 11 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 153 \oper_i_ldst_ldst0__byte_reverse + wire width 1 input 12 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 154 \oper_i_ldst_ldst0__sign_extend - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" + wire width 1 input 13 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 155 \oper_i_ldst_ldst0__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 input 156 \cu_issue_i$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 output 157 \cu_busy_o$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 input 158 \cu_rdmaskn_i$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 159 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 160 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 161 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 162 \cu_rd__rel_o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 input 163 \cu_rd__go_i$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 164 \src2_i$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 165 \cu_rd__rel_o$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 166 \cu_rd__go_i$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 167 \src2_i$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 168 \cu_rd__rel_o$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 input 169 \cu_rd__go_i$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 170 \src2_i$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 171 \cu_rd__rel_o$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 172 \cu_rd__go_i$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 173 \src2_i$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 174 \cu_rd__rel_o$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 175 \cu_rd__go_i$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 176 \src2_i$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 177 \cu_rd__rel_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 178 \cu_rd__go_i$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 179 \src2_i$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 180 \cu_rd__rel_o$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 181 \cu_rd__go_i$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 182 \src2_i$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 183 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 184 \src3_i$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 185 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 186 \src1_i$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 187 \src1_i$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 188 \src1_i$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 189 \cu_rd__rel_o$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 input 190 \cu_rd__go_i$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 191 \src1_i$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 192 \src1_i$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 193 \src1_i$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 194 \src1_i$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 195 \src1_i$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 1 input 196 \src3_i$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 1 input 197 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 1 input 198 \src3_i$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 1 input 199 \src3_i$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 2 input 200 \src4_i$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 2 input 201 \src6_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 2 input 202 \src4_i$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 2 input 203 \src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 32 input 204 \src3_i$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 4 input 205 \src4_i$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 206 \cu_rd__rel_o$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 207 \cu_rd__go_i$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 4 input 208 \src3_i$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 4 input 209 \src5_i$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 4 input 210 \src6_i$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 211 \src1_i$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 212 \src3_i$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 213 \src3_i$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 214 \src2_i$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 input 215 \src4_i$76 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 224 \cu_wr__rel_o$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 input 225 \cu_wr__go_i$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 226 \o_ok$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 227 \cu_wr__rel_o$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 228 \cu_wr__go_i$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 229 \o_ok$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 230 \cu_wr__rel_o$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 input 231 \cu_wr__go_i$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 232 \o_ok$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 233 \cu_wr__rel_o$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 234 \cu_wr__go_i$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 235 \o_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 236 \cu_wr__rel_o$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 237 \cu_wr__go_i$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 238 \o_ok$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 239 \cu_wr__rel_o$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 240 \cu_wr__go_i$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 241 \cu_wr__rel_o$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 input 242 \cu_wr__go_i$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 243 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 244 \dest1_o$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 245 \dest1_o$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 246 \dest1_o$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 247 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\src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 256 \cr_a_ok$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 257 \cr_a_ok$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 258 \cr_a_ok$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 259 \cr_a_ok$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 260 \cr_a_ok$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 261 \dest2_o$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 262 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 263 \dest2_o$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 264 \dest2_o$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 265 \dest2_o$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 output 266 \dest2_o$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 267 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 268 \xer_ca_ok$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 269 \xer_ca_ok$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 270 \xer_ca_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 271 \dest3_o$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 272 \dest3_o$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 273 \dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 274 \dest3_o$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 275 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 276 \xer_ov_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 277 \xer_ov_ok$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 278 \xer_ov_ok$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 279 \dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 280 \dest5_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 281 \dest3_o$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 output 282 \dest3_o$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 283 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 284 \xer_so_ok$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 285 \xer_so_ok$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 286 \xer_so_ok$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 output 287 \dest5_o$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 output 288 \dest4_o$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 output 289 \dest4_o$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 output 290 \dest4_o$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 291 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 292 \cu_wr__rel_o$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 293 \cu_wr__go_i$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 294 \fast1_ok$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 295 \fast1_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 296 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 297 \fast2_ok$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 298 \dest1_o$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 299 \dest2_o$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 300 \dest3_o$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 301 \dest2_o$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 302 \dest3_o$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 303 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 304 \nia_ok$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 305 \dest3_o$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 306 \dest4_o$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 307 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 308 \dest5_o$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 309 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 output 310 \dest2_o$150 - attribute \src "simple/issuer.py:89" - wire width 1 input 311 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 312 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 313 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 314 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 output 315 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 316 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 input 317 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 input 318 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 319 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 320 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 321 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 322 \ldst_port0_st_data_i_ok - cell \alu0 \alu0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type - connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__imm \oper_i_alu_alu0__imm_data__imm - connect \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm_ok - connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc_ok - connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe_ok - connect \oper_i_alu_alu0__invert_a \oper_i_alu_alu0__invert_a - connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a - connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out - connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 - connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry - connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry - connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit - connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed - connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len - connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn - connect \cu_issue_i \cu_issue_i - connect \cu_busy_o \cu_busy_o - connect \cu_rdmaskn_i \cu_rdmaskn_i - connect \cu_rd__rel_o \cu_rd__rel_o - connect \cu_rd__go_i \cu_rd__go_i - connect \src2_i \src2_i - connect \src1_i \src1_i - connect \src3_i \src3_i$60 - connect \src4_i \src4_i$63 - connect \o_ok \o_ok - connect \cu_wr__rel_o \cu_wr__rel_o - connect \cu_wr__go_i \cu_wr__go_i - connect \dest1_o \dest1_o - connect \cr_a_ok \cr_a_ok - connect \dest2_o \dest2_o$113 - connect \xer_ca_ok \xer_ca_ok - connect \dest3_o \dest3_o$121 - connect \xer_ov_ok \xer_ov_ok - connect \dest4_o \dest4_o - connect \xer_so_ok \xer_so_ok - connect \dest5_o \dest5_o$132 - connect \coresync_rst \coresync_rst - end - cell \cr0 \cr0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type - connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit - connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn - connect \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__read_cr_whole - connect \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__write_cr_whole - connect \cu_issue_i \cu_issue_i$1 - connect \cu_busy_o \cu_busy_o$2 - connect \cu_rdmaskn_i \cu_rdmaskn_i$3 - connect \cu_rd__rel_o \cu_rd__rel_o$28 - connect \cu_rd__go_i \cu_rd__go_i$29 - connect \src2_i \src2_i$30 - connect \src1_i \src1_i$50 - connect \src3_i \src3_i$65 - connect \src4_i \src4_i$66 - connect \src5_i \src5_i$70 - connect \src6_i \src6_i$71 - connect \o_ok \o_ok$78 - connect \cu_wr__rel_o \cu_wr__rel_o$79 - connect \cu_wr__go_i \cu_wr__go_i$80 - connect \dest1_o \dest1_o$101 - connect \full_cr_ok \full_cr_ok - connect \dest2_o \dest2_o - connect \cr_a_ok \cr_a_ok$108 - connect \dest3_o \dest3_o - connect \coresync_rst \coresync_rst - end - cell \branch0 \branch0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia - connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type - connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit - connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__imm_data__imm \oper_i_alu_branch0__imm_data__imm - connect \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm_ok - connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk - connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit - connect \cu_issue_i \cu_issue_i$4 - connect \cu_busy_o \cu_busy_o$5 - connect \cu_rdmaskn_i \cu_rdmaskn_i$6 - connect \cu_rd__rel_o \cu_rd__rel_o$67 - connect \cu_rd__go_i \cu_rd__go_i$68 - connect \src3_i \src3_i$69 - connect \src1_i \src1_i$72 - connect \src2_i \src2_i$75 - connect \fast1_ok \fast1_ok - connect \cu_wr__rel_o \cu_wr__rel_o$136 - connect \cu_wr__go_i \cu_wr__go_i$137 - connect \fast2_ok \fast2_ok - connect \dest1_o \dest1_o$141 - connect \dest2_o \dest2_o$144 - connect \nia_ok \nia_ok - connect \dest3_o \dest3_o$147 - connect \coresync_rst \coresync_rst - end - cell \trap0 \trap0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type - connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit - connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn - connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr - connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia - connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit - connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype - connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr - connect \cu_issue_i \cu_issue_i$7 - connect \cu_busy_o \cu_busy_o$8 - connect \cu_rdmaskn_i \cu_rdmaskn_i$9 - connect \cu_rd__rel_o \cu_rd__rel_o$31 - connect \cu_rd__go_i \cu_rd__go_i$32 - connect \src2_i \src2_i$33 - connect \src1_i \src1_i$51 - connect \src3_i \src3_i$73 - connect \src4_i \src4_i$76 - connect \o_ok \o_ok$81 - connect \cu_wr__rel_o \cu_wr__rel_o$82 - connect \cu_wr__go_i \cu_wr__go_i$83 - connect \dest1_o \dest1_o$102 - connect \fast1_ok \fast1_ok$138 - connect \fast2_ok \fast2_ok$140 - connect \dest2_o \dest2_o$142 - connect \dest3_o \dest3_o$145 - connect \nia_ok \nia_ok$146 - connect \dest4_o \dest4_o$148 - connect \msr_ok \msr_ok - connect \dest5_o \dest5_o$149 - connect \coresync_rst \coresync_rst - end - cell \logical0 \logical0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type - connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__imm \oper_i_alu_logical0__imm_data__imm - connect \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm_ok - connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc_ok - connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe_ok - connect \oper_i_alu_logical0__invert_a \oper_i_alu_logical0__invert_a - connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a - connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry - connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out - connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 - connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry - connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit - connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed - connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len - connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn - connect \cu_issue_i \cu_issue_i$10 - connect \cu_busy_o \cu_busy_o$11 - connect \cu_rdmaskn_i \cu_rdmaskn_i$12 - connect \cu_rd__rel_o \cu_rd__rel_o$34 - connect \cu_rd__go_i \cu_rd__go_i$35 - connect \src2_i \src2_i$36 - connect \src1_i \src1_i$52 - connect \o_ok \o_ok$84 - connect \cu_wr__rel_o \cu_wr__rel_o$85 - connect \cu_wr__go_i \cu_wr__go_i$86 - connect \dest1_o \dest1_o$103 - connect \cr_a_ok \cr_a_ok$109 - connect \dest2_o \dest2_o$114 - connect \xer_ca_ok \xer_ca_ok$118 - connect \dest3_o \dest3_o$122 - connect \coresync_rst \coresync_rst - end - cell \spr0 \spr0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type - connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit - connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn - connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit - connect \cu_issue_i \cu_issue_i$13 - connect \cu_busy_o \cu_busy_o$14 - connect \cu_rdmaskn_i \cu_rdmaskn_i$15 - connect \cu_rd__rel_o \cu_rd__rel_o$53 - connect \cu_rd__go_i \cu_rd__go_i$54 - connect \src1_i \src1_i$55 - connect \src4_i \src4_i - connect \src6_i \src6_i - connect \src5_i \src5_i - connect \src3_i \src3_i$74 - connect \src2_i \src2_i$77 - connect \o_ok \o_ok$87 - connect \cu_wr__rel_o \cu_wr__rel_o$88 - connect \cu_wr__go_i \cu_wr__go_i$89 - connect \dest1_o \dest1_o$104 - connect \xer_ca_ok \xer_ca_ok$119 - connect \dest6_o \dest6_o - connect \xer_ov_ok \xer_ov_ok$124 - connect \dest5_o \dest5_o - connect \xer_so_ok \xer_so_ok$129 - connect \dest4_o \dest4_o$133 - connect \fast1_ok \fast1_ok$139 - connect \dest3_o \dest3_o$143 - connect \spr1_ok \spr1_ok - connect \dest2_o \dest2_o$150 - connect \coresync_rst \coresync_rst - end - cell \div0 \div0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type - connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__imm \oper_i_alu_div0__imm_data__imm - connect \oper_i_alu_div0__imm_data__imm_ok \oper_i_alu_div0__imm_data__imm_ok - connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__rc__rc_ok \oper_i_alu_div0__rc__rc_ok - connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__oe_ok \oper_i_alu_div0__oe__oe_ok - connect \oper_i_alu_div0__invert_a \oper_i_alu_div0__invert_a - connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a - connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry - connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out - connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 - connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry - connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit - connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed - connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len - connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn - connect \cu_issue_i \cu_issue_i$16 - connect \cu_busy_o \cu_busy_o$17 - connect \cu_rdmaskn_i \cu_rdmaskn_i$18 - connect \cu_rd__rel_o \cu_rd__rel_o$37 - connect \cu_rd__go_i \cu_rd__go_i$38 - connect \src2_i \src2_i$39 - connect \src1_i \src1_i$56 - connect \src3_i \src3_i$61 - connect \o_ok \o_ok$90 - connect \cu_wr__rel_o \cu_wr__rel_o$91 - connect \cu_wr__go_i \cu_wr__go_i$92 - connect \dest1_o \dest1_o$105 - connect \cr_a_ok \cr_a_ok$110 - connect \dest2_o \dest2_o$115 - connect \xer_ov_ok \xer_ov_ok$125 - connect \dest3_o \dest3_o$127 - connect \xer_so_ok \xer_so_ok$130 - connect \dest4_o \dest4_o$134 - connect \coresync_rst \coresync_rst - end - cell \mul0 \mul0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type - connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit - connect \oper_i_alu_mul0__imm_data__imm \oper_i_alu_mul0__imm_data__imm - connect \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm_ok - connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc - connect \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc_ok - connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe - connect \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe_ok - connect \oper_i_alu_mul0__invert_a \oper_i_alu_mul0__invert_a - connect \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__zero_a - connect \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__invert_out - connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 - connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit - connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed - connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn - connect \cu_issue_i \cu_issue_i$19 - connect \cu_busy_o \cu_busy_o$20 - connect \cu_rdmaskn_i \cu_rdmaskn_i$21 - connect \cu_rd__rel_o \cu_rd__rel_o$40 - connect \cu_rd__go_i \cu_rd__go_i$41 - connect \src2_i \src2_i$42 - connect \src1_i \src1_i$57 - connect \src3_i \src3_i$62 - connect \o_ok \o_ok$93 - connect \cu_wr__rel_o \cu_wr__rel_o$94 - connect \cu_wr__go_i \cu_wr__go_i$95 - connect \dest1_o \dest1_o$106 - connect \cr_a_ok \cr_a_ok$111 - connect \dest2_o \dest2_o$116 - connect \xer_ov_ok \xer_ov_ok$126 - connect \dest3_o \dest3_o$128 - connect \xer_so_ok \xer_so_ok$131 - connect \dest4_o \dest4_o$135 - connect \coresync_rst \coresync_rst - end - cell \shiftrot0 \shiftrot0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type - connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit - connect \oper_i_alu_shift_rot0__imm_data__imm \oper_i_alu_shift_rot0__imm_data__imm - connect \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm_ok - connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc - connect \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc_ok - connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe - connect \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe_ok - connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry - connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry - connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr - connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr - connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit - connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed - connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn - connect \cu_issue_i \cu_issue_i$22 - connect \cu_busy_o \cu_busy_o$23 - connect \cu_rdmaskn_i \cu_rdmaskn_i$24 - connect \cu_rd__rel_o \cu_rd__rel_o$43 - connect \cu_rd__go_i \cu_rd__go_i$44 - connect \src2_i \src2_i$45 - connect \src3_i \src3_i - connect \src1_i \src1_i$58 - connect \src4_i \src4_i$64 - connect \o_ok \o_ok$96 - connect \cu_wr__rel_o \cu_wr__rel_o$97 - connect \cu_wr__go_i \cu_wr__go_i$98 - connect \dest1_o \dest1_o$107 - connect \cr_a_ok \cr_a_ok$112 - connect \dest2_o \dest2_o$117 - connect \xer_ca_ok \xer_ca_ok$120 - connect \dest3_o \dest3_o$123 - connect \coresync_rst \coresync_rst - end - cell \ldst0 \ldst0 - connect \coresync_clk \coresync_clk - connect \cu_st__rel_o \cu_st__rel_o - connect \cu_ad__go_i \cu_ad__go_i - connect \cu_ad__rel_o \cu_ad__rel_o - connect \cu_st__go_i \cu_st__go_i - connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type - connect \oper_i_ldst_ldst0__imm_data__imm \oper_i_ldst_ldst0__imm_data__imm - connect \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm_ok - connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a - connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc - connect \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc_ok - connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe - connect \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe_ok - connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit - connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed - connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len - connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse - connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend - connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode - connect \cu_issue_i \cu_issue_i$25 - connect \cu_busy_o \cu_busy_o$26 - connect \cu_rdmaskn_i \cu_rdmaskn_i$27 - connect \cu_rd__rel_o \cu_rd__rel_o$46 - connect \cu_rd__go_i \cu_rd__go_i$47 - connect \src2_i \src2_i$48 - connect \src3_i \src3_i$49 - connect \src1_i \src1_i$59 - connect \cu_wr__rel_o \cu_wr__rel_o$99 - connect \cu_wr__go_i \cu_wr__go_i$100 - connect \o \o - connect \ea \ea - connect \coresync_rst \coresync_rst - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active" -module \st_active - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 2 \r_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_active - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_st_active - connect \Y $5 + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$250 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_active - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_st_active - connect \Y $11 end process $group_1 - assign \q_st_active 1'0 - assign \q_st_active $11 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_active - connect \Y $13 - end - process $group_2 - assign \qn_st_active 1'0 - assign \qn_st_active $13 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_active - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_st_active 1'0 - assign \qlq_st_active $15 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_done" -module \st_done - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_done - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_st_done - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_done - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_st_done - connect \Y $11 end - process $group_1 - assign \q_st_done 1'0 - assign \q_st_done $11 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_done - connect \Y $13 - end - process $group_2 - assign \qn_st_done 1'0 - assign \qn_st_done $13 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_done - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_st_done 1'0 - assign \qlq_st_done $15 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active" -module \ld_active - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 2 \r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_ld_active - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_ld_active - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_ld_active - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_ld_active - connect \Y $11 end - process $group_1 - assign \q_ld_active 1'0 - assign \q_ld_active $11 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_ld_active - connect \Y $13 - end - process $group_2 - assign \qn_ld_active 1'0 - assign \qn_ld_active $13 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_ld_active - connect \B \q_int - connect \Y $15 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - process $group_3 - assign \qlq_ld_active 1'0 - assign \qlq_ld_active $15 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l" -module \reset_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_reset - connect \Y $1 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_reset - connect \Y $5 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - process $group_1 - assign \q_reset 1'0 - assign \q_reset \q_int + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \Y $7 + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init end - process $group_2 - assign \qn_reset 1'0 - assign \qn_reset $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \B \q_int - connect \Y $9 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init end - process $group_3 - assign \qlq_reset 1'0 - assign \qlq_reset $9 + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l" -module \adrok_l - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_9" +module \pipe_middle_9 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 output 4 \qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 5 \q_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_addr_acked - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_addr_acked - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_addr_acked - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_addr_acked - connect \Y $11 - end - process $group_1 - assign \q_addr_acked 1'0 - assign \q_addr_acked $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_addr_acked - connect \Y $13 - end - process $group_2 - assign \qn_addr_acked 1'0 - assign \qn_addr_acked $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_addr_acked - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_addr_acked 1'0 - assign \qlq_addr_acked $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l" -module \busy_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_busy - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_busy - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_busy - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_busy - connect \Y $11 - end - process $group_1 - assign \q_busy 1'0 - assign \q_busy $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_busy - connect \Y $13 - end - process $group_2 - assign \qn_busy 1'0 - assign \qn_busy $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_busy - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_busy 1'0 - assign \qlq_busy $15 - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 41 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$236 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l" -module \cyc_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_cyc - connect \Y $1 + cell \n$237 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_36_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_36_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_36_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_36_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_36_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_36_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_36_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_36_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_36_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_36_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_36_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_36_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_36_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_36_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_36_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_36_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_36_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_36_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_36_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_36_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_36_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_36_muxid$34 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_36_logical_op__insn_type$35 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_36_logical_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_36_logical_op__imm_data__imm$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__imm_data__imm_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__invert_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_36_logical_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__write_cr0$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_36_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_36_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_36_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_36_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_36_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_36_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_36_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_36_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_36_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_36_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_36_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_36_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_36_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_36_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_36_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_36_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_36_compare_rhs$66 + cell \core_calculate_stage_36 \core_calculate_stage_36 + connect \muxid \core_calculate_stage_36_muxid + connect \logical_op__insn_type \core_calculate_stage_36_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_36_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_36_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_36_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_36_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_36_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_36_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_36_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_36_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_36_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_36_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_36_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_36_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_36_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_36_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_36_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_36_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_36_logical_op__insn + connect \ra \core_calculate_stage_36_ra + connect \rb \core_calculate_stage_36_rb + connect \xer_so \core_calculate_stage_36_xer_so + connect \divisor_neg \core_calculate_stage_36_divisor_neg + connect \dividend_neg \core_calculate_stage_36_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_36_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_36_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_36_div_by_zero + connect \divisor_radicand \core_calculate_stage_36_divisor_radicand + connect \operation \core_calculate_stage_36_operation + connect \quotient_root \core_calculate_stage_36_quotient_root + connect \root_times_radicand \core_calculate_stage_36_root_times_radicand + connect \compare_lhs \core_calculate_stage_36_compare_lhs + connect \compare_rhs \core_calculate_stage_36_compare_rhs + connect \muxid$1 \core_calculate_stage_36_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_36_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_36_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_36_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_36_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_36_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_36_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_36_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_36_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_36_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_36_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_36_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_36_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_36_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_36_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_36_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_36_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_36_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_36_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_36_ra$53 + connect \rb$21 \core_calculate_stage_36_rb$54 + connect \xer_so$22 \core_calculate_stage_36_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_36_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_36_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_36_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_36_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_36_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_36_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_36_operation$62 + connect \quotient_root$30 \core_calculate_stage_36_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_36_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_36_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_36_compare_rhs$66 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_cyc - connect \Y $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_37_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_37_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_37_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_37_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_37_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_37_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_37_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_37_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_37_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_37_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_37_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_37_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_37_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_37_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_37_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_37_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_37_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_37_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_37_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_37_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_37_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_37_muxid$67 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_37_logical_op__insn_type$68 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_37_logical_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_37_logical_op__imm_data__imm$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__imm_data__imm_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__rc__rc_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_37_logical_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__invert_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__write_cr0$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_37_logical_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_37_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_37_logical_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_37_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_37_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_37_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_37_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_37_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_37_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_37_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_37_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_37_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_37_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_37_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_37_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_37_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_37_compare_rhs$99 + cell \core_calculate_stage_37 \core_calculate_stage_37 + connect \muxid \core_calculate_stage_37_muxid + connect \logical_op__insn_type \core_calculate_stage_37_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_37_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_37_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_37_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_37_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_37_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_37_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_37_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_37_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_37_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_37_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_37_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_37_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_37_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_37_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_37_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_37_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_37_logical_op__insn + connect \ra \core_calculate_stage_37_ra + connect \rb \core_calculate_stage_37_rb + connect \xer_so \core_calculate_stage_37_xer_so + connect \divisor_neg \core_calculate_stage_37_divisor_neg + connect \dividend_neg \core_calculate_stage_37_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_37_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_37_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_37_div_by_zero + connect \divisor_radicand \core_calculate_stage_37_divisor_radicand + connect \operation \core_calculate_stage_37_operation + connect \quotient_root \core_calculate_stage_37_quotient_root + connect \root_times_radicand \core_calculate_stage_37_root_times_radicand + connect \compare_lhs \core_calculate_stage_37_compare_lhs + connect \compare_rhs \core_calculate_stage_37_compare_rhs + connect \muxid$1 \core_calculate_stage_37_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_37_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_37_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_37_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_37_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_37_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_37_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_37_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_37_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_37_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_37_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_37_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_37_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_37_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_37_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_37_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_37_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_37_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_37_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_37_ra$86 + connect \rb$21 \core_calculate_stage_37_rb$87 + connect \xer_so$22 \core_calculate_stage_37_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_37_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_37_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_37_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_37_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_37_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_37_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_37_operation$95 + connect \quotient_root$30 \core_calculate_stage_37_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_37_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_37_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_37_compare_rhs$99 end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_38_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_38_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_38_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_38_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_38_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_38_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_38_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_38_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_38_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_38_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_38_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_38_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_38_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_38_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_38_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_38_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_38_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_38_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_38_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_38_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_38_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_38_muxid$100 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_38_logical_op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_38_logical_op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_38_logical_op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__rc__rc$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__rc__rc_ok$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__oe__oe$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_38_logical_op__input_carry$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__invert_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__write_cr0$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__output_carry$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__is_32bit$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_38_logical_op__is_signed$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_38_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_38_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_38_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_38_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_38_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_38_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_38_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_38_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_38_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_38_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_38_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_38_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_38_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_38_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_38_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_38_compare_rhs$132 + cell \core_calculate_stage_38 \core_calculate_stage_38 + connect \muxid \core_calculate_stage_38_muxid + connect \logical_op__insn_type \core_calculate_stage_38_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_38_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_38_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_38_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_38_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_38_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_38_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_38_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_38_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_38_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_38_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_38_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_38_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_38_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_38_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_38_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_38_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_38_logical_op__insn + connect \ra \core_calculate_stage_38_ra + connect \rb \core_calculate_stage_38_rb + connect \xer_so \core_calculate_stage_38_xer_so + connect \divisor_neg \core_calculate_stage_38_divisor_neg + connect \dividend_neg \core_calculate_stage_38_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_38_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_38_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_38_div_by_zero + connect \divisor_radicand \core_calculate_stage_38_divisor_radicand + connect \operation \core_calculate_stage_38_operation + connect \quotient_root \core_calculate_stage_38_quotient_root + connect \root_times_radicand \core_calculate_stage_38_root_times_radicand + connect \compare_lhs \core_calculate_stage_38_compare_lhs + connect \compare_rhs \core_calculate_stage_38_compare_rhs + connect \muxid$1 \core_calculate_stage_38_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_38_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_38_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_38_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_38_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_38_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_38_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_38_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_38_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_38_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_38_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_38_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_38_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_38_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_38_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_38_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_38_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_38_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_38_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_38_ra$119 + connect \rb$21 \core_calculate_stage_38_rb$120 + connect \xer_so$22 \core_calculate_stage_38_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_38_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_38_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_38_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_38_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_38_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_38_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_38_operation$128 + connect \quotient_root$30 \core_calculate_stage_38_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_38_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_38_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_38_compare_rhs$132 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_39_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_39_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_39_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_39_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_39_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_39_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_39_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_39_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_39_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_39_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_39_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_39_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_39_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_39_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_39_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_39_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_39_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_39_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_39_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_39_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_39_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_39_muxid$133 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_39_logical_op__insn_type$134 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_39_logical_op__fn_unit$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_39_logical_op__imm_data__imm$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__imm_data__imm_ok$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__rc__rc$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__rc__rc_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__oe__oe$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__oe__oe_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__invert_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_39_logical_op__input_carry$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__invert_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__write_cr0$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__output_carry$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_39_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_39_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_39_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_39_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_39_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_39_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_39_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_39_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_39_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_39_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_39_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_39_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_39_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_39_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_39_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_39_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_39_compare_rhs$165 + cell \core_calculate_stage_39 \core_calculate_stage_39 + connect \muxid \core_calculate_stage_39_muxid + connect \logical_op__insn_type \core_calculate_stage_39_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_39_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_39_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_39_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_39_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_39_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_39_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_39_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_39_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_39_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_39_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_39_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_39_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_39_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_39_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_39_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_39_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_39_logical_op__insn + connect \ra \core_calculate_stage_39_ra + connect \rb \core_calculate_stage_39_rb + connect \xer_so \core_calculate_stage_39_xer_so + connect \divisor_neg \core_calculate_stage_39_divisor_neg + connect \dividend_neg \core_calculate_stage_39_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_39_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_39_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_39_div_by_zero + connect \divisor_radicand \core_calculate_stage_39_divisor_radicand + connect \operation \core_calculate_stage_39_operation + connect \quotient_root \core_calculate_stage_39_quotient_root + connect \root_times_radicand \core_calculate_stage_39_root_times_radicand + connect \compare_lhs \core_calculate_stage_39_compare_lhs + connect \compare_rhs \core_calculate_stage_39_compare_rhs + connect \muxid$1 \core_calculate_stage_39_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_39_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_39_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_39_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_39_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_39_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_39_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_39_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_39_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_39_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_39_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_39_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_39_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_39_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_39_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_39_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_39_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_39_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_39_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_39_ra$152 + connect \rb$21 \core_calculate_stage_39_rb$153 + connect \xer_so$22 \core_calculate_stage_39_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_39_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_39_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_39_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_39_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_39_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_39_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_39_operation$161 + connect \quotient_root$30 \core_calculate_stage_39_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_39_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_39_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_39_compare_rhs$165 + end + process $group_0 + assign \core_calculate_stage_36_muxid 2'00 + assign \core_calculate_stage_36_muxid \muxid sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end process $group_1 - assign \q_cyc 1'0 - assign \q_cyc \q_int + assign \core_calculate_stage_36_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_36_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_36_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_36_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_36_logical_op__rc__rc 1'0 + assign \core_calculate_stage_36_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_36_logical_op__oe__oe 1'0 + assign \core_calculate_stage_36_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_36_logical_op__invert_in 1'0 + assign \core_calculate_stage_36_logical_op__zero_a 1'0 + assign \core_calculate_stage_36_logical_op__input_carry 2'00 + assign \core_calculate_stage_36_logical_op__invert_out 1'0 + assign \core_calculate_stage_36_logical_op__write_cr0 1'0 + assign \core_calculate_stage_36_logical_op__output_carry 1'0 + assign \core_calculate_stage_36_logical_op__is_32bit 1'0 + assign \core_calculate_stage_36_logical_op__is_signed 1'0 + assign \core_calculate_stage_36_logical_op__data_len 4'0000 + assign \core_calculate_stage_36_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_36_logical_op__insn \core_calculate_stage_36_logical_op__data_len \core_calculate_stage_36_logical_op__is_signed \core_calculate_stage_36_logical_op__is_32bit \core_calculate_stage_36_logical_op__output_carry \core_calculate_stage_36_logical_op__write_cr0 \core_calculate_stage_36_logical_op__invert_out \core_calculate_stage_36_logical_op__input_carry \core_calculate_stage_36_logical_op__zero_a \core_calculate_stage_36_logical_op__invert_in { \core_calculate_stage_36_logical_op__oe__oe_ok \core_calculate_stage_36_logical_op__oe__oe } { \core_calculate_stage_36_logical_op__rc__rc_ok \core_calculate_stage_36_logical_op__rc__rc } { \core_calculate_stage_36_logical_op__imm_data__imm_ok \core_calculate_stage_36_logical_op__imm_data__imm } \core_calculate_stage_36_logical_op__fn_unit \core_calculate_stage_36_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_cyc - connect \Y $7 + process $group_19 + assign \core_calculate_stage_36_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_36_ra \ra + sync init end - process $group_2 - assign \qn_cyc 1'0 - assign \qn_cyc $7 + process $group_20 + assign \core_calculate_stage_36_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_36_rb \rb sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_cyc - connect \B \q_int - connect \Y $9 + process $group_21 + assign \core_calculate_stage_36_xer_so 1'0 + assign \core_calculate_stage_36_xer_so \xer_so + sync init end - process $group_3 - assign \qlq_cyc 1'0 - assign \qlq_cyc $9 + process $group_22 + assign \core_calculate_stage_36_divisor_neg 1'0 + assign \core_calculate_stage_36_divisor_neg \divisor_neg sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp" -module \lenexp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" - wire width 4 input 0 \len_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" - wire width 4 input 1 \addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" - wire width 64 output 2 \lexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" - wire width 176 output 3 \rexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" - wire width 17 \binlen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 21 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 20 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 20 - connect \A 5'00001 - connect \B \len_i - connect \Y $2 + process $group_23 + assign \core_calculate_stage_36_dividend_neg 1'0 + assign \core_calculate_stage_36_dividend_neg \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 21 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 21 - connect \A $2 - connect \B 1'1 - connect \Y $4 + process $group_24 + assign \core_calculate_stage_36_dive_abs_ov32 1'0 + assign \core_calculate_stage_36_dive_abs_ov32 \dive_abs_ov32 + sync init end - connect $1 $4 - process $group_0 - assign \binlen 17'00000000000000000 - assign \binlen $1 [16:0] + process $group_25 + assign \core_calculate_stage_36_dive_abs_ov64 1'0 + assign \core_calculate_stage_36_dive_abs_ov64 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - wire width 64 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - wire width 32 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 17 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 32 - connect \A \binlen - connect \B \addr_i - connect \Y $7 + process $group_26 + assign \core_calculate_stage_36_div_by_zero 1'0 + assign \core_calculate_stage_36_div_by_zero \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A $7 - connect \Y $6 + process $group_27 + assign \core_calculate_stage_36_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_36_divisor_radicand \divisor_radicand + sync init end - process $group_1 - assign \lexp_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \lexp_o $6 + process $group_28 + assign \core_calculate_stage_36_operation 2'00 + assign \core_calculate_stage_36_operation \operation sync init end - process $group_2 - assign \rexp_o 176'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \rexp_o { { \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] } { \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] } { \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] } { \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] } { \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] } { \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] } { \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] } { \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] } { \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] } { \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] } { \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] } { \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] } { \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] } { \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] } { \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] } { \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] } { \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] } { \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] } { \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] } { \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] } { \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] } { \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] } { \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] } { \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] } { \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] } { \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] } { \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] } { \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] } { \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] } { \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] } { \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] } { \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] } { \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] } { \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] } { \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] } { \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] } { \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] } { \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] } { \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] } { \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] } { \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] } { \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] } { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] } { \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] } { \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] } { \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] } { \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] } { \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] } { \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] } { \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] } { \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] } { \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] } { \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] } { \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] } { \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] } { \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] } { \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] } { \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] } { \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] } { \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] } { \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] } { \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] } { \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] } { \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } } [175:0] + process $group_29 + assign \core_calculate_stage_36_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_36_quotient_root \quotient_root sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l" -module \valid_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 3 \q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_valid - connect \Y $1 + process $group_30 + assign \core_calculate_stage_36_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_36_root_times_radicand \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + process $group_31 + assign \core_calculate_stage_36_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_36_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_valid - connect \Y $5 + process $group_32 + assign \core_calculate_stage_36_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_36_compare_rhs \compare_rhs + sync init end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + process $group_33 + assign \core_calculate_stage_37_muxid 2'00 + assign \core_calculate_stage_37_muxid \core_calculate_stage_36_muxid$34 sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_valid - connect \Y $7 + process $group_34 + assign \core_calculate_stage_37_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_37_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_37_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_37_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_37_logical_op__rc__rc 1'0 + assign \core_calculate_stage_37_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_37_logical_op__oe__oe 1'0 + assign \core_calculate_stage_37_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_37_logical_op__invert_in 1'0 + assign \core_calculate_stage_37_logical_op__zero_a 1'0 + assign \core_calculate_stage_37_logical_op__input_carry 2'00 + assign \core_calculate_stage_37_logical_op__invert_out 1'0 + assign \core_calculate_stage_37_logical_op__write_cr0 1'0 + assign \core_calculate_stage_37_logical_op__output_carry 1'0 + assign \core_calculate_stage_37_logical_op__is_32bit 1'0 + assign \core_calculate_stage_37_logical_op__is_signed 1'0 + assign \core_calculate_stage_37_logical_op__data_len 4'0000 + assign \core_calculate_stage_37_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_37_logical_op__insn \core_calculate_stage_37_logical_op__data_len \core_calculate_stage_37_logical_op__is_signed \core_calculate_stage_37_logical_op__is_32bit \core_calculate_stage_37_logical_op__output_carry \core_calculate_stage_37_logical_op__write_cr0 \core_calculate_stage_37_logical_op__invert_out \core_calculate_stage_37_logical_op__input_carry \core_calculate_stage_37_logical_op__zero_a \core_calculate_stage_37_logical_op__invert_in { \core_calculate_stage_37_logical_op__oe__oe_ok \core_calculate_stage_37_logical_op__oe__oe } { \core_calculate_stage_37_logical_op__rc__rc_ok \core_calculate_stage_37_logical_op__rc__rc } { \core_calculate_stage_37_logical_op__imm_data__imm_ok \core_calculate_stage_37_logical_op__imm_data__imm } \core_calculate_stage_37_logical_op__fn_unit \core_calculate_stage_37_logical_op__insn_type } { \core_calculate_stage_36_logical_op__insn$52 \core_calculate_stage_36_logical_op__data_len$51 \core_calculate_stage_36_logical_op__is_signed$50 \core_calculate_stage_36_logical_op__is_32bit$49 \core_calculate_stage_36_logical_op__output_carry$48 \core_calculate_stage_36_logical_op__write_cr0$47 \core_calculate_stage_36_logical_op__invert_out$46 \core_calculate_stage_36_logical_op__input_carry$45 \core_calculate_stage_36_logical_op__zero_a$44 \core_calculate_stage_36_logical_op__invert_in$43 { \core_calculate_stage_36_logical_op__oe__oe_ok$42 \core_calculate_stage_36_logical_op__oe__oe$41 } { \core_calculate_stage_36_logical_op__rc__rc_ok$40 \core_calculate_stage_36_logical_op__rc__rc$39 } { \core_calculate_stage_36_logical_op__imm_data__imm_ok$38 \core_calculate_stage_36_logical_op__imm_data__imm$37 } \core_calculate_stage_36_logical_op__fn_unit$36 \core_calculate_stage_36_logical_op__insn_type$35 } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + process $group_52 + assign \core_calculate_stage_37_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_37_ra \core_calculate_stage_36_ra$53 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_valid - connect \Y $11 + process $group_53 + assign \core_calculate_stage_37_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_37_rb \core_calculate_stage_36_rb$54 + sync init end - process $group_1 - assign \q_valid 1'0 - assign \q_valid $11 + process $group_54 + assign \core_calculate_stage_37_xer_so 1'0 + assign \core_calculate_stage_37_xer_so \core_calculate_stage_36_xer_so$55 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_valid - connect \Y $13 + process $group_55 + assign \core_calculate_stage_37_divisor_neg 1'0 + assign \core_calculate_stage_37_divisor_neg \core_calculate_stage_36_divisor_neg$56 + sync init end - process $group_2 - assign \qn_valid 1'0 - assign \qn_valid $13 + process $group_56 + assign \core_calculate_stage_37_dividend_neg 1'0 + assign \core_calculate_stage_37_dividend_neg \core_calculate_stage_36_dividend_neg$57 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_valid - connect \B \q_int - connect \Y $15 + process $group_57 + assign \core_calculate_stage_37_dive_abs_ov32 1'0 + assign \core_calculate_stage_37_dive_abs_ov32 \core_calculate_stage_36_dive_abs_ov32$58 + sync init end - process $group_3 - assign \qlq_valid 1'0 - assign \qlq_valid $15 + process $group_58 + assign \core_calculate_stage_37_dive_abs_ov64 1'0 + assign \core_calculate_stage_37_dive_abs_ov64 \core_calculate_stage_36_dive_abs_ov64$59 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem" -module \pimem - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 input 2 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 input 3 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 output 4 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 48 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27" - wire width 8 output 8 \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26" - wire width 48 output 9 \x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 10 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 64 input 11 \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 12 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 13 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 14 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 15 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30" - wire width 64 output 16 \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 input 17 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28" - wire width 1 output 18 \x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29" - wire width 1 output 19 \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42" - wire width 1 input 20 \x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37" - wire width 1 output 21 \m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33" - wire width 1 output 22 \x_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \st_active_r_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \st_active_s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \st_active_q_st_active - cell \st_active \st_active - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_st_active \st_active_r_st_active - connect \s_st_active \st_active_s_st_active - connect \q_st_active \st_active_q_st_active + process $group_59 + assign \core_calculate_stage_37_div_by_zero 1'0 + assign \core_calculate_stage_37_div_by_zero \core_calculate_stage_36_div_by_zero$60 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \st_done_s_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \st_done_r_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \st_done_q_st_done - cell \st_done \st_done - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_st_done \st_done_s_st_done - connect \r_st_done \st_done_r_st_done - connect \q_st_done \st_done_q_st_done + process $group_60 + assign \core_calculate_stage_37_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_37_divisor_radicand \core_calculate_stage_36_divisor_radicand$61 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \ld_active_r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \ld_active_s_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \ld_active_q_ld_active - cell \ld_active \ld_active - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_ld_active \ld_active_r_ld_active - connect \s_ld_active \ld_active_s_ld_active - connect \q_ld_active \ld_active_q_ld_active + process $group_61 + assign \core_calculate_stage_37_operation 2'00 + assign \core_calculate_stage_37_operation \core_calculate_stage_36_operation$62 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \reset_l_s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \reset_l_q_reset - cell \reset_l \reset_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_reset \reset_l_s_reset - connect \r_reset \reset_l_r_reset - connect \q_reset \reset_l_q_reset + process $group_62 + assign \core_calculate_stage_37_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_37_quotient_root \core_calculate_stage_36_quotient_root$63 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \adrok_l_s_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \adrok_l_s_addr_acked$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \adrok_l_r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \adrok_l_qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \adrok_l_q_addr_acked - cell \adrok_l \adrok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_addr_acked \adrok_l_s_addr_acked - connect \r_addr_acked \adrok_l_r_addr_acked - connect \qn_addr_acked \adrok_l_qn_addr_acked - connect \q_addr_acked \adrok_l_q_addr_acked + process $group_63 + assign \core_calculate_stage_37_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_37_root_times_radicand \core_calculate_stage_36_root_times_radicand$64 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \busy_l_r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \busy_l_q_busy - cell \busy_l \busy_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_busy \busy_l_s_busy - connect \r_busy \busy_l_r_busy - connect \q_busy \busy_l_q_busy + process $group_64 + assign \core_calculate_stage_37_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_37_compare_lhs \core_calculate_stage_36_compare_lhs$65 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \cyc_l_s_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \cyc_l_r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \cyc_l_q_cyc - cell \cyc_l \cyc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_cyc \cyc_l_s_cyc - connect \r_cyc \cyc_l_r_cyc - connect \q_cyc \cyc_l_q_cyc + process $group_65 + assign \core_calculate_stage_37_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_37_compare_rhs \core_calculate_stage_36_compare_rhs$66 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" - wire width 4 \lenexp_len_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" - wire width 4 \lenexp_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" - wire width 64 \lenexp_lexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" - wire width 176 \lenexp_rexp_o - cell \lenexp \lenexp - connect \len_i \lenexp_len_i - connect \addr_i \lenexp_addr_i - connect \lexp_o \lenexp_lexp_o - connect \rexp_o \lenexp_rexp_o + process $group_66 + assign \core_calculate_stage_38_muxid 2'00 + assign \core_calculate_stage_38_muxid \core_calculate_stage_37_muxid$67 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \valid_l_s_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \valid_l_q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \valid_l_r_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \valid_l_r_valid$next - cell \valid_l \valid_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_valid \valid_l_s_valid - connect \q_valid \valid_l_q_valid - connect \r_valid \valid_l_r_valid + process $group_67 + assign \core_calculate_stage_38_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_38_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_38_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_38_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_38_logical_op__rc__rc 1'0 + assign \core_calculate_stage_38_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_38_logical_op__oe__oe 1'0 + assign \core_calculate_stage_38_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_38_logical_op__invert_in 1'0 + assign \core_calculate_stage_38_logical_op__zero_a 1'0 + assign \core_calculate_stage_38_logical_op__input_carry 2'00 + assign \core_calculate_stage_38_logical_op__invert_out 1'0 + assign \core_calculate_stage_38_logical_op__write_cr0 1'0 + assign \core_calculate_stage_38_logical_op__output_carry 1'0 + assign \core_calculate_stage_38_logical_op__is_32bit 1'0 + assign \core_calculate_stage_38_logical_op__is_signed 1'0 + assign \core_calculate_stage_38_logical_op__data_len 4'0000 + assign \core_calculate_stage_38_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_38_logical_op__insn \core_calculate_stage_38_logical_op__data_len \core_calculate_stage_38_logical_op__is_signed \core_calculate_stage_38_logical_op__is_32bit \core_calculate_stage_38_logical_op__output_carry \core_calculate_stage_38_logical_op__write_cr0 \core_calculate_stage_38_logical_op__invert_out \core_calculate_stage_38_logical_op__input_carry \core_calculate_stage_38_logical_op__zero_a \core_calculate_stage_38_logical_op__invert_in { \core_calculate_stage_38_logical_op__oe__oe_ok \core_calculate_stage_38_logical_op__oe__oe } { \core_calculate_stage_38_logical_op__rc__rc_ok \core_calculate_stage_38_logical_op__rc__rc } { \core_calculate_stage_38_logical_op__imm_data__imm_ok \core_calculate_stage_38_logical_op__imm_data__imm } \core_calculate_stage_38_logical_op__fn_unit \core_calculate_stage_38_logical_op__insn_type } { \core_calculate_stage_37_logical_op__insn$85 \core_calculate_stage_37_logical_op__data_len$84 \core_calculate_stage_37_logical_op__is_signed$83 \core_calculate_stage_37_logical_op__is_32bit$82 \core_calculate_stage_37_logical_op__output_carry$81 \core_calculate_stage_37_logical_op__write_cr0$80 \core_calculate_stage_37_logical_op__invert_out$79 \core_calculate_stage_37_logical_op__input_carry$78 \core_calculate_stage_37_logical_op__zero_a$77 \core_calculate_stage_37_logical_op__invert_in$76 { \core_calculate_stage_37_logical_op__oe__oe_ok$75 \core_calculate_stage_37_logical_op__oe__oe$74 } { \core_calculate_stage_37_logical_op__rc__rc_ok$73 \core_calculate_stage_37_logical_op__rc__rc$72 } { \core_calculate_stage_37_logical_op__imm_data__imm_ok$71 \core_calculate_stage_37_logical_op__imm_data__imm$70 } \core_calculate_stage_37_logical_op__fn_unit$69 \core_calculate_stage_37_logical_op__insn_type$68 } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $1 + process $group_85 + assign \core_calculate_stage_38_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_38_ra \core_calculate_stage_37_ra$86 + sync init end - process $group_0 - assign \st_done_s_st_done 1'0 - assign \st_done_s_st_done 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - case 1'1 - assign \st_done_s_st_done 1'1 - end + process $group_86 + assign \core_calculate_stage_38_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_38_rb \core_calculate_stage_37_rb$87 sync init end - process $group_1 - assign \st_done_r_st_done 1'1 - assign \st_done_r_st_done 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - case 1'1 - assign \st_done_r_st_done 1'1 - end + process $group_87 + assign \core_calculate_stage_38_xer_so 1'0 + assign \core_calculate_stage_38_xer_so \core_calculate_stage_37_xer_so$88 sync init end - process $group_2 - assign \st_active_r_st_active 1'1 - assign \st_active_r_st_active 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - case 1'1 - assign \st_active_r_st_active 1'1 - end + process $group_88 + assign \core_calculate_stage_38_divisor_neg 1'0 + assign \core_calculate_stage_38_divisor_neg \core_calculate_stage_37_divisor_neg$89 sync init end - process $group_3 - assign \ld_active_r_ld_active 1'1 - assign \ld_active_r_ld_active 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - case 1'1 - assign \ld_active_r_ld_active 1'1 - end + process $group_89 + assign \core_calculate_stage_38_dividend_neg 1'0 + assign \core_calculate_stage_38_dividend_neg \core_calculate_stage_37_dividend_neg$90 sync init end - process $group_4 - assign \cyc_l_s_cyc 1'0 - assign \cyc_l_s_cyc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" - switch { \reset_l_s_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" - case 1'1 - assign \cyc_l_s_cyc 1'1 - end + process $group_90 + assign \core_calculate_stage_38_dive_abs_ov32 1'0 + assign \core_calculate_stage_38_dive_abs_ov32 \core_calculate_stage_37_dive_abs_ov32$91 sync init end - process $group_5 - assign \cyc_l_r_cyc 1'1 - assign \cyc_l_r_cyc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:279" - switch { \cyc_l_q_cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:279" - case 1'1 - assign \cyc_l_r_cyc 1'1 - end + process $group_91 + assign \core_calculate_stage_38_dive_abs_ov64 1'0 + assign \core_calculate_stage_38_dive_abs_ov64 \core_calculate_stage_37_dive_abs_ov64$92 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:200" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:200" - cell $or $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $3 + process $group_92 + assign \core_calculate_stage_38_div_by_zero 1'0 + assign \core_calculate_stage_38_div_by_zero \core_calculate_stage_37_div_by_zero$93 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:201" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190" - wire width 1 \busy_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190" - wire width 1 \busy_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:201" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \busy_delay - connect \Y $5 + process $group_93 + assign \core_calculate_stage_38_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_38_divisor_radicand \core_calculate_stage_37_divisor_radicand$94 + sync init end - process $group_6 - assign \busy_l_s_busy 1'0 - assign \busy_l_s_busy 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:200" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:200" - case 1'1 - assign \busy_l_s_busy $5 - end + process $group_94 + assign \core_calculate_stage_38_operation 2'00 + assign \core_calculate_stage_38_operation \core_calculate_stage_37_operation$95 sync init end - process $group_7 - assign \busy_l_r_busy 1'1 - assign \busy_l_r_busy 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - switch { \ldst_port0_addr_exc_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - case 1'1 - assign \busy_l_r_busy 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:279" - switch { \cyc_l_q_cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:279" - case 1'1 - assign \busy_l_r_busy 1'1 - end + process $group_95 + assign \core_calculate_stage_38_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_38_quotient_root \core_calculate_stage_37_quotient_root$96 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $7 + process $group_96 + assign \core_calculate_stage_38_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_38_root_times_radicand \core_calculate_stage_37_root_times_radicand$97 + sync init end - process $group_8 - assign \adrok_l_s_addr_acked$next \adrok_l_s_addr_acked - assign \adrok_l_s_addr_acked$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - case 1'1 - assign \adrok_l_s_addr_acked$next 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - switch { \ldst_port0_addr_i_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - switch { \adrok_l_qn_addr_acked } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - case 1'1 - assign \adrok_l_s_addr_acked$next 1'1 - end - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \adrok_l_s_addr_acked$next 1'0 - end + process $group_97 + assign \core_calculate_stage_38_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_38_compare_lhs \core_calculate_stage_37_compare_lhs$98 sync init - update \adrok_l_s_addr_acked 1'0 - sync posedge \coresync_clk - update \adrok_l_s_addr_acked \adrok_l_s_addr_acked$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - wire width 1 \reset_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - wire width 1 \reset_delay$next - process $group_9 - assign \adrok_l_r_addr_acked 1'1 - assign \adrok_l_r_addr_acked 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch { \reset_delay } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - case 1'1 - assign \adrok_l_r_addr_acked 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - case 1'1 - assign \adrok_l_r_addr_acked 1'1 - end + process $group_98 + assign \core_calculate_stage_38_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_38_compare_rhs \core_calculate_stage_37_compare_rhs$99 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183" - wire width 1 \lds - process $group_10 - assign \lds 1'0 - assign \lds \ldst_port0_is_ld_i + process $group_99 + assign \core_calculate_stage_39_muxid 2'00 + assign \core_calculate_stage_39_muxid \core_calculate_stage_38_muxid$100 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:184" - wire width 1 \sts - process $group_11 - assign \sts 1'0 - assign \sts \ldst_port0_is_st_i + process $group_100 + assign \core_calculate_stage_39_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_39_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_39_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_39_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_39_logical_op__rc__rc 1'0 + assign \core_calculate_stage_39_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_39_logical_op__oe__oe 1'0 + assign \core_calculate_stage_39_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_39_logical_op__invert_in 1'0 + assign \core_calculate_stage_39_logical_op__zero_a 1'0 + assign \core_calculate_stage_39_logical_op__input_carry 2'00 + assign \core_calculate_stage_39_logical_op__invert_out 1'0 + assign \core_calculate_stage_39_logical_op__write_cr0 1'0 + assign \core_calculate_stage_39_logical_op__output_carry 1'0 + assign \core_calculate_stage_39_logical_op__is_32bit 1'0 + assign \core_calculate_stage_39_logical_op__is_signed 1'0 + assign \core_calculate_stage_39_logical_op__data_len 4'0000 + assign \core_calculate_stage_39_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_39_logical_op__insn \core_calculate_stage_39_logical_op__data_len \core_calculate_stage_39_logical_op__is_signed \core_calculate_stage_39_logical_op__is_32bit \core_calculate_stage_39_logical_op__output_carry \core_calculate_stage_39_logical_op__write_cr0 \core_calculate_stage_39_logical_op__invert_out \core_calculate_stage_39_logical_op__input_carry \core_calculate_stage_39_logical_op__zero_a \core_calculate_stage_39_logical_op__invert_in { \core_calculate_stage_39_logical_op__oe__oe_ok \core_calculate_stage_39_logical_op__oe__oe } { \core_calculate_stage_39_logical_op__rc__rc_ok \core_calculate_stage_39_logical_op__rc__rc } { \core_calculate_stage_39_logical_op__imm_data__imm_ok \core_calculate_stage_39_logical_op__imm_data__imm } \core_calculate_stage_39_logical_op__fn_unit \core_calculate_stage_39_logical_op__insn_type } { \core_calculate_stage_38_logical_op__insn$118 \core_calculate_stage_38_logical_op__data_len$117 \core_calculate_stage_38_logical_op__is_signed$116 \core_calculate_stage_38_logical_op__is_32bit$115 \core_calculate_stage_38_logical_op__output_carry$114 \core_calculate_stage_38_logical_op__write_cr0$113 \core_calculate_stage_38_logical_op__invert_out$112 \core_calculate_stage_38_logical_op__input_carry$111 \core_calculate_stage_38_logical_op__zero_a$110 \core_calculate_stage_38_logical_op__invert_in$109 { \core_calculate_stage_38_logical_op__oe__oe_ok$108 \core_calculate_stage_38_logical_op__oe__oe$107 } { \core_calculate_stage_38_logical_op__rc__rc_ok$106 \core_calculate_stage_38_logical_op__rc__rc$105 } { \core_calculate_stage_38_logical_op__imm_data__imm_ok$104 \core_calculate_stage_38_logical_op__imm_data__imm$103 } \core_calculate_stage_38_logical_op__fn_unit$102 \core_calculate_stage_38_logical_op__insn_type$101 } sync init end - process $group_12 - assign \busy_delay$next \busy_delay - assign \busy_delay$next \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \busy_delay$next 1'0 - end + process $group_118 + assign \core_calculate_stage_39_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_39_ra \core_calculate_stage_38_ra$119 sync init - update \busy_delay 1'0 - sync posedge \coresync_clk - update \busy_delay \busy_delay$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:191" - wire width 1 \busy_edge - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:193" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:193" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \busy_delay - connect \Y $9 + process $group_119 + assign \core_calculate_stage_39_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_39_rb \core_calculate_stage_38_rb$120 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:193" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:193" - cell $and $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \B $9 - connect \Y $11 + process $group_120 + assign \core_calculate_stage_39_xer_so 1'0 + assign \core_calculate_stage_39_xer_so \core_calculate_stage_38_xer_so$121 + sync init end - process $group_13 - assign \busy_edge 1'0 - assign \busy_edge $11 + process $group_121 + assign \core_calculate_stage_39_divisor_neg 1'0 + assign \core_calculate_stage_39_divisor_neg \core_calculate_stage_38_divisor_neg$122 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196" - cell $and $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lds - connect \B \busy_edge - connect \Y $13 + process $group_122 + assign \core_calculate_stage_39_dividend_neg 1'0 + assign \core_calculate_stage_39_dividend_neg \core_calculate_stage_38_dividend_neg$123 + sync init end - process $group_14 - assign \ld_active_s_ld_active 1'0 - assign \ld_active_s_ld_active $13 + process $group_123 + assign \core_calculate_stage_39_dive_abs_ov32 1'0 + assign \core_calculate_stage_39_dive_abs_ov32 \core_calculate_stage_38_dive_abs_ov32$124 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:197" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:197" - cell $and $16 + process $group_124 + assign \core_calculate_stage_39_dive_abs_ov64 1'0 + assign \core_calculate_stage_39_dive_abs_ov64 \core_calculate_stage_38_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_39_div_by_zero 1'0 + assign \core_calculate_stage_39_div_by_zero \core_calculate_stage_38_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_39_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_39_divisor_radicand \core_calculate_stage_38_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_39_operation 2'00 + assign \core_calculate_stage_39_operation \core_calculate_stage_38_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_39_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_39_quotient_root \core_calculate_stage_38_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_39_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_39_root_times_radicand \core_calculate_stage_38_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_39_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_39_compare_lhs \core_calculate_stage_38_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_39_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_39_compare_rhs \core_calculate_stage_38_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sts - connect \B \busy_edge - connect \Y $15 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 end - process $group_15 - assign \st_active_s_st_active 1'0 - assign \st_active_s_st_active $15 + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 sync init end - process $group_16 - assign \lenexp_len_i 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_39_muxid$133 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_39_logical_op__insn$151 \core_calculate_stage_39_logical_op__data_len$150 \core_calculate_stage_39_logical_op__is_signed$149 \core_calculate_stage_39_logical_op__is_32bit$148 \core_calculate_stage_39_logical_op__output_carry$147 \core_calculate_stage_39_logical_op__write_cr0$146 \core_calculate_stage_39_logical_op__invert_out$145 \core_calculate_stage_39_logical_op__input_carry$144 \core_calculate_stage_39_logical_op__zero_a$143 \core_calculate_stage_39_logical_op__invert_in$142 { \core_calculate_stage_39_logical_op__oe__oe_ok$141 \core_calculate_stage_39_logical_op__oe__oe$140 } { \core_calculate_stage_39_logical_op__rc__rc_ok$139 \core_calculate_stage_39_logical_op__rc__rc$138 } { \core_calculate_stage_39_logical_op__imm_data__imm_ok$137 \core_calculate_stage_39_logical_op__imm_data__imm$136 } \core_calculate_stage_39_logical_op__fn_unit$135 \core_calculate_stage_39_logical_op__insn_type$134 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_39_ra$152 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_39_rb$153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_39_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_39_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_39_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_39_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_39_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_39_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_39_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_39_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_39_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_39_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_39_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_39_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst case 1'1 - assign \lenexp_len_i \ldst_port0_data_len + assign \r_busy$next 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst case 1'1 - assign \lenexp_len_i \ldst_port0_data_len + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 end sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 4 $17 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A \ldst_port0_addr_i [2:0] - connect \Y $17 + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 4 $19 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A \ldst_port0_addr_i [2:0] - connect \Y $19 + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next end - process $group_17 - assign \lenexp_addr_i 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - case 1'1 - assign \lenexp_addr_i $17 + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - case 1'1 - assign \lenexp_addr_i $19 + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 end sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $21 + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next end - process $group_18 - assign \valid_l_s_valid 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - switch { $21 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - case 1'1 - assign \valid_l_s_valid 1'1 - end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - switch { \ldst_port0_addr_i_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - case 1'1 - assign \valid_l_s_valid 1'1 - end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 end sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - cell $and $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $23 + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next end - process $group_19 - assign \x_mask_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - switch { $23 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - case 1'1 - assign \x_mask_i \lenexp_lexp_o [7:0] - end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - switch { \ldst_port0_addr_i_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - case 1'1 - assign \x_mask_i \lenexp_lexp_o [7:0] - end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 end sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - cell $and $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $25 + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next end - process $group_20 - assign \x_addr_i 48'000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - switch { $25 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - case 1'1 - assign \x_addr_i \ldst_port0_addr_i - end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - switch { \ldst_port0_addr_i_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - case 1'1 - assign \x_addr_i \ldst_port0_addr_i - end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 end sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - cell $and $28 + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.p" +module \p$254 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $27 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 end - process $group_21 - assign \ldst_port0_addr_ok_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - switch { $27 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:210" - case 1'1 - assign \ldst_port0_addr_ok_o 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - switch { \ldst_port0_addr_i_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - switch { \adrok_l_qn_addr_acked } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - case 1'1 - assign \ldst_port0_addr_ok_o 1'1 - end - end - end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - cell $and $30 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.n" +module \n$255 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $29 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:62" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:44" - wire width 1 \lsui_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:62" - cell $not $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_busy - connect \Y $31 + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:59" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:59" - cell $not $34 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_40.core.trial0" +module \trial0$257 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \lsui_busy - connect \Y $33 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - process $group_22 - assign \reset_l_s_reset 1'0 - assign \reset_l_s_reset 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - case 1'1 - assign \reset_l_s_reset $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253" - switch { \st_done_q_st_done } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253" - case 1'1 - assign \reset_l_s_reset $33 - end - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_23 - assign \reset_l_r_reset 1'1 - assign \reset_l_r_reset 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \reset_l_r_reset 1'1 + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:232" - wire width 64 \lddata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235" - wire width 176 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" - wire width 176 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" - cell $and $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 176 - parameter \Y_WIDTH 176 - connect \A \m_ld_data_o - connect \B \lenexp_rexp_o - connect \Y $36 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235" - wire width 8 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235" - cell $mul $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \lenexp_addr_i - connect \B 4'1000 - connect \Y $38 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235" - wire width 176 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:235" - cell $sshr $41 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 176 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 176 - connect \A $36 - connect \B $38 - connect \Y $40 - end - connect $35 $40 - process $group_24 - assign \lddata 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \lddata $35 [63:0] - sync init + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010111 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - cell $and $43 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $42 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_25 - assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - switch { $42 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \ldst_port0_ld_data_o \lddata + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - cell $and $45 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_40.core.trial1" +module \trial1$258 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $44 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:62" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:62" - cell $not $47 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_busy - connect \Y $46 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_26 - assign \ldst_port0_ld_data_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" - switch { $44 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \ldst_port0_ld_data_o_ok $46 + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" - wire width 64 \stdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - cell $and $49 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $48 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - wire width 319 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - wire width 8 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - cell $mul $52 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \lenexp_addr_i - connect \B 4'1000 - connect \Y $51 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010111 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - wire width 319 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" - cell $sshl $54 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 319 - connect \A \ldst_port0_st_data_i - connect \B $51 - connect \Y $53 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - connect $50 $53 - process $group_27 - assign \stdata 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - switch { $48 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \stdata $50 [63:0] + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - cell $and $56 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_40.core.pe" +module \pe$259 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $55 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_28 - assign \x_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:244" - case 1'1 - assign \x_st_data_i \stdata - end + process $group_1 + assign \n 1'0 + assign \n $1 sync init end - process $group_29 - assign \reset_delay$next \reset_delay - assign \reset_delay$next \reset_l_q_reset +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_40.core" +module \core$256 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$257 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$258 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$259 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init - update \reset_delay 1'0 - sync posedge \coresync_clk - update \reset_delay \reset_delay$next end - process $group_30 - assign \ldst_port0_busy_o 1'0 - assign \ldst_port0_busy_o \busy_l_q_busy + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation sync init end - process $group_31 - assign \x_ld_i 1'0 - assign \x_ld_i \ldst_port0_is_ld_i + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init end - process $group_32 - assign \x_st_i 1'0 - assign \x_st_i \ldst_port0_is_st_i + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:83" - wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:83" - wire width 2 \fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - cell $or $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $57 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - cell $and $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $57 - connect \B \valid_l_q_valid - connect \Y $59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init end - process $group_33 - assign \lsui_busy 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:83" - switch \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:84" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - switch { $59 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - case 1'1 - assign \lsui_busy 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:89" - attribute \nmigen.decoding "BUSY/1" - case 2'01 - assign \lsui_busy 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - attribute \nmigen.decoding "WAITDEASSERT/2" - case 2'10 - end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - cell $or $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $61 + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - cell $and $64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A $61 - connect \B \valid_l_q_valid - connect \Y $63 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:93" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:93" - cell $not $66 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \x_busy_o - connect \Y $65 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97" - cell $not $68 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \valid_l_q_valid - connect \Y $67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_34 - assign \fsm_state$next \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:83" - switch \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:84" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - switch { $63 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - case 1'1 - assign \fsm_state$next 2'01 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:89" - attribute \nmigen.decoding "BUSY/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:93" - switch { $65 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:93" - case 1'1 - assign \fsm_state$next 2'10 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - attribute \nmigen.decoding "WAITDEASSERT/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97" - switch { $67 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97" - case 1'1 - assign \fsm_state$next 2'00 - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \fsm_state$next 2'00 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init - update \fsm_state 2'00 - sync posedge \coresync_clk - update \fsm_state \fsm_state$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:101" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:101" - cell $or $70 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \valid_l_q_valid - connect \B \lsui_busy - connect \Y $69 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_35 - assign \m_valid_i 1'0 - assign \m_valid_i $69 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:102" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:102" - cell $or $72 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \valid_l_q_valid - connect \B \lsui_busy - connect \Y $71 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_36 - assign \x_valid_i 1'0 - assign \x_valid_i $71 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:105" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:105" - cell $not $74 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_busy - connect \Y $73 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - process $group_37 - assign \valid_l_r_valid$next \valid_l_r_valid - assign \valid_l_r_valid$next $73 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \valid_l_r_valid$next 1'1 - end - sync init - update \valid_l_r_valid 1'1 - sync posedge \coresync_clk - update \valid_l_r_valid \valid_l_r_valid$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l" -module \idx_l - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_idx_l - connect \Y $1 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'10111 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_idx_l - connect \Y $5 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_40" +module \core_calculate_stage_40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$256 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_idx_l - connect \Y $7 + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_41.core.trial0" +module \trial0$261 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_idx_l - connect \Y $11 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_1 - assign \q_idx_l 1'0 - assign \q_idx_l $11 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_idx_l - connect \Y $13 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_2 - assign \qn_idx_l 1'0 - assign \qn_idx_l $13 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010110 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_idx_l - connect \B \q_int - connect \Y $15 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_3 - assign \qlq_idx_l 1'0 - assign \qlq_idx_l $15 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" -module \reset_l$124 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_41.core.trial1" +module \trial1$262 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_reset - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_reset - connect \Y $5 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \q_int$next 1'0 + assign \dr_times_trial_bits $3 end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - process $group_1 - assign \q_reset 1'0 - assign \q_reset \q_int sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_reset - connect \Y $7 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_2 - assign \qn_reset 1'0 - assign \qn_reset $7 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010110 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \B \q_int - connect \Y $9 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_3 - assign \qlq_reset 1'0 - assign \qlq_reset $9 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.pick" -module \pick +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_41.core.pe" +module \pe$263 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 1 \o + wire width 2 input 0 \i attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 2 \n + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o process $group_0 assign \o 1'0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i } + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 assign \o 1'0 @@ -127712,7 +124325,7 @@ module \pick attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 @@ -127727,12928 +124340,17074 @@ module \pick end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.l0" -module \l0$123 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 input 2 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 input 3 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 input 4 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 input 5 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 6 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 output 7 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 8 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 9 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 10 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 11 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 12 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 13 \ldst_port0_is_ld_i$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 14 \ldst_port0_is_st_i$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 input 15 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 16 \ldst_port0_data_len$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 48 output 17 \ldst_port0_addr_i$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 18 \ldst_port0_addr_i_ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 input 19 \ldst_port0_addr_ok_o$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 20 \ldst_port0_ld_data_o$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 21 \ldst_port0_ld_data_o_ok$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 22 \ldst_port0_st_data_i_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 23 \ldst_port0_st_data_i$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 input 24 \ldst_port0_addr_exc_o$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \idx_l_q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \idx_l_s_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \idx_l_r_idx_l - cell \idx_l \idx_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_idx_l \idx_l_q_idx_l - connect \s_idx_l \idx_l_s_idx_l - connect \r_idx_l \idx_l_r_idx_l - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \reset_l_s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \reset_l_q_reset - cell \reset_l$124 \reset_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_reset \reset_l_s_reset - connect \r_reset \reset_l_r_reset - connect \q_reset \reset_l_q_reset +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_41.core" +module \core$260 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$261 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$262 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 1 \pick_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pick_o + wire width 2 \pe_i attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pick_n - cell \pick \pick - connect \i \pick_i - connect \o \pick_o - connect \n \pick_n - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:283" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:283" - cell $or $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $12 + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$263 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end process $group_0 - assign \pick_i 1'0 - assign \pick_i { $12 } + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \idx_l$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \idx_l$15$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $17 - parameter \WIDTH 1 - connect \A \idx_l$15 - connect \B \pick_o - connect \S \idx_l_q_idx_l - connect \Y $16 - end - connect $14 $16 process $group_1 - assign { } 0'0 - assign { } {} + assign \operation$2 2'00 + assign \operation$2 \operation sync init end process $group_2 - assign \idx_l$15$next \idx_l$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \idx_l$15$next \pick_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \idx_l$15$next 1'0 - end + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init - update \idx_l$15 1'0 - sync posedge \coresync_clk - update \idx_l$15 \idx_l$15$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:299" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:299" - cell $not $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pick_n - connect \Y $18 end process $group_3 - assign \idx_l_s_idx_l 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:299" - switch { $18 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:299" - case 1'1 - assign \idx_l_s_idx_l 1'1 - end + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:309" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:309" - cell $not $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $20 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 process $group_4 - assign \reset_l_s_reset 1'0 - assign \reset_l_s_reset 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:309" - switch { $20 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:309" - case 1'1 - assign \reset_l_s_reset 1'1 - end - end + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 process $group_5 - assign \reset_l_r_reset 1'1 - assign \reset_l_r_reset 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:317" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:317" - case 1'1 - assign \reset_l_r_reset 1'1 - end + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end process $group_6 - assign \ldst_port0_is_ld_i$1 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:115" - switch { } - case 0' - assign \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i - end - end + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end process $group_7 - assign \ldst_port0_is_st_i$2 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:116" - switch { } - case 0' - assign \ldst_port0_is_st_i$2 \ldst_port0_is_st_i - end - end + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger process $group_8 - assign \ldst_port0_data_len$3 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:117" - switch { } - case 0' - assign \ldst_port0_data_len$3 \ldst_port0_data_len - end - end + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" - wire width 1 \ldst_port0_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" - wire width 1 \ldst_port0_go_die_i$22 process $group_9 - assign \ldst_port0_go_die_i 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118" - switch { } - case 0' - assign \ldst_port0_go_die_i \ldst_port0_go_die_i$22 - end - end + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" - wire width 96 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" - wire width 96 $24 - connect $24 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 process $group_10 - assign \ldst_port0_addr_i$4 48'000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" - switch { } - case 0' - assign \ldst_port0_addr_i$4 $24 [47:0] - end - end + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 process $group_11 - assign \ldst_port0_addr_i_ok$5 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" - switch { } - case 0' - assign \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok - end - end + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init end process $group_12 - assign \ldst_port0_st_data_i$10 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ldst_port0_st_data_i_ok$9 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:121" - switch { } - case 0' - assign { \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i$10 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } - end - end + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end process $group_14 - assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ldst_port0_ld_data_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122" - switch { } - case 0' - assign { \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o } { \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o$7 } - end - end + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 \ldst_port0_busy_o$25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end process $group_16 - assign \ldst_port0_busy_o$25 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" - switch { } - case 0' - assign \ldst_port0_busy_o$25 \ldst_port0_busy_o - end - end + assign \pe_i 2'00 + assign \pe_i $12 sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 process $group_17 - assign \ldst_port0_addr_ok_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:124" - switch { } - case 0' - assign \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$6 - end + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end process $group_18 - assign \ldst_port0_addr_exc_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:125" - switch { } - case 0' - assign \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$11 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:313" - wire width 1 \reset_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:313" - wire width 1 \reset_delay$next - process $group_19 - assign \reset_delay$next \reset_delay - assign \reset_delay$next \reset_l_q_reset - sync init - update \reset_delay 1'0 - sync posedge \coresync_clk - update \reset_delay \reset_delay$next - end - process $group_20 - assign \idx_l_r_idx_l 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:317" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:317" - case 1'1 - assign \idx_l_r_idx_l 1'1 - end + assign \nbe 1'0 + assign \nbe $19 sync init end - connect \ldst_port0_go_die_i$22 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem" -module \lsmem - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27" - wire width 8 input 2 \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26" - wire width 48 input 3 \x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 64 output 4 \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 64 \m_ld_data_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30" - wire width 64 input 5 \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28" - wire width 1 input 6 \x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29" - wire width 1 input 7 \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42" - wire width 1 output 8 \x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37" - wire width 1 input 9 \m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33" - wire width 1 input 10 \x_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 11 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 \dbus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 12 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 13 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 14 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 \dbus__stb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 8 output 15 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 8 \dbus__sel$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 input 16 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 45 output 17 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 45 \dbus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 18 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 \dbus__we$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 output 19 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 \dbus__dat_w$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $or $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \x_valid_i - connect \Y $3 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 \x_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $not $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $5 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 - connect \Y $7 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $or $10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $9 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $not $12 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'10110 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $or $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B $11 - connect \Y $13 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_41" +module \core_calculate_stage_41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$260 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \dbus__cyc$next \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - switch { $7 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - case 1'1 - assign \dbus__cyc$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - case 2'1- - assign \dbus__cyc$next 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dbus__cyc$next 1'0 - end + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init - update \dbus__cyc 1'0 - sync posedge \coresync_clk - update \dbus__cyc \dbus__cyc$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $or $16 + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_42.core.trial0" +module \trial0$265 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $15 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $18 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $15 - connect \B \x_valid_i - connect \Y $17 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $19 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $17 - connect \B $19 - connect \Y $21 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $or $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $25 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $or $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $23 - connect \B $25 - connect \Y $27 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end + connect $7 $10 process $group_1 - assign \dbus__stb$next \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - switch { $21 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - switch { $27 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - case 1'1 - assign \dbus__stb$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - case 2'1- - assign \dbus__stb$next 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \dbus__stb$next 1'0 + assign \trial_compare_rhs $7 [191:0] end sync init - update \dbus__stb 1'0 - sync posedge \coresync_clk - update \dbus__stb \dbus__stb$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $or $30 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_42.core.trial1" +module \trial1$266 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $29 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $29 - connect \B \x_valid_i - connect \Y $31 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $not $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $33 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $31 - connect \B $33 - connect \Y $35 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $or $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $39 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $or $42 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $37 - connect \B $39 - connect \Y $41 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_2 - assign \dbus__sel$next \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - switch { $35 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - switch { $41 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - case 1'1 - assign \dbus__sel$next 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - case 2'1- - assign \dbus__sel$next \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101" - case - assign \dbus__sel$next 8'00000000 - assign \dbus__sel$next 8'00000000 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_42.core.pe" +module \pe$267 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \dbus__sel$next 8'00000000 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 end sync init - update \dbus__sel 8'00000000 - sync posedge \coresync_clk - update \dbus__sel \dbus__sel$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $or $44 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $43 + connect \A \i + connect \B 1'0 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $43 - connect \B \x_valid_i - connect \Y $45 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $not $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $47 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_42.core" +module \core$264 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$265 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$266 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $45 - connect \B $47 - connect \Y $49 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$267 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $or $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $51 + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $not $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $53 + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - cell $or $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $51 - connect \B $53 - connect \Y $55 + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init end process $group_3 - assign \m_ld_data_o$next \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - switch { $49 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84" - case 1'1 - assign \m_ld_data_o$next \dbus__dat_r - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - case 2'1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \m_ld_data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init - update \m_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \m_ld_data_o \m_ld_data_o$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $or $58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $57 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $60 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $57 - connect \B \x_valid_i - connect \Y $59 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $not $62 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $61 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $59 - connect \B $61 - connect \Y $63 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_4 - assign \dbus__adr$next \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - switch { $63 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - case 2'1- - assign \dbus__adr$next \x_addr_i [47:3] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101" - case - assign \dbus__adr$next 45'000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \dbus__adr$next 45'000000000000000000000000000000000000000000000 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init - update \dbus__adr 45'000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \dbus__adr \dbus__adr$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $or $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $65 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $68 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $65 - connect \B \x_valid_i - connect \Y $67 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $not $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $69 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $72 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $67 - connect \B $69 - connect \Y $71 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_5 - assign \dbus__we$next \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - switch { $71 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - case 2'1- - assign \dbus__we$next \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101" - case - assign \dbus__we$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dbus__we$next 1'0 - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init - update \dbus__we 1'0 - sync posedge \coresync_clk - update \dbus__we \dbus__we$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $or $74 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $73 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $76 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $73 - connect \B \x_valid_i - connect \Y $75 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $not $78 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $77 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - cell $and $80 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $75 - connect \B $77 - connect \Y $79 - end - process $group_6 - assign \dbus__dat_w$next \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - switch { $79 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:92" - case 2'1- - assign \dbus__dat_w$next \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:101" - case - assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \dbus__dat_w 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \dbus__dat_w \dbus__dat_w$next + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'10101 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 1 \m_load_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 1 \m_load_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - cell $and $82 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__cyc - connect \B \dbus__err - connect \Y $81 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36" - wire width 1 \m_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116" - cell $not $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_stall_i - connect \Y $83 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:112" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:112" - cell $not $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__we - connect \Y $85 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_42" +module \core_calculate_stage_42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$264 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - process $group_7 - assign \m_load_err_o$next \m_load_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - switch { $83 $81 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - case 2'-1 - assign \m_load_err_o$next $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116" - case 2'1- - assign \m_load_err_o$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \m_load_err_o$next 1'0 - end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init - update \m_load_err_o 1'0 - sync posedge \coresync_clk - update \m_load_err_o \m_load_err_o$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" - wire width 1 \m_store_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" - wire width 1 \m_store_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - cell $and $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__cyc - connect \B \dbus__err - connect \Y $87 + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116" - cell $not $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_stall_i - connect \Y $89 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - process $group_8 - assign \m_store_err_o$next \m_store_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - switch { $89 $87 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - case 2'-1 - assign \m_store_err_o$next \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116" - case 2'1- - assign \m_store_err_o$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \m_store_err_o$next 1'0 - end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init - update \m_store_err_o 1'0 - sync posedge \coresync_clk - update \m_store_err_o \m_store_err_o$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" - wire width 45 \m_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" - wire width 45 \m_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - cell $and $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__cyc - connect \B \dbus__err - connect \Y $91 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116" - cell $not $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_stall_i - connect \Y $93 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - process $group_9 - assign \m_badaddr_o$next \m_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - switch { $93 $91 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:110" - case 2'-1 - assign \m_badaddr_o$next \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:116" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \m_badaddr_o$next 45'000000000000000000000000000000000000000000000 - end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init - update \m_badaddr_o 45'000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \m_badaddr_o \m_badaddr_o$next end - process $group_10 - assign \x_busy_o 1'0 - assign \x_busy_o \dbus__cyc + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" - wire width 1 \m_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:124" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:124" - cell $or $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_load_err_o - connect \B \m_store_err_o - connect \Y $95 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - process $group_11 - assign \m_busy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:124" - switch { $95 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:124" - case 1'1 - assign \m_busy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:126" - case - assign \m_busy_o \dbus__cyc - end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - connect \x_stall_i 1'0 - connect \m_stall_i 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0" -module \l0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 input 2 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 input 3 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 input 4 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 input 5 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 6 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 output 7 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 8 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 9 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 10 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 11 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 12 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 13 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 14 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 15 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 16 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 8 output 17 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 input 18 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 45 output 19 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 20 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 output 21 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 \pimem_ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 \pimem_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 \pimem_ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 \pimem_ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 48 \pimem_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pimem_ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27" - wire width 8 \pimem_x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26" - wire width 48 \pimem_x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 \pimem_ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 64 \pimem_m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pimem_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pimem_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pimem_ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pimem_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30" - wire width 64 \pimem_x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 \pimem_ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28" - wire width 1 \pimem_x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29" - wire width 1 \pimem_x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42" - wire width 1 \pimem_x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37" - wire width 1 \pimem_m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33" - wire width 1 \pimem_x_valid_i - cell \pimem \pimem - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i - connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o - connect \ldst_port0_data_len \pimem_ldst_port0_data_len - connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok - connect \x_mask_i \pimem_x_mask_i - connect \x_addr_i \pimem_x_addr_i - connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o - connect \m_ld_data_o \pimem_m_ld_data_o - connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok - connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i - connect \x_st_data_i \pimem_x_st_data_i - connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o - connect \x_ld_i \pimem_x_ld_i - connect \x_st_i \pimem_x_st_i - connect \x_busy_o \pimem_x_busy_o - connect \m_valid_i \pimem_m_valid_i - connect \x_valid_i \pimem_x_valid_i + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - cell \l0$123 \l0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i - connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o - connect \ldst_port0_data_len$3 \pimem_ldst_port0_data_len - connect \ldst_port0_addr_i$4 \pimem_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok$5 \pimem_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o$6 \pimem_ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o$7 \pimem_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok$8 \pimem_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i_ok$9 \pimem_ldst_port0_st_data_i_ok - connect \ldst_port0_st_data_i$10 \pimem_ldst_port0_st_data_i - connect \ldst_port0_addr_exc_o$11 \pimem_ldst_port0_addr_exc_o + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - cell \lsmem \lsmem - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \x_mask_i \pimem_x_mask_i - connect \x_addr_i \pimem_x_addr_i - connect \m_ld_data_o \pimem_m_ld_data_o - connect \x_st_data_i \pimem_x_st_data_i - connect \x_ld_i \pimem_x_ld_i - connect \x_st_i \pimem_x_st_i - connect \x_busy_o \pimem_x_busy_o - connect \m_valid_i \pimem_m_valid_i - connect \x_valid_i \pimem_x_valid_i - connect \dbus__cyc \dbus__cyc - connect \dbus__ack \dbus__ack - connect \dbus__err \dbus__err - connect \dbus__stb \dbus__stb - connect \dbus__sel \dbus__sel - connect \dbus__dat_r \dbus__dat_r - connect \dbus__adr \dbus__adr - connect \dbus__we \dbus__we - connect \dbus__dat_w \dbus__dat_w + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - connect \pimem_ldst_port0_addr_exc_o 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.int" -module \int - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 1 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 2 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 4 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 5 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 6 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 7 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest1__wen - memory width 64 size 32 \memory - cell $meminit $1 - parameter \MEMID "\\memory" - parameter \ABITS 6 - parameter \WIDTH 64 - parameter \WORDS 32 - parameter \PRIORITY 0 - connect \ADDR 6'000000 - connect \DATA 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185" - wire width 5 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185" - wire width 64 \memory_r_data - cell $memrd \rp_src1 - parameter \MEMID "\\memory" - parameter \ABITS 5 - parameter \WIDTH 64 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK 1'0 - connect \EN 1'1 - connect \ADDR \memory_r_addr - connect \DATA \memory_r_data + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185" - wire width 5 \memory_r_addr$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185" - wire width 64 \memory_r_data$3 - cell $memrd \rp_dmi - parameter \MEMID "\\memory" - parameter \ABITS 5 - parameter \WIDTH 64 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK 1'0 - connect \EN 1'1 - connect \ADDR \memory_r_addr$2 - connect \DATA \memory_r_data$3 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193" - wire width 1 \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193" - wire width 5 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193" - wire width 64 \memory_w_data - cell $memwr \wp_dest1 - parameter \MEMID "\\memory" - parameter \ABITS 5 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \PRIORITY 0 - connect \CLK \coresync_clk - connect \EN { { \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en } } - connect \ADDR \memory_w_addr - connect \DATA \memory_w_data + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - process $group_0 - assign \memory_r_addr 5'00000 - assign \memory_r_addr \src1__addr + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208" - wire width 1 \addrmatch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - cell $and $5 + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_43.core.trial0" +module \trial0$269 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dest1__wen - connect \B \addrmatch - connect \Y $4 - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - switch { \src1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - switch { $4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" - cell $eq $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \dest1__addr - connect \B \src1__addr - connect \Y $6 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_2 - assign \addrmatch 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - switch { \src1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \addrmatch $6 + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - cell $and $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dest1__wen - connect \B \addrmatch + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010100 connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - cell $not $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 connect \Y $10 end - process $group_3 - assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - switch { \src1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - case 1'1 - assign \src1__data_o \dest1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - case 1'1 - assign \src1__data_o \memory_r_data - end + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \dmi__addr - process $group_4 - assign \memory_r_addr$2 5'00000 - assign \memory_r_addr$2 \dmi__addr - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203" - wire width 1 \wr_detect$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208" - wire width 1 \addrmatch$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - cell $and $15 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_43.core.trial1" +module \trial1$270 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dest1__wen - connect \B \addrmatch$13 - connect \Y $14 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - process $group_5 - assign \wr_detect$12 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - switch { \dmi__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - case 1'1 - assign \wr_detect$12 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - case 1'1 - assign \wr_detect$12 1'1 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" - cell $eq $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dest1__addr - connect \B \dmi__addr - connect \Y $16 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_6 - assign \addrmatch$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - switch { \dmi__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010100 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \addrmatch$13 $16 + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - cell $and $19 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_43.core.pe" +module \pe$271 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dest1__wen - connect \B \addrmatch$13 - connect \Y $18 + connect \A \i + connect \B 1'0 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - cell $not $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$12 - connect \Y $20 + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_43.core" +module \core$268 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$269 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$270 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$271 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init end process $group_7 - assign \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - switch { \dmi__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - switch { $18 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - case 1'1 - assign \dmi__data_o \dest1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - switch { $20 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - case 1'1 - assign \dmi__data_o \memory_r_data$3 - end - end + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger process $group_8 - assign \memory_w_addr 5'00000 - assign \memory_w_addr \dest1__addr + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end process $group_9 - assign \memory_w_en 1'0 - assign \memory_w_en \dest1__wen + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 process $group_10 - assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \memory_w_data \dest1__data_i + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root sync init end - connect \dmi__addr 5'00000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0" -module \reg_0 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \src10__ren - connect \B 1'1 - connect \Y $1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src10__ren - connect \B 1'1 - connect \Y $3 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg$next - process $group_1 - assign \src10__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src10__data_o \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src10__data_o \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src10__data_o \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src10__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" case - assign \src10__data_o 4'0000 + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src20__ren - connect \B 1'1 - connect \Y $8 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src20__ren + connect \A \next_bits connect \B 1'1 - connect \Y $10 + connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 - end - process $group_3 - assign \src20__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src20__data_o \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src20__data_o \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src20__data_o \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src20__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src20__data_o 4'0000 - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src30__ren - connect \B 1'1 - connect \Y $15 - end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src30__ren - connect \B 1'1 - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$14 - connect \Y $19 - end - process $group_5 - assign \src30__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src30__data_o \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src30__data_o \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src30__data_o \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src30__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src30__data_o 4'0000 - end - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r0__ren - connect \B 1'1 - connect \Y $22 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r0__ren - connect \B 1'1 - connect \Y $24 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'10100 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 - connect \Y $26 - end - process $group_7 - assign \r0__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r0__data_o \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r0__data_o \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r0__data_o \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r0__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r0__data_o 4'0000 - end - sync init + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" -module \reg_1 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src11__ren - connect \B 1'1 - connect \Y $1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10.core_calculate_stage_43" +module \core_calculate_stage_43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$268 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src11__ren - connect \B 1'1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg$next process $group_1 - assign \src11__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src11__data_o \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src11__data_o \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src11__data_o \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src11__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src11__data_o 4'0000 - end + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src21__ren - connect \B 1'1 - connect \Y $8 - end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src21__ren - connect \B 1'1 - connect \Y $10 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 - end - process $group_3 - assign \src21__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src21__data_o \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src21__data_o \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src21__data_o \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src21__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src21__data_o 4'0000 - end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src31__ren - connect \B 1'1 - connect \Y $15 - end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src31__ren - connect \B 1'1 - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$14 - connect \Y $19 - end - process $group_5 - assign \src31__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src31__data_o \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src31__data_o \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src31__data_o \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src31__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src31__data_o 4'0000 - end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r1__ren - connect \B 1'1 - connect \Y $22 - end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r1__ren - connect \B 1'1 - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 - connect \Y $26 - end - process $group_7 - assign \r1__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r1__data_o \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r1__data_o \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r1__data_o \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r1__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r1__data_o 4'0000 - end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" -module \reg_2 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src12__ren - connect \B 1'1 - connect \Y $1 end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src12__ren - connect \B 1'1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg$next - process $group_1 - assign \src12__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src12__data_o \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src12__data_o \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src12__data_o \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src12__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src12__data_o 4'0000 - end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src22__ren - connect \B 1'1 - connect \Y $8 - end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src22__ren - connect \B 1'1 - connect \Y $10 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - process $group_3 - assign \src22__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src22__data_o \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src22__data_o \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src22__data_o \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src22__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src22__data_o 4'0000 - end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src32__ren - connect \B 1'1 - connect \Y $15 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src32__ren - connect \B 1'1 - connect \Y $17 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$14 - connect \Y $19 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - process $group_5 - assign \src32__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src32__data_o \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src32__data_o \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src32__data_o \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src32__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src32__data_o 4'0000 - end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r2__ren - connect \B 1'1 - connect \Y $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r2__ren - connect \B 1'1 - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 - connect \Y $26 - end - process $group_7 - assign \r2__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r2__data_o \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r2__data_o \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r2__data_o \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r2__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r2__data_o 4'0000 - end - sync init - end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end - sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" -module \reg_3 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_10" +module \pipe_middle_10 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src13__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src13__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src33__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src33__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest23__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest23__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w3__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src13__ren - connect \B 1'1 - connect \Y $1 - end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src13__ren - connect \B 1'1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg$next - process $group_1 - assign \src13__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src13__data_o \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src13__data_o \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src13__data_o \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src13__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src13__data_o 4'0000 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src23__ren - connect \B 1'1 - connect \Y $8 - end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src23__ren - connect \B 1'1 - connect \Y $10 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 - end - process $group_3 - assign \src23__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src23__data_o \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src23__data_o \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src23__data_o \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src23__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src23__data_o 4'0000 - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 41 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$254 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src33__ren - connect \B 1'1 - connect \Y $15 + cell \n$255 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_40_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_40_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_40_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_40_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_40_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_40_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_40_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_40_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_40_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_40_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_40_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_40_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_40_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_40_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_40_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_40_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_40_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_40_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_40_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_40_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_40_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_40_muxid$34 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_40_logical_op__insn_type$35 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_40_logical_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_40_logical_op__imm_data__imm$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__imm_data__imm_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__invert_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_40_logical_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__write_cr0$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_40_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_40_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_40_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_40_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_40_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_40_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_40_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_40_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_40_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_40_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_40_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_40_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_40_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_40_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_40_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_40_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_40_compare_rhs$66 + cell \core_calculate_stage_40 \core_calculate_stage_40 + connect \muxid \core_calculate_stage_40_muxid + connect \logical_op__insn_type \core_calculate_stage_40_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_40_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_40_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_40_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_40_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_40_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_40_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_40_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_40_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_40_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_40_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_40_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_40_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_40_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_40_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_40_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_40_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_40_logical_op__insn + connect \ra \core_calculate_stage_40_ra + connect \rb \core_calculate_stage_40_rb + connect \xer_so \core_calculate_stage_40_xer_so + connect \divisor_neg \core_calculate_stage_40_divisor_neg + connect \dividend_neg \core_calculate_stage_40_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_40_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_40_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_40_div_by_zero + connect \divisor_radicand \core_calculate_stage_40_divisor_radicand + connect \operation \core_calculate_stage_40_operation + connect \quotient_root \core_calculate_stage_40_quotient_root + connect \root_times_radicand \core_calculate_stage_40_root_times_radicand + connect \compare_lhs \core_calculate_stage_40_compare_lhs + connect \compare_rhs \core_calculate_stage_40_compare_rhs + connect \muxid$1 \core_calculate_stage_40_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_40_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_40_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_40_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_40_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_40_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_40_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_40_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_40_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_40_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_40_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_40_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_40_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_40_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_40_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_40_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_40_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_40_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_40_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_40_ra$53 + connect \rb$21 \core_calculate_stage_40_rb$54 + connect \xer_so$22 \core_calculate_stage_40_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_40_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_40_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_40_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_40_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_40_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_40_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_40_operation$62 + connect \quotient_root$30 \core_calculate_stage_40_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_40_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_40_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_40_compare_rhs$66 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src33__ren - connect \B 1'1 - connect \Y $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_41_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_41_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_41_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_41_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_41_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_41_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_41_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_41_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_41_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_41_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_41_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_41_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_41_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_41_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_41_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_41_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_41_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_41_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_41_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_41_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_41_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_41_muxid$67 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_41_logical_op__insn_type$68 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_41_logical_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_41_logical_op__imm_data__imm$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__imm_data__imm_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__rc__rc_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_41_logical_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__invert_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__write_cr0$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_41_logical_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_41_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_41_logical_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_41_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_41_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_41_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_41_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_41_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_41_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_41_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_41_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_41_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_41_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_41_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_41_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_41_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_41_compare_rhs$99 + cell \core_calculate_stage_41 \core_calculate_stage_41 + connect \muxid \core_calculate_stage_41_muxid + connect \logical_op__insn_type \core_calculate_stage_41_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_41_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_41_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_41_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_41_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_41_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_41_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_41_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_41_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_41_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_41_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_41_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_41_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_41_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_41_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_41_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_41_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_41_logical_op__insn + connect \ra \core_calculate_stage_41_ra + connect \rb \core_calculate_stage_41_rb + connect \xer_so \core_calculate_stage_41_xer_so + connect \divisor_neg \core_calculate_stage_41_divisor_neg + connect \dividend_neg \core_calculate_stage_41_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_41_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_41_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_41_div_by_zero + connect \divisor_radicand \core_calculate_stage_41_divisor_radicand + connect \operation \core_calculate_stage_41_operation + connect \quotient_root \core_calculate_stage_41_quotient_root + connect \root_times_radicand \core_calculate_stage_41_root_times_radicand + connect \compare_lhs \core_calculate_stage_41_compare_lhs + connect \compare_rhs \core_calculate_stage_41_compare_rhs + connect \muxid$1 \core_calculate_stage_41_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_41_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_41_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_41_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_41_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_41_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_41_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_41_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_41_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_41_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_41_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_41_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_41_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_41_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_41_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_41_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_41_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_41_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_41_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_41_ra$86 + connect \rb$21 \core_calculate_stage_41_rb$87 + connect \xer_so$22 \core_calculate_stage_41_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_41_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_41_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_41_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_41_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_41_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_41_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_41_operation$95 + connect \quotient_root$30 \core_calculate_stage_41_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_41_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_41_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_41_compare_rhs$99 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$14 - connect \Y $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_42_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_42_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_42_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_42_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_42_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_42_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_42_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_42_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_42_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_42_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_42_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_42_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_42_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_42_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_42_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_42_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_42_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_42_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_42_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_42_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_42_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_42_muxid$100 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_42_logical_op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_42_logical_op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_42_logical_op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__rc__rc$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__rc__rc_ok$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__oe__oe$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_42_logical_op__input_carry$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__invert_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__write_cr0$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__output_carry$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__is_32bit$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_42_logical_op__is_signed$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_42_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_42_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_42_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_42_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_42_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_42_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_42_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_42_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_42_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_42_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_42_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_42_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_42_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_42_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_42_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_42_compare_rhs$132 + cell \core_calculate_stage_42 \core_calculate_stage_42 + connect \muxid \core_calculate_stage_42_muxid + connect \logical_op__insn_type \core_calculate_stage_42_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_42_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_42_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_42_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_42_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_42_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_42_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_42_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_42_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_42_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_42_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_42_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_42_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_42_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_42_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_42_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_42_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_42_logical_op__insn + connect \ra \core_calculate_stage_42_ra + connect \rb \core_calculate_stage_42_rb + connect \xer_so \core_calculate_stage_42_xer_so + connect \divisor_neg \core_calculate_stage_42_divisor_neg + connect \dividend_neg \core_calculate_stage_42_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_42_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_42_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_42_div_by_zero + connect \divisor_radicand \core_calculate_stage_42_divisor_radicand + connect \operation \core_calculate_stage_42_operation + connect \quotient_root \core_calculate_stage_42_quotient_root + connect \root_times_radicand \core_calculate_stage_42_root_times_radicand + connect \compare_lhs \core_calculate_stage_42_compare_lhs + connect \compare_rhs \core_calculate_stage_42_compare_rhs + connect \muxid$1 \core_calculate_stage_42_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_42_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_42_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_42_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_42_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_42_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_42_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_42_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_42_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_42_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_42_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_42_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_42_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_42_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_42_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_42_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_42_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_42_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_42_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_42_ra$119 + connect \rb$21 \core_calculate_stage_42_rb$120 + connect \xer_so$22 \core_calculate_stage_42_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_42_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_42_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_42_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_42_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_42_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_42_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_42_operation$128 + connect \quotient_root$30 \core_calculate_stage_42_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_42_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_42_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_42_compare_rhs$132 end - process $group_5 - assign \src33__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src33__data_o \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src33__data_o \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src33__data_o \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src33__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src33__data_o 4'0000 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_43_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_43_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_43_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_43_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_43_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_43_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_43_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_43_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_43_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_43_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_43_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_43_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_43_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_43_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_43_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_43_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_43_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_43_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_43_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_43_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_43_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_43_muxid$133 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_43_logical_op__insn_type$134 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_43_logical_op__fn_unit$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_43_logical_op__imm_data__imm$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__imm_data__imm_ok$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__rc__rc$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__rc__rc_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__oe__oe$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__oe__oe_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__invert_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_43_logical_op__input_carry$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__invert_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__write_cr0$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__output_carry$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_43_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_43_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_43_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_43_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_43_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_43_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_43_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_43_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_43_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_43_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_43_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_43_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_43_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_43_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_43_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_43_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_43_compare_rhs$165 + cell \core_calculate_stage_43 \core_calculate_stage_43 + connect \muxid \core_calculate_stage_43_muxid + connect \logical_op__insn_type \core_calculate_stage_43_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_43_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_43_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_43_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_43_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_43_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_43_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_43_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_43_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_43_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_43_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_43_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_43_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_43_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_43_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_43_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_43_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_43_logical_op__insn + connect \ra \core_calculate_stage_43_ra + connect \rb \core_calculate_stage_43_rb + connect \xer_so \core_calculate_stage_43_xer_so + connect \divisor_neg \core_calculate_stage_43_divisor_neg + connect \dividend_neg \core_calculate_stage_43_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_43_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_43_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_43_div_by_zero + connect \divisor_radicand \core_calculate_stage_43_divisor_radicand + connect \operation \core_calculate_stage_43_operation + connect \quotient_root \core_calculate_stage_43_quotient_root + connect \root_times_radicand \core_calculate_stage_43_root_times_radicand + connect \compare_lhs \core_calculate_stage_43_compare_lhs + connect \compare_rhs \core_calculate_stage_43_compare_rhs + connect \muxid$1 \core_calculate_stage_43_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_43_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_43_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_43_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_43_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_43_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_43_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_43_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_43_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_43_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_43_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_43_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_43_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_43_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_43_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_43_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_43_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_43_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_43_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_43_ra$152 + connect \rb$21 \core_calculate_stage_43_rb$153 + connect \xer_so$22 \core_calculate_stage_43_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_43_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_43_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_43_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_43_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_43_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_43_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_43_operation$161 + connect \quotient_root$30 \core_calculate_stage_43_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_43_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_43_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_43_compare_rhs$165 + end + process $group_0 + assign \core_calculate_stage_40_muxid 2'00 + assign \core_calculate_stage_40_muxid \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r3__ren - connect \B 1'1 - connect \Y $22 + process $group_1 + assign \core_calculate_stage_40_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_40_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_40_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_40_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_40_logical_op__rc__rc 1'0 + assign \core_calculate_stage_40_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_40_logical_op__oe__oe 1'0 + assign \core_calculate_stage_40_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_40_logical_op__invert_in 1'0 + assign \core_calculate_stage_40_logical_op__zero_a 1'0 + assign \core_calculate_stage_40_logical_op__input_carry 2'00 + assign \core_calculate_stage_40_logical_op__invert_out 1'0 + assign \core_calculate_stage_40_logical_op__write_cr0 1'0 + assign \core_calculate_stage_40_logical_op__output_carry 1'0 + assign \core_calculate_stage_40_logical_op__is_32bit 1'0 + assign \core_calculate_stage_40_logical_op__is_signed 1'0 + assign \core_calculate_stage_40_logical_op__data_len 4'0000 + assign \core_calculate_stage_40_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_40_logical_op__insn \core_calculate_stage_40_logical_op__data_len \core_calculate_stage_40_logical_op__is_signed \core_calculate_stage_40_logical_op__is_32bit \core_calculate_stage_40_logical_op__output_carry \core_calculate_stage_40_logical_op__write_cr0 \core_calculate_stage_40_logical_op__invert_out \core_calculate_stage_40_logical_op__input_carry \core_calculate_stage_40_logical_op__zero_a \core_calculate_stage_40_logical_op__invert_in { \core_calculate_stage_40_logical_op__oe__oe_ok \core_calculate_stage_40_logical_op__oe__oe } { \core_calculate_stage_40_logical_op__rc__rc_ok \core_calculate_stage_40_logical_op__rc__rc } { \core_calculate_stage_40_logical_op__imm_data__imm_ok \core_calculate_stage_40_logical_op__imm_data__imm } \core_calculate_stage_40_logical_op__fn_unit \core_calculate_stage_40_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_19 + assign \core_calculate_stage_40_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_40_ra \ra sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r3__ren - connect \B 1'1 - connect \Y $24 + process $group_20 + assign \core_calculate_stage_40_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_40_rb \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 - connect \Y $26 + process $group_21 + assign \core_calculate_stage_40_xer_so 1'0 + assign \core_calculate_stage_40_xer_so \xer_so + sync init end - process $group_7 - assign \r3__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r3__data_o \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r3__data_o \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r3__data_o \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r3__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r3__data_o 4'0000 - end + process $group_22 + assign \core_calculate_stage_40_divisor_neg 1'0 + assign \core_calculate_stage_40_divisor_neg \divisor_neg sync init end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end + process $group_23 + assign \core_calculate_stage_40_dividend_neg 1'0 + assign \core_calculate_stage_40_dividend_neg \dividend_neg sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" -module \reg_4 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src14__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src14__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src34__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src34__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest14__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest14__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest24__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest24__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r4__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r4__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w4__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w4__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src14__ren - connect \B 1'1 - connect \Y $1 + process $group_24 + assign \core_calculate_stage_40_dive_abs_ov32 1'0 + assign \core_calculate_stage_40_dive_abs_ov32 \dive_abs_ov32 + sync init end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_25 + assign \core_calculate_stage_40_dive_abs_ov64 1'0 + assign \core_calculate_stage_40_dive_abs_ov64 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src14__ren - connect \B 1'1 - connect \Y $3 + process $group_26 + assign \core_calculate_stage_40_div_by_zero 1'0 + assign \core_calculate_stage_40_div_by_zero \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + process $group_27 + assign \core_calculate_stage_40_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_40_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg$next - process $group_1 - assign \src14__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src14__data_o \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src14__data_o \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src14__data_o \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src14__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src14__data_o 4'0000 - end + process $group_28 + assign \core_calculate_stage_40_operation 2'00 + assign \core_calculate_stage_40_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src24__ren - connect \B 1'1 - connect \Y $8 + process $group_29 + assign \core_calculate_stage_40_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_40_quotient_root \quotient_root + sync init end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_30 + assign \core_calculate_stage_40_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_40_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src24__ren - connect \B 1'1 - connect \Y $10 + process $group_31 + assign \core_calculate_stage_40_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_40_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 + process $group_32 + assign \core_calculate_stage_40_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_40_compare_rhs \compare_rhs + sync init end - process $group_3 - assign \src24__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src24__data_o \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src24__data_o \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src24__data_o \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src24__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src24__data_o 4'0000 - end + process $group_33 + assign \core_calculate_stage_41_muxid 2'00 + assign \core_calculate_stage_41_muxid \core_calculate_stage_40_muxid$34 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src34__ren - connect \B 1'1 - connect \Y $15 + process $group_34 + assign \core_calculate_stage_41_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_41_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_41_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_41_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_41_logical_op__rc__rc 1'0 + assign \core_calculate_stage_41_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_41_logical_op__oe__oe 1'0 + assign \core_calculate_stage_41_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_41_logical_op__invert_in 1'0 + assign \core_calculate_stage_41_logical_op__zero_a 1'0 + assign \core_calculate_stage_41_logical_op__input_carry 2'00 + assign \core_calculate_stage_41_logical_op__invert_out 1'0 + assign \core_calculate_stage_41_logical_op__write_cr0 1'0 + assign \core_calculate_stage_41_logical_op__output_carry 1'0 + assign \core_calculate_stage_41_logical_op__is_32bit 1'0 + assign \core_calculate_stage_41_logical_op__is_signed 1'0 + assign \core_calculate_stage_41_logical_op__data_len 4'0000 + assign \core_calculate_stage_41_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_41_logical_op__insn \core_calculate_stage_41_logical_op__data_len \core_calculate_stage_41_logical_op__is_signed \core_calculate_stage_41_logical_op__is_32bit \core_calculate_stage_41_logical_op__output_carry \core_calculate_stage_41_logical_op__write_cr0 \core_calculate_stage_41_logical_op__invert_out \core_calculate_stage_41_logical_op__input_carry \core_calculate_stage_41_logical_op__zero_a \core_calculate_stage_41_logical_op__invert_in { \core_calculate_stage_41_logical_op__oe__oe_ok \core_calculate_stage_41_logical_op__oe__oe } { \core_calculate_stage_41_logical_op__rc__rc_ok \core_calculate_stage_41_logical_op__rc__rc } { \core_calculate_stage_41_logical_op__imm_data__imm_ok \core_calculate_stage_41_logical_op__imm_data__imm } \core_calculate_stage_41_logical_op__fn_unit \core_calculate_stage_41_logical_op__insn_type } { \core_calculate_stage_40_logical_op__insn$52 \core_calculate_stage_40_logical_op__data_len$51 \core_calculate_stage_40_logical_op__is_signed$50 \core_calculate_stage_40_logical_op__is_32bit$49 \core_calculate_stage_40_logical_op__output_carry$48 \core_calculate_stage_40_logical_op__write_cr0$47 \core_calculate_stage_40_logical_op__invert_out$46 \core_calculate_stage_40_logical_op__input_carry$45 \core_calculate_stage_40_logical_op__zero_a$44 \core_calculate_stage_40_logical_op__invert_in$43 { \core_calculate_stage_40_logical_op__oe__oe_ok$42 \core_calculate_stage_40_logical_op__oe__oe$41 } { \core_calculate_stage_40_logical_op__rc__rc_ok$40 \core_calculate_stage_40_logical_op__rc__rc$39 } { \core_calculate_stage_40_logical_op__imm_data__imm_ok$38 \core_calculate_stage_40_logical_op__imm_data__imm$37 } \core_calculate_stage_40_logical_op__fn_unit$36 \core_calculate_stage_40_logical_op__insn_type$35 } + sync init end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_52 + assign \core_calculate_stage_41_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_41_ra \core_calculate_stage_40_ra$53 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src34__ren - connect \B 1'1 - connect \Y $17 + process $group_53 + assign \core_calculate_stage_41_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_41_rb \core_calculate_stage_40_rb$54 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$14 - connect \Y $19 + process $group_54 + assign \core_calculate_stage_41_xer_so 1'0 + assign \core_calculate_stage_41_xer_so \core_calculate_stage_40_xer_so$55 + sync init end - process $group_5 - assign \src34__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src34__data_o \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src34__data_o \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src34__data_o \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src34__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src34__data_o 4'0000 - end + process $group_55 + assign \core_calculate_stage_41_divisor_neg 1'0 + assign \core_calculate_stage_41_divisor_neg \core_calculate_stage_40_divisor_neg$56 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r4__ren - connect \B 1'1 - connect \Y $22 + process $group_56 + assign \core_calculate_stage_41_dividend_neg 1'0 + assign \core_calculate_stage_41_dividend_neg \core_calculate_stage_40_dividend_neg$57 + sync init end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_57 + assign \core_calculate_stage_41_dive_abs_ov32 1'0 + assign \core_calculate_stage_41_dive_abs_ov32 \core_calculate_stage_40_dive_abs_ov32$58 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r4__ren - connect \B 1'1 - connect \Y $24 + process $group_58 + assign \core_calculate_stage_41_dive_abs_ov64 1'0 + assign \core_calculate_stage_41_dive_abs_ov64 \core_calculate_stage_40_dive_abs_ov64$59 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 - connect \Y $26 + process $group_59 + assign \core_calculate_stage_41_div_by_zero 1'0 + assign \core_calculate_stage_41_div_by_zero \core_calculate_stage_40_div_by_zero$60 + sync init end - process $group_7 - assign \r4__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r4__data_o \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r4__data_o \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r4__data_o \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r4__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r4__data_o 4'0000 - end + process $group_60 + assign \core_calculate_stage_41_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_41_divisor_radicand \core_calculate_stage_40_divisor_radicand$61 sync init end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end + process $group_61 + assign \core_calculate_stage_41_operation 2'00 + assign \core_calculate_stage_41_operation \core_calculate_stage_40_operation$62 sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" -module \reg_5 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src15__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src15__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src35__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src35__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest15__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest15__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest25__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest25__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r5__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r5__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w5__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w5__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src15__ren - connect \B 1'1 - connect \Y $1 + process $group_62 + assign \core_calculate_stage_41_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_41_quotient_root \core_calculate_stage_40_quotient_root$63 + sync init end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_63 + assign \core_calculate_stage_41_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_41_root_times_radicand \core_calculate_stage_40_root_times_radicand$64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src15__ren - connect \B 1'1 - connect \Y $3 + process $group_64 + assign \core_calculate_stage_41_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_41_compare_lhs \core_calculate_stage_40_compare_lhs$65 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + process $group_65 + assign \core_calculate_stage_41_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_41_compare_rhs \core_calculate_stage_40_compare_rhs$66 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg$next - process $group_1 - assign \src15__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src15__data_o \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src15__data_o \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src15__data_o \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src15__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src15__data_o 4'0000 - end + process $group_66 + assign \core_calculate_stage_42_muxid 2'00 + assign \core_calculate_stage_42_muxid \core_calculate_stage_41_muxid$67 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src25__ren - connect \B 1'1 - connect \Y $8 + process $group_67 + assign \core_calculate_stage_42_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_42_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_42_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_42_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_42_logical_op__rc__rc 1'0 + assign \core_calculate_stage_42_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_42_logical_op__oe__oe 1'0 + assign \core_calculate_stage_42_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_42_logical_op__invert_in 1'0 + assign \core_calculate_stage_42_logical_op__zero_a 1'0 + assign \core_calculate_stage_42_logical_op__input_carry 2'00 + assign \core_calculate_stage_42_logical_op__invert_out 1'0 + assign \core_calculate_stage_42_logical_op__write_cr0 1'0 + assign \core_calculate_stage_42_logical_op__output_carry 1'0 + assign \core_calculate_stage_42_logical_op__is_32bit 1'0 + assign \core_calculate_stage_42_logical_op__is_signed 1'0 + assign \core_calculate_stage_42_logical_op__data_len 4'0000 + assign \core_calculate_stage_42_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_42_logical_op__insn \core_calculate_stage_42_logical_op__data_len \core_calculate_stage_42_logical_op__is_signed \core_calculate_stage_42_logical_op__is_32bit \core_calculate_stage_42_logical_op__output_carry \core_calculate_stage_42_logical_op__write_cr0 \core_calculate_stage_42_logical_op__invert_out \core_calculate_stage_42_logical_op__input_carry \core_calculate_stage_42_logical_op__zero_a \core_calculate_stage_42_logical_op__invert_in { \core_calculate_stage_42_logical_op__oe__oe_ok \core_calculate_stage_42_logical_op__oe__oe } { \core_calculate_stage_42_logical_op__rc__rc_ok \core_calculate_stage_42_logical_op__rc__rc } { \core_calculate_stage_42_logical_op__imm_data__imm_ok \core_calculate_stage_42_logical_op__imm_data__imm } \core_calculate_stage_42_logical_op__fn_unit \core_calculate_stage_42_logical_op__insn_type } { \core_calculate_stage_41_logical_op__insn$85 \core_calculate_stage_41_logical_op__data_len$84 \core_calculate_stage_41_logical_op__is_signed$83 \core_calculate_stage_41_logical_op__is_32bit$82 \core_calculate_stage_41_logical_op__output_carry$81 \core_calculate_stage_41_logical_op__write_cr0$80 \core_calculate_stage_41_logical_op__invert_out$79 \core_calculate_stage_41_logical_op__input_carry$78 \core_calculate_stage_41_logical_op__zero_a$77 \core_calculate_stage_41_logical_op__invert_in$76 { \core_calculate_stage_41_logical_op__oe__oe_ok$75 \core_calculate_stage_41_logical_op__oe__oe$74 } { \core_calculate_stage_41_logical_op__rc__rc_ok$73 \core_calculate_stage_41_logical_op__rc__rc$72 } { \core_calculate_stage_41_logical_op__imm_data__imm_ok$71 \core_calculate_stage_41_logical_op__imm_data__imm$70 } \core_calculate_stage_41_logical_op__fn_unit$69 \core_calculate_stage_41_logical_op__insn_type$68 } + sync init end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_85 + assign \core_calculate_stage_42_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_42_ra \core_calculate_stage_41_ra$86 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 + process $group_86 + assign \core_calculate_stage_42_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_42_rb \core_calculate_stage_41_rb$87 + sync init + end + process $group_87 + assign \core_calculate_stage_42_xer_so 1'0 + assign \core_calculate_stage_42_xer_so \core_calculate_stage_41_xer_so$88 + sync init + end + process $group_88 + assign \core_calculate_stage_42_divisor_neg 1'0 + assign \core_calculate_stage_42_divisor_neg \core_calculate_stage_41_divisor_neg$89 + sync init + end + process $group_89 + assign \core_calculate_stage_42_dividend_neg 1'0 + assign \core_calculate_stage_42_dividend_neg \core_calculate_stage_41_dividend_neg$90 + sync init + end + process $group_90 + assign \core_calculate_stage_42_dive_abs_ov32 1'0 + assign \core_calculate_stage_42_dive_abs_ov32 \core_calculate_stage_41_dive_abs_ov32$91 + sync init + end + process $group_91 + assign \core_calculate_stage_42_dive_abs_ov64 1'0 + assign \core_calculate_stage_42_dive_abs_ov64 \core_calculate_stage_41_dive_abs_ov64$92 + sync init + end + process $group_92 + assign \core_calculate_stage_42_div_by_zero 1'0 + assign \core_calculate_stage_42_div_by_zero \core_calculate_stage_41_div_by_zero$93 + sync init + end + process $group_93 + assign \core_calculate_stage_42_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_42_divisor_radicand \core_calculate_stage_41_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_42_operation 2'00 + assign \core_calculate_stage_42_operation \core_calculate_stage_41_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_42_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_42_quotient_root \core_calculate_stage_41_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_42_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_42_root_times_radicand \core_calculate_stage_41_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_42_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_42_compare_lhs \core_calculate_stage_41_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_42_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_42_compare_rhs \core_calculate_stage_41_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_43_muxid 2'00 + assign \core_calculate_stage_43_muxid \core_calculate_stage_42_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_43_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_43_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_43_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_43_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_43_logical_op__rc__rc 1'0 + assign \core_calculate_stage_43_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_43_logical_op__oe__oe 1'0 + assign \core_calculate_stage_43_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_43_logical_op__invert_in 1'0 + assign \core_calculate_stage_43_logical_op__zero_a 1'0 + assign \core_calculate_stage_43_logical_op__input_carry 2'00 + assign \core_calculate_stage_43_logical_op__invert_out 1'0 + assign \core_calculate_stage_43_logical_op__write_cr0 1'0 + assign \core_calculate_stage_43_logical_op__output_carry 1'0 + assign \core_calculate_stage_43_logical_op__is_32bit 1'0 + assign \core_calculate_stage_43_logical_op__is_signed 1'0 + assign \core_calculate_stage_43_logical_op__data_len 4'0000 + assign \core_calculate_stage_43_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_43_logical_op__insn \core_calculate_stage_43_logical_op__data_len \core_calculate_stage_43_logical_op__is_signed \core_calculate_stage_43_logical_op__is_32bit \core_calculate_stage_43_logical_op__output_carry \core_calculate_stage_43_logical_op__write_cr0 \core_calculate_stage_43_logical_op__invert_out \core_calculate_stage_43_logical_op__input_carry \core_calculate_stage_43_logical_op__zero_a \core_calculate_stage_43_logical_op__invert_in { \core_calculate_stage_43_logical_op__oe__oe_ok \core_calculate_stage_43_logical_op__oe__oe } { \core_calculate_stage_43_logical_op__rc__rc_ok \core_calculate_stage_43_logical_op__rc__rc } { \core_calculate_stage_43_logical_op__imm_data__imm_ok \core_calculate_stage_43_logical_op__imm_data__imm } \core_calculate_stage_43_logical_op__fn_unit \core_calculate_stage_43_logical_op__insn_type } { \core_calculate_stage_42_logical_op__insn$118 \core_calculate_stage_42_logical_op__data_len$117 \core_calculate_stage_42_logical_op__is_signed$116 \core_calculate_stage_42_logical_op__is_32bit$115 \core_calculate_stage_42_logical_op__output_carry$114 \core_calculate_stage_42_logical_op__write_cr0$113 \core_calculate_stage_42_logical_op__invert_out$112 \core_calculate_stage_42_logical_op__input_carry$111 \core_calculate_stage_42_logical_op__zero_a$110 \core_calculate_stage_42_logical_op__invert_in$109 { \core_calculate_stage_42_logical_op__oe__oe_ok$108 \core_calculate_stage_42_logical_op__oe__oe$107 } { \core_calculate_stage_42_logical_op__rc__rc_ok$106 \core_calculate_stage_42_logical_op__rc__rc$105 } { \core_calculate_stage_42_logical_op__imm_data__imm_ok$104 \core_calculate_stage_42_logical_op__imm_data__imm$103 } \core_calculate_stage_42_logical_op__fn_unit$102 \core_calculate_stage_42_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_43_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_43_ra \core_calculate_stage_42_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_43_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_43_rb \core_calculate_stage_42_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_43_xer_so 1'0 + assign \core_calculate_stage_43_xer_so \core_calculate_stage_42_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_43_divisor_neg 1'0 + assign \core_calculate_stage_43_divisor_neg \core_calculate_stage_42_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_43_dividend_neg 1'0 + assign \core_calculate_stage_43_dividend_neg \core_calculate_stage_42_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_43_dive_abs_ov32 1'0 + assign \core_calculate_stage_43_dive_abs_ov32 \core_calculate_stage_42_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_43_dive_abs_ov64 1'0 + assign \core_calculate_stage_43_dive_abs_ov64 \core_calculate_stage_42_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_43_div_by_zero 1'0 + assign \core_calculate_stage_43_div_by_zero \core_calculate_stage_42_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_43_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_43_divisor_radicand \core_calculate_stage_42_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_43_operation 2'00 + assign \core_calculate_stage_43_operation \core_calculate_stage_42_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_43_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_43_quotient_root \core_calculate_stage_42_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_43_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_43_root_times_radicand \core_calculate_stage_42_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_43_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_43_compare_lhs \core_calculate_stage_42_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_43_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_43_compare_rhs \core_calculate_stage_42_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src25__ren - connect \B 1'1 - connect \Y $10 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 + sync init end - process $group_3 - assign \src25__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_43_muxid$133 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_43_logical_op__insn$151 \core_calculate_stage_43_logical_op__data_len$150 \core_calculate_stage_43_logical_op__is_signed$149 \core_calculate_stage_43_logical_op__is_32bit$148 \core_calculate_stage_43_logical_op__output_carry$147 \core_calculate_stage_43_logical_op__write_cr0$146 \core_calculate_stage_43_logical_op__invert_out$145 \core_calculate_stage_43_logical_op__input_carry$144 \core_calculate_stage_43_logical_op__zero_a$143 \core_calculate_stage_43_logical_op__invert_in$142 { \core_calculate_stage_43_logical_op__oe__oe_ok$141 \core_calculate_stage_43_logical_op__oe__oe$140 } { \core_calculate_stage_43_logical_op__rc__rc_ok$139 \core_calculate_stage_43_logical_op__rc__rc$138 } { \core_calculate_stage_43_logical_op__imm_data__imm_ok$137 \core_calculate_stage_43_logical_op__imm_data__imm$136 } \core_calculate_stage_43_logical_op__fn_unit$135 \core_calculate_stage_43_logical_op__insn_type$134 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_43_ra$152 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_43_rb$153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_43_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_43_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_43_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_43_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_43_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_43_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_43_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_43_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_43_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_43_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_43_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_43_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src25__data_o \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src25__data_o \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src25__data_o \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src25__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src25__data_o 4'0000 + assign \r_busy$next 1'0 end sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src35__ren - connect \B 1'1 - connect \Y $15 + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 end sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next + end + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end + sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next + end + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.p" +module \p$272 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src35__ren - connect \B 1'1 - connect \Y $17 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.n" +module \n$273 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_detect$14 - connect \Y $19 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 end - process $group_5 - assign \src35__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src35__data_o \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src35__data_o \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src35__data_o \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src35__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src35__data_o 4'0000 - end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $23 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_44.core.trial0" +module \trial0$275 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r5__ren + connect \A \operation connect \B 1'1 - connect \Y $22 + connect \Y $1 end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r5__ren + connect \A \operation connect \B 1'1 - connect \Y $24 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 - connect \Y $26 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010011 + connect \Y $8 end - process $group_7 - assign \r5__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r5__data_o \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r5__data_o \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r5__data_o \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r5__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r5__data_o 4'0000 - end - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \reg$next 4'0000 + assign \trial_compare_rhs $7 [191:0] end sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" -module \reg_6 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src16__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src16__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src36__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src36__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest16__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest16__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest26__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest26__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r6__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r6__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w6__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w6__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_44.core.trial1" +module \trial1$276 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src16__ren + connect \A \operation connect \B 1'1 connect \Y $1 end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src16__ren + connect \A \operation connect \B 1'1 - connect \Y $3 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010011 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 process $group_1 - assign \src16__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src16__data_o \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src16__data_o \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src16__data_o \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src16__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src16__data_o 4'0000 + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_44.core.pe" +module \pe$277 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src26__ren - connect \B 1'1 - connect \Y $8 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_44.core" +module \core$274 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$275 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$276 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$277 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init end process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \src26__ren - connect \B 1'1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags connect \Y $12 end - process $group_3 - assign \src26__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src26__data_o \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src26__data_o \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src26__data_o \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src26__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src26__data_o 4'0000 - end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src36__ren + parameter \Y_WIDTH 2 + connect \A \pe_o connect \B 1'1 - connect \Y $15 + connect \Y $17 end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src36__ren - connect \B 1'1 - connect \Y $17 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_detect$14 - connect \Y $19 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_5 - assign \src36__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src36__data_o \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src36__data_o \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src36__data_o \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src36__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src36__data_o 4'0000 - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'10011 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_44" +module \core_calculate_stage_44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$274 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_45.core.trial0" +module \trial0$279 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r6__ren + connect \A \operation connect \B 1'1 - connect \Y $22 + connect \Y $1 end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r6__ren + connect \A \operation connect \B 1'1 - connect \Y $24 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 - connect \Y $26 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010010 + connect \Y $8 end - process $group_7 - assign \r6__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r6__data_o \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r6__data_o \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r6__data_o \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r6__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r6__data_o 4'0000 - end - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \reg$next 4'0000 + assign \trial_compare_rhs $7 [191:0] end sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" -module \reg_7 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src17__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src17__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src37__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src37__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest17__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest17__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest27__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest27__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r7__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 14 \w7__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \w7__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_45.core.trial1" +module \trial1$280 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src17__ren + connect \A \operation connect \B 1'1 connect \Y $1 end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src17__ren + connect \A \operation connect \B 1'1 - connect \Y $3 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010010 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 process $group_1 - assign \src17__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src17__data_o \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src17__data_o \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src17__data_o \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src17__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src17__data_o 4'0000 + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_45.core.pe" +module \pe$281 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src27__ren - connect \B 1'1 - connect \Y $8 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_45.core" +module \core$278 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$279 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$280 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$281 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init end process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \src27__ren - connect \B 1'1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags connect \Y $12 end - process $group_3 - assign \src27__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src27__data_o \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src27__data_o \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src27__data_o \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src27__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src27__data_o 4'0000 - end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src37__ren + parameter \Y_WIDTH 2 + connect \A \pe_o connect \B 1'1 - connect \Y $15 + connect \Y $17 end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src37__ren - connect \B 1'1 - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$14 + connect \A \next_bits + connect \B 1'0 connect \Y $19 end - process $group_5 - assign \src37__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src37__data_o \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src37__data_o \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src37__data_o \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src37__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src37__data_o 4'0000 - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r7__ren + connect \A \next_bits connect \B 1'1 connect \Y $22 end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r7__ren - connect \B 1'1 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs connect \Y $26 end - process $group_7 - assign \r7__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r7__data_o \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r7__data_o \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r7__data_o \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r7__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r7__data_o 4'0000 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'10010 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr" -module \cr - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 output 1 \full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 2 \full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 4 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 6 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 8 \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 input 9 \full_wr__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 10 \full_wr__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 12 \wen - attribute \src "simple/issuer.py:89" - wire width 1 input 13 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_w0__wen - cell \reg_0 \reg_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src10__ren \reg_0_src10__ren - connect \src10__data_o \reg_0_src10__data_o - connect \src20__ren \reg_0_src20__ren - connect \src20__data_o \reg_0_src20__data_o - connect \src30__ren \reg_0_src30__ren - connect \src30__data_o \reg_0_src30__data_o - connect \dest10__wen \reg_0_dest10__wen - connect \dest10__data_i \reg_0_dest10__data_i - connect \dest20__wen \reg_0_dest20__wen - connect \dest20__data_i \reg_0_dest20__data_i - connect \r0__data_o \reg_0_r0__data_o - connect \r0__ren \reg_0_r0__ren - connect \w0__data_i \reg_0_w0__data_i - connect \w0__wen \reg_0_w0__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_w1__wen - cell \reg_1 \reg_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src11__ren \reg_1_src11__ren - connect \src11__data_o \reg_1_src11__data_o - connect \src21__ren \reg_1_src21__ren - connect \src21__data_o \reg_1_src21__data_o - connect \src31__ren \reg_1_src31__ren - connect \src31__data_o \reg_1_src31__data_o - connect \dest11__wen \reg_1_dest11__wen - connect \dest11__data_i \reg_1_dest11__data_i - connect \dest21__wen \reg_1_dest21__wen - connect \dest21__data_i \reg_1_dest21__data_i - connect \r1__data_o \reg_1_r1__data_o - connect \r1__ren \reg_1_r1__ren - connect \w1__data_i \reg_1_w1__data_i - connect \w1__wen \reg_1_w1__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_w2__wen - cell \reg_2 \reg_2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src12__ren \reg_2_src12__ren - connect \src12__data_o \reg_2_src12__data_o - connect \src22__ren \reg_2_src22__ren - connect \src22__data_o \reg_2_src22__data_o - connect \src32__ren \reg_2_src32__ren - connect \src32__data_o \reg_2_src32__data_o - connect \dest12__wen \reg_2_dest12__wen - connect \dest12__data_i \reg_2_dest12__data_i - connect \dest22__wen \reg_2_dest22__wen - connect \dest22__data_i \reg_2_dest22__data_i - connect \r2__data_o \reg_2_r2__data_o - connect \r2__ren \reg_2_r2__ren - connect \w2__data_i \reg_2_w2__data_i - connect \w2__wen \reg_2_w2__wen +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_45" +module \core_calculate_stage_45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$278 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_src13__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_src13__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_src23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_src23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_src33__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_src33__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_dest13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_dest13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_dest23__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_dest23__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_r3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_r3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_w3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_w3__wen - cell \reg_3 \reg_3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src13__ren \reg_3_src13__ren - connect \src13__data_o \reg_3_src13__data_o - connect \src23__ren \reg_3_src23__ren - connect \src23__data_o \reg_3_src23__data_o - connect \src33__ren \reg_3_src33__ren - connect \src33__data_o \reg_3_src33__data_o - connect \dest13__wen \reg_3_dest13__wen - connect \dest13__data_i \reg_3_dest13__data_i - connect \dest23__wen \reg_3_dest23__wen - connect \dest23__data_i \reg_3_dest23__data_i - connect \r3__data_o \reg_3_r3__data_o - connect \r3__ren \reg_3_r3__ren - connect \w3__data_i \reg_3_w3__data_i - connect \w3__wen \reg_3_w3__wen + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_src14__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_src14__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_src24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_src24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_src34__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_src34__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_dest14__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_dest14__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_dest24__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_dest24__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_r4__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_r4__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_w4__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_w4__wen - cell \reg_4 \reg_4 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src14__ren \reg_4_src14__ren - connect \src14__data_o \reg_4_src14__data_o - connect \src24__ren \reg_4_src24__ren - connect \src24__data_o \reg_4_src24__data_o - connect \src34__ren \reg_4_src34__ren - connect \src34__data_o \reg_4_src34__data_o - connect \dest14__wen \reg_4_dest14__wen - connect \dest14__data_i \reg_4_dest14__data_i - connect \dest24__wen \reg_4_dest24__wen - connect \dest24__data_i \reg_4_dest24__data_i - connect \r4__data_o \reg_4_r4__data_o - connect \r4__ren \reg_4_r4__ren - connect \w4__data_i \reg_4_w4__data_i - connect \w4__wen \reg_4_w4__wen + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_src15__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_src15__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_src25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_src25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_src35__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_src35__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_dest15__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_dest15__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_dest25__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_dest25__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_r5__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_r5__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_w5__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_w5__wen - cell \reg_5 \reg_5 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src15__ren \reg_5_src15__ren - connect \src15__data_o \reg_5_src15__data_o - connect \src25__ren \reg_5_src25__ren - connect \src25__data_o \reg_5_src25__data_o - connect \src35__ren \reg_5_src35__ren - connect \src35__data_o \reg_5_src35__data_o - connect \dest15__wen \reg_5_dest15__wen - connect \dest15__data_i \reg_5_dest15__data_i - connect \dest25__wen \reg_5_dest25__wen - connect \dest25__data_i \reg_5_dest25__data_i - connect \r5__data_o \reg_5_r5__data_o - connect \r5__ren \reg_5_r5__ren - connect \w5__data_i \reg_5_w5__data_i - connect \w5__wen \reg_5_w5__wen + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_src16__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_src16__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_src26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_src26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_src36__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_src36__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_dest16__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_dest16__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_dest26__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_dest26__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_r6__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_r6__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_w6__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_w6__wen - cell \reg_6 \reg_6 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src16__ren \reg_6_src16__ren - connect \src16__data_o \reg_6_src16__data_o - connect \src26__ren \reg_6_src26__ren - connect \src26__data_o \reg_6_src26__data_o - connect \src36__ren \reg_6_src36__ren - connect \src36__data_o \reg_6_src36__data_o - connect \dest16__wen \reg_6_dest16__wen - connect \dest16__data_i \reg_6_dest16__data_i - connect \dest26__wen \reg_6_dest26__wen - connect \dest26__data_i \reg_6_dest26__data_i - connect \r6__data_o \reg_6_r6__data_o - connect \r6__ren \reg_6_r6__ren - connect \w6__data_i \reg_6_w6__data_i - connect \w6__wen \reg_6_w6__wen + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_src17__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_src17__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_src27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_src27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_src37__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_src37__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_dest17__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_dest17__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_dest27__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_dest27__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_r7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_r7__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_w7__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_w7__wen - cell \reg_7 \reg_7 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src17__ren \reg_7_src17__ren - connect \src17__data_o \reg_7_src17__data_o - connect \src27__ren \reg_7_src27__ren - connect \src27__data_o \reg_7_src27__data_o - connect \src37__ren \reg_7_src37__ren - connect \src37__data_o \reg_7_src37__data_o - connect \dest17__wen \reg_7_dest17__wen - connect \dest17__data_i \reg_7_dest17__data_i - connect \dest27__wen \reg_7_dest27__wen - connect \dest27__data_i \reg_7_dest27__data_i - connect \r7__data_o \reg_7_r7__data_o - connect \r7__ren \reg_7_r7__ren - connect \w7__data_i \reg_7_w7__data_i - connect \w7__wen \reg_7_w7__wen + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - process $group_0 - assign \reg_0_src10__ren 1'0 - assign \reg_1_src11__ren 1'0 - assign \reg_2_src12__ren 1'0 - assign \reg_3_src13__ren 1'0 - assign \reg_4_src14__ren 1'0 - assign \reg_5_src15__ren 1'0 - assign \reg_6_src16__ren 1'0 - assign \reg_7_src17__ren 1'0 - assign { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_0_src10__data_o - connect \B \reg_1_src11__data_o - connect \Y $1 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_2_src12__data_o - connect \B \reg_3_src13__data_o - connect \Y $3 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $1 - connect \B $3 - connect \Y $5 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_4_src14__data_o - connect \B \reg_5_src15__data_o - connect \Y $7 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_6_src16__data_o - connect \B \reg_7_src17__data_o - connect \Y $9 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $7 - connect \B $9 - connect \Y $11 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $5 - connect \B $11 - connect \Y $13 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - process $group_8 - assign \src1__data_o 4'0000 - assign \src1__data_o $13 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - process $group_9 - assign \reg_0_src20__ren 1'0 - assign \reg_1_src21__ren 1'0 - assign \reg_2_src22__ren 1'0 - assign \reg_3_src23__ren 1'0 - assign \reg_4_src24__ren 1'0 - assign \reg_5_src25__ren 1'0 - assign \reg_6_src26__ren 1'0 - assign \reg_7_src27__ren 1'0 - assign { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_0_src20__data_o - connect \B \reg_1_src21__data_o - connect \Y $15 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_2_src22__data_o - connect \B \reg_3_src23__data_o - connect \Y $17 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $20 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_46.core.trial0" +module \trial0$283 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $15 - connect \B $17 - connect \Y $19 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_4_src24__data_o - connect \B \reg_5_src25__data_o - connect \Y $21 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $24 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_6_src26__data_o - connect \B \reg_7_src27__data_o - connect \Y $23 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $21 - connect \B $23 - connect \Y $25 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010001 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $19 - connect \B $25 - connect \Y $27 - end - process $group_17 - assign \src2__data_o 4'0000 - assign \src2__data_o $27 - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_18 - assign \reg_0_src30__ren 1'0 - assign \reg_1_src31__ren 1'0 - assign \reg_2_src32__ren 1'0 - assign \reg_3_src33__ren 1'0 - assign \reg_4_src34__ren 1'0 - assign \reg_5_src35__ren 1'0 - assign \reg_6_src36__ren 1'0 - assign \reg_7_src37__ren 1'0 - assign { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $30 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_46.core.trial1" +module \trial1$284 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_0_src30__data_o - connect \B \reg_1_src31__data_o - connect \Y $29 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_2_src32__data_o - connect \B \reg_3_src33__data_o - connect \Y $31 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $29 - connect \B $31 - connect \Y $33 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_4_src34__data_o - connect \B \reg_5_src35__data_o - connect \Y $35 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 65 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_6_src36__data_o - connect \B \reg_7_src37__data_o - connect \Y $37 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010001 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $35 - connect \B $37 - connect \Y $39 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $42 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_46.core.pe" +module \pe$285 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $33 - connect \B $39 - connect \Y $41 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_26 - assign \src3__data_o 4'0000 - assign \src3__data_o $41 + process $group_1 + assign \n 1'0 + assign \n $1 sync init end - process $group_27 - assign \reg_0_dest10__wen 1'0 - assign \reg_1_dest11__wen 1'0 - assign \reg_2_dest12__wen 1'0 - assign \reg_3_dest13__wen 1'0 - assign \reg_4_dest14__wen 1'0 - assign \reg_5_dest15__wen 1'0 - assign \reg_6_dest16__wen 1'0 - assign \reg_7_dest17__wen 1'0 - assign { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_46.core" +module \core$282 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$283 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$284 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - process $group_35 - assign \reg_0_dest10__data_i 4'0000 - assign \reg_0_dest10__data_i \data_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$285 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - process $group_36 - assign \reg_1_dest11__data_i 4'0000 - assign \reg_1_dest11__data_i \data_i + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation sync init end - process $group_37 - assign \reg_2_dest12__data_i 4'0000 - assign \reg_2_dest12__data_i \data_i + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init end - process $group_38 - assign \reg_3_dest13__data_i 4'0000 - assign \reg_3_dest13__data_i \data_i + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - process $group_39 - assign \reg_4_dest14__data_i 4'0000 - assign \reg_4_dest14__data_i \data_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init end - process $group_40 - assign \reg_5_dest15__data_i 4'0000 - assign \reg_5_dest15__data_i \data_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end - process $group_41 - assign \reg_6_dest16__data_i 4'0000 - assign \reg_6_dest16__data_i \data_i + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end - process $group_42 - assign \reg_7_dest17__data_i 4'0000 - assign \reg_7_dest17__data_i \data_i + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \wen$43 - process $group_43 - assign \reg_0_dest20__wen 1'0 - assign \reg_1_dest21__wen 1'0 - assign \reg_2_dest22__wen 1'0 - assign \reg_3_dest23__wen 1'0 - assign \reg_4_dest24__wen 1'0 - assign \reg_5_dest25__wen 1'0 - assign \reg_6_dest26__wen 1'0 - assign \reg_7_dest27__wen 1'0 - assign { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen$43 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \data_i$44 - process $group_51 - assign \reg_0_dest20__data_i 4'0000 - assign \reg_0_dest20__data_i \data_i$44 + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end - process $group_52 - assign \reg_1_dest21__data_i 4'0000 - assign \reg_1_dest21__data_i \data_i$44 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root sync init end - process $group_53 - assign \reg_2_dest22__data_i 4'0000 - assign \reg_2_dest22__data_i \data_i$44 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init end - process $group_54 - assign \reg_3_dest23__data_i 4'0000 - assign \reg_3_dest23__data_i \data_i$44 + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end - process $group_55 - assign \reg_4_dest24__data_i 4'0000 - assign \reg_4_dest24__data_i \data_i$44 - sync init - end - process $group_56 - assign \reg_5_dest25__data_i 4'0000 - assign \reg_5_dest25__data_i \data_i$44 + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - process $group_57 - assign \reg_6_dest26__data_i 4'0000 - assign \reg_6_dest26__data_i \data_i$44 - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - process $group_58 - assign \reg_7_dest27__data_i 4'0000 - assign \reg_7_dest27__data_i \data_i$44 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - process $group_59 - assign \full_rd__data_o 32'00000000000000000000000000000000 - assign \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } sync init end - process $group_60 - assign \reg_0_r0__ren 1'0 - assign \reg_1_r1__ren 1'0 - assign \reg_2_r2__ren 1'0 - assign \reg_3_r3__ren 1'0 - assign \reg_4_r4__ren 1'0 - assign \reg_5_r5__ren 1'0 - assign \reg_6_r6__ren 1'0 - assign \reg_7_r7__ren 1'0 - assign { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - process $group_68 - assign \reg_0_w0__data_i 4'0000 - assign \reg_1_w1__data_i 4'0000 - assign \reg_2_w2__data_i 4'0000 - assign \reg_3_w3__data_i 4'0000 - assign \reg_4_w4__data_i 4'0000 - assign \reg_5_w5__data_i 4'0000 - assign \reg_6_w6__data_i 4'0000 - assign \reg_7_w7__data_i 4'0000 - assign { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - process $group_76 - assign \reg_0_w0__wen 1'0 - assign \reg_1_w1__wen 1'0 - assign \reg_2_w2__wen 1'0 - assign \reg_3_w3__wen 1'0 - assign \reg_4_w4__wen 1'0 - assign \reg_5_w5__wen 1'0 - assign \reg_6_w6__wen 1'0 - assign \reg_7_w7__wen 1'0 - assign { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 end - connect \wen$43 8'00000000 - connect \data_i$44 4'0000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" -module \reg_0$125 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 12 \dest30__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest30__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src10__ren + parameter \Y_WIDTH 2 + connect \A \pe_o connect \B 1'1 - connect \Y $1 + connect \Y $17 end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src10__ren - connect \B 1'1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 2 \reg$next - process $group_1 - assign \src10__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src10__data_o \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src10__data_o \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src10__data_o \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src10__data_o \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src10__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src10__data_o 2'00 - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src20__ren + connect \A \next_bits connect \B 1'1 - connect \Y $8 + connect \Y $22 end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src20__ren - connect \B 1'1 - connect \Y $10 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - process $group_3 - assign \src20__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src20__data_o \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src20__data_o \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src20__data_o \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src20__data_o \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src20__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src20__data_o 2'00 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'10001 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_46" +module \core_calculate_stage_46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$282 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_47.core.trial0" +module \trial0$287 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src30__ren + connect \A \operation connect \B 1'1 - connect \Y $15 + connect \Y $1 end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src30__ren + connect \A \operation connect \B 1'1 - connect \Y $17 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$14 - connect \Y $19 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010000 + connect \Y $8 end - process $group_5 - assign \src30__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src30__data_o \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src30__data_o \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src30__data_o \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src30__data_o \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src30__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src30__data_o 2'00 + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $23 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_47.core.trial1" +module \trial1$288 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r0__ren + connect \A \operation connect \B 1'1 - connect \Y $22 + connect \Y $1 end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \r0__ren + connect \A \operation connect \B 1'1 - connect \Y $24 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 - connect \Y $26 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1010000 + connect \Y $8 end - process $group_7 - assign \r0__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r0__data_o \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r0__data_o \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r0__data_o \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r0__data_o \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r0__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r0__data_o 2'00 + assign \trial_compare_rhs $7 [191:0] end sync init end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_47.core.pe" +module \pe$289 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \reg$next \w0__data_i + assign \o 1'1 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \reg$next 2'00 + assign \o 1'0 end sync init - update \reg 2'00 - sync posedge \coresync_clk - update \reg \reg$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" -module \reg_1$126 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 12 \dest31__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest31__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src11__ren - connect \B 1'1 + connect \A \i + connect \B 1'0 connect \Y $1 end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_47.core" +module \core$286 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$287 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$288 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$289 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \src11__ren - connect \B 1'1 - connect \Y $3 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 2 \reg$next - process $group_1 - assign \src11__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src11__data_o \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src11__data_o \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src11__data_o \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src11__data_o \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src11__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" case - assign \src11__data_o 2'00 + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src21__ren - connect \B 1'1 - connect \Y $8 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \src21__ren + connect \A \next_bits connect \B 1'1 - connect \Y $10 + connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 - end - process $group_3 - assign \src21__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src21__data_o \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src21__data_o \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src21__data_o \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src21__data_o \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src21__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src21__data_o 2'00 - end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src31__ren - connect \B 1'1 - connect \Y $15 - end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src31__ren - connect \B 1'1 - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$14 - connect \Y $19 - end - process $group_5 - assign \src31__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src31__data_o \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src31__data_o \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src31__data_o \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src31__data_o \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src31__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src31__data_o 2'00 - end - sync init + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r1__ren - connect \B 1'1 - connect \Y $22 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 32 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r1__ren - connect \B 1'1 - connect \Y $24 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 32 + connect \A \next_bits + connect \B 5'10000 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 - connect \Y $26 - end - process $group_7 - assign \r1__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r1__data_o \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r1__data_o \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r1__data_o \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r1__data_o \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r1__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r1__data_o 2'00 - end - sync init + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 2'00 - end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init - update \reg 2'00 - sync posedge \coresync_clk - update \reg \reg$next end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" -module \reg_2$127 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 12 \dest32__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest32__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src12__ren - connect \B 1'1 - connect \Y $1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11.core_calculate_stage_47" +module \core_calculate_stage_47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$286 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src12__ren - connect \B 1'1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 2 \reg$next process $group_1 - assign \src12__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src12__data_o \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src12__data_o \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src12__data_o \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src12__data_o \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src12__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src12__data_o 2'00 - end + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src22__ren - connect \B 1'1 - connect \Y $8 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src22__ren - connect \B 1'1 - connect \Y $10 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - process $group_3 - assign \src22__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src22__data_o \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src22__data_o \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src22__data_o \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src22__data_o \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src22__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src22__data_o 2'00 - end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src32__ren - connect \B 1'1 - connect \Y $15 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - process $group_4 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$14 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$14 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src32__ren - connect \B 1'1 - connect \Y $17 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$14 - connect \Y $19 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - process $group_5 - assign \src32__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src32__data_o \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src32__data_o \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src32__data_o \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src32__data_o \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src32__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src32__data_o 2'00 - end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r2__ren - connect \B 1'1 - connect \Y $22 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - process $group_6 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$21 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r2__ren - connect \B 1'1 - connect \Y $24 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$21 - connect \Y $26 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_7 - assign \r2__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $24 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r2__data_o \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r2__data_o \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r2__data_o \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \r2__data_o \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \r2__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \r2__data_o 2'00 - end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 2'00 - end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 sync init - update \reg 2'00 - sync posedge \coresync_clk - update \reg \reg$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.xer" -module \xer - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 1 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 2 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 4 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 6 \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 7 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 8 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \data_i$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 10 \wen$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \data_i$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 12 \wen$4 - attribute \src "simple/issuer.py:89" - wire width 1 input 13 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest30__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_dest30__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_w0__wen - cell \reg_0$125 \reg_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src10__ren \reg_0_src10__ren - connect \src10__data_o \reg_0_src10__data_o - connect \src20__ren \reg_0_src20__ren - connect \src20__data_o \reg_0_src20__data_o - connect \src30__ren \reg_0_src30__ren - connect \src30__data_o \reg_0_src30__data_o - connect \dest10__wen \reg_0_dest10__wen - connect \dest10__data_i \reg_0_dest10__data_i - connect \dest20__wen \reg_0_dest20__wen - connect \dest20__data_i \reg_0_dest20__data_i - connect \dest30__wen \reg_0_dest30__wen - connect \dest30__data_i \reg_0_dest30__data_i - connect \r0__data_o \reg_0_r0__data_o - connect \r0__ren \reg_0_r0__ren - connect \w0__data_i \reg_0_w0__data_i - connect \w0__wen \reg_0_w0__wen + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest31__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_dest31__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_w1__wen - cell \reg_1$126 \reg_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src11__ren \reg_1_src11__ren - connect \src11__data_o \reg_1_src11__data_o - connect \src21__ren \reg_1_src21__ren - connect \src21__data_o \reg_1_src21__data_o - connect \src31__ren \reg_1_src31__ren - connect \src31__data_o \reg_1_src31__data_o - connect \dest11__wen \reg_1_dest11__wen - connect \dest11__data_i \reg_1_dest11__data_i - connect \dest21__wen \reg_1_dest21__wen - connect \dest21__data_i \reg_1_dest21__data_i - connect \dest31__wen \reg_1_dest31__wen - connect \dest31__data_i \reg_1_dest31__data_i - connect \r1__data_o \reg_1_r1__data_o - connect \r1__ren \reg_1_r1__ren - connect \w1__data_i \reg_1_w1__data_i - connect \w1__wen \reg_1_w1__wen + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest32__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_dest32__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_w2__wen - cell \reg_2$127 \reg_2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src12__ren \reg_2_src12__ren - connect \src12__data_o \reg_2_src12__data_o - connect \src22__ren \reg_2_src22__ren - connect \src22__data_o \reg_2_src22__data_o - connect \src32__ren \reg_2_src32__ren - connect \src32__data_o \reg_2_src32__data_o - connect \dest12__wen \reg_2_dest12__wen - connect \dest12__data_i \reg_2_dest12__data_i - connect \dest22__wen \reg_2_dest22__wen - connect \dest22__data_i \reg_2_dest22__data_i - connect \dest32__wen \reg_2_dest32__wen - connect \dest32__data_i \reg_2_dest32__data_i - connect \r2__data_o \reg_2_r2__data_o - connect \r2__ren \reg_2_r2__ren - connect \w2__data_i \reg_2_w2__data_i - connect \w2__wen \reg_2_w2__wen + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init end - process $group_0 - assign \reg_0_src10__ren 1'0 - assign \reg_1_src11__ren 1'0 - assign \reg_2_src12__ren 1'0 - assign { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src11__data_o - connect \B \reg_2_src12__data_o - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src10__data_o - connect \B $5 - connect \Y $7 - end - process $group_3 - assign \src1__data_o 2'00 - assign \src1__data_o $7 - sync init - end - process $group_4 - assign \reg_0_src20__ren 1'0 - assign \reg_1_src21__ren 1'0 - assign \reg_2_src22__ren 1'0 - assign { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src21__data_o - connect \B \reg_2_src22__data_o - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src20__data_o - connect \B $9 - connect \Y $11 - end - process $group_7 - assign \src2__data_o 2'00 - assign \src2__data_o $11 - sync init - end - process $group_8 - assign \reg_0_src30__ren 1'0 - assign \reg_1_src31__ren 1'0 - assign \reg_2_src32__ren 1'0 - assign { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src31__data_o - connect \B \reg_2_src32__data_o - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src30__data_o - connect \B $13 - connect \Y $15 - end - process $group_11 - assign \src3__data_o 2'00 - assign \src3__data_o $15 - sync init - end - process $group_12 - assign \reg_0_dest10__wen 1'0 - assign \reg_1_dest11__wen 1'0 - assign \reg_2_dest12__wen 1'0 - assign { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 - sync init - end - process $group_15 - assign \reg_0_dest10__data_i 2'00 - assign \reg_0_dest10__data_i \data_i$3 - sync init - end - process $group_16 - assign \reg_1_dest11__data_i 2'00 - assign \reg_1_dest11__data_i \data_i$3 - sync init - end - process $group_17 - assign \reg_2_dest12__data_i 2'00 - assign \reg_2_dest12__data_i \data_i$3 - sync init - end - process $group_18 - assign \reg_0_dest20__wen 1'0 - assign \reg_1_dest21__wen 1'0 - assign \reg_2_dest22__wen 1'0 - assign { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen - sync init - end - process $group_21 - assign \reg_0_dest20__data_i 2'00 - assign \reg_0_dest20__data_i \data_i - sync init - end - process $group_22 - assign \reg_1_dest21__data_i 2'00 - assign \reg_1_dest21__data_i \data_i - sync init - end - process $group_23 - assign \reg_2_dest22__data_i 2'00 - assign \reg_2_dest22__data_i \data_i - sync init - end - process $group_24 - assign \reg_0_dest30__wen 1'0 - assign \reg_1_dest31__wen 1'0 - assign \reg_2_dest32__wen 1'0 - assign { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 - sync init - end - process $group_27 - assign \reg_0_dest30__data_i 2'00 - assign \reg_0_dest30__data_i \data_i$1 - sync init - end - process $group_28 - assign \reg_1_dest31__data_i 2'00 - assign \reg_1_dest31__data_i \data_i$1 - sync init - end - process $group_29 - assign \reg_2_dest32__data_i 2'00 - assign \reg_2_dest32__data_i \data_i$1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 \full_rd__data_o - process $group_30 - assign \full_rd__data_o 6'000000 - assign \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \full_rd__ren - process $group_31 - assign \reg_0_r0__ren 1'0 - assign \reg_1_r1__ren 1'0 - assign \reg_2_r2__ren 1'0 - assign { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 \full_wr__data_i - process $group_34 - assign \reg_0_w0__data_i 2'00 - assign \reg_1_w1__data_i 2'00 - assign \reg_2_w2__data_i 2'00 - assign { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \full_wr__wen - process $group_37 - assign \reg_0_w0__wen 1'0 - assign \reg_1_w1__wen 1'0 - assign \reg_2_w2__wen 1'0 - assign { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen - sync init - end - connect \full_rd__ren 3'000 - connect \full_wr__data_i 6'000000 - connect \full_wr__wen 3'000 + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fast.reg_0" -module \reg_0$128 - attribute \src "simple/issuer.py:89" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_11" +module \pipe_middle_11 + attribute \src "simple/issuer.py:102" wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" + attribute \src "simple/issuer.py:102" wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \dest30__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 5 \dest30__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src10__ren - connect \B 1'1 - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 41 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$272 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end - sync init + cell \n$273 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src10__ren - connect \B 1'1 - connect \Y $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_44_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_44_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_44_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_44_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_44_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_44_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_44_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_44_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_44_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_44_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_44_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_44_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_44_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_44_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_44_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_44_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_44_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_44_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_44_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_44_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_44_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_44_muxid$34 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_44_logical_op__insn_type$35 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_44_logical_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_44_logical_op__imm_data__imm$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__imm_data__imm_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__invert_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_44_logical_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__write_cr0$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_44_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_44_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_44_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_44_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_44_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_44_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_44_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_44_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_44_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_44_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_44_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_44_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_44_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_44_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_44_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_44_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_44_compare_rhs$66 + cell \core_calculate_stage_44 \core_calculate_stage_44 + connect \muxid \core_calculate_stage_44_muxid + connect \logical_op__insn_type \core_calculate_stage_44_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_44_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_44_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_44_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_44_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_44_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_44_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_44_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_44_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_44_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_44_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_44_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_44_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_44_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_44_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_44_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_44_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_44_logical_op__insn + connect \ra \core_calculate_stage_44_ra + connect \rb \core_calculate_stage_44_rb + connect \xer_so \core_calculate_stage_44_xer_so + connect \divisor_neg \core_calculate_stage_44_divisor_neg + connect \dividend_neg \core_calculate_stage_44_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_44_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_44_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_44_div_by_zero + connect \divisor_radicand \core_calculate_stage_44_divisor_radicand + connect \operation \core_calculate_stage_44_operation + connect \quotient_root \core_calculate_stage_44_quotient_root + connect \root_times_radicand \core_calculate_stage_44_root_times_radicand + connect \compare_lhs \core_calculate_stage_44_compare_lhs + connect \compare_rhs \core_calculate_stage_44_compare_rhs + connect \muxid$1 \core_calculate_stage_44_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_44_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_44_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_44_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_44_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_44_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_44_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_44_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_44_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_44_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_44_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_44_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_44_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_44_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_44_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_44_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_44_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_44_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_44_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_44_ra$53 + connect \rb$21 \core_calculate_stage_44_rb$54 + connect \xer_so$22 \core_calculate_stage_44_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_44_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_44_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_44_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_44_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_44_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_44_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_44_operation$62 + connect \quotient_root$30 \core_calculate_stage_44_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_44_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_44_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_44_compare_rhs$66 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_45_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_45_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_45_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_45_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_45_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_45_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_45_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_45_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_45_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_45_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_45_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_45_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_45_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_45_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_45_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_45_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_45_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_45_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_45_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_45_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_45_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_45_muxid$67 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_45_logical_op__insn_type$68 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_45_logical_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_45_logical_op__imm_data__imm$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__imm_data__imm_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__rc__rc_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_45_logical_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__invert_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__write_cr0$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_45_logical_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_45_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_45_logical_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_45_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_45_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_45_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_45_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_45_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_45_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_45_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_45_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_45_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_45_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_45_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_45_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_45_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_45_compare_rhs$99 + cell \core_calculate_stage_45 \core_calculate_stage_45 + connect \muxid \core_calculate_stage_45_muxid + connect \logical_op__insn_type \core_calculate_stage_45_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_45_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_45_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_45_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_45_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_45_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_45_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_45_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_45_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_45_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_45_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_45_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_45_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_45_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_45_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_45_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_45_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_45_logical_op__insn + connect \ra \core_calculate_stage_45_ra + connect \rb \core_calculate_stage_45_rb + connect \xer_so \core_calculate_stage_45_xer_so + connect \divisor_neg \core_calculate_stage_45_divisor_neg + connect \dividend_neg \core_calculate_stage_45_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_45_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_45_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_45_div_by_zero + connect \divisor_radicand \core_calculate_stage_45_divisor_radicand + connect \operation \core_calculate_stage_45_operation + connect \quotient_root \core_calculate_stage_45_quotient_root + connect \root_times_radicand \core_calculate_stage_45_root_times_radicand + connect \compare_lhs \core_calculate_stage_45_compare_lhs + connect \compare_rhs \core_calculate_stage_45_compare_rhs + connect \muxid$1 \core_calculate_stage_45_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_45_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_45_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_45_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_45_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_45_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_45_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_45_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_45_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_45_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_45_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_45_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_45_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_45_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_45_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_45_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_45_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_45_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_45_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_45_ra$86 + connect \rb$21 \core_calculate_stage_45_rb$87 + connect \xer_so$22 \core_calculate_stage_45_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_45_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_45_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_45_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_45_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_45_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_45_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_45_operation$95 + connect \quotient_root$30 \core_calculate_stage_45_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_45_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_45_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_45_compare_rhs$99 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg$next - process $group_1 - assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src10__data_o \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src10__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_46_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_46_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_46_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_46_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_46_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_46_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_46_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_46_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_46_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_46_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_46_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_46_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_46_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_46_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_46_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_46_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_46_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_46_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_46_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_46_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_46_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_46_muxid$100 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_46_logical_op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_46_logical_op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_46_logical_op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__rc__rc$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__rc__rc_ok$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__oe__oe$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_46_logical_op__input_carry$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__invert_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__write_cr0$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__output_carry$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__is_32bit$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_46_logical_op__is_signed$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_46_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_46_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_46_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_46_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_46_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_46_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_46_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_46_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_46_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_46_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_46_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_46_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_46_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_46_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_46_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_46_compare_rhs$132 + cell \core_calculate_stage_46 \core_calculate_stage_46 + connect \muxid \core_calculate_stage_46_muxid + connect \logical_op__insn_type \core_calculate_stage_46_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_46_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_46_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_46_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_46_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_46_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_46_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_46_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_46_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_46_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_46_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_46_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_46_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_46_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_46_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_46_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_46_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_46_logical_op__insn + connect \ra \core_calculate_stage_46_ra + connect \rb \core_calculate_stage_46_rb + connect \xer_so \core_calculate_stage_46_xer_so + connect \divisor_neg \core_calculate_stage_46_divisor_neg + connect \dividend_neg \core_calculate_stage_46_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_46_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_46_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_46_div_by_zero + connect \divisor_radicand \core_calculate_stage_46_divisor_radicand + connect \operation \core_calculate_stage_46_operation + connect \quotient_root \core_calculate_stage_46_quotient_root + connect \root_times_radicand \core_calculate_stage_46_root_times_radicand + connect \compare_lhs \core_calculate_stage_46_compare_lhs + connect \compare_rhs \core_calculate_stage_46_compare_rhs + connect \muxid$1 \core_calculate_stage_46_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_46_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_46_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_46_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_46_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_46_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_46_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_46_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_46_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_46_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_46_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_46_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_46_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_46_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_46_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_46_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_46_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_46_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_46_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_46_ra$119 + connect \rb$21 \core_calculate_stage_46_rb$120 + connect \xer_so$22 \core_calculate_stage_46_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_46_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_46_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_46_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_46_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_46_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_46_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_46_operation$128 + connect \quotient_root$30 \core_calculate_stage_46_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_46_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_46_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_46_compare_rhs$132 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_47_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_47_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_47_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_47_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_47_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_47_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_47_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_47_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_47_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_47_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_47_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_47_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_47_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_47_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_47_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_47_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_47_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_47_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_47_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_47_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_47_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_47_muxid$133 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_47_logical_op__insn_type$134 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_47_logical_op__fn_unit$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_47_logical_op__imm_data__imm$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__imm_data__imm_ok$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__rc__rc$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__rc__rc_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__oe__oe$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__oe__oe_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__invert_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_47_logical_op__input_carry$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__invert_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__write_cr0$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__output_carry$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_47_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_47_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_47_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_47_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_47_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_47_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_47_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_47_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_47_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_47_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_47_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_47_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_47_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_47_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_47_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_47_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_47_compare_rhs$165 + cell \core_calculate_stage_47 \core_calculate_stage_47 + connect \muxid \core_calculate_stage_47_muxid + connect \logical_op__insn_type \core_calculate_stage_47_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_47_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_47_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_47_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_47_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_47_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_47_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_47_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_47_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_47_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_47_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_47_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_47_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_47_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_47_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_47_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_47_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_47_logical_op__insn + connect \ra \core_calculate_stage_47_ra + connect \rb \core_calculate_stage_47_rb + connect \xer_so \core_calculate_stage_47_xer_so + connect \divisor_neg \core_calculate_stage_47_divisor_neg + connect \dividend_neg \core_calculate_stage_47_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_47_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_47_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_47_div_by_zero + connect \divisor_radicand \core_calculate_stage_47_divisor_radicand + connect \operation \core_calculate_stage_47_operation + connect \quotient_root \core_calculate_stage_47_quotient_root + connect \root_times_radicand \core_calculate_stage_47_root_times_radicand + connect \compare_lhs \core_calculate_stage_47_compare_lhs + connect \compare_rhs \core_calculate_stage_47_compare_rhs + connect \muxid$1 \core_calculate_stage_47_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_47_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_47_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_47_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_47_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_47_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_47_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_47_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_47_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_47_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_47_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_47_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_47_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_47_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_47_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_47_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_47_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_47_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_47_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_47_ra$152 + connect \rb$21 \core_calculate_stage_47_rb$153 + connect \xer_so$22 \core_calculate_stage_47_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_47_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_47_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_47_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_47_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_47_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_47_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_47_operation$161 + connect \quotient_root$30 \core_calculate_stage_47_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_47_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_47_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_47_compare_rhs$165 + end + process $group_0 + assign \core_calculate_stage_44_muxid 2'00 + assign \core_calculate_stage_44_muxid \muxid sync init end - process $group_2 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end + process $group_1 + assign \core_calculate_stage_44_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_44_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_44_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_44_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_44_logical_op__rc__rc 1'0 + assign \core_calculate_stage_44_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_44_logical_op__oe__oe 1'0 + assign \core_calculate_stage_44_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_44_logical_op__invert_in 1'0 + assign \core_calculate_stage_44_logical_op__zero_a 1'0 + assign \core_calculate_stage_44_logical_op__input_carry 2'00 + assign \core_calculate_stage_44_logical_op__invert_out 1'0 + assign \core_calculate_stage_44_logical_op__write_cr0 1'0 + assign \core_calculate_stage_44_logical_op__output_carry 1'0 + assign \core_calculate_stage_44_logical_op__is_32bit 1'0 + assign \core_calculate_stage_44_logical_op__is_signed 1'0 + assign \core_calculate_stage_44_logical_op__data_len 4'0000 + assign \core_calculate_stage_44_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_44_logical_op__insn \core_calculate_stage_44_logical_op__data_len \core_calculate_stage_44_logical_op__is_signed \core_calculate_stage_44_logical_op__is_32bit \core_calculate_stage_44_logical_op__output_carry \core_calculate_stage_44_logical_op__write_cr0 \core_calculate_stage_44_logical_op__invert_out \core_calculate_stage_44_logical_op__input_carry \core_calculate_stage_44_logical_op__zero_a \core_calculate_stage_44_logical_op__invert_in { \core_calculate_stage_44_logical_op__oe__oe_ok \core_calculate_stage_44_logical_op__oe__oe } { \core_calculate_stage_44_logical_op__rc__rc_ok \core_calculate_stage_44_logical_op__rc__rc } { \core_calculate_stage_44_logical_op__imm_data__imm_ok \core_calculate_stage_44_logical_op__imm_data__imm } \core_calculate_stage_44_logical_op__fn_unit \core_calculate_stage_44_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \reg \reg$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fast.reg_1" -module \reg_1$129 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \dest31__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 5 \dest31__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src11__ren - connect \B 1'1 - connect \Y $1 + process $group_19 + assign \core_calculate_stage_44_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_44_ra \ra + sync init end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_20 + assign \core_calculate_stage_44_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_44_rb \rb sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src11__ren - connect \B 1'1 - connect \Y $3 + process $group_21 + assign \core_calculate_stage_44_xer_so 1'0 + assign \core_calculate_stage_44_xer_so \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + process $group_22 + assign \core_calculate_stage_44_divisor_neg 1'0 + assign \core_calculate_stage_44_divisor_neg \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg$next - process $group_1 - assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src11__data_o \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src11__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - end + process $group_23 + assign \core_calculate_stage_44_dividend_neg 1'0 + assign \core_calculate_stage_44_dividend_neg \dividend_neg sync init end - process $group_2 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end + process $group_24 + assign \core_calculate_stage_44_dive_abs_ov32 1'0 + assign \core_calculate_stage_44_dive_abs_ov32 \dive_abs_ov32 sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \reg \reg$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fast.reg_2" -module \reg_2$130 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \dest32__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 5 \dest32__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src12__ren - connect \B 1'1 - connect \Y $1 + process $group_25 + assign \core_calculate_stage_44_dive_abs_ov64 1'0 + assign \core_calculate_stage_44_dive_abs_ov64 \dive_abs_ov64 + sync init end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_26 + assign \core_calculate_stage_44_div_by_zero 1'0 + assign \core_calculate_stage_44_div_by_zero \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src12__ren - connect \B 1'1 - connect \Y $3 + process $group_27 + assign \core_calculate_stage_44_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_44_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + process $group_28 + assign \core_calculate_stage_44_operation 2'00 + assign \core_calculate_stage_44_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg$next - process $group_1 - assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src12__data_o \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src12__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - end + process $group_29 + assign \core_calculate_stage_44_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_44_quotient_root \quotient_root sync init end - process $group_2 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end + process $group_30 + assign \core_calculate_stage_44_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_44_root_times_radicand \root_times_radicand sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \reg \reg$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fast.reg_3" -module \reg_3$131 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src13__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \src13__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \dest33__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 5 \dest33__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src13__ren - connect \B 1'1 - connect \Y $1 + process $group_31 + assign \core_calculate_stage_44_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_44_compare_lhs \compare_lhs + sync init end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest33__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_32 + assign \core_calculate_stage_44_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_44_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src13__ren - connect \B 1'1 - connect \Y $3 + process $group_33 + assign \core_calculate_stage_45_muxid 2'00 + assign \core_calculate_stage_45_muxid \core_calculate_stage_44_muxid$34 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + process $group_34 + assign \core_calculate_stage_45_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_45_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_45_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_45_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_45_logical_op__rc__rc 1'0 + assign \core_calculate_stage_45_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_45_logical_op__oe__oe 1'0 + assign \core_calculate_stage_45_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_45_logical_op__invert_in 1'0 + assign \core_calculate_stage_45_logical_op__zero_a 1'0 + assign \core_calculate_stage_45_logical_op__input_carry 2'00 + assign \core_calculate_stage_45_logical_op__invert_out 1'0 + assign \core_calculate_stage_45_logical_op__write_cr0 1'0 + assign \core_calculate_stage_45_logical_op__output_carry 1'0 + assign \core_calculate_stage_45_logical_op__is_32bit 1'0 + assign \core_calculate_stage_45_logical_op__is_signed 1'0 + assign \core_calculate_stage_45_logical_op__data_len 4'0000 + assign \core_calculate_stage_45_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_45_logical_op__insn \core_calculate_stage_45_logical_op__data_len \core_calculate_stage_45_logical_op__is_signed \core_calculate_stage_45_logical_op__is_32bit \core_calculate_stage_45_logical_op__output_carry \core_calculate_stage_45_logical_op__write_cr0 \core_calculate_stage_45_logical_op__invert_out \core_calculate_stage_45_logical_op__input_carry \core_calculate_stage_45_logical_op__zero_a \core_calculate_stage_45_logical_op__invert_in { \core_calculate_stage_45_logical_op__oe__oe_ok \core_calculate_stage_45_logical_op__oe__oe } { \core_calculate_stage_45_logical_op__rc__rc_ok \core_calculate_stage_45_logical_op__rc__rc } { \core_calculate_stage_45_logical_op__imm_data__imm_ok \core_calculate_stage_45_logical_op__imm_data__imm } \core_calculate_stage_45_logical_op__fn_unit \core_calculate_stage_45_logical_op__insn_type } { \core_calculate_stage_44_logical_op__insn$52 \core_calculate_stage_44_logical_op__data_len$51 \core_calculate_stage_44_logical_op__is_signed$50 \core_calculate_stage_44_logical_op__is_32bit$49 \core_calculate_stage_44_logical_op__output_carry$48 \core_calculate_stage_44_logical_op__write_cr0$47 \core_calculate_stage_44_logical_op__invert_out$46 \core_calculate_stage_44_logical_op__input_carry$45 \core_calculate_stage_44_logical_op__zero_a$44 \core_calculate_stage_44_logical_op__invert_in$43 { \core_calculate_stage_44_logical_op__oe__oe_ok$42 \core_calculate_stage_44_logical_op__oe__oe$41 } { \core_calculate_stage_44_logical_op__rc__rc_ok$40 \core_calculate_stage_44_logical_op__rc__rc$39 } { \core_calculate_stage_44_logical_op__imm_data__imm_ok$38 \core_calculate_stage_44_logical_op__imm_data__imm$37 } \core_calculate_stage_44_logical_op__fn_unit$36 \core_calculate_stage_44_logical_op__insn_type$35 } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg$next - process $group_1 - assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest33__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src13__data_o \dest33__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src13__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - end + process $group_52 + assign \core_calculate_stage_45_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_45_ra \core_calculate_stage_44_ra$53 sync init end - process $group_2 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest33__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest33__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end + process $group_53 + assign \core_calculate_stage_45_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_45_rb \core_calculate_stage_44_rb$54 sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \reg \reg$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fast.reg_4" -module \reg_4$132 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src14__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \src14__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \dest34__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 5 \dest34__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src14__ren - connect \B 1'1 - connect \Y $1 + process $group_54 + assign \core_calculate_stage_45_xer_so 1'0 + assign \core_calculate_stage_45_xer_so \core_calculate_stage_44_xer_so$55 + sync init end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest34__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_55 + assign \core_calculate_stage_45_divisor_neg 1'0 + assign \core_calculate_stage_45_divisor_neg \core_calculate_stage_44_divisor_neg$56 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src14__ren - connect \B 1'1 - connect \Y $3 + process $group_56 + assign \core_calculate_stage_45_dividend_neg 1'0 + assign \core_calculate_stage_45_dividend_neg \core_calculate_stage_44_dividend_neg$57 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + process $group_57 + assign \core_calculate_stage_45_dive_abs_ov32 1'0 + assign \core_calculate_stage_45_dive_abs_ov32 \core_calculate_stage_44_dive_abs_ov32$58 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg$next - process $group_1 - assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \dest34__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \src14__data_o \dest34__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \src14__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - end + process $group_58 + assign \core_calculate_stage_45_dive_abs_ov64 1'0 + assign \core_calculate_stage_45_dive_abs_ov64 \core_calculate_stage_44_dive_abs_ov64$59 sync init end - process $group_2 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \dest34__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \dest34__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end + process $group_59 + assign \core_calculate_stage_45_div_by_zero 1'0 + assign \core_calculate_stage_45_div_by_zero \core_calculate_stage_44_div_by_zero$60 sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \reg \reg$next end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fast" -module \fast - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 1 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 2 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 3 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 4 \wen - attribute \src "simple/issuer.py:89" - wire width 1 input 5 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest30__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_dest30__data_i - cell \reg_0$128 \reg_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src10__ren \reg_0_src10__ren - connect \src10__data_o \reg_0_src10__data_o - connect \dest30__wen \reg_0_dest30__wen - connect \dest30__data_i \reg_0_dest30__data_i + process $group_60 + assign \core_calculate_stage_45_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_45_divisor_radicand \core_calculate_stage_44_divisor_radicand$61 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest31__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_dest31__data_i - cell \reg_1$129 \reg_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src11__ren \reg_1_src11__ren - connect \src11__data_o \reg_1_src11__data_o - connect \dest31__wen \reg_1_dest31__wen - connect \dest31__data_i \reg_1_dest31__data_i + process $group_61 + assign \core_calculate_stage_45_operation 2'00 + assign \core_calculate_stage_45_operation \core_calculate_stage_44_operation$62 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest32__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_dest32__data_i - cell \reg_2$130 \reg_2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src12__ren \reg_2_src12__ren - connect \src12__data_o \reg_2_src12__data_o - connect \dest32__wen \reg_2_dest32__wen - connect \dest32__data_i \reg_2_dest32__data_i + process $group_62 + assign \core_calculate_stage_45_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_45_quotient_root \core_calculate_stage_44_quotient_root$63 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_src13__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_src13__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_dest33__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_dest33__data_i - cell \reg_3$131 \reg_3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src13__ren \reg_3_src13__ren - connect \src13__data_o \reg_3_src13__data_o - connect \dest33__wen \reg_3_dest33__wen - connect \dest33__data_i \reg_3_dest33__data_i + process $group_63 + assign \core_calculate_stage_45_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_45_root_times_radicand \core_calculate_stage_44_root_times_radicand$64 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_src14__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_4_src14__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_dest34__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_4_dest34__data_i - cell \reg_4$132 \reg_4 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src14__ren \reg_4_src14__ren - connect \src14__data_o \reg_4_src14__data_o - connect \dest34__wen \reg_4_dest34__wen - connect \dest34__data_i \reg_4_dest34__data_i + process $group_64 + assign \core_calculate_stage_45_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_45_compare_lhs \core_calculate_stage_44_compare_lhs$65 + sync init end - process $group_0 - assign \reg_0_src10__ren 1'0 - assign \reg_1_src11__ren 1'0 - assign \reg_2_src12__ren 1'0 - assign \reg_3_src13__ren 1'0 - assign \reg_4_src14__ren 1'0 - assign { \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren + process $group_65 + assign \core_calculate_stage_45_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_45_compare_rhs \core_calculate_stage_44_compare_rhs$66 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_0_src10__data_o - connect \B \reg_1_src11__data_o - connect \Y $1 + process $group_66 + assign \core_calculate_stage_46_muxid 2'00 + assign \core_calculate_stage_46_muxid \core_calculate_stage_45_muxid$67 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_3_src13__data_o - connect \B \reg_4_src14__data_o - connect \Y $3 + process $group_67 + assign \core_calculate_stage_46_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_46_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_46_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_46_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_46_logical_op__rc__rc 1'0 + assign \core_calculate_stage_46_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_46_logical_op__oe__oe 1'0 + assign \core_calculate_stage_46_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_46_logical_op__invert_in 1'0 + assign \core_calculate_stage_46_logical_op__zero_a 1'0 + assign \core_calculate_stage_46_logical_op__input_carry 2'00 + assign \core_calculate_stage_46_logical_op__invert_out 1'0 + assign \core_calculate_stage_46_logical_op__write_cr0 1'0 + assign \core_calculate_stage_46_logical_op__output_carry 1'0 + assign \core_calculate_stage_46_logical_op__is_32bit 1'0 + assign \core_calculate_stage_46_logical_op__is_signed 1'0 + assign \core_calculate_stage_46_logical_op__data_len 4'0000 + assign \core_calculate_stage_46_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_46_logical_op__insn \core_calculate_stage_46_logical_op__data_len \core_calculate_stage_46_logical_op__is_signed \core_calculate_stage_46_logical_op__is_32bit \core_calculate_stage_46_logical_op__output_carry \core_calculate_stage_46_logical_op__write_cr0 \core_calculate_stage_46_logical_op__invert_out \core_calculate_stage_46_logical_op__input_carry \core_calculate_stage_46_logical_op__zero_a \core_calculate_stage_46_logical_op__invert_in { \core_calculate_stage_46_logical_op__oe__oe_ok \core_calculate_stage_46_logical_op__oe__oe } { \core_calculate_stage_46_logical_op__rc__rc_ok \core_calculate_stage_46_logical_op__rc__rc } { \core_calculate_stage_46_logical_op__imm_data__imm_ok \core_calculate_stage_46_logical_op__imm_data__imm } \core_calculate_stage_46_logical_op__fn_unit \core_calculate_stage_46_logical_op__insn_type } { \core_calculate_stage_45_logical_op__insn$85 \core_calculate_stage_45_logical_op__data_len$84 \core_calculate_stage_45_logical_op__is_signed$83 \core_calculate_stage_45_logical_op__is_32bit$82 \core_calculate_stage_45_logical_op__output_carry$81 \core_calculate_stage_45_logical_op__write_cr0$80 \core_calculate_stage_45_logical_op__invert_out$79 \core_calculate_stage_45_logical_op__input_carry$78 \core_calculate_stage_45_logical_op__zero_a$77 \core_calculate_stage_45_logical_op__invert_in$76 { \core_calculate_stage_45_logical_op__oe__oe_ok$75 \core_calculate_stage_45_logical_op__oe__oe$74 } { \core_calculate_stage_45_logical_op__rc__rc_ok$73 \core_calculate_stage_45_logical_op__rc__rc$72 } { \core_calculate_stage_45_logical_op__imm_data__imm_ok$71 \core_calculate_stage_45_logical_op__imm_data__imm$70 } \core_calculate_stage_45_logical_op__fn_unit$69 \core_calculate_stage_45_logical_op__insn_type$68 } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_2_src12__data_o - connect \B $3 - connect \Y $5 + process $group_85 + assign \core_calculate_stage_46_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_46_ra \core_calculate_stage_45_ra$86 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $1 - connect \B $5 - connect \Y $7 + process $group_86 + assign \core_calculate_stage_46_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_46_rb \core_calculate_stage_45_rb$87 + sync init end - process $group_5 - assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1__data_o $7 + process $group_87 + assign \core_calculate_stage_46_xer_so 1'0 + assign \core_calculate_stage_46_xer_so \core_calculate_stage_45_xer_so$88 sync init end - process $group_6 - assign \reg_0_dest30__wen 1'0 - assign \reg_1_dest31__wen 1'0 - assign \reg_2_dest32__wen 1'0 - assign \reg_3_dest33__wen 1'0 - assign \reg_4_dest34__wen 1'0 - assign { \reg_4_dest34__wen \reg_3_dest33__wen \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen + process $group_88 + assign \core_calculate_stage_46_divisor_neg 1'0 + assign \core_calculate_stage_46_divisor_neg \core_calculate_stage_45_divisor_neg$89 sync init end - process $group_11 - assign \reg_0_dest30__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_0_dest30__data_i \data_i + process $group_89 + assign \core_calculate_stage_46_dividend_neg 1'0 + assign \core_calculate_stage_46_dividend_neg \core_calculate_stage_45_dividend_neg$90 sync init end - process $group_12 - assign \reg_1_dest31__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_1_dest31__data_i \data_i + process $group_90 + assign \core_calculate_stage_46_dive_abs_ov32 1'0 + assign \core_calculate_stage_46_dive_abs_ov32 \core_calculate_stage_45_dive_abs_ov32$91 sync init end - process $group_13 - assign \reg_2_dest32__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_2_dest32__data_i \data_i + process $group_91 + assign \core_calculate_stage_46_dive_abs_ov64 1'0 + assign \core_calculate_stage_46_dive_abs_ov64 \core_calculate_stage_45_dive_abs_ov64$92 sync init end - process $group_14 - assign \reg_3_dest33__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_3_dest33__data_i \data_i + process $group_92 + assign \core_calculate_stage_46_div_by_zero 1'0 + assign \core_calculate_stage_46_div_by_zero \core_calculate_stage_45_div_by_zero$93 sync init end - process $group_15 - assign \reg_4_dest34__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_4_dest34__data_i \data_i + process $group_93 + assign \core_calculate_stage_46_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_46_divisor_radicand \core_calculate_stage_45_divisor_radicand$94 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.state.reg_0" -module \reg_0$133 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \msr0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \nia0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \msr0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \d_wr10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr10__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cia0__ren - connect \B 1'1 - connect \Y $1 + process $group_94 + assign \core_calculate_stage_46_operation 2'00 + assign \core_calculate_stage_46_operation \core_calculate_stage_45_operation$95 + sync init end - process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_95 + assign \core_calculate_stage_46_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_46_quotient_root \core_calculate_stage_45_quotient_root$96 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cia0__ren - connect \B 1'1 - connect \Y $3 + process $group_96 + assign \core_calculate_stage_46_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_46_root_times_radicand \core_calculate_stage_45_root_times_radicand$97 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $5 + process $group_97 + assign \core_calculate_stage_46_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_46_compare_lhs \core_calculate_stage_45_compare_lhs$98 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg$next - process $group_1 - assign \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \cia0__data_o \nia0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \cia0__data_o \msr0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \cia0__data_o \d_wr10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \cia0__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - end + process $group_98 + assign \core_calculate_stage_46_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_46_compare_rhs \core_calculate_stage_45_compare_rhs$99 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr0__ren - connect \B 1'1 - connect \Y $8 + process $group_99 + assign \core_calculate_stage_47_muxid 2'00 + assign \core_calculate_stage_47_muxid \core_calculate_stage_46_muxid$100 + sync init end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + process $group_100 + assign \core_calculate_stage_47_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_47_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_47_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_47_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_47_logical_op__rc__rc 1'0 + assign \core_calculate_stage_47_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_47_logical_op__oe__oe 1'0 + assign \core_calculate_stage_47_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_47_logical_op__invert_in 1'0 + assign \core_calculate_stage_47_logical_op__zero_a 1'0 + assign \core_calculate_stage_47_logical_op__input_carry 2'00 + assign \core_calculate_stage_47_logical_op__invert_out 1'0 + assign \core_calculate_stage_47_logical_op__write_cr0 1'0 + assign \core_calculate_stage_47_logical_op__output_carry 1'0 + assign \core_calculate_stage_47_logical_op__is_32bit 1'0 + assign \core_calculate_stage_47_logical_op__is_signed 1'0 + assign \core_calculate_stage_47_logical_op__data_len 4'0000 + assign \core_calculate_stage_47_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_47_logical_op__insn \core_calculate_stage_47_logical_op__data_len \core_calculate_stage_47_logical_op__is_signed \core_calculate_stage_47_logical_op__is_32bit \core_calculate_stage_47_logical_op__output_carry \core_calculate_stage_47_logical_op__write_cr0 \core_calculate_stage_47_logical_op__invert_out \core_calculate_stage_47_logical_op__input_carry \core_calculate_stage_47_logical_op__zero_a \core_calculate_stage_47_logical_op__invert_in { \core_calculate_stage_47_logical_op__oe__oe_ok \core_calculate_stage_47_logical_op__oe__oe } { \core_calculate_stage_47_logical_op__rc__rc_ok \core_calculate_stage_47_logical_op__rc__rc } { \core_calculate_stage_47_logical_op__imm_data__imm_ok \core_calculate_stage_47_logical_op__imm_data__imm } \core_calculate_stage_47_logical_op__fn_unit \core_calculate_stage_47_logical_op__insn_type } { \core_calculate_stage_46_logical_op__insn$118 \core_calculate_stage_46_logical_op__data_len$117 \core_calculate_stage_46_logical_op__is_signed$116 \core_calculate_stage_46_logical_op__is_32bit$115 \core_calculate_stage_46_logical_op__output_carry$114 \core_calculate_stage_46_logical_op__write_cr0$113 \core_calculate_stage_46_logical_op__invert_out$112 \core_calculate_stage_46_logical_op__input_carry$111 \core_calculate_stage_46_logical_op__zero_a$110 \core_calculate_stage_46_logical_op__invert_in$109 { \core_calculate_stage_46_logical_op__oe__oe_ok$108 \core_calculate_stage_46_logical_op__oe__oe$107 } { \core_calculate_stage_46_logical_op__rc__rc_ok$106 \core_calculate_stage_46_logical_op__rc__rc$105 } { \core_calculate_stage_46_logical_op__imm_data__imm_ok$104 \core_calculate_stage_46_logical_op__imm_data__imm$103 } \core_calculate_stage_46_logical_op__fn_unit$102 \core_calculate_stage_46_logical_op__insn_type$101 } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 + process $group_118 + assign \core_calculate_stage_47_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_47_ra \core_calculate_stage_46_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_47_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_47_rb \core_calculate_stage_46_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_47_xer_so 1'0 + assign \core_calculate_stage_47_xer_so \core_calculate_stage_46_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_47_divisor_neg 1'0 + assign \core_calculate_stage_47_divisor_neg \core_calculate_stage_46_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_47_dividend_neg 1'0 + assign \core_calculate_stage_47_dividend_neg \core_calculate_stage_46_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_47_dive_abs_ov32 1'0 + assign \core_calculate_stage_47_dive_abs_ov32 \core_calculate_stage_46_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_47_dive_abs_ov64 1'0 + assign \core_calculate_stage_47_dive_abs_ov64 \core_calculate_stage_46_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_47_div_by_zero 1'0 + assign \core_calculate_stage_47_div_by_zero \core_calculate_stage_46_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_47_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_47_divisor_radicand \core_calculate_stage_46_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_47_operation 2'00 + assign \core_calculate_stage_47_operation \core_calculate_stage_46_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_47_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_47_quotient_root \core_calculate_stage_46_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_47_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_47_root_times_radicand \core_calculate_stage_46_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_47_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_47_compare_lhs \core_calculate_stage_46_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_47_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_47_compare_rhs \core_calculate_stage_46_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msr0__ren - connect \B 1'1 - connect \Y $10 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 + sync init end - process $group_3 - assign \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \msr0__data_o \nia0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \msr0__data_o \msr0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \msr0__data_o \d_wr10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \msr0__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_47_muxid$133 sync init end - process $group_4 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \nia0__data_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_47_logical_op__insn$151 \core_calculate_stage_47_logical_op__data_len$150 \core_calculate_stage_47_logical_op__is_signed$149 \core_calculate_stage_47_logical_op__is_32bit$148 \core_calculate_stage_47_logical_op__output_carry$147 \core_calculate_stage_47_logical_op__write_cr0$146 \core_calculate_stage_47_logical_op__invert_out$145 \core_calculate_stage_47_logical_op__input_carry$144 \core_calculate_stage_47_logical_op__zero_a$143 \core_calculate_stage_47_logical_op__invert_in$142 { \core_calculate_stage_47_logical_op__oe__oe_ok$141 \core_calculate_stage_47_logical_op__oe__oe$140 } { \core_calculate_stage_47_logical_op__rc__rc_ok$139 \core_calculate_stage_47_logical_op__rc__rc$138 } { \core_calculate_stage_47_logical_op__imm_data__imm_ok$137 \core_calculate_stage_47_logical_op__imm_data__imm$136 } \core_calculate_stage_47_logical_op__fn_unit$135 \core_calculate_stage_47_logical_op__insn_type$134 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_47_ra$152 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_47_rb$153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_47_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_47_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_47_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_47_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_47_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_47_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_47_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_47_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_47_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_47_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_47_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_47_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst case 1'1 - assign \reg$next \msr0__data_i + assign \r_busy$next 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \d_wr10__data_i + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \coresync_rst case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 end sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 sync posedge \coresync_clk - update \reg \reg$next + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next + end + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end + sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next + end + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.state.reg_1" -module \reg_1$134 - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:89" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \msr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \nia1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \msr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \d_wr11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr11__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.p" +module \p$290 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cia1__ren - connect \B 1'1 + connect \A \p_valid_i + connect \B \p_ready_o connect \Y $1 end process $group_0 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - end + assign \trigger 1'0 + assign \trigger $1 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $4 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.n" +module \n$291 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cia1__ren + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_48.core.trial0" +module \trial0$293 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_detect + connect \A \operation + connect \B 1'1 connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:57" - wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 process $group_1 - assign \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \cia1__data_o \nia1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \cia1__data_o \msr1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \cia1__data_o \d_wr11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \cia1__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial_compare_rhs $7 [191:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:63" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $9 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_48.core.trial1" +module \trial1$294 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msr1__ren + connect \A \operation connect \B 1'1 - connect \Y $8 + connect \Y $1 end - process $group_2 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case + assign \dr_times_trial_bits $3 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - cell $eq $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \msr1__ren + connect \A \operation connect \B 1'1 - connect \Y $10 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - cell $not $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $12 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001111 + connect \Y $8 end - process $group_3 - assign \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" - switch { $10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \msr1__data_o \nia1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \msr1__data_o \msr1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:66" - case 1'1 - assign \msr1__data_o \d_wr11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \msr1__data_o \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" - case - assign \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial_compare_rhs $7 [191:0] end sync init end - process $group_4 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \nia1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - case 1'1 - assign \reg$next \msr1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" - switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:78" +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_48.core.pe" +module \pe$295 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \reg$next \d_wr11__data_i + assign \o 1'1 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o 1'0 end sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \reg \reg$next + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.state" -module \state - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 1 \cia__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 2 \cia__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 3 \msr__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 4 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 5 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 6 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 8 \data_i$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \data_i$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 10 \wen$3 - attribute \src "simple/issuer.py:89" - wire width 1 input 11 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_cia0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_cia0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_msr0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_msr0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_nia0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_nia0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_msr0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_msr0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_d_wr10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_d_wr10__data_i - cell \reg_0$133 \reg_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cia0__ren \reg_0_cia0__ren - connect \cia0__data_o \reg_0_cia0__data_o - connect \msr0__ren \reg_0_msr0__ren - connect \msr0__data_o \reg_0_msr0__data_o - connect \nia0__wen \reg_0_nia0__wen - connect \nia0__data_i \reg_0_nia0__data_i - connect \msr0__wen \reg_0_msr0__wen - connect \msr0__data_i \reg_0_msr0__data_i - connect \d_wr10__wen \reg_0_d_wr10__wen - connect \d_wr10__data_i \reg_0_d_wr10__data_i +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_48.core" +module \core$292 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$293 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$294 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_cia1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_cia1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_msr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_msr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_nia1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_nia1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_msr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_msr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_d_wr11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_d_wr11__data_i - cell \reg_1$134 \reg_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cia1__ren \reg_1_cia1__ren - connect \cia1__data_o \reg_1_cia1__data_o - connect \msr1__ren \reg_1_msr1__ren - connect \msr1__data_o \reg_1_msr1__data_o - connect \nia1__wen \reg_1_nia1__wen - connect \nia1__data_i \reg_1_nia1__data_i - connect \msr1__wen \reg_1_msr1__wen - connect \msr1__data_i \reg_1_msr1__data_i - connect \d_wr11__wen \reg_1_d_wr11__wen - connect \d_wr11__data_i \reg_1_d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$295 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end process $group_0 - assign \reg_0_cia0__ren 1'0 - assign \reg_1_cia1__ren 1'0 - assign { \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_0_cia0__data_o - connect \B \reg_1_cia1__data_o - connect \Y $4 + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init end process $group_2 - assign \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \cia__data_o $4 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init end process $group_3 - assign \reg_0_msr0__ren 1'0 - assign \reg_1_msr1__ren 1'0 - assign { \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_0_msr0__data_o - connect \B \reg_1_msr1__data_o - connect \Y $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 process $group_5 - assign \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \msr__data_o $6 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end process $group_6 - assign \reg_0_nia0__wen 1'0 - assign \reg_1_nia1__wen 1'0 - assign { \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger process $group_8 - assign \reg_0_nia0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_0_nia0__data_i \data_i$1 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger sync init + update $verilog_initial_trigger 1'0 end process $group_9 - assign \reg_1_nia1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_1_nia1__data_i \data_i$1 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 process $group_10 - assign \reg_0_msr0__wen 1'0 - assign \reg_1_msr1__wen 1'0 - assign { \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init end process $group_12 - assign \reg_0_msr0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_0_msr0__data_i \data_i$2 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end process $group_13 - assign \reg_1_msr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_1_msr1__data_i \data_i$2 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end process $group_14 - assign \reg_0_d_wr10__wen 1'0 - assign \reg_1_d_wr11__wen 1'0 - assign { \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end - process $group_16 - assign \reg_0_d_wr10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_0_d_wr10__data_i \data_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } sync init end - process $group_17 - assign \reg_1_d_wr11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_1_d_wr11__data_i \data_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.spr" -module \spr - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 1 \spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 input 2 \spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 3 \spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 4 \spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 input 5 \spr1__addr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \spr1__wen - memory width 64 size 110 \memory - cell $meminit $2 - parameter \MEMID "\\memory" - parameter \ABITS 7 - parameter \WIDTH 64 - parameter \WORDS 110 - parameter \PRIORITY 0 - connect \ADDR 7'0000000 - connect \DATA 7040'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185" - wire width 7 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:185" - wire width 64 \memory_r_data - cell $memrd \rp_spr1 - parameter \MEMID "\\memory" - parameter \ABITS 7 - parameter \WIDTH 64 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK 1'0 - connect \EN 1'1 - connect \ADDR \memory_r_addr - connect \DATA \memory_r_data - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193" - wire width 1 \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193" - wire width 7 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:193" - wire width 64 \memory_w_data - cell $memwr \wp_spr1 - parameter \MEMID "\\memory" - parameter \ABITS 7 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \PRIORITY 0 - connect \CLK \coresync_clk - connect \EN { { \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en } } - connect \ADDR \memory_w_addr - connect \DATA \memory_w_data - end - process $group_0 - assign \memory_r_addr 7'0000000 - assign \memory_r_addr \spr1__addr - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:208" - wire width 1 \addrmatch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - cell $and $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \spr1__wen - connect \B \addrmatch - connect \Y $3 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - switch { \spr1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - case 1'1 - assign \wr_detect 1'1 - end + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" - cell $eq $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr1__addr$1 - connect \B \spr1__addr - connect \Y $5 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - process $group_2 - assign \addrmatch 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - switch { \spr1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - case 1'1 - assign \addrmatch $5 - end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - cell $and $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \spr1__wen - connect \B \addrmatch - connect \Y $7 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - cell $not $10 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $9 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - process $group_3 - assign \spr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - switch { \spr1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:205" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - case 1'1 - assign \spr1__data_o \spr1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:213" - case 1'1 - assign \spr1__data_o \memory_r_data - end - end - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - process $group_4 - assign \memory_w_addr 7'0000000 - assign \memory_w_addr \spr1__addr$1 - sync init + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_5 - assign \memory_w_en 1'0 - assign \memory_w_en \spr1__wen + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - process $group_6 - assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \memory_w_data \spr1__data_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 16 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \next_bits + connect \B 4'1111 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rabc" -module \rdpick_INT_rabc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 19 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 19 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 19 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 19 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 19 - parameter \Y_WIDTH 19 - connect \A \i - connect \Y $1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_48" +module \core_calculate_stage_48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$292 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \ni 19'0000000000000000000 - assign \ni $1 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 process $group_1 - assign \t0 1'0 - assign \t0 \i [0] + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init end - process $group_2 - assign \t1 1'0 - assign \t1 $3 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init end - process $group_3 - assign \t2 1'0 - assign \t2 $7 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init end - process $group_4 - assign \t3 1'0 - assign \t3 $11 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } - connect \Y $16 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init end - process $group_5 - assign \t4 1'0 - assign \t4 $15 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } - connect \Y $20 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init end - process $group_6 - assign \t5 1'0 - assign \t5 $19 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } - connect \Y $24 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init end - process $group_7 - assign \t6 1'0 - assign \t6 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $29 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_49.core.trial0" +module \trial0$297 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] } - connect \Y $28 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_8 - assign \t7 1'0 - assign \t7 $27 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 9 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] } - connect \Y $32 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \Y $31 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001110 + connect \Y $8 end - process $group_9 - assign \t8 1'0 - assign \t8 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $37 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_49.core.trial1" +module \trial1$298 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [8:0] [8] \i [8:0] [7] \i [8:0] [6] \i [8:0] [5] \i [8:0] [4] \i [8:0] [3] \i [8:0] [2] \i [8:0] [1] \i [8:0] [0] \ni [9] } - connect \Y $36 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $36 - connect \Y $35 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_10 - assign \t9 1'0 - assign \t9 $35 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $41 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 11 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [9:0] [9] \i [9:0] [8] \i [9:0] [7] \i [9:0] [6] \i [9:0] [5] \i [9:0] [4] \i [9:0] [3] \i [9:0] [2] \i [9:0] [1] \i [9:0] [0] \ni [10] } - connect \Y $40 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $42 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $40 - connect \Y $39 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001110 + connect \Y $8 end - process $group_11 - assign \t10 1'0 - assign \t10 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \Y_WIDTH 1 - connect \A { \i [10:0] [10] \i [10:0] [9] \i [10:0] [8] \i [10:0] [7] \i [10:0] [6] \i [10:0] [5] \i [10:0] [4] \i [10:0] [3] \i [10:0] [2] \i [10:0] [1] \i [10:0] [0] \ni [11] } - connect \Y $44 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_49.core.pe" +module \pe$299 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $46 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $44 - connect \Y $43 + connect \A \i + connect \B 1'0 + connect \Y $1 end - process $group_12 - assign \t11 1'0 - assign \t11 $43 + process $group_1 + assign \n 1'0 + assign \n $1 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A { \i [11:0] [11] \i [11:0] [10] \i [11:0] [9] \i [11:0] [8] \i [11:0] [7] \i [11:0] [6] \i [11:0] [5] \i [11:0] [4] \i [11:0] [3] \i [11:0] [2] \i [11:0] [1] \i [11:0] [0] \ni [12] } - connect \Y $48 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_49.core" +module \core$296 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$297 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$298 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $48 - connect \Y $47 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$299 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o end - process $group_13 - assign \t12 1'0 - assign \t12 $47 + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \Y_WIDTH 1 - connect \A { \i [12:0] [12] \i [12:0] [11] \i [12:0] [10] \i [12:0] [9] \i [12:0] [8] \i [12:0] [7] \i [12:0] [6] \i [12:0] [5] \i [12:0] [4] \i [12:0] [3] \i [12:0] [2] \i [12:0] [1] \i [12:0] [0] \ni [13] } - connect \Y $52 + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $52 - connect \Y $51 + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init end - process $group_14 - assign \t13 1'0 - assign \t13 $51 + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \Y_WIDTH 1 - connect \A { \i [13:0] [13] \i [13:0] [12] \i [13:0] [11] \i [13:0] [10] \i [13:0] [9] \i [13:0] [8] \i [13:0] [7] \i [13:0] [6] \i [13:0] [5] \i [13:0] [4] \i [13:0] [3] \i [13:0] [2] \i [13:0] [1] \i [13:0] [0] \ni [14] } - connect \Y $56 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $56 - connect \Y $55 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init end - process $group_15 - assign \t14 1'0 - assign \t14 $55 + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $60 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $61 + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A { \i [14:0] [14] \i [14:0] [13] \i [14:0] [12] \i [14:0] [11] \i [14:0] [10] \i [14:0] [9] \i [14:0] [8] \i [14:0] [7] \i [14:0] [6] \i [14:0] [5] \i [14:0] [4] \i [14:0] [3] \i [14:0] [2] \i [14:0] [1] \i [14:0] [0] \ni [15] } - connect \Y $60 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $62 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $60 - connect \Y $59 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end process $group_16 - assign \t15 1'0 - assign \t15 $59 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 - parameter \A_WIDTH 17 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [15:0] [15] \i [15:0] [14] \i [15:0] [13] \i [15:0] [12] \i [15:0] [11] \i [15:0] [10] \i [15:0] [9] \i [15:0] [8] \i [15:0] [7] \i [15:0] [6] \i [15:0] [5] \i [15:0] [4] \i [15:0] [3] \i [15:0] [2] \i [15:0] [1] \i [15:0] [0] \ni [16] } - connect \Y $64 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $66 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $64 - connect \Y $63 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end + connect $16 $17 process $group_17 - assign \t16 1'0 - assign \t16 $63 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $68 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 18 - parameter \Y_WIDTH 1 - connect \A { \i [16:0] [16] \i [16:0] [15] \i [16:0] [14] \i [16:0] [13] \i [16:0] [12] \i [16:0] [11] \i [16:0] [10] \i [16:0] [9] \i [16:0] [8] \i [16:0] [7] \i [16:0] [6] \i [16:0] [5] \i [16:0] [4] \i [16:0] [3] \i [16:0] [2] \i [16:0] [1] \i [16:0] [0] \ni [17] } - connect \Y $68 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $70 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $68 - connect \Y $67 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end process $group_18 - assign \t17 1'0 - assign \t17 $67 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $72 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 19 - parameter \Y_WIDTH 1 - connect \A { \i [17:0] [17] \i [17:0] [16] \i [17:0] [15] \i [17:0] [14] \i [17:0] [13] \i [17:0] [12] \i [17:0] [11] \i [17:0] [10] \i [17:0] [9] \i [17:0] [8] \i [17:0] [7] \i [17:0] [6] \i [17:0] [5] \i [17:0] [4] \i [17:0] [3] \i [17:0] [2] \i [17:0] [1] \i [17:0] [0] \ni [18] } - connect \Y $72 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $74 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $72 - connect \Y $71 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end process $group_19 - assign \t18 1'0 - assign \t18 $71 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end process $group_20 - assign \o 19'0000000000000000000 - assign \o { \t18 \t17 \t16 \t15 \t14 \t13 \t12 \t11 \t10 \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $76 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 16 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 - parameter \A_WIDTH 19 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $75 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \next_bits + connect \B 4'1110 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end process $group_21 - assign \en_o 1'0 - assign \en_o $75 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so" -module \rdpick_XER_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \i - connect \Y $1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_49" +module \core_calculate_stage_49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$296 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \ni 4'0000 - assign \ni $1 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 process $group_1 - assign \t0 1'0 - assign \t0 \i [0] + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init end - process $group_4 - assign \t3 1'0 - assign \t3 $11 + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - process $group_5 - assign \o 4'0000 - assign \o { \t3 \t2 \t1 \t0 } + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $15 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - process $group_6 - assign \en_o 1'0 - assign \en_o $15 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca" -module \rdpick_XER_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 3 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \i - connect \Y $1 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - process $group_0 - assign \ni 3'000 - assign \ni $1 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - process $group_2 - assign \t1 1'0 - assign \t1 $3 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - process $group_3 - assign \t2 1'0 - assign \t2 $7 + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init end - process $group_4 - assign \o 3'000 - assign \o { \t2 \t1 \t0 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $11 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init end - process $group_5 - assign \en_o 1'0 - assign \en_o $11 + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ov" -module \rdpick_XER_xer_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_50.core.trial0" +module \trial0$301 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A \operation + connect \B 1'1 connect \Y $1 end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end process $group_0 - assign \ni 1'0 - assign \ni $1 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_2 - assign \o 1'0 - assign \o { \t0 } - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr" -module \rdpick_CR_full_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_50.core.trial1" +module \trial1$302 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A \operation + connect \B 1'1 connect \Y $1 end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end process $group_0 - assign \ni 1'0 - assign \ni $1 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - process $group_2 - assign \o 1'0 - assign \o { \t0 } - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001101 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_a" -module \rdpick_CR_cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_50.core.pe" +module \pe$303 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 connect \A \i + connect \B 1'0 connect \Y $1 end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_50.core" +module \core$300 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$301 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$302 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$303 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end process $group_0 - assign \ni 2'00 - assign \ni $1 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 process $group_1 - assign \t0 1'0 - assign \t0 \i [0] + assign \operation$2 2'00 + assign \operation$2 \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end process $group_2 - assign \t1 1'0 - assign \t1 $3 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init end process $group_3 - assign \o 2'00 - assign \o { \t1 \t0 } + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $7 - end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 process $group_4 - assign \en_o 1'0 - assign \en_o $7 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_b" -module \rdpick_CR_cr_b - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 1'0 - assign \ni $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end - process $group_2 - assign \o 1'0 - assign \o { \t0 } + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c" -module \rdpick_CR_cr_c - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init end - process $group_0 - assign \ni 1'0 - assign \ni $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end - process $group_2 - assign \o 1'0 - assign \o { \t0 } + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1" -module \rdpick_FAST_fast1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 5 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 5 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 5 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 5 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 5'00000 - assign \ni $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_2 - assign \t1 1'0 - assign \t1 $3 + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_3 - assign \t2 1'0 - assign \t2 $7 + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } - connect \Y $16 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_5 - assign \t4 1'0 - assign \t4 $15 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end - process $group_6 - assign \o 5'00000 - assign \o { \t4 \t3 \t2 \t1 \t0 } - sync init + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 16 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \next_bits + connect \B 4'1101 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $19 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_7 - assign \en_o 1'0 - assign \en_o $19 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1" -module \rdpick_SPR_spr1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_50" +module \core_calculate_stage_50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$300 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 end process $group_0 - assign \ni 1'0 - assign \ni $1 + assign \muxid$1 2'00 + assign \muxid$1 \muxid sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 process $group_1 - assign \t0 1'0 - assign \t0 \i + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } sync init end - process $group_2 - assign \o 1'0 - assign \o { \t0 } + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 - end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o" -module \wrpick_INT_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 10 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 10 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 10 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 10 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 10 - connect \A \i - connect \Y $1 + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init end - process $group_0 - assign \ni 10'0000000000 - assign \ni $1 + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init end - process $group_2 - assign \t1 1'0 - assign \t1 $3 + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init end - process $group_3 - assign \t2 1'0 - assign \t2 $7 + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init end - process $group_4 - assign \t3 1'0 - assign \t3 $11 + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } - connect \Y $16 + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init end - process $group_5 - assign \t4 1'0 - assign \t4 $15 + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } - connect \Y $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init end - process $group_6 - assign \t5 1'0 - assign \t5 $19 + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $25 + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_51.core.trial0" +module \trial0$305 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } - connect \Y $24 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 end - process $group_7 - assign \t6 1'0 - assign \t6 $23 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] } - connect \Y $28 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001100 + connect \Y $8 end - process $group_8 - assign \t7 1'0 - assign \t7 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $33 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_51.core.trial1" +module \trial1$306 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 9 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] } - connect \Y $32 + connect \A \operation + connect \B 1'1 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \Y $31 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 end - process $group_9 - assign \t8 1'0 - assign \t8 $31 + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [8:0] [8] \i [8:0] [7] \i [8:0] [6] \i [8:0] [5] \i [8:0] [4] \i [8:0] [3] \i [8:0] [2] \i [8:0] [1] \i [8:0] [0] \ni [9] } - connect \Y $36 + connect \A \operation + connect \B 1'1 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $36 - connect \Y $35 - end - process $group_10 - assign \t9 1'0 - assign \t9 $35 - sync init - end - process $group_11 - assign \o 10'0000000000 - assign \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - sync init + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001100 + connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $39 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 end - process $group_12 - assign \en_o 1'0 - assign \en_o $39 + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr" -module \wrpick_CR_full_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_51.core.pe" +module \pe$307 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i + connect \B 1'0 connect \Y $1 end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_51.core" +module \core$304 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$305 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$306 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$307 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end process $group_0 - assign \ni 1'0 - assign \ni $1 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 process $group_1 - assign \t0 1'0 - assign \t0 \i + assign \operation$2 2'00 + assign \operation$2 \operation sync init end process $group_2 - assign \o 1'0 - assign \o { \t0 } + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 - end process $group_3 - assign \en_o 1'0 - assign \en_o $3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a" -module \wrpick_CR_cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 6 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 6 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \i - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init end - process $group_0 - assign \ni 6'000000 - assign \ni $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 end - process $group_2 - assign \t1 1'0 - assign \t1 $3 + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init end - process $group_3 - assign \t2 1'0 - assign \t2 $7 + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 end - process $group_4 - assign \t3 1'0 - assign \t3 $11 + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } - connect \Y $16 + connect \A \pe_n + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $18 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 end - process $group_5 - assign \t4 1'0 - assign \t4 $15 + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $20 + connect \A \next_bits + connect \B 1'0 connect \Y $19 end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - process $group_7 - assign \o 6'000000 - assign \o { \t5 \t4 \t3 \t2 \t1 \t0 } + process $group_18 + assign \nbe 1'0 + assign \nbe $19 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $23 - end - process $group_8 - assign \en_o 1'0 - assign \en_o $23 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca" -module \wrpick_XER_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 4'0000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - process $group_5 - assign \o 4'0000 - assign \o { \t3 \t2 \t1 \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $15 - end - process $group_6 - assign \en_o 1'0 - assign \en_o $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov" -module \wrpick_XER_xer_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 4'0000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - process $group_5 - assign \o 4'0000 - assign \o { \t3 \t2 \t1 \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $15 - end - process $group_6 - assign \en_o 1'0 - assign \en_o $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so" -module \wrpick_XER_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 4'0000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - process $group_5 - assign \o 4'0000 - assign \o { \t3 \t2 \t1 \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $15 - end - process $group_6 - assign \en_o 1'0 - assign \en_o $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast1" -module \wrpick_FAST_fast1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 5 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 5 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 5 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 5 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 5'00000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - process $group_6 - assign \o 5'00000 - assign \o { \t4 \t3 \t2 \t1 \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $19 - end - process $group_7 - assign \en_o 1'0 - assign \en_o $19 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_nia" -module \wrpick_STATE_nia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 2'00 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init + connect \A \next_bits + connect \B 1'1 + connect \Y $22 end - process $group_3 - assign \o 2'00 - assign \o { \t1 \t0 } + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $7 - end - process $group_4 - assign \en_o 1'0 - assign \en_o $7 - sync init + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_msr" -module \wrpick_STATE_msr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 1'0 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i - sync init - end - process $group_2 - assign \o 1'0 - assign \o { \t0 } - sync init + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 sync init end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_SPR_spr1" -module \wrpick_SPR_spr1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 16 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 1'0 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i - sync init - end - process $group_2 - assign \o 1'0 - assign \o { \t0 } - sync init + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \next_bits + connect \B 4'1100 + connect \Y $30 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core" -module \core - attribute \src "simple/issuer.py:89" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:82" - wire width 1 output 1 \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332" - wire width 1 input 2 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 3 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 input 4 \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 5 \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 input 6 \cu_st__go_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 7 \cia__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 8 \cia__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:90" - wire width 1 input 9 \core_reset_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:91" - wire width 1 output 10 \core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:91" - wire width 1 \core_terminate_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \msr__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 12 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire width 1 input 13 \valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:81" - wire width 1 input 14 \issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331" - wire width 32 input 15 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 16 \dec2_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 17 \dec2_msr +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12.core_calculate_stage_51" +module \core_calculate_stage_51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -140722,38 +141481,8 @@ module \core attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39" - wire width 7 output 18 \insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 19 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 20 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 21 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 22 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 23 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 24 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 25 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 26 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 27 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 8 output 28 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 input 29 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 45 output 30 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 31 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 output 32 \dbus__dat_w - attribute \src "simple/issuer.py:89" - wire width 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -140766,406 +141495,74 @@ module \core attribute \enum_value_00100000000 "MUL" attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40" - wire width 11 \pdecode2_fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pdecode2_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 1 \pdecode2_invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 1 \pdecode2_zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 1 \pdecode2_invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 \pdecode2_write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 2 \pdecode2_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 \pdecode2_output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 1 \pdecode2_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 1 \pdecode2_is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" - wire width 4 \pdecode2_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38" - wire width 32 \pdecode2_insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82" - wire width 1 \pdecode2_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" - wire width 1 \pdecode2_read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" - wire width 1 \pdecode2_write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_cr_in2_ok$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" - wire width 64 \pdecode2_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 1 \pdecode2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" - wire width 64 \pdecode2_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 5 \pdecode2_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" - wire width 13 \pdecode2_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" - wire width 1 \pdecode2_input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" - wire width 1 \pdecode2_output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pdecode2_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 1 \pdecode2_byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 \pdecode2_sign_extend - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" - wire width 2 \pdecode2_ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \pdecode2_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \pdecode2_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \pdecode2_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \pdecode2_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \pdecode2_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \pdecode2_cr_in2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \pdecode2_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \pdecode2_fast2 - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute 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attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \pdecode2_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \pdecode2_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \pdecode2_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \pdecode2_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \pdecode2_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \pdecode2_fasto2 - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \pdecode2_spro - cell \pdecode2 \pdecode2 - connect \bigendian \bigendian - connect \raw_opcode_in \raw_opcode_in - connect \dec2_pc \dec2_pc - connect \dec2_msr \dec2_msr - connect \insn_type \insn_type - connect \fn_unit \pdecode2_fn_unit - connect \imm \pdecode2_imm - connect \imm_ok \pdecode2_imm_ok - connect \rc \pdecode2_rc - connect \rc_ok \pdecode2_rc_ok - connect \oe \pdecode2_oe - connect \oe_ok \pdecode2_oe_ok - connect \invert_a \pdecode2_invert_a - connect \zero_a \pdecode2_zero_a - connect \invert_out \pdecode2_invert_out - connect \write_cr0 \pdecode2_write_cr0 - connect \input_carry \pdecode2_input_carry - connect \output_carry \pdecode2_output_carry - connect \is_32bit \pdecode2_is_32bit - connect \is_signed \pdecode2_is_signed - connect \data_len \pdecode2_data_len - connect \insn \pdecode2_insn - connect \reg1_ok \pdecode2_reg1_ok - connect \reg2_ok \pdecode2_reg2_ok - connect \xer_in \pdecode2_xer_in - connect \read_cr_whole \pdecode2_read_cr_whole - connect \write_cr_whole \pdecode2_write_cr_whole - connect \cr_in1_ok \pdecode2_cr_in1_ok - connect \cr_in2_ok \pdecode2_cr_in2_ok - connect \cr_in2_ok$1 \pdecode2_cr_in2_ok$1 - connect \cia \pdecode2_cia - connect \lk \pdecode2_lk - connect \fast1_ok \pdecode2_fast1_ok - connect \fast2_ok \pdecode2_fast2_ok - connect \msr \pdecode2_msr - connect \traptype \pdecode2_traptype - connect \trapaddr \pdecode2_trapaddr - connect \spr1_ok \pdecode2_spr1_ok - connect \input_cr \pdecode2_input_cr - connect \output_cr \pdecode2_output_cr - connect \reg3_ok \pdecode2_reg3_ok - connect \byte_reverse \pdecode2_byte_reverse - connect \sign_extend \pdecode2_sign_extend - connect \ldst_mode \pdecode2_ldst_mode - connect \reg2 \pdecode2_reg2 - connect \reg3 \pdecode2_reg3 - connect \reg1 \pdecode2_reg1 - connect \cr_in1 \pdecode2_cr_in1 - connect \cr_in2 \pdecode2_cr_in2 - connect \cr_in2$2 \pdecode2_cr_in2$2 - connect \fast1 \pdecode2_fast1 - connect \fast2 \pdecode2_fast2 - connect \spr1 \pdecode2_spr1 - connect \rego \pdecode2_rego - connect \ea \pdecode2_ea - connect \cr_out \pdecode2_cr_out - connect \fasto1 \pdecode2_fasto1 - connect \fasto2 \pdecode2_fasto2 - connect \spro \pdecode2_spro - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -141240,7 +141637,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_alu0__insn_type + wire width 7 output 34 \logical_op__insn_type$2 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -141254,49 +141651,411 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_alu0__fn_unit + wire width 11 output 35 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_alu0__imm_data__imm + wire width 64 output 36 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__imm_data__imm_ok + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__rc__rc + wire width 1 output 38 \logical_op__rc__rc$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__rc__rc_ok + wire width 1 output 39 \logical_op__rc__rc_ok$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__oe__oe + wire width 1 output 40 \logical_op__oe__oe$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__oe__oe_ok + wire width 1 output 41 \logical_op__oe__oe_ok$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__invert_a + wire width 1 output 42 \logical_op__invert_in$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__zero_a + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__invert_out + wire width 2 output 44 \logical_op__input_carry$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__write_cr0 + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$304 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_12" +module \pipe_middle_12 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_alu_alu0__input_carry + wire width 2 input 15 \logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__output_carry + wire width 1 input 16 \logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__is_32bit + wire width 1 input 17 \logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_alu0__is_signed + wire width 1 input 18 \logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \fus_oper_i_alu_alu0__data_len + wire width 1 input 19 \logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_alu0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 \fus_cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 \fus_cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 4 \fus_cu_rdmaskn_i + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -141371,7 +142130,9 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_cr0__insn_type + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -141385,21 +142146,143 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_cr0__fn_unit + wire width 11 output 41 \logical_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_cr0__insn + wire width 11 \logical_op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_cr0__read_cr_whole + wire width 64 output 42 \logical_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_cr0__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 \fus_cu_issue_i$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 \fus_cu_busy_o$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 6 \fus_cu_rdmaskn_i$5 + wire width 64 \logical_op__imm_data__imm$4$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_branch0__cia + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$290 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$291 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_48_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -141474,7 +142357,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_branch0__insn_type + wire width 7 \core_calculate_stage_48_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -141488,23 +142371,73 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_branch0__fn_unit + wire width 11 \core_calculate_stage_48_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_branch0__insn + wire width 64 \core_calculate_stage_48_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_branch0__imm_data__imm + wire width 1 \core_calculate_stage_48_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_branch0__imm_data__imm_ok + wire width 1 \core_calculate_stage_48_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_branch0__lk + wire width 1 \core_calculate_stage_48_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_branch0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 \fus_cu_issue_i$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 \fus_cu_busy_o$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 \fus_cu_rdmaskn_i$8 + wire width 1 \core_calculate_stage_48_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_48_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_48_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_48_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_48_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_48_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_48_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_48_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_48_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_48_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_48_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_48_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_48_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_48_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_48_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_48_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_48_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_48_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_48_muxid$34 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -141579,7 +142512,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_trap0__insn_type + wire width 7 \core_calculate_stage_48_logical_op__insn_type$35 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -141593,25 +142526,141 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_trap0__fn_unit + wire width 11 \core_calculate_stage_48_logical_op__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_trap0__insn + wire width 64 \core_calculate_stage_48_logical_op__imm_data__imm$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_trap0__msr + wire width 1 \core_calculate_stage_48_logical_op__imm_data__imm_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_trap0__cia + wire width 1 \core_calculate_stage_48_logical_op__rc__rc$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_trap0__is_32bit + wire width 1 \core_calculate_stage_48_logical_op__rc__rc_ok$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 5 \fus_oper_i_alu_trap0__traptype + wire width 1 \core_calculate_stage_48_logical_op__oe__oe$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \fus_oper_i_alu_trap0__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 \fus_cu_issue_i$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 \fus_cu_busy_o$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 4 \fus_cu_rdmaskn_i$11 + wire width 1 \core_calculate_stage_48_logical_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__invert_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_48_logical_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__write_cr0$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_48_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_48_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_48_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_48_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_48_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_48_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_48_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_48_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_48_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_48_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_48_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_48_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_48_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_48_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_48_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_48_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_48_compare_rhs$66 + cell \core_calculate_stage_48 \core_calculate_stage_48 + connect \muxid \core_calculate_stage_48_muxid + connect \logical_op__insn_type \core_calculate_stage_48_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_48_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_48_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_48_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_48_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_48_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_48_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_48_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_48_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_48_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_48_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_48_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_48_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_48_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_48_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_48_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_48_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_48_logical_op__insn + connect \ra \core_calculate_stage_48_ra + connect \rb \core_calculate_stage_48_rb + connect \xer_so \core_calculate_stage_48_xer_so + connect \divisor_neg \core_calculate_stage_48_divisor_neg + connect \dividend_neg \core_calculate_stage_48_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_48_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_48_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_48_div_by_zero + connect \divisor_radicand \core_calculate_stage_48_divisor_radicand + connect \operation \core_calculate_stage_48_operation + connect \quotient_root \core_calculate_stage_48_quotient_root + connect \root_times_radicand \core_calculate_stage_48_root_times_radicand + connect \compare_lhs \core_calculate_stage_48_compare_lhs + connect \compare_rhs \core_calculate_stage_48_compare_rhs + connect \muxid$1 \core_calculate_stage_48_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_48_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_48_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_48_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_48_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_48_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_48_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_48_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_48_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_48_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_48_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_48_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_48_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_48_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_48_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_48_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_48_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_48_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_48_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_48_ra$53 + connect \rb$21 \core_calculate_stage_48_rb$54 + connect \xer_so$22 \core_calculate_stage_48_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_48_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_48_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_48_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_48_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_48_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_48_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_48_operation$62 + connect \quotient_root$30 \core_calculate_stage_48_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_48_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_48_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_48_compare_rhs$66 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_49_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -141686,7 +142735,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_logical0__insn_type + wire width 7 \core_calculate_stage_49_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -141700,49 +142749,73 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_logical0__fn_unit + wire width 11 \core_calculate_stage_49_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_logical0__imm_data__imm + wire width 64 \core_calculate_stage_49_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__imm_data__imm_ok + wire width 1 \core_calculate_stage_49_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__rc__rc + wire width 1 \core_calculate_stage_49_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__rc__rc_ok + wire width 1 \core_calculate_stage_49_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__oe__oe + wire width 1 \core_calculate_stage_49_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__oe__oe_ok + wire width 1 \core_calculate_stage_49_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__invert_a + wire width 1 \core_calculate_stage_49_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__zero_a + wire width 1 \core_calculate_stage_49_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_alu_logical0__input_carry + wire width 2 \core_calculate_stage_49_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__invert_out + wire width 1 \core_calculate_stage_49_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__write_cr0 + wire width 1 \core_calculate_stage_49_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__output_carry + wire width 1 \core_calculate_stage_49_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__is_32bit + wire width 1 \core_calculate_stage_49_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_logical0__is_signed + wire width 1 \core_calculate_stage_49_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \fus_oper_i_alu_logical0__data_len + wire width 4 \core_calculate_stage_49_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_logical0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 \fus_cu_issue_i$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 \fus_cu_busy_o$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 2 \fus_cu_rdmaskn_i$14 + wire width 32 \core_calculate_stage_49_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_49_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_49_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_49_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_49_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_49_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_49_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_49_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_49_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_49_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_49_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_49_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_49_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_49_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_49_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_49_muxid$67 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -141817,7 +142890,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_spr0__insn_type + wire width 7 \core_calculate_stage_49_logical_op__insn_type$68 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -141831,17 +142904,141 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_spr0__fn_unit + wire width 11 \core_calculate_stage_49_logical_op__fn_unit$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_spr0__insn + wire width 64 \core_calculate_stage_49_logical_op__imm_data__imm$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_spr0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 \fus_cu_issue_i$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 \fus_cu_busy_o$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 6 \fus_cu_rdmaskn_i$17 + wire width 1 \core_calculate_stage_49_logical_op__imm_data__imm_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__rc__rc_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_49_logical_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__invert_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__write_cr0$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_49_logical_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_49_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_49_logical_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_49_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_49_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_49_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_49_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_49_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_49_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_49_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_49_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_49_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_49_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_49_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_49_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_49_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_49_compare_rhs$99 + cell \core_calculate_stage_49 \core_calculate_stage_49 + connect \muxid \core_calculate_stage_49_muxid + connect \logical_op__insn_type \core_calculate_stage_49_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_49_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_49_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_49_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_49_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_49_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_49_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_49_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_49_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_49_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_49_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_49_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_49_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_49_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_49_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_49_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_49_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_49_logical_op__insn + connect \ra \core_calculate_stage_49_ra + connect \rb \core_calculate_stage_49_rb + connect \xer_so \core_calculate_stage_49_xer_so + connect \divisor_neg \core_calculate_stage_49_divisor_neg + connect \dividend_neg \core_calculate_stage_49_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_49_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_49_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_49_div_by_zero + connect \divisor_radicand \core_calculate_stage_49_divisor_radicand + connect \operation \core_calculate_stage_49_operation + connect \quotient_root \core_calculate_stage_49_quotient_root + connect \root_times_radicand \core_calculate_stage_49_root_times_radicand + connect \compare_lhs \core_calculate_stage_49_compare_lhs + connect \compare_rhs \core_calculate_stage_49_compare_rhs + connect \muxid$1 \core_calculate_stage_49_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_49_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_49_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_49_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_49_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_49_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_49_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_49_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_49_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_49_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_49_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_49_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_49_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_49_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_49_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_49_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_49_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_49_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_49_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_49_ra$86 + connect \rb$21 \core_calculate_stage_49_rb$87 + connect \xer_so$22 \core_calculate_stage_49_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_49_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_49_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_49_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_49_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_49_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_49_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_49_operation$95 + connect \quotient_root$30 \core_calculate_stage_49_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_49_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_49_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_49_compare_rhs$99 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_50_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -141916,7 +143113,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_div0__insn_type + wire width 7 \core_calculate_stage_50_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -141930,49 +143127,73 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_div0__fn_unit + wire width 11 \core_calculate_stage_50_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_div0__imm_data__imm + wire width 64 \core_calculate_stage_50_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__imm_data__imm_ok + wire width 1 \core_calculate_stage_50_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__rc__rc + wire width 1 \core_calculate_stage_50_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__rc__rc_ok + wire width 1 \core_calculate_stage_50_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__oe__oe + wire width 1 \core_calculate_stage_50_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__oe__oe_ok + wire width 1 \core_calculate_stage_50_logical_op__oe__oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__invert_a + wire width 1 \core_calculate_stage_50_logical_op__invert_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__zero_a + wire width 1 \core_calculate_stage_50_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_alu_div0__input_carry + wire width 2 \core_calculate_stage_50_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__invert_out + wire width 1 \core_calculate_stage_50_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__write_cr0 + wire width 1 \core_calculate_stage_50_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__output_carry + wire width 1 \core_calculate_stage_50_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__is_32bit + wire width 1 \core_calculate_stage_50_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_div0__is_signed + wire width 1 \core_calculate_stage_50_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \fus_oper_i_alu_div0__data_len + wire width 4 \core_calculate_stage_50_logical_op__data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_div0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 \fus_cu_issue_i$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 \fus_cu_busy_o$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 \fus_cu_rdmaskn_i$20 + wire width 32 \core_calculate_stage_50_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_50_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_50_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_50_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_50_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_50_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_50_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_50_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_50_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_50_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_50_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_50_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_50_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_50_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_50_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_50_muxid$100 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -142047,7 +143268,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_mul0__insn_type + wire width 7 \core_calculate_stage_50_logical_op__insn_type$101 attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -142061,39 +143282,141 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_mul0__fn_unit + wire width 11 \core_calculate_stage_50_logical_op__fn_unit$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_mul0__imm_data__imm + wire width 64 \core_calculate_stage_50_logical_op__imm_data__imm$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__imm_data__imm_ok + wire width 1 \core_calculate_stage_50_logical_op__imm_data__imm_ok$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__rc__rc + wire width 1 \core_calculate_stage_50_logical_op__rc__rc$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__rc__rc_ok + wire width 1 \core_calculate_stage_50_logical_op__rc__rc_ok$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__oe__oe + wire width 1 \core_calculate_stage_50_logical_op__oe__oe$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__oe__oe_ok + wire width 1 \core_calculate_stage_50_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_50_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_50_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__invert_a + wire width 2 \core_calculate_stage_50_logical_op__input_carry$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__zero_a + wire width 1 \core_calculate_stage_50_logical_op__invert_out$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__invert_out + wire width 1 \core_calculate_stage_50_logical_op__write_cr0$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__write_cr0 + wire width 1 \core_calculate_stage_50_logical_op__output_carry$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__is_32bit + wire width 1 \core_calculate_stage_50_logical_op__is_32bit$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_mul0__is_signed + wire width 1 \core_calculate_stage_50_logical_op__is_signed$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_mul0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 \fus_cu_issue_i$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 \fus_cu_busy_o$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 \fus_cu_rdmaskn_i$23 + wire width 4 \core_calculate_stage_50_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_50_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_50_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_50_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_50_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_50_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_50_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_50_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_50_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_50_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_50_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_50_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_50_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_50_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_50_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_50_compare_rhs$132 + cell \core_calculate_stage_50 \core_calculate_stage_50 + connect \muxid \core_calculate_stage_50_muxid + connect \logical_op__insn_type \core_calculate_stage_50_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_50_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_50_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_50_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_50_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_50_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_50_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_50_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_50_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_50_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_50_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_50_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_50_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_50_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_50_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_50_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_50_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_50_logical_op__insn + connect \ra \core_calculate_stage_50_ra + connect \rb \core_calculate_stage_50_rb + connect \xer_so \core_calculate_stage_50_xer_so + connect \divisor_neg \core_calculate_stage_50_divisor_neg + connect \dividend_neg \core_calculate_stage_50_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_50_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_50_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_50_div_by_zero + connect \divisor_radicand \core_calculate_stage_50_divisor_radicand + connect \operation \core_calculate_stage_50_operation + connect \quotient_root \core_calculate_stage_50_quotient_root + connect \root_times_radicand \core_calculate_stage_50_root_times_radicand + connect \compare_lhs \core_calculate_stage_50_compare_lhs + connect \compare_rhs \core_calculate_stage_50_compare_rhs + connect \muxid$1 \core_calculate_stage_50_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_50_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_50_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_50_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_50_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_50_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_50_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_50_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_50_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_50_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_50_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_50_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_50_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_50_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_50_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_50_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_50_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_50_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_50_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_50_ra$119 + connect \rb$21 \core_calculate_stage_50_rb$120 + connect \xer_so$22 \core_calculate_stage_50_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_50_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_50_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_50_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_50_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_50_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_50_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_50_operation$128 + connect \quotient_root$30 \core_calculate_stage_50_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_50_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_50_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_50_compare_rhs$132 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_51_muxid attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -142168,7 +143491,7 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_alu_shift_rot0__insn_type + wire width 7 \core_calculate_stage_51_logical_op__insn_type attribute \enum_base_type "Function" attribute \enum_value_00000000000 "NONE" attribute \enum_value_00000000010 "ALU" @@ -142182,43 +143505,73 @@ module \core attribute \enum_value_01000000000 "DIV" attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \fus_oper_i_alu_shift_rot0__fn_unit + wire width 11 \core_calculate_stage_51_logical_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__imm + wire width 64 \core_calculate_stage_51_logical_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__imm_data__imm_ok + wire width 1 \core_calculate_stage_51_logical_op__imm_data__imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__rc__rc + wire width 1 \core_calculate_stage_51_logical_op__rc__rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__rc__rc_ok + wire width 1 \core_calculate_stage_51_logical_op__rc__rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__oe__oe + wire width 1 \core_calculate_stage_51_logical_op__oe__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__oe__oe_ok + wire width 1 \core_calculate_stage_51_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_51_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_51_logical_op__zero_a attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_alu_shift_rot0__input_carry + wire width 2 \core_calculate_stage_51_logical_op__input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__output_carry + wire width 1 \core_calculate_stage_51_logical_op__invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__input_cr + wire width 1 \core_calculate_stage_51_logical_op__write_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__output_cr + wire width 1 \core_calculate_stage_51_logical_op__output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__is_32bit + wire width 1 \core_calculate_stage_51_logical_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_alu_shift_rot0__is_signed + wire width 1 \core_calculate_stage_51_logical_op__is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \fus_oper_i_alu_shift_rot0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 \fus_cu_issue_i$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 \fus_cu_busy_o$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 4 \fus_cu_rdmaskn_i$26 + wire width 4 \core_calculate_stage_51_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_51_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_51_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_51_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_51_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_51_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_51_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_51_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_51_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_51_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_51_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_51_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_51_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_51_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_51_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_51_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_51_muxid$133 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -142293,466 +143646,82679 @@ module \core attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \fus_oper_i_ldst_ldst0__insn_type + wire width 7 \core_calculate_stage_51_logical_op__insn_type$134 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \fus_oper_i_ldst_ldst0__imm_data__imm + wire width 11 \core_calculate_stage_51_logical_op__fn_unit$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__imm_data__imm_ok + wire width 64 \core_calculate_stage_51_logical_op__imm_data__imm$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__zero_a + wire width 1 \core_calculate_stage_51_logical_op__imm_data__imm_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__rc__rc + wire width 1 \core_calculate_stage_51_logical_op__rc__rc$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__rc__rc_ok + wire width 1 \core_calculate_stage_51_logical_op__rc__rc_ok$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__oe__oe + wire width 1 \core_calculate_stage_51_logical_op__oe__oe$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__oe__oe_ok + wire width 1 \core_calculate_stage_51_logical_op__oe__oe_ok$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__is_32bit + wire width 1 \core_calculate_stage_51_logical_op__invert_in$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__is_signed + wire width 1 \core_calculate_stage_51_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \fus_oper_i_ldst_ldst0__data_len + wire width 2 \core_calculate_stage_51_logical_op__input_carry$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__byte_reverse + wire width 1 \core_calculate_stage_51_logical_op__invert_out$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \fus_oper_i_ldst_ldst0__sign_extend - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" + wire width 1 \core_calculate_stage_51_logical_op__write_cr0$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \fus_oper_i_ldst_ldst0__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 \fus_cu_issue_i$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106" - wire width 1 \fus_cu_busy_o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 3 \fus_cu_rdmaskn_i$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 \fus_cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 \fus_cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 \fus_cu_rd__rel_o$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 \fus_cu_rd__go_i$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src2_i$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 \fus_cu_rd__rel_o$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 \fus_cu_rd__go_i$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src2_i$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 \fus_cu_rd__rel_o$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 \fus_cu_rd__go_i$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src2_i$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_rd__rel_o$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_rd__go_i$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src2_i$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_rd__rel_o$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_rd__go_i$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src2_i$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 \fus_cu_rd__rel_o$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 \fus_cu_rd__go_i$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src2_i$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_rd__rel_o$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_rd__go_i$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src2_i$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src3_i$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src1_i$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src1_i$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71" - wire width 64 \fus_src1_i$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 \fus_cu_rd__rel_o$55 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 \fus_cu_wr__rel_o$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 \fus_cu_wr__go_i$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_wr__rel_o$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_wr__go_i$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 \fus_cu_wr__rel_o$90 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_wr__rel_o$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_wr__go_i$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 \fus_cu_wr__rel_o$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 \fus_cu_wr__go_i$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest1_o$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest1_o$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest1_o$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest1_o$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest1_o$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest1_o$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest1_o$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 32 \fus_dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 \fus_dest2_o$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 \fus_dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 \fus_dest2_o$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 \fus_dest2_o$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 \fus_dest2_o$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 4 \fus_dest2_o$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 \fus_dest3_o$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 \fus_dest3_o$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 \fus_dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 \fus_dest3_o$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 \fus_dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 \fus_dest5_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 \fus_dest3_o$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 2 \fus_dest3_o$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 \fus_dest5_o$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 \fus_dest4_o$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 \fus_dest4_o$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 1 \fus_dest4_o$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_wr__rel_o$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \fus_cu_wr__go_i$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast1_ok$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast1_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast2_ok$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest1_o$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest2_o$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest3_o$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest2_o$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest3_o$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_nia_ok$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest3_o$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest4_o$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest5_o$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83" - wire width 64 \fus_dest2_o$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 \fus_ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 \fus_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 \fus_ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 \fus_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 \fus_ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 \fus_ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_ldst_port0_st_data_i_ok - cell \fus \fus - connect \coresync_clk \coresync_clk - connect \cu_st__rel_o \cu_st__rel_o - connect \cu_ad__go_i \cu_ad__go_i - connect \cu_ad__rel_o \cu_ad__rel_o - connect \cu_st__go_i \cu_st__go_i - connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type - connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__imm \fus_oper_i_alu_alu0__imm_data__imm - connect \oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm_ok - connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc_ok - connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe_ok - connect \oper_i_alu_alu0__invert_a \fus_oper_i_alu_alu0__invert_a - connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a - connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out - connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 - connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry - connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry - connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit - connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed - connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len - connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn - connect \cu_issue_i \fus_cu_issue_i - connect \cu_busy_o \fus_cu_busy_o - connect \cu_rdmaskn_i \fus_cu_rdmaskn_i - connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type - connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit - connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn - connect \oper_i_alu_cr0__read_cr_whole \fus_oper_i_alu_cr0__read_cr_whole - connect \oper_i_alu_cr0__write_cr_whole \fus_oper_i_alu_cr0__write_cr_whole - connect \cu_issue_i$1 \fus_cu_issue_i$3 - connect \cu_busy_o$2 \fus_cu_busy_o$4 - connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$5 - connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia - connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type - connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit - connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__imm_data__imm \fus_oper_i_alu_branch0__imm_data__imm - connect \oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm_ok - connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk - connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit - connect \cu_issue_i$4 \fus_cu_issue_i$6 - connect \cu_busy_o$5 \fus_cu_busy_o$7 - connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$8 - connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type - connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit - connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn - connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr - connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia - connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit - connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype - connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr - connect \cu_issue_i$7 \fus_cu_issue_i$9 - connect \cu_busy_o$8 \fus_cu_busy_o$10 - connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$11 - connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type - connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__imm \fus_oper_i_alu_logical0__imm_data__imm - connect \oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm_ok - connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc_ok - connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe_ok - connect \oper_i_alu_logical0__invert_a \fus_oper_i_alu_logical0__invert_a - connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a - connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry - connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out - connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 - connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry - connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit - connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed - connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len - connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn - connect \cu_issue_i$10 \fus_cu_issue_i$12 - connect \cu_busy_o$11 \fus_cu_busy_o$13 - connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$14 - connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type - connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit - connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn - connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit - connect \cu_issue_i$13 \fus_cu_issue_i$15 - connect \cu_busy_o$14 \fus_cu_busy_o$16 - connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$17 - connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type - connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__imm \fus_oper_i_alu_div0__imm_data__imm - connect \oper_i_alu_div0__imm_data__imm_ok \fus_oper_i_alu_div0__imm_data__imm_ok - connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__rc__rc_ok \fus_oper_i_alu_div0__rc__rc_ok - connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__oe_ok \fus_oper_i_alu_div0__oe__oe_ok - connect \oper_i_alu_div0__invert_a \fus_oper_i_alu_div0__invert_a - connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a - connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry + wire width 1 \core_calculate_stage_51_logical_op__output_carry$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_51_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_51_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_51_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_51_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_51_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_51_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_51_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_51_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_51_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_51_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_51_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_51_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_51_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_51_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_51_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_51_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_51_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_51_compare_rhs$165 + cell \core_calculate_stage_51 \core_calculate_stage_51 + connect \muxid \core_calculate_stage_51_muxid + connect \logical_op__insn_type \core_calculate_stage_51_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_51_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_51_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_51_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_51_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_51_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_51_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_51_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_51_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_51_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_51_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_51_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_51_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_51_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_51_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_51_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_51_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_51_logical_op__insn + connect \ra \core_calculate_stage_51_ra + connect \rb \core_calculate_stage_51_rb + connect \xer_so \core_calculate_stage_51_xer_so + connect \divisor_neg \core_calculate_stage_51_divisor_neg + connect \dividend_neg \core_calculate_stage_51_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_51_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_51_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_51_div_by_zero + connect \divisor_radicand \core_calculate_stage_51_divisor_radicand + connect \operation \core_calculate_stage_51_operation + connect \quotient_root \core_calculate_stage_51_quotient_root + connect \root_times_radicand \core_calculate_stage_51_root_times_radicand + connect \compare_lhs \core_calculate_stage_51_compare_lhs + connect \compare_rhs \core_calculate_stage_51_compare_rhs + connect \muxid$1 \core_calculate_stage_51_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_51_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_51_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_51_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_51_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_51_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_51_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_51_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_51_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_51_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_51_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_51_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_51_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_51_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_51_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_51_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_51_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_51_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_51_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_51_ra$152 + connect \rb$21 \core_calculate_stage_51_rb$153 + connect \xer_so$22 \core_calculate_stage_51_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_51_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_51_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_51_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_51_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_51_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_51_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_51_operation$161 + connect \quotient_root$30 \core_calculate_stage_51_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_51_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_51_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_51_compare_rhs$165 + end + process $group_0 + assign \core_calculate_stage_48_muxid 2'00 + assign \core_calculate_stage_48_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_48_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_48_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_48_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_48_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_48_logical_op__rc__rc 1'0 + assign \core_calculate_stage_48_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_48_logical_op__oe__oe 1'0 + assign \core_calculate_stage_48_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_48_logical_op__invert_in 1'0 + assign \core_calculate_stage_48_logical_op__zero_a 1'0 + assign \core_calculate_stage_48_logical_op__input_carry 2'00 + assign \core_calculate_stage_48_logical_op__invert_out 1'0 + assign \core_calculate_stage_48_logical_op__write_cr0 1'0 + assign \core_calculate_stage_48_logical_op__output_carry 1'0 + assign \core_calculate_stage_48_logical_op__is_32bit 1'0 + assign \core_calculate_stage_48_logical_op__is_signed 1'0 + assign \core_calculate_stage_48_logical_op__data_len 4'0000 + assign \core_calculate_stage_48_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_48_logical_op__insn \core_calculate_stage_48_logical_op__data_len \core_calculate_stage_48_logical_op__is_signed \core_calculate_stage_48_logical_op__is_32bit \core_calculate_stage_48_logical_op__output_carry \core_calculate_stage_48_logical_op__write_cr0 \core_calculate_stage_48_logical_op__invert_out \core_calculate_stage_48_logical_op__input_carry \core_calculate_stage_48_logical_op__zero_a \core_calculate_stage_48_logical_op__invert_in { \core_calculate_stage_48_logical_op__oe__oe_ok \core_calculate_stage_48_logical_op__oe__oe } { \core_calculate_stage_48_logical_op__rc__rc_ok \core_calculate_stage_48_logical_op__rc__rc } { \core_calculate_stage_48_logical_op__imm_data__imm_ok \core_calculate_stage_48_logical_op__imm_data__imm } \core_calculate_stage_48_logical_op__fn_unit \core_calculate_stage_48_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \core_calculate_stage_48_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_48_ra \ra + sync init + end + process $group_20 + assign \core_calculate_stage_48_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_48_rb \rb + sync init + end + process $group_21 + assign \core_calculate_stage_48_xer_so 1'0 + assign \core_calculate_stage_48_xer_so \xer_so + sync init + end + process $group_22 + assign \core_calculate_stage_48_divisor_neg 1'0 + assign \core_calculate_stage_48_divisor_neg \divisor_neg + sync init + end + process $group_23 + assign \core_calculate_stage_48_dividend_neg 1'0 + assign \core_calculate_stage_48_dividend_neg \dividend_neg + sync init + end + process $group_24 + assign \core_calculate_stage_48_dive_abs_ov32 1'0 + assign \core_calculate_stage_48_dive_abs_ov32 \dive_abs_ov32 + sync init + end + process $group_25 + assign \core_calculate_stage_48_dive_abs_ov64 1'0 + assign \core_calculate_stage_48_dive_abs_ov64 \dive_abs_ov64 + sync init + end + process $group_26 + assign \core_calculate_stage_48_div_by_zero 1'0 + assign \core_calculate_stage_48_div_by_zero \div_by_zero + sync init + end + process $group_27 + assign \core_calculate_stage_48_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_48_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_calculate_stage_48_operation 2'00 + assign \core_calculate_stage_48_operation \operation + sync init + end + process $group_29 + assign \core_calculate_stage_48_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_48_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_calculate_stage_48_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_48_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_calculate_stage_48_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_48_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_calculate_stage_48_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_48_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \core_calculate_stage_49_muxid 2'00 + assign \core_calculate_stage_49_muxid \core_calculate_stage_48_muxid$34 + sync init + end + process $group_34 + assign \core_calculate_stage_49_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_49_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_49_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_49_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_49_logical_op__rc__rc 1'0 + assign \core_calculate_stage_49_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_49_logical_op__oe__oe 1'0 + assign \core_calculate_stage_49_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_49_logical_op__invert_in 1'0 + assign \core_calculate_stage_49_logical_op__zero_a 1'0 + assign \core_calculate_stage_49_logical_op__input_carry 2'00 + assign \core_calculate_stage_49_logical_op__invert_out 1'0 + assign \core_calculate_stage_49_logical_op__write_cr0 1'0 + assign \core_calculate_stage_49_logical_op__output_carry 1'0 + assign \core_calculate_stage_49_logical_op__is_32bit 1'0 + assign \core_calculate_stage_49_logical_op__is_signed 1'0 + assign \core_calculate_stage_49_logical_op__data_len 4'0000 + assign \core_calculate_stage_49_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_49_logical_op__insn \core_calculate_stage_49_logical_op__data_len \core_calculate_stage_49_logical_op__is_signed \core_calculate_stage_49_logical_op__is_32bit \core_calculate_stage_49_logical_op__output_carry \core_calculate_stage_49_logical_op__write_cr0 \core_calculate_stage_49_logical_op__invert_out \core_calculate_stage_49_logical_op__input_carry \core_calculate_stage_49_logical_op__zero_a \core_calculate_stage_49_logical_op__invert_in { \core_calculate_stage_49_logical_op__oe__oe_ok \core_calculate_stage_49_logical_op__oe__oe } { \core_calculate_stage_49_logical_op__rc__rc_ok \core_calculate_stage_49_logical_op__rc__rc } { \core_calculate_stage_49_logical_op__imm_data__imm_ok \core_calculate_stage_49_logical_op__imm_data__imm } \core_calculate_stage_49_logical_op__fn_unit \core_calculate_stage_49_logical_op__insn_type } { \core_calculate_stage_48_logical_op__insn$52 \core_calculate_stage_48_logical_op__data_len$51 \core_calculate_stage_48_logical_op__is_signed$50 \core_calculate_stage_48_logical_op__is_32bit$49 \core_calculate_stage_48_logical_op__output_carry$48 \core_calculate_stage_48_logical_op__write_cr0$47 \core_calculate_stage_48_logical_op__invert_out$46 \core_calculate_stage_48_logical_op__input_carry$45 \core_calculate_stage_48_logical_op__zero_a$44 \core_calculate_stage_48_logical_op__invert_in$43 { \core_calculate_stage_48_logical_op__oe__oe_ok$42 \core_calculate_stage_48_logical_op__oe__oe$41 } { \core_calculate_stage_48_logical_op__rc__rc_ok$40 \core_calculate_stage_48_logical_op__rc__rc$39 } { \core_calculate_stage_48_logical_op__imm_data__imm_ok$38 \core_calculate_stage_48_logical_op__imm_data__imm$37 } \core_calculate_stage_48_logical_op__fn_unit$36 \core_calculate_stage_48_logical_op__insn_type$35 } + sync init + end + process $group_52 + assign \core_calculate_stage_49_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_49_ra \core_calculate_stage_48_ra$53 + sync init + end + process $group_53 + assign \core_calculate_stage_49_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_49_rb \core_calculate_stage_48_rb$54 + sync init + end + process $group_54 + assign \core_calculate_stage_49_xer_so 1'0 + assign \core_calculate_stage_49_xer_so \core_calculate_stage_48_xer_so$55 + sync init + end + process $group_55 + assign \core_calculate_stage_49_divisor_neg 1'0 + assign \core_calculate_stage_49_divisor_neg \core_calculate_stage_48_divisor_neg$56 + sync init + end + process $group_56 + assign \core_calculate_stage_49_dividend_neg 1'0 + assign \core_calculate_stage_49_dividend_neg \core_calculate_stage_48_dividend_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_49_dive_abs_ov32 1'0 + assign \core_calculate_stage_49_dive_abs_ov32 \core_calculate_stage_48_dive_abs_ov32$58 + sync init + end + process $group_58 + assign \core_calculate_stage_49_dive_abs_ov64 1'0 + assign \core_calculate_stage_49_dive_abs_ov64 \core_calculate_stage_48_dive_abs_ov64$59 + sync init + end + process $group_59 + assign \core_calculate_stage_49_div_by_zero 1'0 + assign \core_calculate_stage_49_div_by_zero \core_calculate_stage_48_div_by_zero$60 + sync init + end + process $group_60 + assign \core_calculate_stage_49_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_49_divisor_radicand \core_calculate_stage_48_divisor_radicand$61 + sync init + end + process $group_61 + assign \core_calculate_stage_49_operation 2'00 + assign \core_calculate_stage_49_operation \core_calculate_stage_48_operation$62 + sync init + end + process $group_62 + assign \core_calculate_stage_49_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_49_quotient_root \core_calculate_stage_48_quotient_root$63 + sync init + end + process $group_63 + assign \core_calculate_stage_49_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_49_root_times_radicand \core_calculate_stage_48_root_times_radicand$64 + sync init + end + process $group_64 + assign \core_calculate_stage_49_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_49_compare_lhs \core_calculate_stage_48_compare_lhs$65 + sync init + end + process $group_65 + assign \core_calculate_stage_49_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_49_compare_rhs \core_calculate_stage_48_compare_rhs$66 + sync init + end + process $group_66 + assign \core_calculate_stage_50_muxid 2'00 + assign \core_calculate_stage_50_muxid \core_calculate_stage_49_muxid$67 + sync init + end + process $group_67 + assign \core_calculate_stage_50_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_50_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_50_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_50_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_50_logical_op__rc__rc 1'0 + assign \core_calculate_stage_50_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_50_logical_op__oe__oe 1'0 + assign \core_calculate_stage_50_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_50_logical_op__invert_in 1'0 + assign \core_calculate_stage_50_logical_op__zero_a 1'0 + assign \core_calculate_stage_50_logical_op__input_carry 2'00 + assign \core_calculate_stage_50_logical_op__invert_out 1'0 + assign \core_calculate_stage_50_logical_op__write_cr0 1'0 + assign \core_calculate_stage_50_logical_op__output_carry 1'0 + assign \core_calculate_stage_50_logical_op__is_32bit 1'0 + assign \core_calculate_stage_50_logical_op__is_signed 1'0 + assign \core_calculate_stage_50_logical_op__data_len 4'0000 + assign \core_calculate_stage_50_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_50_logical_op__insn \core_calculate_stage_50_logical_op__data_len \core_calculate_stage_50_logical_op__is_signed \core_calculate_stage_50_logical_op__is_32bit \core_calculate_stage_50_logical_op__output_carry \core_calculate_stage_50_logical_op__write_cr0 \core_calculate_stage_50_logical_op__invert_out \core_calculate_stage_50_logical_op__input_carry \core_calculate_stage_50_logical_op__zero_a \core_calculate_stage_50_logical_op__invert_in { \core_calculate_stage_50_logical_op__oe__oe_ok \core_calculate_stage_50_logical_op__oe__oe } { \core_calculate_stage_50_logical_op__rc__rc_ok \core_calculate_stage_50_logical_op__rc__rc } { \core_calculate_stage_50_logical_op__imm_data__imm_ok \core_calculate_stage_50_logical_op__imm_data__imm } \core_calculate_stage_50_logical_op__fn_unit \core_calculate_stage_50_logical_op__insn_type } { \core_calculate_stage_49_logical_op__insn$85 \core_calculate_stage_49_logical_op__data_len$84 \core_calculate_stage_49_logical_op__is_signed$83 \core_calculate_stage_49_logical_op__is_32bit$82 \core_calculate_stage_49_logical_op__output_carry$81 \core_calculate_stage_49_logical_op__write_cr0$80 \core_calculate_stage_49_logical_op__invert_out$79 \core_calculate_stage_49_logical_op__input_carry$78 \core_calculate_stage_49_logical_op__zero_a$77 \core_calculate_stage_49_logical_op__invert_in$76 { \core_calculate_stage_49_logical_op__oe__oe_ok$75 \core_calculate_stage_49_logical_op__oe__oe$74 } { \core_calculate_stage_49_logical_op__rc__rc_ok$73 \core_calculate_stage_49_logical_op__rc__rc$72 } { \core_calculate_stage_49_logical_op__imm_data__imm_ok$71 \core_calculate_stage_49_logical_op__imm_data__imm$70 } \core_calculate_stage_49_logical_op__fn_unit$69 \core_calculate_stage_49_logical_op__insn_type$68 } + sync init + end + process $group_85 + assign \core_calculate_stage_50_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_50_ra \core_calculate_stage_49_ra$86 + sync init + end + process $group_86 + assign \core_calculate_stage_50_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_50_rb \core_calculate_stage_49_rb$87 + sync init + end + process $group_87 + assign \core_calculate_stage_50_xer_so 1'0 + assign \core_calculate_stage_50_xer_so \core_calculate_stage_49_xer_so$88 + sync init + end + process $group_88 + assign \core_calculate_stage_50_divisor_neg 1'0 + assign \core_calculate_stage_50_divisor_neg \core_calculate_stage_49_divisor_neg$89 + sync init + end + process $group_89 + assign \core_calculate_stage_50_dividend_neg 1'0 + assign \core_calculate_stage_50_dividend_neg \core_calculate_stage_49_dividend_neg$90 + sync init + end + process $group_90 + assign \core_calculate_stage_50_dive_abs_ov32 1'0 + assign \core_calculate_stage_50_dive_abs_ov32 \core_calculate_stage_49_dive_abs_ov32$91 + sync init + end + process $group_91 + assign \core_calculate_stage_50_dive_abs_ov64 1'0 + assign \core_calculate_stage_50_dive_abs_ov64 \core_calculate_stage_49_dive_abs_ov64$92 + sync init + end + process $group_92 + assign \core_calculate_stage_50_div_by_zero 1'0 + assign \core_calculate_stage_50_div_by_zero \core_calculate_stage_49_div_by_zero$93 + sync init + end + process $group_93 + assign \core_calculate_stage_50_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_50_divisor_radicand \core_calculate_stage_49_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_50_operation 2'00 + assign \core_calculate_stage_50_operation \core_calculate_stage_49_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_50_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_50_quotient_root \core_calculate_stage_49_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_50_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_50_root_times_radicand \core_calculate_stage_49_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_50_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_50_compare_lhs \core_calculate_stage_49_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_50_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_50_compare_rhs \core_calculate_stage_49_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_51_muxid 2'00 + assign \core_calculate_stage_51_muxid \core_calculate_stage_50_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_51_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_51_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_51_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_51_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_51_logical_op__rc__rc 1'0 + assign \core_calculate_stage_51_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_51_logical_op__oe__oe 1'0 + assign \core_calculate_stage_51_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_51_logical_op__invert_in 1'0 + assign \core_calculate_stage_51_logical_op__zero_a 1'0 + assign \core_calculate_stage_51_logical_op__input_carry 2'00 + assign \core_calculate_stage_51_logical_op__invert_out 1'0 + assign \core_calculate_stage_51_logical_op__write_cr0 1'0 + assign \core_calculate_stage_51_logical_op__output_carry 1'0 + assign \core_calculate_stage_51_logical_op__is_32bit 1'0 + assign \core_calculate_stage_51_logical_op__is_signed 1'0 + assign \core_calculate_stage_51_logical_op__data_len 4'0000 + assign \core_calculate_stage_51_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_51_logical_op__insn \core_calculate_stage_51_logical_op__data_len \core_calculate_stage_51_logical_op__is_signed \core_calculate_stage_51_logical_op__is_32bit \core_calculate_stage_51_logical_op__output_carry \core_calculate_stage_51_logical_op__write_cr0 \core_calculate_stage_51_logical_op__invert_out \core_calculate_stage_51_logical_op__input_carry \core_calculate_stage_51_logical_op__zero_a \core_calculate_stage_51_logical_op__invert_in { \core_calculate_stage_51_logical_op__oe__oe_ok \core_calculate_stage_51_logical_op__oe__oe } { \core_calculate_stage_51_logical_op__rc__rc_ok \core_calculate_stage_51_logical_op__rc__rc } { \core_calculate_stage_51_logical_op__imm_data__imm_ok \core_calculate_stage_51_logical_op__imm_data__imm } \core_calculate_stage_51_logical_op__fn_unit \core_calculate_stage_51_logical_op__insn_type } { \core_calculate_stage_50_logical_op__insn$118 \core_calculate_stage_50_logical_op__data_len$117 \core_calculate_stage_50_logical_op__is_signed$116 \core_calculate_stage_50_logical_op__is_32bit$115 \core_calculate_stage_50_logical_op__output_carry$114 \core_calculate_stage_50_logical_op__write_cr0$113 \core_calculate_stage_50_logical_op__invert_out$112 \core_calculate_stage_50_logical_op__input_carry$111 \core_calculate_stage_50_logical_op__zero_a$110 \core_calculate_stage_50_logical_op__invert_in$109 { \core_calculate_stage_50_logical_op__oe__oe_ok$108 \core_calculate_stage_50_logical_op__oe__oe$107 } { \core_calculate_stage_50_logical_op__rc__rc_ok$106 \core_calculate_stage_50_logical_op__rc__rc$105 } { \core_calculate_stage_50_logical_op__imm_data__imm_ok$104 \core_calculate_stage_50_logical_op__imm_data__imm$103 } \core_calculate_stage_50_logical_op__fn_unit$102 \core_calculate_stage_50_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_51_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_51_ra \core_calculate_stage_50_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_51_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_51_rb \core_calculate_stage_50_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_51_xer_so 1'0 + assign \core_calculate_stage_51_xer_so \core_calculate_stage_50_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_51_divisor_neg 1'0 + assign \core_calculate_stage_51_divisor_neg \core_calculate_stage_50_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_51_dividend_neg 1'0 + assign \core_calculate_stage_51_dividend_neg \core_calculate_stage_50_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_51_dive_abs_ov32 1'0 + assign \core_calculate_stage_51_dive_abs_ov32 \core_calculate_stage_50_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_51_dive_abs_ov64 1'0 + assign \core_calculate_stage_51_dive_abs_ov64 \core_calculate_stage_50_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_51_div_by_zero 1'0 + assign \core_calculate_stage_51_div_by_zero \core_calculate_stage_50_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_51_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_51_divisor_radicand \core_calculate_stage_50_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_51_operation 2'00 + assign \core_calculate_stage_51_operation \core_calculate_stage_50_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_51_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_51_quotient_root \core_calculate_stage_50_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_51_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_51_root_times_radicand \core_calculate_stage_50_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_51_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_51_compare_lhs \core_calculate_stage_50_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_51_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_51_compare_rhs \core_calculate_stage_50_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 + end + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_51_muxid$133 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_51_logical_op__insn$151 \core_calculate_stage_51_logical_op__data_len$150 \core_calculate_stage_51_logical_op__is_signed$149 \core_calculate_stage_51_logical_op__is_32bit$148 \core_calculate_stage_51_logical_op__output_carry$147 \core_calculate_stage_51_logical_op__write_cr0$146 \core_calculate_stage_51_logical_op__invert_out$145 \core_calculate_stage_51_logical_op__input_carry$144 \core_calculate_stage_51_logical_op__zero_a$143 \core_calculate_stage_51_logical_op__invert_in$142 { \core_calculate_stage_51_logical_op__oe__oe_ok$141 \core_calculate_stage_51_logical_op__oe__oe$140 } { \core_calculate_stage_51_logical_op__rc__rc_ok$139 \core_calculate_stage_51_logical_op__rc__rc$138 } { \core_calculate_stage_51_logical_op__imm_data__imm_ok$137 \core_calculate_stage_51_logical_op__imm_data__imm$136 } \core_calculate_stage_51_logical_op__fn_unit$135 \core_calculate_stage_51_logical_op__insn_type$134 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_51_ra$152 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_51_rb$153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_51_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_51_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_51_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_51_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_51_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_51_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_51_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_51_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_51_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_51_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_51_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_51_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next + end + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end + sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next + end + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.p" +module \p$308 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.n" +module \n$309 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_52.core.trial0" +module \trial0$311 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001011 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_52.core.trial1" +module \trial1$312 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001011 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_52.core.pe" +module \pe$313 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_52.core" +module \core$310 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$311 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$312 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$313 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 16 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \next_bits + connect \B 4'1011 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_52" +module \core_calculate_stage_52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$310 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_53.core.trial0" +module \trial0$315 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001010 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_53.core.trial1" +module \trial1$316 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001010 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_53.core.pe" +module \pe$317 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_53.core" +module \core$314 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$315 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$316 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$317 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 16 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \next_bits + connect \B 4'1010 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_53" +module \core_calculate_stage_53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$314 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_54.core.trial0" +module \trial0$319 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001001 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_54.core.trial1" +module \trial1$320 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001001 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_54.core.pe" +module \pe$321 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_54.core" +module \core$318 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$319 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$320 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$321 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 16 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \next_bits + connect \B 4'1001 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_54" +module \core_calculate_stage_54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$318 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_55.core.trial0" +module \trial0$323 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001000 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_55.core.trial1" +module \trial1$324 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1001000 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_55.core.pe" +module \pe$325 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_55.core" +module \core$322 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$323 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$324 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$325 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 16 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \next_bits + connect \B 4'1000 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13.core_calculate_stage_55" +module \core_calculate_stage_55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$322 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_13" +module \pipe_middle_13 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 41 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$308 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$309 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_52_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_52_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_52_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_52_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_52_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_52_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_52_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_52_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_52_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_52_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_52_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_52_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_52_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_52_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_52_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_52_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_52_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_52_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_52_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_52_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_52_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_52_muxid$34 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_52_logical_op__insn_type$35 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_52_logical_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_52_logical_op__imm_data__imm$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__imm_data__imm_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__invert_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_52_logical_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__write_cr0$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_52_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_52_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_52_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_52_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_52_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_52_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_52_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_52_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_52_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_52_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_52_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_52_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_52_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_52_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_52_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_52_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_52_compare_rhs$66 + cell \core_calculate_stage_52 \core_calculate_stage_52 + connect \muxid \core_calculate_stage_52_muxid + connect \logical_op__insn_type \core_calculate_stage_52_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_52_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_52_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_52_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_52_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_52_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_52_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_52_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_52_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_52_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_52_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_52_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_52_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_52_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_52_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_52_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_52_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_52_logical_op__insn + connect \ra \core_calculate_stage_52_ra + connect \rb \core_calculate_stage_52_rb + connect \xer_so \core_calculate_stage_52_xer_so + connect \divisor_neg \core_calculate_stage_52_divisor_neg + connect \dividend_neg \core_calculate_stage_52_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_52_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_52_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_52_div_by_zero + connect \divisor_radicand \core_calculate_stage_52_divisor_radicand + connect \operation \core_calculate_stage_52_operation + connect \quotient_root \core_calculate_stage_52_quotient_root + connect \root_times_radicand \core_calculate_stage_52_root_times_radicand + connect \compare_lhs \core_calculate_stage_52_compare_lhs + connect \compare_rhs \core_calculate_stage_52_compare_rhs + connect \muxid$1 \core_calculate_stage_52_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_52_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_52_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_52_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_52_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_52_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_52_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_52_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_52_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_52_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_52_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_52_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_52_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_52_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_52_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_52_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_52_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_52_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_52_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_52_ra$53 + connect \rb$21 \core_calculate_stage_52_rb$54 + connect \xer_so$22 \core_calculate_stage_52_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_52_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_52_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_52_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_52_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_52_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_52_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_52_operation$62 + connect \quotient_root$30 \core_calculate_stage_52_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_52_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_52_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_52_compare_rhs$66 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_53_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_53_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_53_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_53_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_53_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_53_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_53_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_53_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_53_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_53_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_53_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_53_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_53_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_53_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_53_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_53_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_53_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_53_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_53_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_53_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_53_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_53_muxid$67 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_53_logical_op__insn_type$68 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_53_logical_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_53_logical_op__imm_data__imm$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__imm_data__imm_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__rc__rc_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_53_logical_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__invert_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__write_cr0$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_53_logical_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_53_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_53_logical_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_53_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_53_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_53_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_53_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_53_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_53_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_53_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_53_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_53_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_53_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_53_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_53_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_53_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_53_compare_rhs$99 + cell \core_calculate_stage_53 \core_calculate_stage_53 + connect \muxid \core_calculate_stage_53_muxid + connect \logical_op__insn_type \core_calculate_stage_53_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_53_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_53_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_53_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_53_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_53_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_53_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_53_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_53_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_53_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_53_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_53_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_53_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_53_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_53_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_53_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_53_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_53_logical_op__insn + connect \ra \core_calculate_stage_53_ra + connect \rb \core_calculate_stage_53_rb + connect \xer_so \core_calculate_stage_53_xer_so + connect \divisor_neg \core_calculate_stage_53_divisor_neg + connect \dividend_neg \core_calculate_stage_53_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_53_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_53_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_53_div_by_zero + connect \divisor_radicand \core_calculate_stage_53_divisor_radicand + connect \operation \core_calculate_stage_53_operation + connect \quotient_root \core_calculate_stage_53_quotient_root + connect \root_times_radicand \core_calculate_stage_53_root_times_radicand + connect \compare_lhs \core_calculate_stage_53_compare_lhs + connect \compare_rhs \core_calculate_stage_53_compare_rhs + connect \muxid$1 \core_calculate_stage_53_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_53_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_53_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_53_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_53_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_53_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_53_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_53_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_53_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_53_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_53_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_53_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_53_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_53_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_53_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_53_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_53_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_53_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_53_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_53_ra$86 + connect \rb$21 \core_calculate_stage_53_rb$87 + connect \xer_so$22 \core_calculate_stage_53_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_53_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_53_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_53_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_53_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_53_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_53_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_53_operation$95 + connect \quotient_root$30 \core_calculate_stage_53_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_53_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_53_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_53_compare_rhs$99 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_54_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_54_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_54_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_54_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_54_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_54_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_54_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_54_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_54_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_54_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_54_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_54_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_54_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_54_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_54_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_54_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_54_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_54_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_54_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_54_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_54_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_54_muxid$100 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_54_logical_op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_54_logical_op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_54_logical_op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__rc__rc$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__rc__rc_ok$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__oe__oe$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_54_logical_op__input_carry$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__invert_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__write_cr0$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__output_carry$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__is_32bit$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_54_logical_op__is_signed$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_54_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_54_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_54_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_54_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_54_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_54_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_54_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_54_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_54_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_54_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_54_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_54_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_54_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_54_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_54_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_54_compare_rhs$132 + cell \core_calculate_stage_54 \core_calculate_stage_54 + connect \muxid \core_calculate_stage_54_muxid + connect \logical_op__insn_type \core_calculate_stage_54_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_54_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_54_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_54_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_54_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_54_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_54_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_54_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_54_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_54_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_54_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_54_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_54_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_54_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_54_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_54_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_54_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_54_logical_op__insn + connect \ra \core_calculate_stage_54_ra + connect \rb \core_calculate_stage_54_rb + connect \xer_so \core_calculate_stage_54_xer_so + connect \divisor_neg \core_calculate_stage_54_divisor_neg + connect \dividend_neg \core_calculate_stage_54_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_54_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_54_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_54_div_by_zero + connect \divisor_radicand \core_calculate_stage_54_divisor_radicand + connect \operation \core_calculate_stage_54_operation + connect \quotient_root \core_calculate_stage_54_quotient_root + connect \root_times_radicand \core_calculate_stage_54_root_times_radicand + connect \compare_lhs \core_calculate_stage_54_compare_lhs + connect \compare_rhs \core_calculate_stage_54_compare_rhs + connect \muxid$1 \core_calculate_stage_54_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_54_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_54_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_54_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_54_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_54_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_54_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_54_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_54_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_54_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_54_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_54_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_54_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_54_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_54_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_54_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_54_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_54_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_54_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_54_ra$119 + connect \rb$21 \core_calculate_stage_54_rb$120 + connect \xer_so$22 \core_calculate_stage_54_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_54_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_54_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_54_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_54_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_54_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_54_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_54_operation$128 + connect \quotient_root$30 \core_calculate_stage_54_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_54_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_54_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_54_compare_rhs$132 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_55_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_55_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_55_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_55_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_55_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_55_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_55_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_55_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_55_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_55_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_55_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_55_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_55_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_55_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_55_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_55_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_55_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_55_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_55_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_55_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_55_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_55_muxid$133 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_55_logical_op__insn_type$134 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_55_logical_op__fn_unit$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_55_logical_op__imm_data__imm$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__imm_data__imm_ok$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__rc__rc$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__rc__rc_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__oe__oe$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__oe__oe_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__invert_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_55_logical_op__input_carry$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__invert_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__write_cr0$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__output_carry$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_55_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_55_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_55_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_55_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_55_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_55_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_55_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_55_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_55_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_55_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_55_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_55_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_55_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_55_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_55_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_55_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_55_compare_rhs$165 + cell \core_calculate_stage_55 \core_calculate_stage_55 + connect \muxid \core_calculate_stage_55_muxid + connect \logical_op__insn_type \core_calculate_stage_55_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_55_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_55_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_55_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_55_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_55_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_55_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_55_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_55_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_55_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_55_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_55_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_55_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_55_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_55_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_55_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_55_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_55_logical_op__insn + connect \ra \core_calculate_stage_55_ra + connect \rb \core_calculate_stage_55_rb + connect \xer_so \core_calculate_stage_55_xer_so + connect \divisor_neg \core_calculate_stage_55_divisor_neg + connect \dividend_neg \core_calculate_stage_55_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_55_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_55_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_55_div_by_zero + connect \divisor_radicand \core_calculate_stage_55_divisor_radicand + connect \operation \core_calculate_stage_55_operation + connect \quotient_root \core_calculate_stage_55_quotient_root + connect \root_times_radicand \core_calculate_stage_55_root_times_radicand + connect \compare_lhs \core_calculate_stage_55_compare_lhs + connect \compare_rhs \core_calculate_stage_55_compare_rhs + connect \muxid$1 \core_calculate_stage_55_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_55_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_55_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_55_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_55_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_55_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_55_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_55_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_55_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_55_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_55_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_55_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_55_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_55_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_55_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_55_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_55_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_55_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_55_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_55_ra$152 + connect \rb$21 \core_calculate_stage_55_rb$153 + connect \xer_so$22 \core_calculate_stage_55_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_55_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_55_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_55_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_55_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_55_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_55_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_55_operation$161 + connect \quotient_root$30 \core_calculate_stage_55_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_55_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_55_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_55_compare_rhs$165 + end + process $group_0 + assign \core_calculate_stage_52_muxid 2'00 + assign \core_calculate_stage_52_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_52_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_52_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_52_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_52_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_52_logical_op__rc__rc 1'0 + assign \core_calculate_stage_52_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_52_logical_op__oe__oe 1'0 + assign \core_calculate_stage_52_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_52_logical_op__invert_in 1'0 + assign \core_calculate_stage_52_logical_op__zero_a 1'0 + assign \core_calculate_stage_52_logical_op__input_carry 2'00 + assign \core_calculate_stage_52_logical_op__invert_out 1'0 + assign \core_calculate_stage_52_logical_op__write_cr0 1'0 + assign \core_calculate_stage_52_logical_op__output_carry 1'0 + assign \core_calculate_stage_52_logical_op__is_32bit 1'0 + assign \core_calculate_stage_52_logical_op__is_signed 1'0 + assign \core_calculate_stage_52_logical_op__data_len 4'0000 + assign \core_calculate_stage_52_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_52_logical_op__insn \core_calculate_stage_52_logical_op__data_len \core_calculate_stage_52_logical_op__is_signed \core_calculate_stage_52_logical_op__is_32bit \core_calculate_stage_52_logical_op__output_carry \core_calculate_stage_52_logical_op__write_cr0 \core_calculate_stage_52_logical_op__invert_out \core_calculate_stage_52_logical_op__input_carry \core_calculate_stage_52_logical_op__zero_a \core_calculate_stage_52_logical_op__invert_in { \core_calculate_stage_52_logical_op__oe__oe_ok \core_calculate_stage_52_logical_op__oe__oe } { \core_calculate_stage_52_logical_op__rc__rc_ok \core_calculate_stage_52_logical_op__rc__rc } { \core_calculate_stage_52_logical_op__imm_data__imm_ok \core_calculate_stage_52_logical_op__imm_data__imm } \core_calculate_stage_52_logical_op__fn_unit \core_calculate_stage_52_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \core_calculate_stage_52_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_52_ra \ra + sync init + end + process $group_20 + assign \core_calculate_stage_52_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_52_rb \rb + sync init + end + process $group_21 + assign \core_calculate_stage_52_xer_so 1'0 + assign \core_calculate_stage_52_xer_so \xer_so + sync init + end + process $group_22 + assign \core_calculate_stage_52_divisor_neg 1'0 + assign \core_calculate_stage_52_divisor_neg \divisor_neg + sync init + end + process $group_23 + assign \core_calculate_stage_52_dividend_neg 1'0 + assign \core_calculate_stage_52_dividend_neg \dividend_neg + sync init + end + process $group_24 + assign \core_calculate_stage_52_dive_abs_ov32 1'0 + assign \core_calculate_stage_52_dive_abs_ov32 \dive_abs_ov32 + sync init + end + process $group_25 + assign \core_calculate_stage_52_dive_abs_ov64 1'0 + assign \core_calculate_stage_52_dive_abs_ov64 \dive_abs_ov64 + sync init + end + process $group_26 + assign \core_calculate_stage_52_div_by_zero 1'0 + assign \core_calculate_stage_52_div_by_zero \div_by_zero + sync init + end + process $group_27 + assign \core_calculate_stage_52_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_52_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_calculate_stage_52_operation 2'00 + assign \core_calculate_stage_52_operation \operation + sync init + end + process $group_29 + assign \core_calculate_stage_52_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_52_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_calculate_stage_52_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_52_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_calculate_stage_52_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_52_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_calculate_stage_52_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_52_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \core_calculate_stage_53_muxid 2'00 + assign \core_calculate_stage_53_muxid \core_calculate_stage_52_muxid$34 + sync init + end + process $group_34 + assign \core_calculate_stage_53_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_53_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_53_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_53_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_53_logical_op__rc__rc 1'0 + assign \core_calculate_stage_53_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_53_logical_op__oe__oe 1'0 + assign \core_calculate_stage_53_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_53_logical_op__invert_in 1'0 + assign \core_calculate_stage_53_logical_op__zero_a 1'0 + assign \core_calculate_stage_53_logical_op__input_carry 2'00 + assign \core_calculate_stage_53_logical_op__invert_out 1'0 + assign \core_calculate_stage_53_logical_op__write_cr0 1'0 + assign \core_calculate_stage_53_logical_op__output_carry 1'0 + assign \core_calculate_stage_53_logical_op__is_32bit 1'0 + assign \core_calculate_stage_53_logical_op__is_signed 1'0 + assign \core_calculate_stage_53_logical_op__data_len 4'0000 + assign \core_calculate_stage_53_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_53_logical_op__insn \core_calculate_stage_53_logical_op__data_len \core_calculate_stage_53_logical_op__is_signed \core_calculate_stage_53_logical_op__is_32bit \core_calculate_stage_53_logical_op__output_carry \core_calculate_stage_53_logical_op__write_cr0 \core_calculate_stage_53_logical_op__invert_out \core_calculate_stage_53_logical_op__input_carry \core_calculate_stage_53_logical_op__zero_a \core_calculate_stage_53_logical_op__invert_in { \core_calculate_stage_53_logical_op__oe__oe_ok \core_calculate_stage_53_logical_op__oe__oe } { \core_calculate_stage_53_logical_op__rc__rc_ok \core_calculate_stage_53_logical_op__rc__rc } { \core_calculate_stage_53_logical_op__imm_data__imm_ok \core_calculate_stage_53_logical_op__imm_data__imm } \core_calculate_stage_53_logical_op__fn_unit \core_calculate_stage_53_logical_op__insn_type } { \core_calculate_stage_52_logical_op__insn$52 \core_calculate_stage_52_logical_op__data_len$51 \core_calculate_stage_52_logical_op__is_signed$50 \core_calculate_stage_52_logical_op__is_32bit$49 \core_calculate_stage_52_logical_op__output_carry$48 \core_calculate_stage_52_logical_op__write_cr0$47 \core_calculate_stage_52_logical_op__invert_out$46 \core_calculate_stage_52_logical_op__input_carry$45 \core_calculate_stage_52_logical_op__zero_a$44 \core_calculate_stage_52_logical_op__invert_in$43 { \core_calculate_stage_52_logical_op__oe__oe_ok$42 \core_calculate_stage_52_logical_op__oe__oe$41 } { \core_calculate_stage_52_logical_op__rc__rc_ok$40 \core_calculate_stage_52_logical_op__rc__rc$39 } { \core_calculate_stage_52_logical_op__imm_data__imm_ok$38 \core_calculate_stage_52_logical_op__imm_data__imm$37 } \core_calculate_stage_52_logical_op__fn_unit$36 \core_calculate_stage_52_logical_op__insn_type$35 } + sync init + end + process $group_52 + assign \core_calculate_stage_53_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_53_ra \core_calculate_stage_52_ra$53 + sync init + end + process $group_53 + assign \core_calculate_stage_53_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_53_rb \core_calculate_stage_52_rb$54 + sync init + end + process $group_54 + assign \core_calculate_stage_53_xer_so 1'0 + assign \core_calculate_stage_53_xer_so \core_calculate_stage_52_xer_so$55 + sync init + end + process $group_55 + assign \core_calculate_stage_53_divisor_neg 1'0 + assign \core_calculate_stage_53_divisor_neg \core_calculate_stage_52_divisor_neg$56 + sync init + end + process $group_56 + assign \core_calculate_stage_53_dividend_neg 1'0 + assign \core_calculate_stage_53_dividend_neg \core_calculate_stage_52_dividend_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_53_dive_abs_ov32 1'0 + assign \core_calculate_stage_53_dive_abs_ov32 \core_calculate_stage_52_dive_abs_ov32$58 + sync init + end + process $group_58 + assign \core_calculate_stage_53_dive_abs_ov64 1'0 + assign \core_calculate_stage_53_dive_abs_ov64 \core_calculate_stage_52_dive_abs_ov64$59 + sync init + end + process $group_59 + assign \core_calculate_stage_53_div_by_zero 1'0 + assign \core_calculate_stage_53_div_by_zero \core_calculate_stage_52_div_by_zero$60 + sync init + end + process $group_60 + assign \core_calculate_stage_53_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_53_divisor_radicand \core_calculate_stage_52_divisor_radicand$61 + sync init + end + process $group_61 + assign \core_calculate_stage_53_operation 2'00 + assign \core_calculate_stage_53_operation \core_calculate_stage_52_operation$62 + sync init + end + process $group_62 + assign \core_calculate_stage_53_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_53_quotient_root \core_calculate_stage_52_quotient_root$63 + sync init + end + process $group_63 + assign \core_calculate_stage_53_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_53_root_times_radicand \core_calculate_stage_52_root_times_radicand$64 + sync init + end + process $group_64 + assign \core_calculate_stage_53_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_53_compare_lhs \core_calculate_stage_52_compare_lhs$65 + sync init + end + process $group_65 + assign \core_calculate_stage_53_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_53_compare_rhs \core_calculate_stage_52_compare_rhs$66 + sync init + end + process $group_66 + assign \core_calculate_stage_54_muxid 2'00 + assign \core_calculate_stage_54_muxid \core_calculate_stage_53_muxid$67 + sync init + end + process $group_67 + assign \core_calculate_stage_54_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_54_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_54_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_54_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_54_logical_op__rc__rc 1'0 + assign \core_calculate_stage_54_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_54_logical_op__oe__oe 1'0 + assign \core_calculate_stage_54_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_54_logical_op__invert_in 1'0 + assign \core_calculate_stage_54_logical_op__zero_a 1'0 + assign \core_calculate_stage_54_logical_op__input_carry 2'00 + assign \core_calculate_stage_54_logical_op__invert_out 1'0 + assign \core_calculate_stage_54_logical_op__write_cr0 1'0 + assign \core_calculate_stage_54_logical_op__output_carry 1'0 + assign \core_calculate_stage_54_logical_op__is_32bit 1'0 + assign \core_calculate_stage_54_logical_op__is_signed 1'0 + assign \core_calculate_stage_54_logical_op__data_len 4'0000 + assign \core_calculate_stage_54_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_54_logical_op__insn \core_calculate_stage_54_logical_op__data_len \core_calculate_stage_54_logical_op__is_signed \core_calculate_stage_54_logical_op__is_32bit \core_calculate_stage_54_logical_op__output_carry \core_calculate_stage_54_logical_op__write_cr0 \core_calculate_stage_54_logical_op__invert_out \core_calculate_stage_54_logical_op__input_carry \core_calculate_stage_54_logical_op__zero_a \core_calculate_stage_54_logical_op__invert_in { \core_calculate_stage_54_logical_op__oe__oe_ok \core_calculate_stage_54_logical_op__oe__oe } { \core_calculate_stage_54_logical_op__rc__rc_ok \core_calculate_stage_54_logical_op__rc__rc } { \core_calculate_stage_54_logical_op__imm_data__imm_ok \core_calculate_stage_54_logical_op__imm_data__imm } \core_calculate_stage_54_logical_op__fn_unit \core_calculate_stage_54_logical_op__insn_type } { \core_calculate_stage_53_logical_op__insn$85 \core_calculate_stage_53_logical_op__data_len$84 \core_calculate_stage_53_logical_op__is_signed$83 \core_calculate_stage_53_logical_op__is_32bit$82 \core_calculate_stage_53_logical_op__output_carry$81 \core_calculate_stage_53_logical_op__write_cr0$80 \core_calculate_stage_53_logical_op__invert_out$79 \core_calculate_stage_53_logical_op__input_carry$78 \core_calculate_stage_53_logical_op__zero_a$77 \core_calculate_stage_53_logical_op__invert_in$76 { \core_calculate_stage_53_logical_op__oe__oe_ok$75 \core_calculate_stage_53_logical_op__oe__oe$74 } { \core_calculate_stage_53_logical_op__rc__rc_ok$73 \core_calculate_stage_53_logical_op__rc__rc$72 } { \core_calculate_stage_53_logical_op__imm_data__imm_ok$71 \core_calculate_stage_53_logical_op__imm_data__imm$70 } \core_calculate_stage_53_logical_op__fn_unit$69 \core_calculate_stage_53_logical_op__insn_type$68 } + sync init + end + process $group_85 + assign \core_calculate_stage_54_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_54_ra \core_calculate_stage_53_ra$86 + sync init + end + process $group_86 + assign \core_calculate_stage_54_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_54_rb \core_calculate_stage_53_rb$87 + sync init + end + process $group_87 + assign \core_calculate_stage_54_xer_so 1'0 + assign \core_calculate_stage_54_xer_so \core_calculate_stage_53_xer_so$88 + sync init + end + process $group_88 + assign \core_calculate_stage_54_divisor_neg 1'0 + assign \core_calculate_stage_54_divisor_neg \core_calculate_stage_53_divisor_neg$89 + sync init + end + process $group_89 + assign \core_calculate_stage_54_dividend_neg 1'0 + assign \core_calculate_stage_54_dividend_neg \core_calculate_stage_53_dividend_neg$90 + sync init + end + process $group_90 + assign \core_calculate_stage_54_dive_abs_ov32 1'0 + assign \core_calculate_stage_54_dive_abs_ov32 \core_calculate_stage_53_dive_abs_ov32$91 + sync init + end + process $group_91 + assign \core_calculate_stage_54_dive_abs_ov64 1'0 + assign \core_calculate_stage_54_dive_abs_ov64 \core_calculate_stage_53_dive_abs_ov64$92 + sync init + end + process $group_92 + assign \core_calculate_stage_54_div_by_zero 1'0 + assign \core_calculate_stage_54_div_by_zero \core_calculate_stage_53_div_by_zero$93 + sync init + end + process $group_93 + assign \core_calculate_stage_54_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_54_divisor_radicand \core_calculate_stage_53_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_54_operation 2'00 + assign \core_calculate_stage_54_operation \core_calculate_stage_53_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_54_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_54_quotient_root \core_calculate_stage_53_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_54_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_54_root_times_radicand \core_calculate_stage_53_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_54_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_54_compare_lhs \core_calculate_stage_53_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_54_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_54_compare_rhs \core_calculate_stage_53_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_55_muxid 2'00 + assign \core_calculate_stage_55_muxid \core_calculate_stage_54_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_55_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_55_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_55_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_55_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_55_logical_op__rc__rc 1'0 + assign \core_calculate_stage_55_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_55_logical_op__oe__oe 1'0 + assign \core_calculate_stage_55_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_55_logical_op__invert_in 1'0 + assign \core_calculate_stage_55_logical_op__zero_a 1'0 + assign \core_calculate_stage_55_logical_op__input_carry 2'00 + assign \core_calculate_stage_55_logical_op__invert_out 1'0 + assign \core_calculate_stage_55_logical_op__write_cr0 1'0 + assign \core_calculate_stage_55_logical_op__output_carry 1'0 + assign \core_calculate_stage_55_logical_op__is_32bit 1'0 + assign \core_calculate_stage_55_logical_op__is_signed 1'0 + assign \core_calculate_stage_55_logical_op__data_len 4'0000 + assign \core_calculate_stage_55_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_55_logical_op__insn \core_calculate_stage_55_logical_op__data_len \core_calculate_stage_55_logical_op__is_signed \core_calculate_stage_55_logical_op__is_32bit \core_calculate_stage_55_logical_op__output_carry \core_calculate_stage_55_logical_op__write_cr0 \core_calculate_stage_55_logical_op__invert_out \core_calculate_stage_55_logical_op__input_carry \core_calculate_stage_55_logical_op__zero_a \core_calculate_stage_55_logical_op__invert_in { \core_calculate_stage_55_logical_op__oe__oe_ok \core_calculate_stage_55_logical_op__oe__oe } { \core_calculate_stage_55_logical_op__rc__rc_ok \core_calculate_stage_55_logical_op__rc__rc } { \core_calculate_stage_55_logical_op__imm_data__imm_ok \core_calculate_stage_55_logical_op__imm_data__imm } \core_calculate_stage_55_logical_op__fn_unit \core_calculate_stage_55_logical_op__insn_type } { \core_calculate_stage_54_logical_op__insn$118 \core_calculate_stage_54_logical_op__data_len$117 \core_calculate_stage_54_logical_op__is_signed$116 \core_calculate_stage_54_logical_op__is_32bit$115 \core_calculate_stage_54_logical_op__output_carry$114 \core_calculate_stage_54_logical_op__write_cr0$113 \core_calculate_stage_54_logical_op__invert_out$112 \core_calculate_stage_54_logical_op__input_carry$111 \core_calculate_stage_54_logical_op__zero_a$110 \core_calculate_stage_54_logical_op__invert_in$109 { \core_calculate_stage_54_logical_op__oe__oe_ok$108 \core_calculate_stage_54_logical_op__oe__oe$107 } { \core_calculate_stage_54_logical_op__rc__rc_ok$106 \core_calculate_stage_54_logical_op__rc__rc$105 } { \core_calculate_stage_54_logical_op__imm_data__imm_ok$104 \core_calculate_stage_54_logical_op__imm_data__imm$103 } \core_calculate_stage_54_logical_op__fn_unit$102 \core_calculate_stage_54_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_55_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_55_ra \core_calculate_stage_54_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_55_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_55_rb \core_calculate_stage_54_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_55_xer_so 1'0 + assign \core_calculate_stage_55_xer_so \core_calculate_stage_54_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_55_divisor_neg 1'0 + assign \core_calculate_stage_55_divisor_neg \core_calculate_stage_54_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_55_dividend_neg 1'0 + assign \core_calculate_stage_55_dividend_neg \core_calculate_stage_54_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_55_dive_abs_ov32 1'0 + assign \core_calculate_stage_55_dive_abs_ov32 \core_calculate_stage_54_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_55_dive_abs_ov64 1'0 + assign \core_calculate_stage_55_dive_abs_ov64 \core_calculate_stage_54_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_55_div_by_zero 1'0 + assign \core_calculate_stage_55_div_by_zero \core_calculate_stage_54_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_55_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_55_divisor_radicand \core_calculate_stage_54_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_55_operation 2'00 + assign \core_calculate_stage_55_operation \core_calculate_stage_54_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_55_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_55_quotient_root \core_calculate_stage_54_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_55_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_55_root_times_radicand \core_calculate_stage_54_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_55_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_55_compare_lhs \core_calculate_stage_54_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_55_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_55_compare_rhs \core_calculate_stage_54_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 + end + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_55_muxid$133 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_55_logical_op__insn$151 \core_calculate_stage_55_logical_op__data_len$150 \core_calculate_stage_55_logical_op__is_signed$149 \core_calculate_stage_55_logical_op__is_32bit$148 \core_calculate_stage_55_logical_op__output_carry$147 \core_calculate_stage_55_logical_op__write_cr0$146 \core_calculate_stage_55_logical_op__invert_out$145 \core_calculate_stage_55_logical_op__input_carry$144 \core_calculate_stage_55_logical_op__zero_a$143 \core_calculate_stage_55_logical_op__invert_in$142 { \core_calculate_stage_55_logical_op__oe__oe_ok$141 \core_calculate_stage_55_logical_op__oe__oe$140 } { \core_calculate_stage_55_logical_op__rc__rc_ok$139 \core_calculate_stage_55_logical_op__rc__rc$138 } { \core_calculate_stage_55_logical_op__imm_data__imm_ok$137 \core_calculate_stage_55_logical_op__imm_data__imm$136 } \core_calculate_stage_55_logical_op__fn_unit$135 \core_calculate_stage_55_logical_op__insn_type$134 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_55_ra$152 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_55_rb$153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_55_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_55_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_55_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_55_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_55_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_55_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_55_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_55_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_55_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_55_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_55_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_55_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next + end + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end + sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next + end + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.p" +module \p$326 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.n" +module \n$327 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_56.core.trial0" +module \trial0$329 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_56.core.trial1" +module \trial1$330 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000111 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_56.core.pe" +module \pe$331 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_56.core" +module \core$328 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$329 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$330 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$331 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 8 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A \next_bits + connect \B 3'111 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_56" +module \core_calculate_stage_56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$328 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_57.core.trial0" +module \trial0$333 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000110 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_57.core.trial1" +module \trial1$334 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000110 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_57.core.pe" +module \pe$335 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_57.core" +module \core$332 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$333 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$334 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$335 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 8 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A \next_bits + connect \B 3'110 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_57" +module \core_calculate_stage_57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute 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\enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$332 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_58.core.trial0" +module \trial0$337 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000101 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_58.core.trial1" +module \trial1$338 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000101 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_58.core.pe" +module \pe$339 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_58.core" +module \core$336 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$337 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$338 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$339 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 8 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A \next_bits + connect \B 3'101 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_58" +module \core_calculate_stage_58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$336 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_59.core.trial0" +module \trial0$341 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000100 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_59.core.trial1" +module \trial1$342 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000100 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_59.core.pe" +module \pe$343 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_59.core" +module \core$340 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$341 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$342 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$343 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 8 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 8 + connect \A \next_bits + connect \B 3'100 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14.core_calculate_stage_59" +module \core_calculate_stage_59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute 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"OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$340 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_14" +module \pipe_middle_14 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 41 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$326 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$327 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_56_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_56_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_56_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_56_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_56_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_56_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_56_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_56_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_56_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_56_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_56_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_56_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_56_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_56_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_56_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_56_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_56_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_56_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_56_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_56_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_56_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_56_muxid$34 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_56_logical_op__insn_type$35 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_56_logical_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_56_logical_op__imm_data__imm$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__imm_data__imm_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__invert_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_56_logical_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__write_cr0$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_56_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_56_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_56_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_56_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_56_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_56_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_56_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_56_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_56_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_56_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_56_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_56_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_56_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_56_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_56_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_56_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_56_compare_rhs$66 + cell \core_calculate_stage_56 \core_calculate_stage_56 + connect \muxid \core_calculate_stage_56_muxid + connect \logical_op__insn_type \core_calculate_stage_56_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_56_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_56_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_56_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_56_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_56_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_56_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_56_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_56_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_56_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_56_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_56_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_56_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_56_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_56_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_56_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_56_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_56_logical_op__insn + connect \ra \core_calculate_stage_56_ra + connect \rb \core_calculate_stage_56_rb + connect \xer_so \core_calculate_stage_56_xer_so + connect \divisor_neg \core_calculate_stage_56_divisor_neg + connect \dividend_neg \core_calculate_stage_56_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_56_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_56_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_56_div_by_zero + connect \divisor_radicand \core_calculate_stage_56_divisor_radicand + connect \operation \core_calculate_stage_56_operation + connect \quotient_root \core_calculate_stage_56_quotient_root + connect \root_times_radicand \core_calculate_stage_56_root_times_radicand + connect \compare_lhs \core_calculate_stage_56_compare_lhs + connect \compare_rhs \core_calculate_stage_56_compare_rhs + connect \muxid$1 \core_calculate_stage_56_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_56_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_56_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_56_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_56_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_56_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_56_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_56_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_56_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_56_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_56_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_56_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_56_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_56_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_56_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_56_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_56_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_56_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_56_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_56_ra$53 + connect \rb$21 \core_calculate_stage_56_rb$54 + connect \xer_so$22 \core_calculate_stage_56_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_56_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_56_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_56_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_56_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_56_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_56_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_56_operation$62 + connect \quotient_root$30 \core_calculate_stage_56_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_56_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_56_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_56_compare_rhs$66 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_57_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_57_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_57_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_57_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_57_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_57_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_57_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_57_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_57_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_57_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_57_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_57_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_57_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_57_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_57_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_57_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_57_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_57_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_57_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_57_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_57_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_57_muxid$67 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_57_logical_op__insn_type$68 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_57_logical_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_57_logical_op__imm_data__imm$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__imm_data__imm_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__rc__rc_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_57_logical_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__invert_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__write_cr0$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_57_logical_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_57_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_57_logical_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_57_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_57_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_57_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_57_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_57_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_57_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_57_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_57_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_57_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_57_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_57_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_57_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_57_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_57_compare_rhs$99 + cell \core_calculate_stage_57 \core_calculate_stage_57 + connect \muxid \core_calculate_stage_57_muxid + connect \logical_op__insn_type \core_calculate_stage_57_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_57_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_57_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_57_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_57_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_57_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_57_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_57_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_57_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_57_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_57_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_57_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_57_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_57_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_57_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_57_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_57_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_57_logical_op__insn + connect \ra \core_calculate_stage_57_ra + connect \rb \core_calculate_stage_57_rb + connect \xer_so \core_calculate_stage_57_xer_so + connect \divisor_neg \core_calculate_stage_57_divisor_neg + connect \dividend_neg \core_calculate_stage_57_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_57_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_57_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_57_div_by_zero + connect \divisor_radicand \core_calculate_stage_57_divisor_radicand + connect \operation \core_calculate_stage_57_operation + connect \quotient_root \core_calculate_stage_57_quotient_root + connect \root_times_radicand \core_calculate_stage_57_root_times_radicand + connect \compare_lhs \core_calculate_stage_57_compare_lhs + connect \compare_rhs \core_calculate_stage_57_compare_rhs + connect \muxid$1 \core_calculate_stage_57_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_57_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_57_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_57_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_57_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_57_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_57_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_57_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_57_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_57_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_57_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_57_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_57_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_57_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_57_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_57_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_57_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_57_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_57_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_57_ra$86 + connect \rb$21 \core_calculate_stage_57_rb$87 + connect \xer_so$22 \core_calculate_stage_57_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_57_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_57_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_57_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_57_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_57_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_57_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_57_operation$95 + connect \quotient_root$30 \core_calculate_stage_57_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_57_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_57_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_57_compare_rhs$99 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_58_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_58_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_58_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_58_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_58_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_58_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_58_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_58_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_58_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_58_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_58_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_58_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_58_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_58_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_58_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_58_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_58_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_58_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_58_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_58_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_58_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_58_muxid$100 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_58_logical_op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_58_logical_op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_58_logical_op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__rc__rc$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__rc__rc_ok$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__oe__oe$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_58_logical_op__input_carry$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__invert_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__write_cr0$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__output_carry$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__is_32bit$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_58_logical_op__is_signed$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_58_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_58_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_58_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_58_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_58_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_58_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_58_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_58_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_58_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_58_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_58_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_58_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_58_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_58_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_58_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_58_compare_rhs$132 + cell \core_calculate_stage_58 \core_calculate_stage_58 + connect \muxid \core_calculate_stage_58_muxid + connect \logical_op__insn_type \core_calculate_stage_58_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_58_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_58_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_58_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_58_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_58_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_58_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_58_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_58_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_58_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_58_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_58_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_58_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_58_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_58_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_58_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_58_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_58_logical_op__insn + connect \ra \core_calculate_stage_58_ra + connect \rb \core_calculate_stage_58_rb + connect \xer_so \core_calculate_stage_58_xer_so + connect \divisor_neg \core_calculate_stage_58_divisor_neg + connect \dividend_neg \core_calculate_stage_58_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_58_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_58_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_58_div_by_zero + connect \divisor_radicand \core_calculate_stage_58_divisor_radicand + connect \operation \core_calculate_stage_58_operation + connect \quotient_root \core_calculate_stage_58_quotient_root + connect \root_times_radicand \core_calculate_stage_58_root_times_radicand + connect \compare_lhs \core_calculate_stage_58_compare_lhs + connect \compare_rhs \core_calculate_stage_58_compare_rhs + connect \muxid$1 \core_calculate_stage_58_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_58_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_58_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_58_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_58_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_58_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_58_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_58_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_58_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_58_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_58_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_58_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_58_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_58_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_58_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_58_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_58_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_58_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_58_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_58_ra$119 + connect \rb$21 \core_calculate_stage_58_rb$120 + connect \xer_so$22 \core_calculate_stage_58_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_58_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_58_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_58_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_58_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_58_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_58_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_58_operation$128 + connect \quotient_root$30 \core_calculate_stage_58_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_58_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_58_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_58_compare_rhs$132 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_59_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_59_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_59_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_59_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_59_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_59_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_59_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_59_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_59_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_59_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_59_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_59_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_59_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_59_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_59_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_59_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_59_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_59_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_59_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_59_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_59_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_59_muxid$133 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_59_logical_op__insn_type$134 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_59_logical_op__fn_unit$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_59_logical_op__imm_data__imm$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__imm_data__imm_ok$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__rc__rc$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__rc__rc_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__oe__oe$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__oe__oe_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__invert_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_59_logical_op__input_carry$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__invert_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__write_cr0$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__output_carry$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_59_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_59_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_59_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_59_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_59_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_59_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_59_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_59_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_59_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_59_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_59_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_59_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_59_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_59_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_59_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_59_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_59_compare_rhs$165 + cell \core_calculate_stage_59 \core_calculate_stage_59 + connect \muxid \core_calculate_stage_59_muxid + connect \logical_op__insn_type \core_calculate_stage_59_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_59_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_59_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_59_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_59_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_59_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_59_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_59_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_59_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_59_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_59_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_59_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_59_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_59_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_59_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_59_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_59_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_59_logical_op__insn + connect \ra \core_calculate_stage_59_ra + connect \rb \core_calculate_stage_59_rb + connect \xer_so \core_calculate_stage_59_xer_so + connect \divisor_neg \core_calculate_stage_59_divisor_neg + connect \dividend_neg \core_calculate_stage_59_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_59_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_59_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_59_div_by_zero + connect \divisor_radicand \core_calculate_stage_59_divisor_radicand + connect \operation \core_calculate_stage_59_operation + connect \quotient_root \core_calculate_stage_59_quotient_root + connect \root_times_radicand \core_calculate_stage_59_root_times_radicand + connect \compare_lhs \core_calculate_stage_59_compare_lhs + connect \compare_rhs \core_calculate_stage_59_compare_rhs + connect \muxid$1 \core_calculate_stage_59_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_59_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_59_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_59_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_59_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_59_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_59_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_59_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_59_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_59_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_59_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_59_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_59_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_59_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_59_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_59_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_59_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_59_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_59_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_59_ra$152 + connect \rb$21 \core_calculate_stage_59_rb$153 + connect \xer_so$22 \core_calculate_stage_59_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_59_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_59_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_59_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_59_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_59_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_59_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_59_operation$161 + connect \quotient_root$30 \core_calculate_stage_59_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_59_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_59_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_59_compare_rhs$165 + end + process $group_0 + assign \core_calculate_stage_56_muxid 2'00 + assign \core_calculate_stage_56_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_56_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_56_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_56_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_56_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_56_logical_op__rc__rc 1'0 + assign \core_calculate_stage_56_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_56_logical_op__oe__oe 1'0 + assign \core_calculate_stage_56_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_56_logical_op__invert_in 1'0 + assign \core_calculate_stage_56_logical_op__zero_a 1'0 + assign \core_calculate_stage_56_logical_op__input_carry 2'00 + assign \core_calculate_stage_56_logical_op__invert_out 1'0 + assign \core_calculate_stage_56_logical_op__write_cr0 1'0 + assign \core_calculate_stage_56_logical_op__output_carry 1'0 + assign \core_calculate_stage_56_logical_op__is_32bit 1'0 + assign \core_calculate_stage_56_logical_op__is_signed 1'0 + assign \core_calculate_stage_56_logical_op__data_len 4'0000 + assign \core_calculate_stage_56_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_56_logical_op__insn \core_calculate_stage_56_logical_op__data_len \core_calculate_stage_56_logical_op__is_signed \core_calculate_stage_56_logical_op__is_32bit \core_calculate_stage_56_logical_op__output_carry \core_calculate_stage_56_logical_op__write_cr0 \core_calculate_stage_56_logical_op__invert_out \core_calculate_stage_56_logical_op__input_carry \core_calculate_stage_56_logical_op__zero_a \core_calculate_stage_56_logical_op__invert_in { \core_calculate_stage_56_logical_op__oe__oe_ok \core_calculate_stage_56_logical_op__oe__oe } { \core_calculate_stage_56_logical_op__rc__rc_ok \core_calculate_stage_56_logical_op__rc__rc } { \core_calculate_stage_56_logical_op__imm_data__imm_ok \core_calculate_stage_56_logical_op__imm_data__imm } \core_calculate_stage_56_logical_op__fn_unit \core_calculate_stage_56_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \core_calculate_stage_56_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_56_ra \ra + sync init + end + process $group_20 + assign \core_calculate_stage_56_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_56_rb \rb + sync init + end + process $group_21 + assign \core_calculate_stage_56_xer_so 1'0 + assign \core_calculate_stage_56_xer_so \xer_so + sync init + end + process $group_22 + assign \core_calculate_stage_56_divisor_neg 1'0 + assign \core_calculate_stage_56_divisor_neg \divisor_neg + sync init + end + process $group_23 + assign \core_calculate_stage_56_dividend_neg 1'0 + assign \core_calculate_stage_56_dividend_neg \dividend_neg + sync init + end + process $group_24 + assign \core_calculate_stage_56_dive_abs_ov32 1'0 + assign \core_calculate_stage_56_dive_abs_ov32 \dive_abs_ov32 + sync init + end + process $group_25 + assign \core_calculate_stage_56_dive_abs_ov64 1'0 + assign \core_calculate_stage_56_dive_abs_ov64 \dive_abs_ov64 + sync init + end + process $group_26 + assign \core_calculate_stage_56_div_by_zero 1'0 + assign \core_calculate_stage_56_div_by_zero \div_by_zero + sync init + end + process $group_27 + assign \core_calculate_stage_56_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_56_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_calculate_stage_56_operation 2'00 + assign \core_calculate_stage_56_operation \operation + sync init + end + process $group_29 + assign \core_calculate_stage_56_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_56_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_calculate_stage_56_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_56_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_calculate_stage_56_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_56_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_calculate_stage_56_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_56_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \core_calculate_stage_57_muxid 2'00 + assign \core_calculate_stage_57_muxid \core_calculate_stage_56_muxid$34 + sync init + end + process $group_34 + assign \core_calculate_stage_57_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_57_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_57_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_57_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_57_logical_op__rc__rc 1'0 + assign \core_calculate_stage_57_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_57_logical_op__oe__oe 1'0 + assign \core_calculate_stage_57_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_57_logical_op__invert_in 1'0 + assign \core_calculate_stage_57_logical_op__zero_a 1'0 + assign \core_calculate_stage_57_logical_op__input_carry 2'00 + assign \core_calculate_stage_57_logical_op__invert_out 1'0 + assign \core_calculate_stage_57_logical_op__write_cr0 1'0 + assign \core_calculate_stage_57_logical_op__output_carry 1'0 + assign \core_calculate_stage_57_logical_op__is_32bit 1'0 + assign \core_calculate_stage_57_logical_op__is_signed 1'0 + assign \core_calculate_stage_57_logical_op__data_len 4'0000 + assign \core_calculate_stage_57_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_57_logical_op__insn \core_calculate_stage_57_logical_op__data_len \core_calculate_stage_57_logical_op__is_signed \core_calculate_stage_57_logical_op__is_32bit \core_calculate_stage_57_logical_op__output_carry \core_calculate_stage_57_logical_op__write_cr0 \core_calculate_stage_57_logical_op__invert_out \core_calculate_stage_57_logical_op__input_carry \core_calculate_stage_57_logical_op__zero_a \core_calculate_stage_57_logical_op__invert_in { \core_calculate_stage_57_logical_op__oe__oe_ok \core_calculate_stage_57_logical_op__oe__oe } { \core_calculate_stage_57_logical_op__rc__rc_ok \core_calculate_stage_57_logical_op__rc__rc } { \core_calculate_stage_57_logical_op__imm_data__imm_ok \core_calculate_stage_57_logical_op__imm_data__imm } \core_calculate_stage_57_logical_op__fn_unit \core_calculate_stage_57_logical_op__insn_type } { \core_calculate_stage_56_logical_op__insn$52 \core_calculate_stage_56_logical_op__data_len$51 \core_calculate_stage_56_logical_op__is_signed$50 \core_calculate_stage_56_logical_op__is_32bit$49 \core_calculate_stage_56_logical_op__output_carry$48 \core_calculate_stage_56_logical_op__write_cr0$47 \core_calculate_stage_56_logical_op__invert_out$46 \core_calculate_stage_56_logical_op__input_carry$45 \core_calculate_stage_56_logical_op__zero_a$44 \core_calculate_stage_56_logical_op__invert_in$43 { \core_calculate_stage_56_logical_op__oe__oe_ok$42 \core_calculate_stage_56_logical_op__oe__oe$41 } { \core_calculate_stage_56_logical_op__rc__rc_ok$40 \core_calculate_stage_56_logical_op__rc__rc$39 } { \core_calculate_stage_56_logical_op__imm_data__imm_ok$38 \core_calculate_stage_56_logical_op__imm_data__imm$37 } \core_calculate_stage_56_logical_op__fn_unit$36 \core_calculate_stage_56_logical_op__insn_type$35 } + sync init + end + process $group_52 + assign \core_calculate_stage_57_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_57_ra \core_calculate_stage_56_ra$53 + sync init + end + process $group_53 + assign \core_calculate_stage_57_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_57_rb \core_calculate_stage_56_rb$54 + sync init + end + process $group_54 + assign \core_calculate_stage_57_xer_so 1'0 + assign \core_calculate_stage_57_xer_so \core_calculate_stage_56_xer_so$55 + sync init + end + process $group_55 + assign \core_calculate_stage_57_divisor_neg 1'0 + assign \core_calculate_stage_57_divisor_neg \core_calculate_stage_56_divisor_neg$56 + sync init + end + process $group_56 + assign \core_calculate_stage_57_dividend_neg 1'0 + assign \core_calculate_stage_57_dividend_neg \core_calculate_stage_56_dividend_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_57_dive_abs_ov32 1'0 + assign \core_calculate_stage_57_dive_abs_ov32 \core_calculate_stage_56_dive_abs_ov32$58 + sync init + end + process $group_58 + assign \core_calculate_stage_57_dive_abs_ov64 1'0 + assign \core_calculate_stage_57_dive_abs_ov64 \core_calculate_stage_56_dive_abs_ov64$59 + sync init + end + process $group_59 + assign \core_calculate_stage_57_div_by_zero 1'0 + assign \core_calculate_stage_57_div_by_zero \core_calculate_stage_56_div_by_zero$60 + sync init + end + process $group_60 + assign \core_calculate_stage_57_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_57_divisor_radicand \core_calculate_stage_56_divisor_radicand$61 + sync init + end + process $group_61 + assign \core_calculate_stage_57_operation 2'00 + assign \core_calculate_stage_57_operation \core_calculate_stage_56_operation$62 + sync init + end + process $group_62 + assign \core_calculate_stage_57_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_57_quotient_root \core_calculate_stage_56_quotient_root$63 + sync init + end + process $group_63 + assign \core_calculate_stage_57_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_57_root_times_radicand \core_calculate_stage_56_root_times_radicand$64 + sync init + end + process $group_64 + assign \core_calculate_stage_57_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_57_compare_lhs \core_calculate_stage_56_compare_lhs$65 + sync init + end + process $group_65 + assign \core_calculate_stage_57_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_57_compare_rhs \core_calculate_stage_56_compare_rhs$66 + sync init + end + process $group_66 + assign \core_calculate_stage_58_muxid 2'00 + assign \core_calculate_stage_58_muxid \core_calculate_stage_57_muxid$67 + sync init + end + process $group_67 + assign \core_calculate_stage_58_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_58_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_58_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_58_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_58_logical_op__rc__rc 1'0 + assign \core_calculate_stage_58_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_58_logical_op__oe__oe 1'0 + assign \core_calculate_stage_58_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_58_logical_op__invert_in 1'0 + assign \core_calculate_stage_58_logical_op__zero_a 1'0 + assign \core_calculate_stage_58_logical_op__input_carry 2'00 + assign \core_calculate_stage_58_logical_op__invert_out 1'0 + assign \core_calculate_stage_58_logical_op__write_cr0 1'0 + assign \core_calculate_stage_58_logical_op__output_carry 1'0 + assign \core_calculate_stage_58_logical_op__is_32bit 1'0 + assign \core_calculate_stage_58_logical_op__is_signed 1'0 + assign \core_calculate_stage_58_logical_op__data_len 4'0000 + assign \core_calculate_stage_58_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_58_logical_op__insn \core_calculate_stage_58_logical_op__data_len \core_calculate_stage_58_logical_op__is_signed \core_calculate_stage_58_logical_op__is_32bit \core_calculate_stage_58_logical_op__output_carry \core_calculate_stage_58_logical_op__write_cr0 \core_calculate_stage_58_logical_op__invert_out \core_calculate_stage_58_logical_op__input_carry \core_calculate_stage_58_logical_op__zero_a \core_calculate_stage_58_logical_op__invert_in { \core_calculate_stage_58_logical_op__oe__oe_ok \core_calculate_stage_58_logical_op__oe__oe } { \core_calculate_stage_58_logical_op__rc__rc_ok \core_calculate_stage_58_logical_op__rc__rc } { \core_calculate_stage_58_logical_op__imm_data__imm_ok \core_calculate_stage_58_logical_op__imm_data__imm } \core_calculate_stage_58_logical_op__fn_unit \core_calculate_stage_58_logical_op__insn_type } { \core_calculate_stage_57_logical_op__insn$85 \core_calculate_stage_57_logical_op__data_len$84 \core_calculate_stage_57_logical_op__is_signed$83 \core_calculate_stage_57_logical_op__is_32bit$82 \core_calculate_stage_57_logical_op__output_carry$81 \core_calculate_stage_57_logical_op__write_cr0$80 \core_calculate_stage_57_logical_op__invert_out$79 \core_calculate_stage_57_logical_op__input_carry$78 \core_calculate_stage_57_logical_op__zero_a$77 \core_calculate_stage_57_logical_op__invert_in$76 { \core_calculate_stage_57_logical_op__oe__oe_ok$75 \core_calculate_stage_57_logical_op__oe__oe$74 } { \core_calculate_stage_57_logical_op__rc__rc_ok$73 \core_calculate_stage_57_logical_op__rc__rc$72 } { \core_calculate_stage_57_logical_op__imm_data__imm_ok$71 \core_calculate_stage_57_logical_op__imm_data__imm$70 } \core_calculate_stage_57_logical_op__fn_unit$69 \core_calculate_stage_57_logical_op__insn_type$68 } + sync init + end + process $group_85 + assign \core_calculate_stage_58_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_58_ra \core_calculate_stage_57_ra$86 + sync init + end + process $group_86 + assign \core_calculate_stage_58_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_58_rb \core_calculate_stage_57_rb$87 + sync init + end + process $group_87 + assign \core_calculate_stage_58_xer_so 1'0 + assign \core_calculate_stage_58_xer_so \core_calculate_stage_57_xer_so$88 + sync init + end + process $group_88 + assign \core_calculate_stage_58_divisor_neg 1'0 + assign \core_calculate_stage_58_divisor_neg \core_calculate_stage_57_divisor_neg$89 + sync init + end + process $group_89 + assign \core_calculate_stage_58_dividend_neg 1'0 + assign \core_calculate_stage_58_dividend_neg \core_calculate_stage_57_dividend_neg$90 + sync init + end + process $group_90 + assign \core_calculate_stage_58_dive_abs_ov32 1'0 + assign \core_calculate_stage_58_dive_abs_ov32 \core_calculate_stage_57_dive_abs_ov32$91 + sync init + end + process $group_91 + assign \core_calculate_stage_58_dive_abs_ov64 1'0 + assign \core_calculate_stage_58_dive_abs_ov64 \core_calculate_stage_57_dive_abs_ov64$92 + sync init + end + process $group_92 + assign \core_calculate_stage_58_div_by_zero 1'0 + assign \core_calculate_stage_58_div_by_zero \core_calculate_stage_57_div_by_zero$93 + sync init + end + process $group_93 + assign \core_calculate_stage_58_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_58_divisor_radicand \core_calculate_stage_57_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_58_operation 2'00 + assign \core_calculate_stage_58_operation \core_calculate_stage_57_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_58_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_58_quotient_root \core_calculate_stage_57_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_58_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_58_root_times_radicand \core_calculate_stage_57_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_58_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_58_compare_lhs \core_calculate_stage_57_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_58_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_58_compare_rhs \core_calculate_stage_57_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_59_muxid 2'00 + assign \core_calculate_stage_59_muxid \core_calculate_stage_58_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_59_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_59_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_59_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_59_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_59_logical_op__rc__rc 1'0 + assign \core_calculate_stage_59_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_59_logical_op__oe__oe 1'0 + assign \core_calculate_stage_59_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_59_logical_op__invert_in 1'0 + assign \core_calculate_stage_59_logical_op__zero_a 1'0 + assign \core_calculate_stage_59_logical_op__input_carry 2'00 + assign \core_calculate_stage_59_logical_op__invert_out 1'0 + assign \core_calculate_stage_59_logical_op__write_cr0 1'0 + assign \core_calculate_stage_59_logical_op__output_carry 1'0 + assign \core_calculate_stage_59_logical_op__is_32bit 1'0 + assign \core_calculate_stage_59_logical_op__is_signed 1'0 + assign \core_calculate_stage_59_logical_op__data_len 4'0000 + assign \core_calculate_stage_59_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_59_logical_op__insn \core_calculate_stage_59_logical_op__data_len \core_calculate_stage_59_logical_op__is_signed \core_calculate_stage_59_logical_op__is_32bit \core_calculate_stage_59_logical_op__output_carry \core_calculate_stage_59_logical_op__write_cr0 \core_calculate_stage_59_logical_op__invert_out \core_calculate_stage_59_logical_op__input_carry \core_calculate_stage_59_logical_op__zero_a \core_calculate_stage_59_logical_op__invert_in { \core_calculate_stage_59_logical_op__oe__oe_ok \core_calculate_stage_59_logical_op__oe__oe } { \core_calculate_stage_59_logical_op__rc__rc_ok \core_calculate_stage_59_logical_op__rc__rc } { \core_calculate_stage_59_logical_op__imm_data__imm_ok \core_calculate_stage_59_logical_op__imm_data__imm } \core_calculate_stage_59_logical_op__fn_unit \core_calculate_stage_59_logical_op__insn_type } { \core_calculate_stage_58_logical_op__insn$118 \core_calculate_stage_58_logical_op__data_len$117 \core_calculate_stage_58_logical_op__is_signed$116 \core_calculate_stage_58_logical_op__is_32bit$115 \core_calculate_stage_58_logical_op__output_carry$114 \core_calculate_stage_58_logical_op__write_cr0$113 \core_calculate_stage_58_logical_op__invert_out$112 \core_calculate_stage_58_logical_op__input_carry$111 \core_calculate_stage_58_logical_op__zero_a$110 \core_calculate_stage_58_logical_op__invert_in$109 { \core_calculate_stage_58_logical_op__oe__oe_ok$108 \core_calculate_stage_58_logical_op__oe__oe$107 } { \core_calculate_stage_58_logical_op__rc__rc_ok$106 \core_calculate_stage_58_logical_op__rc__rc$105 } { \core_calculate_stage_58_logical_op__imm_data__imm_ok$104 \core_calculate_stage_58_logical_op__imm_data__imm$103 } \core_calculate_stage_58_logical_op__fn_unit$102 \core_calculate_stage_58_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_59_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_59_ra \core_calculate_stage_58_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_59_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_59_rb \core_calculate_stage_58_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_59_xer_so 1'0 + assign \core_calculate_stage_59_xer_so \core_calculate_stage_58_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_59_divisor_neg 1'0 + assign \core_calculate_stage_59_divisor_neg \core_calculate_stage_58_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_59_dividend_neg 1'0 + assign \core_calculate_stage_59_dividend_neg \core_calculate_stage_58_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_59_dive_abs_ov32 1'0 + assign \core_calculate_stage_59_dive_abs_ov32 \core_calculate_stage_58_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_59_dive_abs_ov64 1'0 + assign \core_calculate_stage_59_dive_abs_ov64 \core_calculate_stage_58_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_59_div_by_zero 1'0 + assign \core_calculate_stage_59_div_by_zero \core_calculate_stage_58_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_59_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_59_divisor_radicand \core_calculate_stage_58_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_59_operation 2'00 + assign \core_calculate_stage_59_operation \core_calculate_stage_58_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_59_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_59_quotient_root \core_calculate_stage_58_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_59_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_59_root_times_radicand \core_calculate_stage_58_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_59_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_59_compare_lhs \core_calculate_stage_58_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_59_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_59_compare_rhs \core_calculate_stage_58_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 + end + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_59_muxid$133 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_59_logical_op__insn$151 \core_calculate_stage_59_logical_op__data_len$150 \core_calculate_stage_59_logical_op__is_signed$149 \core_calculate_stage_59_logical_op__is_32bit$148 \core_calculate_stage_59_logical_op__output_carry$147 \core_calculate_stage_59_logical_op__write_cr0$146 \core_calculate_stage_59_logical_op__invert_out$145 \core_calculate_stage_59_logical_op__input_carry$144 \core_calculate_stage_59_logical_op__zero_a$143 \core_calculate_stage_59_logical_op__invert_in$142 { \core_calculate_stage_59_logical_op__oe__oe_ok$141 \core_calculate_stage_59_logical_op__oe__oe$140 } { \core_calculate_stage_59_logical_op__rc__rc_ok$139 \core_calculate_stage_59_logical_op__rc__rc$138 } { \core_calculate_stage_59_logical_op__imm_data__imm_ok$137 \core_calculate_stage_59_logical_op__imm_data__imm$136 } \core_calculate_stage_59_logical_op__fn_unit$135 \core_calculate_stage_59_logical_op__insn_type$134 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_59_ra$152 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_59_rb$153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_59_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_59_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_59_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_59_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_59_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_59_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_59_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_59_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_59_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_59_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_59_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_59_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next + end + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end + sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next + end + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.p" +module \p$344 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.n" +module \n$345 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_60.core.trial0" +module \trial0$347 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000011 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_60.core.trial1" +module \trial1$348 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000011 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_60.core.pe" +module \pe$349 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_60.core" +module \core$346 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$347 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$348 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$349 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 4 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 4 + connect \A \next_bits + connect \B 2'11 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_60" +module \core_calculate_stage_60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$346 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_61.core.trial0" +module \trial0$351 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000010 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_61.core.trial1" +module \trial1$352 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000010 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_61.core.pe" +module \pe$353 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_61.core" +module \core$350 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$351 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$352 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$353 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 4 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 4 + connect \A \next_bits + connect \B 2'10 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_61" +module \core_calculate_stage_61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$350 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_62.core.trial0" +module \trial0$355 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000001 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_62.core.trial1" +module \trial1$356 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000001 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_62.core.pe" +module \pe$357 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_62.core" +module \core$354 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$355 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$356 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$357 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 2 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \next_bits + connect \B 1'1 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_62" +module \core_calculate_stage_62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$354 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_63.core.trial0" +module \trial0$359 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000000 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_63.core.trial1" +module \trial1$360 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 input 1 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 output 3 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:319" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:320" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_0 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \dr_times_trial_bits $3 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $eq $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \operation + connect \B 1'1 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 192 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $sshl $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000000 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + wire width 193 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:326" + cell $add $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $8 + connect \Y $10 + end + connect $7 $10 + process $group_1 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + case 1'1 + assign \trial_compare_rhs $7 [191:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_63.core.pe" +module \pe$361 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_63.core" +module \core$358 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 9 \compare_lhs$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 10 \compare_rhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$359 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:298" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:300" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:299" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$360 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$361 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$4 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$4 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$6 + process $group_4 + assign \quotient_root$6 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$6 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$7 + process $group_5 + assign \root_times_radicand$7 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$7 \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_0 + wire width 1 $verilog_initial_trigger + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:296" + wire width 64 \quotient_root$8 + process $group_10 + assign \quotient_root$8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$8 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:297" + wire width 128 \root_times_radicand$9 + process $group_11 + assign \root_times_radicand$9 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$9 \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:451" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:456" + cell $ge $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $10 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:460" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + wire width 2 $12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:473" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $12 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $12 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:472" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + cell $not $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + wire width 2 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:475" + cell $sub $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $17 + end + connect $16 $17 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + switch { $14 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:474" + case 1'1 + assign \next_bits $16 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:476" + case + assign \next_bits 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'0 + connect \Y $19 + end + process $group_18 + assign \nbe 1'0 + assign \nbe $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:484" + wire width 1 \nbe$21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:485" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \next_bits + connect \B 1'1 + connect \Y $22 + end + process $group_19 + assign \nbe$21 1'0 + assign \nbe$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe \nbe } + connect \B \trial0_trial_compare_rhs + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + wire width 192 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:486" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A { \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 \nbe$21 } + connect \B \trial1_trial_compare_rhs + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 192 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $24 + connect \B $26 + connect \Y $28 + end + process $group_20 + assign \compare_rhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$5 $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 2 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \next_bits + connect \B 1'0 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:491" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_21 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15.core_calculate_stage_63" +module \core_calculate_stage_63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 60 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 61 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 62 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 63 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 64 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 65 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_divisor_radicand$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_operation$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs$38 + cell \core$358 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$34 + connect \operation$2 \core_operation$35 + connect \quotient_root$3 \core_quotient_root$36 + connect \compare_lhs$4 \core_compare_lhs$37 + connect \compare_rhs$5 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$28 \core_divisor_radicand$34 + sync init + end + process $group_34 + assign \operation$29 2'00 + assign \operation$29 \core_operation$35 + sync init + end + process $group_35 + assign \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$30 \core_quotient_root$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$39 + process $group_36 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand$39 + sync init + end + process $group_37 + assign \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$32 \core_compare_lhs$37 + sync init + end + process $group_38 + assign \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$33 \core_compare_rhs$38 + sync init + end + connect \root_times_radicand$39 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_15" +module \pipe_middle_15 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 41 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 58 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 59 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 60 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 61 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 62 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 63 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 64 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 65 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 output 66 \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 output 67 \operation$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 output 68 \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 output 69 \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 output 70 \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$32$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 output 71 \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$33$next + cell \p$344 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$345 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_60_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_60_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_60_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_60_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_60_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_60_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_60_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_60_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_60_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_60_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_60_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_60_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_60_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_60_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_60_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_60_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_60_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_60_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_60_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_60_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_60_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_60_muxid$34 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_60_logical_op__insn_type$35 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_60_logical_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_60_logical_op__imm_data__imm$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__imm_data__imm_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__invert_in$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_60_logical_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__write_cr0$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__is_32bit$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_60_logical_op__is_signed$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_60_logical_op__data_len$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_60_logical_op__insn$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_60_ra$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_60_rb$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_60_xer_so$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_60_divisor_neg$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_60_dividend_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_60_dive_abs_ov32$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_60_dive_abs_ov64$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_60_div_by_zero$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_60_divisor_radicand$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_60_operation$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_60_quotient_root$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_60_root_times_radicand$64 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_60_compare_lhs$65 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_60_compare_rhs$66 + cell \core_calculate_stage_60 \core_calculate_stage_60 + connect \muxid \core_calculate_stage_60_muxid + connect \logical_op__insn_type \core_calculate_stage_60_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_60_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_60_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_60_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_60_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_60_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_60_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_60_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_60_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_60_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_60_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_60_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_60_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_60_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_60_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_60_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_60_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_60_logical_op__insn + connect \ra \core_calculate_stage_60_ra + connect \rb \core_calculate_stage_60_rb + connect \xer_so \core_calculate_stage_60_xer_so + connect \divisor_neg \core_calculate_stage_60_divisor_neg + connect \dividend_neg \core_calculate_stage_60_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_60_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_60_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_60_div_by_zero + connect \divisor_radicand \core_calculate_stage_60_divisor_radicand + connect \operation \core_calculate_stage_60_operation + connect \quotient_root \core_calculate_stage_60_quotient_root + connect \root_times_radicand \core_calculate_stage_60_root_times_radicand + connect \compare_lhs \core_calculate_stage_60_compare_lhs + connect \compare_rhs \core_calculate_stage_60_compare_rhs + connect \muxid$1 \core_calculate_stage_60_muxid$34 + connect \logical_op__insn_type$2 \core_calculate_stage_60_logical_op__insn_type$35 + connect \logical_op__fn_unit$3 \core_calculate_stage_60_logical_op__fn_unit$36 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_60_logical_op__imm_data__imm$37 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_60_logical_op__imm_data__imm_ok$38 + connect \logical_op__rc__rc$6 \core_calculate_stage_60_logical_op__rc__rc$39 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_60_logical_op__rc__rc_ok$40 + connect \logical_op__oe__oe$8 \core_calculate_stage_60_logical_op__oe__oe$41 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_60_logical_op__oe__oe_ok$42 + connect \logical_op__invert_in$10 \core_calculate_stage_60_logical_op__invert_in$43 + connect \logical_op__zero_a$11 \core_calculate_stage_60_logical_op__zero_a$44 + connect \logical_op__input_carry$12 \core_calculate_stage_60_logical_op__input_carry$45 + connect \logical_op__invert_out$13 \core_calculate_stage_60_logical_op__invert_out$46 + connect \logical_op__write_cr0$14 \core_calculate_stage_60_logical_op__write_cr0$47 + connect \logical_op__output_carry$15 \core_calculate_stage_60_logical_op__output_carry$48 + connect \logical_op__is_32bit$16 \core_calculate_stage_60_logical_op__is_32bit$49 + connect \logical_op__is_signed$17 \core_calculate_stage_60_logical_op__is_signed$50 + connect \logical_op__data_len$18 \core_calculate_stage_60_logical_op__data_len$51 + connect \logical_op__insn$19 \core_calculate_stage_60_logical_op__insn$52 + connect \ra$20 \core_calculate_stage_60_ra$53 + connect \rb$21 \core_calculate_stage_60_rb$54 + connect \xer_so$22 \core_calculate_stage_60_xer_so$55 + connect \divisor_neg$23 \core_calculate_stage_60_divisor_neg$56 + connect \dividend_neg$24 \core_calculate_stage_60_dividend_neg$57 + connect \dive_abs_ov32$25 \core_calculate_stage_60_dive_abs_ov32$58 + connect \dive_abs_ov64$26 \core_calculate_stage_60_dive_abs_ov64$59 + connect \div_by_zero$27 \core_calculate_stage_60_div_by_zero$60 + connect \divisor_radicand$28 \core_calculate_stage_60_divisor_radicand$61 + connect \operation$29 \core_calculate_stage_60_operation$62 + connect \quotient_root$30 \core_calculate_stage_60_quotient_root$63 + connect \root_times_radicand$31 \core_calculate_stage_60_root_times_radicand$64 + connect \compare_lhs$32 \core_calculate_stage_60_compare_lhs$65 + connect \compare_rhs$33 \core_calculate_stage_60_compare_rhs$66 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_61_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_61_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_61_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_61_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_61_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_61_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_61_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_61_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_61_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_61_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_61_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_61_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_61_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_61_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_61_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_61_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_61_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_61_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_61_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_61_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_61_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_61_muxid$67 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_61_logical_op__insn_type$68 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_61_logical_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_61_logical_op__imm_data__imm$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__imm_data__imm_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__rc__rc_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__oe__oe_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__invert_in$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__zero_a$77 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_61_logical_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__invert_out$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__write_cr0$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_61_logical_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_61_logical_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_61_logical_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_61_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_61_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_61_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_61_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_61_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_61_dive_abs_ov32$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_61_dive_abs_ov64$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_61_div_by_zero$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_61_divisor_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_61_operation$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_61_quotient_root$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_61_root_times_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_61_compare_lhs$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_61_compare_rhs$99 + cell \core_calculate_stage_61 \core_calculate_stage_61 + connect \muxid \core_calculate_stage_61_muxid + connect \logical_op__insn_type \core_calculate_stage_61_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_61_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_61_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_61_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_61_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_61_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_61_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_61_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_61_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_61_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_61_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_61_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_61_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_61_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_61_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_61_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_61_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_61_logical_op__insn + connect \ra \core_calculate_stage_61_ra + connect \rb \core_calculate_stage_61_rb + connect \xer_so \core_calculate_stage_61_xer_so + connect \divisor_neg \core_calculate_stage_61_divisor_neg + connect \dividend_neg \core_calculate_stage_61_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_61_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_61_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_61_div_by_zero + connect \divisor_radicand \core_calculate_stage_61_divisor_radicand + connect \operation \core_calculate_stage_61_operation + connect \quotient_root \core_calculate_stage_61_quotient_root + connect \root_times_radicand \core_calculate_stage_61_root_times_radicand + connect \compare_lhs \core_calculate_stage_61_compare_lhs + connect \compare_rhs \core_calculate_stage_61_compare_rhs + connect \muxid$1 \core_calculate_stage_61_muxid$67 + connect \logical_op__insn_type$2 \core_calculate_stage_61_logical_op__insn_type$68 + connect \logical_op__fn_unit$3 \core_calculate_stage_61_logical_op__fn_unit$69 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_61_logical_op__imm_data__imm$70 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_61_logical_op__imm_data__imm_ok$71 + connect \logical_op__rc__rc$6 \core_calculate_stage_61_logical_op__rc__rc$72 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_61_logical_op__rc__rc_ok$73 + connect \logical_op__oe__oe$8 \core_calculate_stage_61_logical_op__oe__oe$74 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_61_logical_op__oe__oe_ok$75 + connect \logical_op__invert_in$10 \core_calculate_stage_61_logical_op__invert_in$76 + connect \logical_op__zero_a$11 \core_calculate_stage_61_logical_op__zero_a$77 + connect \logical_op__input_carry$12 \core_calculate_stage_61_logical_op__input_carry$78 + connect \logical_op__invert_out$13 \core_calculate_stage_61_logical_op__invert_out$79 + connect \logical_op__write_cr0$14 \core_calculate_stage_61_logical_op__write_cr0$80 + connect \logical_op__output_carry$15 \core_calculate_stage_61_logical_op__output_carry$81 + connect \logical_op__is_32bit$16 \core_calculate_stage_61_logical_op__is_32bit$82 + connect \logical_op__is_signed$17 \core_calculate_stage_61_logical_op__is_signed$83 + connect \logical_op__data_len$18 \core_calculate_stage_61_logical_op__data_len$84 + connect \logical_op__insn$19 \core_calculate_stage_61_logical_op__insn$85 + connect \ra$20 \core_calculate_stage_61_ra$86 + connect \rb$21 \core_calculate_stage_61_rb$87 + connect \xer_so$22 \core_calculate_stage_61_xer_so$88 + connect \divisor_neg$23 \core_calculate_stage_61_divisor_neg$89 + connect \dividend_neg$24 \core_calculate_stage_61_dividend_neg$90 + connect \dive_abs_ov32$25 \core_calculate_stage_61_dive_abs_ov32$91 + connect \dive_abs_ov64$26 \core_calculate_stage_61_dive_abs_ov64$92 + connect \div_by_zero$27 \core_calculate_stage_61_div_by_zero$93 + connect \divisor_radicand$28 \core_calculate_stage_61_divisor_radicand$94 + connect \operation$29 \core_calculate_stage_61_operation$95 + connect \quotient_root$30 \core_calculate_stage_61_quotient_root$96 + connect \root_times_radicand$31 \core_calculate_stage_61_root_times_radicand$97 + connect \compare_lhs$32 \core_calculate_stage_61_compare_lhs$98 + connect \compare_rhs$33 \core_calculate_stage_61_compare_rhs$99 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_62_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_62_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_62_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_62_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_62_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_62_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_62_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_62_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_62_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_62_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_62_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_62_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_62_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_62_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_62_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_62_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_62_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_62_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_62_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_62_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_62_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_62_muxid$100 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_62_logical_op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_62_logical_op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_62_logical_op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__rc__rc$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__rc__rc_ok$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__oe__oe$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__oe__oe_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__invert_in$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__zero_a$110 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_62_logical_op__input_carry$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__invert_out$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__write_cr0$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__output_carry$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__is_32bit$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_62_logical_op__is_signed$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_62_logical_op__data_len$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_62_logical_op__insn$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_62_ra$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_62_rb$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_62_xer_so$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_62_divisor_neg$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_62_dividend_neg$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_62_dive_abs_ov32$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_62_dive_abs_ov64$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_62_div_by_zero$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_62_divisor_radicand$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_62_operation$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_62_quotient_root$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_62_root_times_radicand$130 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_62_compare_lhs$131 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_62_compare_rhs$132 + cell \core_calculate_stage_62 \core_calculate_stage_62 + connect \muxid \core_calculate_stage_62_muxid + connect \logical_op__insn_type \core_calculate_stage_62_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_62_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_62_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_62_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_62_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_62_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_62_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_62_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_62_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_62_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_62_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_62_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_62_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_62_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_62_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_62_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_62_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_62_logical_op__insn + connect \ra \core_calculate_stage_62_ra + connect \rb \core_calculate_stage_62_rb + connect \xer_so \core_calculate_stage_62_xer_so + connect \divisor_neg \core_calculate_stage_62_divisor_neg + connect \dividend_neg \core_calculate_stage_62_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_62_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_62_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_62_div_by_zero + connect \divisor_radicand \core_calculate_stage_62_divisor_radicand + connect \operation \core_calculate_stage_62_operation + connect \quotient_root \core_calculate_stage_62_quotient_root + connect \root_times_radicand \core_calculate_stage_62_root_times_radicand + connect \compare_lhs \core_calculate_stage_62_compare_lhs + connect \compare_rhs \core_calculate_stage_62_compare_rhs + connect \muxid$1 \core_calculate_stage_62_muxid$100 + connect \logical_op__insn_type$2 \core_calculate_stage_62_logical_op__insn_type$101 + connect \logical_op__fn_unit$3 \core_calculate_stage_62_logical_op__fn_unit$102 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_62_logical_op__imm_data__imm$103 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_62_logical_op__imm_data__imm_ok$104 + connect \logical_op__rc__rc$6 \core_calculate_stage_62_logical_op__rc__rc$105 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_62_logical_op__rc__rc_ok$106 + connect \logical_op__oe__oe$8 \core_calculate_stage_62_logical_op__oe__oe$107 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_62_logical_op__oe__oe_ok$108 + connect \logical_op__invert_in$10 \core_calculate_stage_62_logical_op__invert_in$109 + connect \logical_op__zero_a$11 \core_calculate_stage_62_logical_op__zero_a$110 + connect \logical_op__input_carry$12 \core_calculate_stage_62_logical_op__input_carry$111 + connect \logical_op__invert_out$13 \core_calculate_stage_62_logical_op__invert_out$112 + connect \logical_op__write_cr0$14 \core_calculate_stage_62_logical_op__write_cr0$113 + connect \logical_op__output_carry$15 \core_calculate_stage_62_logical_op__output_carry$114 + connect \logical_op__is_32bit$16 \core_calculate_stage_62_logical_op__is_32bit$115 + connect \logical_op__is_signed$17 \core_calculate_stage_62_logical_op__is_signed$116 + connect \logical_op__data_len$18 \core_calculate_stage_62_logical_op__data_len$117 + connect \logical_op__insn$19 \core_calculate_stage_62_logical_op__insn$118 + connect \ra$20 \core_calculate_stage_62_ra$119 + connect \rb$21 \core_calculate_stage_62_rb$120 + connect \xer_so$22 \core_calculate_stage_62_xer_so$121 + connect \divisor_neg$23 \core_calculate_stage_62_divisor_neg$122 + connect \dividend_neg$24 \core_calculate_stage_62_dividend_neg$123 + connect \dive_abs_ov32$25 \core_calculate_stage_62_dive_abs_ov32$124 + connect \dive_abs_ov64$26 \core_calculate_stage_62_dive_abs_ov64$125 + connect \div_by_zero$27 \core_calculate_stage_62_div_by_zero$126 + connect \divisor_radicand$28 \core_calculate_stage_62_divisor_radicand$127 + connect \operation$29 \core_calculate_stage_62_operation$128 + connect \quotient_root$30 \core_calculate_stage_62_quotient_root$129 + connect \root_times_radicand$31 \core_calculate_stage_62_root_times_radicand$130 + connect \compare_lhs$32 \core_calculate_stage_62_compare_lhs$131 + connect \compare_rhs$33 \core_calculate_stage_62_compare_rhs$132 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_63_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_63_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_63_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_63_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_63_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_63_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_63_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_63_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_63_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_63_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_63_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_63_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_63_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_63_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_63_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_63_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_63_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_63_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_63_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_63_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_63_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_calculate_stage_63_muxid$133 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_calculate_stage_63_logical_op__insn_type$134 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_calculate_stage_63_logical_op__fn_unit$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_calculate_stage_63_logical_op__imm_data__imm$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__imm_data__imm_ok$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__rc__rc$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__rc__rc_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__oe__oe$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__oe__oe_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__invert_in$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__zero_a$143 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_calculate_stage_63_logical_op__input_carry$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__invert_out$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__write_cr0$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__output_carry$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__is_32bit$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_calculate_stage_63_logical_op__is_signed$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_calculate_stage_63_logical_op__data_len$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_calculate_stage_63_logical_op__insn$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_63_ra$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_calculate_stage_63_rb$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_calculate_stage_63_xer_so$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_calculate_stage_63_divisor_neg$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_calculate_stage_63_dividend_neg$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_calculate_stage_63_dive_abs_ov32$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_calculate_stage_63_dive_abs_ov64$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_calculate_stage_63_div_by_zero$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_calculate_stage_63_divisor_radicand$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_calculate_stage_63_operation$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_calculate_stage_63_quotient_root$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_calculate_stage_63_root_times_radicand$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_calculate_stage_63_compare_lhs$164 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_calculate_stage_63_compare_rhs$165 + cell \core_calculate_stage_63 \core_calculate_stage_63 + connect \muxid \core_calculate_stage_63_muxid + connect \logical_op__insn_type \core_calculate_stage_63_logical_op__insn_type + connect \logical_op__fn_unit \core_calculate_stage_63_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_calculate_stage_63_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_calculate_stage_63_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_calculate_stage_63_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_calculate_stage_63_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_calculate_stage_63_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_calculate_stage_63_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_calculate_stage_63_logical_op__invert_in + connect \logical_op__zero_a \core_calculate_stage_63_logical_op__zero_a + connect \logical_op__input_carry \core_calculate_stage_63_logical_op__input_carry + connect \logical_op__invert_out \core_calculate_stage_63_logical_op__invert_out + connect \logical_op__write_cr0 \core_calculate_stage_63_logical_op__write_cr0 + connect \logical_op__output_carry \core_calculate_stage_63_logical_op__output_carry + connect \logical_op__is_32bit \core_calculate_stage_63_logical_op__is_32bit + connect \logical_op__is_signed \core_calculate_stage_63_logical_op__is_signed + connect \logical_op__data_len \core_calculate_stage_63_logical_op__data_len + connect \logical_op__insn \core_calculate_stage_63_logical_op__insn + connect \ra \core_calculate_stage_63_ra + connect \rb \core_calculate_stage_63_rb + connect \xer_so \core_calculate_stage_63_xer_so + connect \divisor_neg \core_calculate_stage_63_divisor_neg + connect \dividend_neg \core_calculate_stage_63_dividend_neg + connect \dive_abs_ov32 \core_calculate_stage_63_dive_abs_ov32 + connect \dive_abs_ov64 \core_calculate_stage_63_dive_abs_ov64 + connect \div_by_zero \core_calculate_stage_63_div_by_zero + connect \divisor_radicand \core_calculate_stage_63_divisor_radicand + connect \operation \core_calculate_stage_63_operation + connect \quotient_root \core_calculate_stage_63_quotient_root + connect \root_times_radicand \core_calculate_stage_63_root_times_radicand + connect \compare_lhs \core_calculate_stage_63_compare_lhs + connect \compare_rhs \core_calculate_stage_63_compare_rhs + connect \muxid$1 \core_calculate_stage_63_muxid$133 + connect \logical_op__insn_type$2 \core_calculate_stage_63_logical_op__insn_type$134 + connect \logical_op__fn_unit$3 \core_calculate_stage_63_logical_op__fn_unit$135 + connect \logical_op__imm_data__imm$4 \core_calculate_stage_63_logical_op__imm_data__imm$136 + connect \logical_op__imm_data__imm_ok$5 \core_calculate_stage_63_logical_op__imm_data__imm_ok$137 + connect \logical_op__rc__rc$6 \core_calculate_stage_63_logical_op__rc__rc$138 + connect \logical_op__rc__rc_ok$7 \core_calculate_stage_63_logical_op__rc__rc_ok$139 + connect \logical_op__oe__oe$8 \core_calculate_stage_63_logical_op__oe__oe$140 + connect \logical_op__oe__oe_ok$9 \core_calculate_stage_63_logical_op__oe__oe_ok$141 + connect \logical_op__invert_in$10 \core_calculate_stage_63_logical_op__invert_in$142 + connect \logical_op__zero_a$11 \core_calculate_stage_63_logical_op__zero_a$143 + connect \logical_op__input_carry$12 \core_calculate_stage_63_logical_op__input_carry$144 + connect \logical_op__invert_out$13 \core_calculate_stage_63_logical_op__invert_out$145 + connect \logical_op__write_cr0$14 \core_calculate_stage_63_logical_op__write_cr0$146 + connect \logical_op__output_carry$15 \core_calculate_stage_63_logical_op__output_carry$147 + connect \logical_op__is_32bit$16 \core_calculate_stage_63_logical_op__is_32bit$148 + connect \logical_op__is_signed$17 \core_calculate_stage_63_logical_op__is_signed$149 + connect \logical_op__data_len$18 \core_calculate_stage_63_logical_op__data_len$150 + connect \logical_op__insn$19 \core_calculate_stage_63_logical_op__insn$151 + connect \ra$20 \core_calculate_stage_63_ra$152 + connect \rb$21 \core_calculate_stage_63_rb$153 + connect \xer_so$22 \core_calculate_stage_63_xer_so$154 + connect \divisor_neg$23 \core_calculate_stage_63_divisor_neg$155 + connect \dividend_neg$24 \core_calculate_stage_63_dividend_neg$156 + connect \dive_abs_ov32$25 \core_calculate_stage_63_dive_abs_ov32$157 + connect \dive_abs_ov64$26 \core_calculate_stage_63_dive_abs_ov64$158 + connect \div_by_zero$27 \core_calculate_stage_63_div_by_zero$159 + connect \divisor_radicand$28 \core_calculate_stage_63_divisor_radicand$160 + connect \operation$29 \core_calculate_stage_63_operation$161 + connect \quotient_root$30 \core_calculate_stage_63_quotient_root$162 + connect \root_times_radicand$31 \core_calculate_stage_63_root_times_radicand$163 + connect \compare_lhs$32 \core_calculate_stage_63_compare_lhs$164 + connect \compare_rhs$33 \core_calculate_stage_63_compare_rhs$165 + end + process $group_0 + assign \core_calculate_stage_60_muxid 2'00 + assign \core_calculate_stage_60_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_60_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_60_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_60_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_60_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_60_logical_op__rc__rc 1'0 + assign \core_calculate_stage_60_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_60_logical_op__oe__oe 1'0 + assign \core_calculate_stage_60_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_60_logical_op__invert_in 1'0 + assign \core_calculate_stage_60_logical_op__zero_a 1'0 + assign \core_calculate_stage_60_logical_op__input_carry 2'00 + assign \core_calculate_stage_60_logical_op__invert_out 1'0 + assign \core_calculate_stage_60_logical_op__write_cr0 1'0 + assign \core_calculate_stage_60_logical_op__output_carry 1'0 + assign \core_calculate_stage_60_logical_op__is_32bit 1'0 + assign \core_calculate_stage_60_logical_op__is_signed 1'0 + assign \core_calculate_stage_60_logical_op__data_len 4'0000 + assign \core_calculate_stage_60_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_60_logical_op__insn \core_calculate_stage_60_logical_op__data_len \core_calculate_stage_60_logical_op__is_signed \core_calculate_stage_60_logical_op__is_32bit \core_calculate_stage_60_logical_op__output_carry \core_calculate_stage_60_logical_op__write_cr0 \core_calculate_stage_60_logical_op__invert_out \core_calculate_stage_60_logical_op__input_carry \core_calculate_stage_60_logical_op__zero_a \core_calculate_stage_60_logical_op__invert_in { \core_calculate_stage_60_logical_op__oe__oe_ok \core_calculate_stage_60_logical_op__oe__oe } { \core_calculate_stage_60_logical_op__rc__rc_ok \core_calculate_stage_60_logical_op__rc__rc } { \core_calculate_stage_60_logical_op__imm_data__imm_ok \core_calculate_stage_60_logical_op__imm_data__imm } \core_calculate_stage_60_logical_op__fn_unit \core_calculate_stage_60_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \core_calculate_stage_60_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_60_ra \ra + sync init + end + process $group_20 + assign \core_calculate_stage_60_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_60_rb \rb + sync init + end + process $group_21 + assign \core_calculate_stage_60_xer_so 1'0 + assign \core_calculate_stage_60_xer_so \xer_so + sync init + end + process $group_22 + assign \core_calculate_stage_60_divisor_neg 1'0 + assign \core_calculate_stage_60_divisor_neg \divisor_neg + sync init + end + process $group_23 + assign \core_calculate_stage_60_dividend_neg 1'0 + assign \core_calculate_stage_60_dividend_neg \dividend_neg + sync init + end + process $group_24 + assign \core_calculate_stage_60_dive_abs_ov32 1'0 + assign \core_calculate_stage_60_dive_abs_ov32 \dive_abs_ov32 + sync init + end + process $group_25 + assign \core_calculate_stage_60_dive_abs_ov64 1'0 + assign \core_calculate_stage_60_dive_abs_ov64 \dive_abs_ov64 + sync init + end + process $group_26 + assign \core_calculate_stage_60_div_by_zero 1'0 + assign \core_calculate_stage_60_div_by_zero \div_by_zero + sync init + end + process $group_27 + assign \core_calculate_stage_60_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_60_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_calculate_stage_60_operation 2'00 + assign \core_calculate_stage_60_operation \operation + sync init + end + process $group_29 + assign \core_calculate_stage_60_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_60_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_calculate_stage_60_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_60_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_calculate_stage_60_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_60_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_calculate_stage_60_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_60_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \core_calculate_stage_61_muxid 2'00 + assign \core_calculate_stage_61_muxid \core_calculate_stage_60_muxid$34 + sync init + end + process $group_34 + assign \core_calculate_stage_61_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_61_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_61_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_61_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_61_logical_op__rc__rc 1'0 + assign \core_calculate_stage_61_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_61_logical_op__oe__oe 1'0 + assign \core_calculate_stage_61_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_61_logical_op__invert_in 1'0 + assign \core_calculate_stage_61_logical_op__zero_a 1'0 + assign \core_calculate_stage_61_logical_op__input_carry 2'00 + assign \core_calculate_stage_61_logical_op__invert_out 1'0 + assign \core_calculate_stage_61_logical_op__write_cr0 1'0 + assign \core_calculate_stage_61_logical_op__output_carry 1'0 + assign \core_calculate_stage_61_logical_op__is_32bit 1'0 + assign \core_calculate_stage_61_logical_op__is_signed 1'0 + assign \core_calculate_stage_61_logical_op__data_len 4'0000 + assign \core_calculate_stage_61_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_61_logical_op__insn \core_calculate_stage_61_logical_op__data_len \core_calculate_stage_61_logical_op__is_signed \core_calculate_stage_61_logical_op__is_32bit \core_calculate_stage_61_logical_op__output_carry \core_calculate_stage_61_logical_op__write_cr0 \core_calculate_stage_61_logical_op__invert_out \core_calculate_stage_61_logical_op__input_carry \core_calculate_stage_61_logical_op__zero_a \core_calculate_stage_61_logical_op__invert_in { \core_calculate_stage_61_logical_op__oe__oe_ok \core_calculate_stage_61_logical_op__oe__oe } { \core_calculate_stage_61_logical_op__rc__rc_ok \core_calculate_stage_61_logical_op__rc__rc } { \core_calculate_stage_61_logical_op__imm_data__imm_ok \core_calculate_stage_61_logical_op__imm_data__imm } \core_calculate_stage_61_logical_op__fn_unit \core_calculate_stage_61_logical_op__insn_type } { \core_calculate_stage_60_logical_op__insn$52 \core_calculate_stage_60_logical_op__data_len$51 \core_calculate_stage_60_logical_op__is_signed$50 \core_calculate_stage_60_logical_op__is_32bit$49 \core_calculate_stage_60_logical_op__output_carry$48 \core_calculate_stage_60_logical_op__write_cr0$47 \core_calculate_stage_60_logical_op__invert_out$46 \core_calculate_stage_60_logical_op__input_carry$45 \core_calculate_stage_60_logical_op__zero_a$44 \core_calculate_stage_60_logical_op__invert_in$43 { \core_calculate_stage_60_logical_op__oe__oe_ok$42 \core_calculate_stage_60_logical_op__oe__oe$41 } { \core_calculate_stage_60_logical_op__rc__rc_ok$40 \core_calculate_stage_60_logical_op__rc__rc$39 } { \core_calculate_stage_60_logical_op__imm_data__imm_ok$38 \core_calculate_stage_60_logical_op__imm_data__imm$37 } \core_calculate_stage_60_logical_op__fn_unit$36 \core_calculate_stage_60_logical_op__insn_type$35 } + sync init + end + process $group_52 + assign \core_calculate_stage_61_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_61_ra \core_calculate_stage_60_ra$53 + sync init + end + process $group_53 + assign \core_calculate_stage_61_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_61_rb \core_calculate_stage_60_rb$54 + sync init + end + process $group_54 + assign \core_calculate_stage_61_xer_so 1'0 + assign \core_calculate_stage_61_xer_so \core_calculate_stage_60_xer_so$55 + sync init + end + process $group_55 + assign \core_calculate_stage_61_divisor_neg 1'0 + assign \core_calculate_stage_61_divisor_neg \core_calculate_stage_60_divisor_neg$56 + sync init + end + process $group_56 + assign \core_calculate_stage_61_dividend_neg 1'0 + assign \core_calculate_stage_61_dividend_neg \core_calculate_stage_60_dividend_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_61_dive_abs_ov32 1'0 + assign \core_calculate_stage_61_dive_abs_ov32 \core_calculate_stage_60_dive_abs_ov32$58 + sync init + end + process $group_58 + assign \core_calculate_stage_61_dive_abs_ov64 1'0 + assign \core_calculate_stage_61_dive_abs_ov64 \core_calculate_stage_60_dive_abs_ov64$59 + sync init + end + process $group_59 + assign \core_calculate_stage_61_div_by_zero 1'0 + assign \core_calculate_stage_61_div_by_zero \core_calculate_stage_60_div_by_zero$60 + sync init + end + process $group_60 + assign \core_calculate_stage_61_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_61_divisor_radicand \core_calculate_stage_60_divisor_radicand$61 + sync init + end + process $group_61 + assign \core_calculate_stage_61_operation 2'00 + assign \core_calculate_stage_61_operation \core_calculate_stage_60_operation$62 + sync init + end + process $group_62 + assign \core_calculate_stage_61_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_61_quotient_root \core_calculate_stage_60_quotient_root$63 + sync init + end + process $group_63 + assign \core_calculate_stage_61_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_61_root_times_radicand \core_calculate_stage_60_root_times_radicand$64 + sync init + end + process $group_64 + assign \core_calculate_stage_61_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_61_compare_lhs \core_calculate_stage_60_compare_lhs$65 + sync init + end + process $group_65 + assign \core_calculate_stage_61_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_61_compare_rhs \core_calculate_stage_60_compare_rhs$66 + sync init + end + process $group_66 + assign \core_calculate_stage_62_muxid 2'00 + assign \core_calculate_stage_62_muxid \core_calculate_stage_61_muxid$67 + sync init + end + process $group_67 + assign \core_calculate_stage_62_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_62_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_62_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_62_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_62_logical_op__rc__rc 1'0 + assign \core_calculate_stage_62_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_62_logical_op__oe__oe 1'0 + assign \core_calculate_stage_62_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_62_logical_op__invert_in 1'0 + assign \core_calculate_stage_62_logical_op__zero_a 1'0 + assign \core_calculate_stage_62_logical_op__input_carry 2'00 + assign \core_calculate_stage_62_logical_op__invert_out 1'0 + assign \core_calculate_stage_62_logical_op__write_cr0 1'0 + assign \core_calculate_stage_62_logical_op__output_carry 1'0 + assign \core_calculate_stage_62_logical_op__is_32bit 1'0 + assign \core_calculate_stage_62_logical_op__is_signed 1'0 + assign \core_calculate_stage_62_logical_op__data_len 4'0000 + assign \core_calculate_stage_62_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_62_logical_op__insn \core_calculate_stage_62_logical_op__data_len \core_calculate_stage_62_logical_op__is_signed \core_calculate_stage_62_logical_op__is_32bit \core_calculate_stage_62_logical_op__output_carry \core_calculate_stage_62_logical_op__write_cr0 \core_calculate_stage_62_logical_op__invert_out \core_calculate_stage_62_logical_op__input_carry \core_calculate_stage_62_logical_op__zero_a \core_calculate_stage_62_logical_op__invert_in { \core_calculate_stage_62_logical_op__oe__oe_ok \core_calculate_stage_62_logical_op__oe__oe } { \core_calculate_stage_62_logical_op__rc__rc_ok \core_calculate_stage_62_logical_op__rc__rc } { \core_calculate_stage_62_logical_op__imm_data__imm_ok \core_calculate_stage_62_logical_op__imm_data__imm } \core_calculate_stage_62_logical_op__fn_unit \core_calculate_stage_62_logical_op__insn_type } { \core_calculate_stage_61_logical_op__insn$85 \core_calculate_stage_61_logical_op__data_len$84 \core_calculate_stage_61_logical_op__is_signed$83 \core_calculate_stage_61_logical_op__is_32bit$82 \core_calculate_stage_61_logical_op__output_carry$81 \core_calculate_stage_61_logical_op__write_cr0$80 \core_calculate_stage_61_logical_op__invert_out$79 \core_calculate_stage_61_logical_op__input_carry$78 \core_calculate_stage_61_logical_op__zero_a$77 \core_calculate_stage_61_logical_op__invert_in$76 { \core_calculate_stage_61_logical_op__oe__oe_ok$75 \core_calculate_stage_61_logical_op__oe__oe$74 } { \core_calculate_stage_61_logical_op__rc__rc_ok$73 \core_calculate_stage_61_logical_op__rc__rc$72 } { \core_calculate_stage_61_logical_op__imm_data__imm_ok$71 \core_calculate_stage_61_logical_op__imm_data__imm$70 } \core_calculate_stage_61_logical_op__fn_unit$69 \core_calculate_stage_61_logical_op__insn_type$68 } + sync init + end + process $group_85 + assign \core_calculate_stage_62_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_62_ra \core_calculate_stage_61_ra$86 + sync init + end + process $group_86 + assign \core_calculate_stage_62_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_62_rb \core_calculate_stage_61_rb$87 + sync init + end + process $group_87 + assign \core_calculate_stage_62_xer_so 1'0 + assign \core_calculate_stage_62_xer_so \core_calculate_stage_61_xer_so$88 + sync init + end + process $group_88 + assign \core_calculate_stage_62_divisor_neg 1'0 + assign \core_calculate_stage_62_divisor_neg \core_calculate_stage_61_divisor_neg$89 + sync init + end + process $group_89 + assign \core_calculate_stage_62_dividend_neg 1'0 + assign \core_calculate_stage_62_dividend_neg \core_calculate_stage_61_dividend_neg$90 + sync init + end + process $group_90 + assign \core_calculate_stage_62_dive_abs_ov32 1'0 + assign \core_calculate_stage_62_dive_abs_ov32 \core_calculate_stage_61_dive_abs_ov32$91 + sync init + end + process $group_91 + assign \core_calculate_stage_62_dive_abs_ov64 1'0 + assign \core_calculate_stage_62_dive_abs_ov64 \core_calculate_stage_61_dive_abs_ov64$92 + sync init + end + process $group_92 + assign \core_calculate_stage_62_div_by_zero 1'0 + assign \core_calculate_stage_62_div_by_zero \core_calculate_stage_61_div_by_zero$93 + sync init + end + process $group_93 + assign \core_calculate_stage_62_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_62_divisor_radicand \core_calculate_stage_61_divisor_radicand$94 + sync init + end + process $group_94 + assign \core_calculate_stage_62_operation 2'00 + assign \core_calculate_stage_62_operation \core_calculate_stage_61_operation$95 + sync init + end + process $group_95 + assign \core_calculate_stage_62_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_62_quotient_root \core_calculate_stage_61_quotient_root$96 + sync init + end + process $group_96 + assign \core_calculate_stage_62_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_62_root_times_radicand \core_calculate_stage_61_root_times_radicand$97 + sync init + end + process $group_97 + assign \core_calculate_stage_62_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_62_compare_lhs \core_calculate_stage_61_compare_lhs$98 + sync init + end + process $group_98 + assign \core_calculate_stage_62_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_62_compare_rhs \core_calculate_stage_61_compare_rhs$99 + sync init + end + process $group_99 + assign \core_calculate_stage_63_muxid 2'00 + assign \core_calculate_stage_63_muxid \core_calculate_stage_62_muxid$100 + sync init + end + process $group_100 + assign \core_calculate_stage_63_logical_op__insn_type 7'0000000 + assign \core_calculate_stage_63_logical_op__fn_unit 11'00000000000 + assign \core_calculate_stage_63_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_63_logical_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_63_logical_op__rc__rc 1'0 + assign \core_calculate_stage_63_logical_op__rc__rc_ok 1'0 + assign \core_calculate_stage_63_logical_op__oe__oe 1'0 + assign \core_calculate_stage_63_logical_op__oe__oe_ok 1'0 + assign \core_calculate_stage_63_logical_op__invert_in 1'0 + assign \core_calculate_stage_63_logical_op__zero_a 1'0 + assign \core_calculate_stage_63_logical_op__input_carry 2'00 + assign \core_calculate_stage_63_logical_op__invert_out 1'0 + assign \core_calculate_stage_63_logical_op__write_cr0 1'0 + assign \core_calculate_stage_63_logical_op__output_carry 1'0 + assign \core_calculate_stage_63_logical_op__is_32bit 1'0 + assign \core_calculate_stage_63_logical_op__is_signed 1'0 + assign \core_calculate_stage_63_logical_op__data_len 4'0000 + assign \core_calculate_stage_63_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_63_logical_op__insn \core_calculate_stage_63_logical_op__data_len \core_calculate_stage_63_logical_op__is_signed \core_calculate_stage_63_logical_op__is_32bit \core_calculate_stage_63_logical_op__output_carry \core_calculate_stage_63_logical_op__write_cr0 \core_calculate_stage_63_logical_op__invert_out \core_calculate_stage_63_logical_op__input_carry \core_calculate_stage_63_logical_op__zero_a \core_calculate_stage_63_logical_op__invert_in { \core_calculate_stage_63_logical_op__oe__oe_ok \core_calculate_stage_63_logical_op__oe__oe } { \core_calculate_stage_63_logical_op__rc__rc_ok \core_calculate_stage_63_logical_op__rc__rc } { \core_calculate_stage_63_logical_op__imm_data__imm_ok \core_calculate_stage_63_logical_op__imm_data__imm } \core_calculate_stage_63_logical_op__fn_unit \core_calculate_stage_63_logical_op__insn_type } { \core_calculate_stage_62_logical_op__insn$118 \core_calculate_stage_62_logical_op__data_len$117 \core_calculate_stage_62_logical_op__is_signed$116 \core_calculate_stage_62_logical_op__is_32bit$115 \core_calculate_stage_62_logical_op__output_carry$114 \core_calculate_stage_62_logical_op__write_cr0$113 \core_calculate_stage_62_logical_op__invert_out$112 \core_calculate_stage_62_logical_op__input_carry$111 \core_calculate_stage_62_logical_op__zero_a$110 \core_calculate_stage_62_logical_op__invert_in$109 { \core_calculate_stage_62_logical_op__oe__oe_ok$108 \core_calculate_stage_62_logical_op__oe__oe$107 } { \core_calculate_stage_62_logical_op__rc__rc_ok$106 \core_calculate_stage_62_logical_op__rc__rc$105 } { \core_calculate_stage_62_logical_op__imm_data__imm_ok$104 \core_calculate_stage_62_logical_op__imm_data__imm$103 } \core_calculate_stage_62_logical_op__fn_unit$102 \core_calculate_stage_62_logical_op__insn_type$101 } + sync init + end + process $group_118 + assign \core_calculate_stage_63_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_63_ra \core_calculate_stage_62_ra$119 + sync init + end + process $group_119 + assign \core_calculate_stage_63_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_63_rb \core_calculate_stage_62_rb$120 + sync init + end + process $group_120 + assign \core_calculate_stage_63_xer_so 1'0 + assign \core_calculate_stage_63_xer_so \core_calculate_stage_62_xer_so$121 + sync init + end + process $group_121 + assign \core_calculate_stage_63_divisor_neg 1'0 + assign \core_calculate_stage_63_divisor_neg \core_calculate_stage_62_divisor_neg$122 + sync init + end + process $group_122 + assign \core_calculate_stage_63_dividend_neg 1'0 + assign \core_calculate_stage_63_dividend_neg \core_calculate_stage_62_dividend_neg$123 + sync init + end + process $group_123 + assign \core_calculate_stage_63_dive_abs_ov32 1'0 + assign \core_calculate_stage_63_dive_abs_ov32 \core_calculate_stage_62_dive_abs_ov32$124 + sync init + end + process $group_124 + assign \core_calculate_stage_63_dive_abs_ov64 1'0 + assign \core_calculate_stage_63_dive_abs_ov64 \core_calculate_stage_62_dive_abs_ov64$125 + sync init + end + process $group_125 + assign \core_calculate_stage_63_div_by_zero 1'0 + assign \core_calculate_stage_63_div_by_zero \core_calculate_stage_62_div_by_zero$126 + sync init + end + process $group_126 + assign \core_calculate_stage_63_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_63_divisor_radicand \core_calculate_stage_62_divisor_radicand$127 + sync init + end + process $group_127 + assign \core_calculate_stage_63_operation 2'00 + assign \core_calculate_stage_63_operation \core_calculate_stage_62_operation$128 + sync init + end + process $group_128 + assign \core_calculate_stage_63_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_63_quotient_root \core_calculate_stage_62_quotient_root$129 + sync init + end + process $group_129 + assign \core_calculate_stage_63_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_63_root_times_radicand \core_calculate_stage_62_root_times_radicand$130 + sync init + end + process $group_130 + assign \core_calculate_stage_63_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_63_compare_lhs \core_calculate_stage_62_compare_lhs$131 + sync init + end + process $group_131 + assign \core_calculate_stage_63_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_63_compare_rhs \core_calculate_stage_62_compare_rhs$132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$166 + process $group_132 + assign \p_valid_i$166 1'0 + assign \p_valid_i$166 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_133 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$166 + connect \B \p_ready_o + connect \Y $167 + end + process $group_134 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $167 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$169 + process $group_135 + assign \muxid$169 2'00 + assign \muxid$169 \core_calculate_stage_63_muxid$133 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$170 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$179 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$187 + process $group_136 + assign \logical_op__insn_type$170 7'0000000 + assign \logical_op__fn_unit$171 11'00000000000 + assign \logical_op__imm_data__imm$172 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$173 1'0 + assign \logical_op__rc__rc$174 1'0 + assign \logical_op__rc__rc_ok$175 1'0 + assign \logical_op__oe__oe$176 1'0 + assign \logical_op__oe__oe_ok$177 1'0 + assign \logical_op__invert_in$178 1'0 + assign \logical_op__zero_a$179 1'0 + assign \logical_op__input_carry$180 2'00 + assign \logical_op__invert_out$181 1'0 + assign \logical_op__write_cr0$182 1'0 + assign \logical_op__output_carry$183 1'0 + assign \logical_op__is_32bit$184 1'0 + assign \logical_op__is_signed$185 1'0 + assign \logical_op__data_len$186 4'0000 + assign \logical_op__insn$187 32'00000000000000000000000000000000 + assign { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } { \core_calculate_stage_63_logical_op__insn$151 \core_calculate_stage_63_logical_op__data_len$150 \core_calculate_stage_63_logical_op__is_signed$149 \core_calculate_stage_63_logical_op__is_32bit$148 \core_calculate_stage_63_logical_op__output_carry$147 \core_calculate_stage_63_logical_op__write_cr0$146 \core_calculate_stage_63_logical_op__invert_out$145 \core_calculate_stage_63_logical_op__input_carry$144 \core_calculate_stage_63_logical_op__zero_a$143 \core_calculate_stage_63_logical_op__invert_in$142 { \core_calculate_stage_63_logical_op__oe__oe_ok$141 \core_calculate_stage_63_logical_op__oe__oe$140 } { \core_calculate_stage_63_logical_op__rc__rc_ok$139 \core_calculate_stage_63_logical_op__rc__rc$138 } { \core_calculate_stage_63_logical_op__imm_data__imm_ok$137 \core_calculate_stage_63_logical_op__imm_data__imm$136 } \core_calculate_stage_63_logical_op__fn_unit$135 \core_calculate_stage_63_logical_op__insn_type$134 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$188 + process $group_154 + assign \ra$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$188 \core_calculate_stage_63_ra$152 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$189 + process $group_155 + assign \rb$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$189 \core_calculate_stage_63_rb$153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$190 + process $group_156 + assign \xer_so$190 1'0 + assign \xer_so$190 \core_calculate_stage_63_xer_so$154 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \divisor_neg$191 + process $group_157 + assign \divisor_neg$191 1'0 + assign \divisor_neg$191 \core_calculate_stage_63_divisor_neg$155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \dividend_neg$192 + process $group_158 + assign \dividend_neg$192 1'0 + assign \dividend_neg$192 \core_calculate_stage_63_dividend_neg$156 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \dive_abs_ov32$193 + process $group_159 + assign \dive_abs_ov32$193 1'0 + assign \dive_abs_ov32$193 \core_calculate_stage_63_dive_abs_ov32$157 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \dive_abs_ov64$194 + process $group_160 + assign \dive_abs_ov64$194 1'0 + assign \dive_abs_ov64$194 \core_calculate_stage_63_dive_abs_ov64$158 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \div_by_zero$195 + process $group_161 + assign \div_by_zero$195 1'0 + assign \div_by_zero$195 \core_calculate_stage_63_div_by_zero$159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$196 + process $group_162 + assign \divisor_radicand$196 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$196 \core_calculate_stage_63_divisor_radicand$160 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$197 + process $group_163 + assign \operation$197 2'00 + assign \operation$197 \core_calculate_stage_63_operation$161 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \quotient_root$198 + process $group_164 + assign \quotient_root$198 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$198 \core_calculate_stage_63_quotient_root$162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$199 + process $group_165 + assign \root_times_radicand$199 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$199 \core_calculate_stage_63_root_times_radicand$163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \compare_lhs$200 + process $group_166 + assign \compare_lhs$200 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$200 \core_calculate_stage_63_compare_lhs$164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \compare_rhs$201 + process $group_167 + assign \compare_rhs$201 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$201 \core_calculate_stage_63_compare_rhs$165 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_168 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_169 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$169 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_170 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$187 \logical_op__data_len$186 \logical_op__is_signed$185 \logical_op__is_32bit$184 \logical_op__output_carry$183 \logical_op__write_cr0$182 \logical_op__invert_out$181 \logical_op__input_carry$180 \logical_op__zero_a$179 \logical_op__invert_in$178 { \logical_op__oe__oe_ok$177 \logical_op__oe__oe$176 } { \logical_op__rc__rc_ok$175 \logical_op__rc__rc$174 } { \logical_op__imm_data__imm_ok$173 \logical_op__imm_data__imm$172 } \logical_op__fn_unit$171 \logical_op__insn_type$170 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_188 + assign \ra$20$next \ra$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$20$next \ra$188 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$20$next \ra$188 + end + sync init + update \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra$20 \ra$20$next + end + process $group_189 + assign \rb$21$next \rb$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$21$next \rb$189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$21$next \rb$189 + end + sync init + update \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb$21 \rb$21$next + end + process $group_190 + assign \xer_so$22$next \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$22$next \xer_so$190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$22$next \xer_so$190 + end + sync init + update \xer_so$22 1'0 + sync posedge \coresync_clk + update \xer_so$22 \xer_so$22$next + end + process $group_191 + assign \divisor_neg$23$next \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$23$next \divisor_neg$191 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$23$next \divisor_neg$191 + end + sync init + update \divisor_neg$23 1'0 + sync posedge \coresync_clk + update \divisor_neg$23 \divisor_neg$23$next + end + process $group_192 + assign \dividend_neg$24$next \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$24$next \dividend_neg$192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$24$next \dividend_neg$192 + end + sync init + update \dividend_neg$24 1'0 + sync posedge \coresync_clk + update \dividend_neg$24 \dividend_neg$24$next + end + process $group_193 + assign \dive_abs_ov32$25$next \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov32$25$next \dive_abs_ov32$193 + end + sync init + update \dive_abs_ov32$25 1'0 + sync posedge \coresync_clk + update \dive_abs_ov32$25 \dive_abs_ov32$25$next + end + process $group_194 + assign \dive_abs_ov64$26$next \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dive_abs_ov64$26$next \dive_abs_ov64$194 + end + sync init + update \dive_abs_ov64$26 1'0 + sync posedge \coresync_clk + update \dive_abs_ov64$26 \dive_abs_ov64$26$next + end + process $group_195 + assign \div_by_zero$27$next \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \div_by_zero$27$next \div_by_zero$195 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \div_by_zero$27$next \div_by_zero$195 + end + sync init + update \div_by_zero$27 1'0 + sync posedge \coresync_clk + update \div_by_zero$27 \div_by_zero$27$next + end + process $group_196 + assign \divisor_radicand$28$next \divisor_radicand$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$28$next \divisor_radicand$196 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$28$next \divisor_radicand$196 + end + sync init + update \divisor_radicand$28 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \divisor_radicand$28 \divisor_radicand$28$next + end + process $group_197 + assign \operation$29$next \operation$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$29$next \operation$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$29$next \operation$197 + end + sync init + update \operation$29 2'00 + sync posedge \coresync_clk + update \operation$29 \operation$29$next + end + process $group_198 + assign \quotient_root$30$next \quotient_root$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$30$next \quotient_root$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$30$next \quotient_root$198 + end + sync init + update \quotient_root$30 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \quotient_root$30 \quotient_root$30$next + end + process $group_199 + assign \root_times_radicand$31$next \root_times_radicand$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$31$next \root_times_radicand$199 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$31$next \root_times_radicand$199 + end + sync init + update \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \root_times_radicand$31 \root_times_radicand$31$next + end + process $group_200 + assign \compare_lhs$32$next \compare_lhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$32$next \compare_lhs$200 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$32$next \compare_lhs$200 + end + sync init + update \compare_lhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_lhs$32 \compare_lhs$32$next + end + process $group_201 + assign \compare_rhs$33$next \compare_rhs$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$33$next \compare_rhs$201 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$33$next \compare_rhs$201 + end + sync init + update \compare_rhs$33 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \compare_rhs$33 \compare_rhs$33$next + end + process $group_202 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_203 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.p" +module \p$362 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.n" +module \n$363 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.core_final_stage.core" +module \core$364 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 0 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 1 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 2 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" + wire width 64 output 3 \quotient_root$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:210" + wire width 192 output 4 \remainder + process $group_0 + assign \quotient_root$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$1 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:533" + wire width 193 $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:533" + wire width 193 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:533" + cell $sub $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_lhs + connect \B \compare_rhs + connect \Y $3 + end + connect $2 $3 + process $group_1 + assign \remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \remainder $2 [191:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.core_final_stage" +module \core_final_stage + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 24 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 25 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 26 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 29 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 30 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 31 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 32 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 33 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 34 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 35 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 36 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 44 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 50 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 51 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 52 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 53 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 54 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 output 55 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 output 56 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 output 57 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 output 58 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 output 59 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" + wire width 64 output 60 \quotient_root$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:210" + wire width 192 output 61 \remainder + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" + wire width 64 \core_quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:210" + wire width 192 \core_remainder + cell \core$364 \core + connect \quotient_root \core_quotient_root + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \quotient_root$1 \core_quotient_root$29 + connect \remainder \core_remainder + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$20 \ra + sync init + end + process $group_20 + assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$21 \rb + sync init + end + process $group_21 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_22 + assign \divisor_neg$23 1'0 + assign \divisor_neg$23 \divisor_neg + sync init + end + process $group_23 + assign \dividend_neg$24 1'0 + assign \dividend_neg$24 \dividend_neg + sync init + end + process $group_24 + assign \dive_abs_ov32$25 1'0 + assign \dive_abs_ov32$25 \dive_abs_ov32 + sync init + end + process $group_25 + assign \dive_abs_ov64$26 1'0 + assign \dive_abs_ov64$26 \dive_abs_ov64 + sync init + end + process $group_26 + assign \div_by_zero$27 1'0 + assign \div_by_zero$27 \div_by_zero + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \divisor_radicand$30 + process $group_27 + assign \divisor_radicand$30 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$30 \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \operation$31 + process $group_28 + assign \operation$31 2'00 + assign \operation$31 \operation + sync init + end + process $group_29 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \root_times_radicand$32 + process $group_30 + assign \root_times_radicand$32 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$32 \root_times_radicand + sync init + end + process $group_31 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \quotient_root$28 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$28 \core_quotient_root$29 + sync init + end + process $group_34 + assign \remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \remainder \core_remainder + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output_stage" +module \output_stage + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 20 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 21 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 22 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 23 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 24 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" + wire width 64 input 25 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:210" + wire width 192 input 26 \remainder + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 27 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 28 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 29 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 30 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 31 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 36 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 38 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 44 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 45 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 46 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 47 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 50 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" + wire width 1 \quotient_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + cell $xor $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dividend_neg + connect \B \divisor_neg + connect \Y $21 + end + process $group_0 + assign \quotient_neg 1'0 + assign \quotient_neg $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" + wire width 1 \remainder_neg + process $group_1 + assign \remainder_neg 1'0 + assign \remainder_neg \dividend_neg + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" + wire width 65 \quotient_65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + wire width 65 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $neg $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" + wire width 65 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" + cell $pos $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + wire width 65 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $mux $28 + parameter \WIDTH 65 + connect \A $25 + connect \B $23 + connect \S \quotient_neg + connect \Y $27 + end + process $group_2 + assign \quotient_65 65'00000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_65 $27 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" + wire width 64 \remainder_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $neg $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 65 $32 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 65 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $mux $35 + parameter \WIDTH 65 + connect \A $32 + connect \B $30 + connect \S \remainder_neg + connect \Y $34 + end + connect $29 $34 + process $group_3 + assign \remainder_64 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \remainder_64 $29 [63:0] + sync init + end + wire width 1 $verilog_initial_trigger + process $group_4 + assign \xer_ov_ok 1'0 + assign \xer_ov_ok 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" + wire width 1 \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + cell $not $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_32bit + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $xor $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [64] + connect \B \quotient_65 [63] + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $and $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_signed + connect \B $38 + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + cell $ne $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [32] + connect \B \quotient_65 [31] + connect \Y $42 + end + process $group_5 + assign \ov 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + switch { \logical_op__is_signed $36 \div_by_zero } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + case 3'--1 + assign \ov 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + case 3'-1- + assign \ov \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + switch { $40 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + case 1'1 + assign \ov 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:82" + case 3'1-- + assign \ov \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + switch { $42 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + case 1'1 + assign \ov 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:86" + case + assign \ov \dive_abs_ov32 + end + sync init + end + process $group_6 + assign \xer_ov 2'00 + assign \xer_ov { \ov \ov } + sync init + end + process $group_7 + assign \o_ok 1'0 + assign \o_ok 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + cell $not $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ov + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + wire width 64 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $pos $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $46 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" + wire width 64 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" + cell $pos $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $48 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + wire width 64 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + cell $pos $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $50 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" + wire width 64 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" + cell $pos $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $52 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" + wire width 64 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" + cell $pos $55 + parameter \A_SIGNED 1 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $54 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" + wire width 64 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" + cell $pos $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $56 + end + process $group_8 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + switch { $44 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:98" + attribute \nmigen.decoding "OP_DIVE/30" + case 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + switch { \logical_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" + switch { \logical_op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" + case 1'1 + assign \o $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" + case + assign \o $48 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" + case + assign \o \quotient_65 [63:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:107" + attribute \nmigen.decoding "OP_DIV/29" + case 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + switch { \logical_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" + switch { \logical_op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" + case 1'1 + assign \o $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:112" + case + assign \o $52 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" + case + assign \o \quotient_65 [63:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:116" + attribute \nmigen.decoding "OP_MOD/47" + case 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + switch { \logical_op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" + switch { \logical_op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" + case 1'1 + assign \o $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:121" + case + assign \o $56 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" + case + assign \o \remainder_64 + end + end + end + sync init + end + process $group_9 + assign \xer_so$20 1'0 + assign \xer_so$20 \xer_so + sync init + end + process $group_10 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_11 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output" +module \output$365 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 24 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 25 \logical_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 26 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 27 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 31 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \logical_op__zero_a$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 35 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 36 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 38 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 39 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 41 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 42 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 43 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 44 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 45 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 46 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 47 \xer_ov$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 48 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 49 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 50 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" + wire width 65 \o$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + wire width 65 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + wire width 64 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + cell $not $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26" + cell $pos $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A $27 + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $30 + end + process $group_0 + assign \o$25 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + switch { \logical_op__invert_out } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25" + case 1'1 + assign \o$25 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + case + assign \o$25 $30 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + wire width 64 \target + process $group_1 + assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \target \o$25 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + wire width 1 \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + cell $eq $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $32 + end + process $group_2 + assign \is_cmp 1'0 + assign \is_cmp $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + wire width 1 \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + cell $eq $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $34 + end + process $group_3 + assign \is_cmpeqb 1'0 + assign \is_cmpeqb $34 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + wire width 1 \msb_test + process $group_4 + assign \msb_test 1'0 + assign \msb_test \target [63] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 1 \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + cell $reduce_bool $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $36 + end + process $group_5 + assign \is_nzero 1'0 + assign \is_nzero $36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + wire width 1 \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $not $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $and $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $38 + connect \Y $40 + end + process $group_6 + assign \is_positive 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_positive \msb_test + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_positive $40 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" + wire width 1 \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $not $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $and $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $42 + connect \Y $44 + end + process $group_7 + assign \is_negative 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_negative $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_negative \msb_test + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + cell $not $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $46 + end + process $group_8 + assign \cr0 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + switch { \is_cmpeqb } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + case 1'1 + assign \cr0 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + case + assign \cr0 { \is_negative \is_positive $46 \xer_so$24 } + end + sync init + end + process $group_9 + assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o$20 \o$25 [63:0] + sync init + end + process $group_10 + assign \o_ok$21 1'0 + assign \o_ok$21 \o_ok + sync init + end + process $group_11 + assign \cr_a$22 4'0000 + assign \cr_a$22 \cr0 + sync init + end + process $group_12 + assign \cr_a_ok 1'0 + assign \cr_a_ok \logical_op__write_cr0 + sync init + end + process $group_13 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_14 + assign \logical_op__insn_type$2 7'0000000 + assign \logical_op__fn_unit$3 11'00000000000 + assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5 1'0 + assign \logical_op__rc__rc$6 1'0 + assign \logical_op__rc__rc_ok$7 1'0 + assign \logical_op__oe__oe$8 1'0 + assign \logical_op__oe__oe_ok$9 1'0 + assign \logical_op__invert_in$10 1'0 + assign \logical_op__zero_a$11 1'0 + assign \logical_op__input_carry$12 2'00 + assign \logical_op__invert_out$13 1'0 + assign \logical_op__write_cr0$14 1'0 + assign \logical_op__output_carry$15 1'0 + assign \logical_op__is_32bit$16 1'0 + assign \logical_op__is_signed$17 1'0 + assign \logical_op__data_len$18 4'0000 + assign \logical_op__insn$19 32'00000000000000000000000000000000 + assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" + wire width 1 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire width 1 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + cell $and $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__oe_ok + connect \Y $48 + end + process $group_32 + assign \oe 1'0 + assign \oe $48 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" + wire width 1 \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" + cell $or $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $50 + end + process $group_33 + assign \so 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \so $50 + end + sync init + end + process $group_34 + assign \xer_so$24 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_so$24 \so + end + sync init + end + process $group_35 + assign \xer_so_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_so_ok 1'1 + end + sync init + end + process $group_36 + assign \xer_ov$23 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_ov$23 \xer_ov + end + sync init + end + process $group_37 + assign \xer_ov_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_ov_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end" +module \pipe_end + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 input 31 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 input 32 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 input 33 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 input 34 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 input 35 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 input 36 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 37 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 38 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 39 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 40 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 41 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 42 \logical_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \logical_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 45 \logical_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 46 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 47 \logical_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 48 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 49 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 50 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 51 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 52 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 53 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 54 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 55 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 56 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 57 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 58 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 59 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 60 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 61 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 62 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 63 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 64 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 65 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$next + cell \p$362 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$363 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_final_stage_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_final_stage_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_final_stage_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_final_stage_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_final_stage_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_final_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_final_stage_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_final_stage_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_final_stage_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_final_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_final_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_final_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_final_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_final_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_final_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \core_final_stage_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \core_final_stage_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \core_final_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \core_final_stage_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \core_final_stage_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \core_final_stage_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \core_final_stage_muxid$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \core_final_stage_logical_op__insn_type$22 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \core_final_stage_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \core_final_stage_logical_op__imm_data__imm$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__imm_data__imm_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__rc__rc_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__oe__oe_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__zero_a$31 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \core_final_stage_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \core_final_stage_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \core_final_stage_logical_op__data_len$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \core_final_stage_logical_op__insn$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_final_stage_ra$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \core_final_stage_rb$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \core_final_stage_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \core_final_stage_divisor_neg$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \core_final_stage_dividend_neg$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \core_final_stage_dive_abs_ov32$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \core_final_stage_dive_abs_ov64$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \core_final_stage_div_by_zero$47 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" + wire width 64 \core_final_stage_quotient_root$48 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:210" + wire width 192 \core_final_stage_remainder + cell \core_final_stage \core_final_stage + connect \muxid \core_final_stage_muxid + connect \logical_op__insn_type \core_final_stage_logical_op__insn_type + connect \logical_op__fn_unit \core_final_stage_logical_op__fn_unit + connect \logical_op__imm_data__imm \core_final_stage_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \core_final_stage_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \core_final_stage_logical_op__rc__rc + connect \logical_op__rc__rc_ok \core_final_stage_logical_op__rc__rc_ok + connect \logical_op__oe__oe \core_final_stage_logical_op__oe__oe + connect \logical_op__oe__oe_ok \core_final_stage_logical_op__oe__oe_ok + connect \logical_op__invert_in \core_final_stage_logical_op__invert_in + connect \logical_op__zero_a \core_final_stage_logical_op__zero_a + connect \logical_op__input_carry \core_final_stage_logical_op__input_carry + connect \logical_op__invert_out \core_final_stage_logical_op__invert_out + connect \logical_op__write_cr0 \core_final_stage_logical_op__write_cr0 + connect \logical_op__output_carry \core_final_stage_logical_op__output_carry + connect \logical_op__is_32bit \core_final_stage_logical_op__is_32bit + connect \logical_op__is_signed \core_final_stage_logical_op__is_signed + connect \logical_op__data_len \core_final_stage_logical_op__data_len + connect \logical_op__insn \core_final_stage_logical_op__insn + connect \ra \core_final_stage_ra + connect \rb \core_final_stage_rb + connect \xer_so \core_final_stage_xer_so + connect \divisor_neg \core_final_stage_divisor_neg + connect \dividend_neg \core_final_stage_dividend_neg + connect \dive_abs_ov32 \core_final_stage_dive_abs_ov32 + connect \dive_abs_ov64 \core_final_stage_dive_abs_ov64 + connect \div_by_zero \core_final_stage_div_by_zero + connect \divisor_radicand \core_final_stage_divisor_radicand + connect \operation \core_final_stage_operation + connect \quotient_root \core_final_stage_quotient_root + connect \root_times_radicand \core_final_stage_root_times_radicand + connect \compare_lhs \core_final_stage_compare_lhs + connect \compare_rhs \core_final_stage_compare_rhs + connect \muxid$1 \core_final_stage_muxid$21 + connect \logical_op__insn_type$2 \core_final_stage_logical_op__insn_type$22 + connect \logical_op__fn_unit$3 \core_final_stage_logical_op__fn_unit$23 + connect \logical_op__imm_data__imm$4 \core_final_stage_logical_op__imm_data__imm$24 + connect \logical_op__imm_data__imm_ok$5 \core_final_stage_logical_op__imm_data__imm_ok$25 + connect \logical_op__rc__rc$6 \core_final_stage_logical_op__rc__rc$26 + connect \logical_op__rc__rc_ok$7 \core_final_stage_logical_op__rc__rc_ok$27 + connect \logical_op__oe__oe$8 \core_final_stage_logical_op__oe__oe$28 + connect \logical_op__oe__oe_ok$9 \core_final_stage_logical_op__oe__oe_ok$29 + connect \logical_op__invert_in$10 \core_final_stage_logical_op__invert_in$30 + connect \logical_op__zero_a$11 \core_final_stage_logical_op__zero_a$31 + connect \logical_op__input_carry$12 \core_final_stage_logical_op__input_carry$32 + connect \logical_op__invert_out$13 \core_final_stage_logical_op__invert_out$33 + connect \logical_op__write_cr0$14 \core_final_stage_logical_op__write_cr0$34 + connect \logical_op__output_carry$15 \core_final_stage_logical_op__output_carry$35 + connect \logical_op__is_32bit$16 \core_final_stage_logical_op__is_32bit$36 + connect \logical_op__is_signed$17 \core_final_stage_logical_op__is_signed$37 + connect \logical_op__data_len$18 \core_final_stage_logical_op__data_len$38 + connect \logical_op__insn$19 \core_final_stage_logical_op__insn$39 + connect \ra$20 \core_final_stage_ra$40 + connect \rb$21 \core_final_stage_rb$41 + connect \xer_so$22 \core_final_stage_xer_so$42 + connect \divisor_neg$23 \core_final_stage_divisor_neg$43 + connect \dividend_neg$24 \core_final_stage_dividend_neg$44 + connect \dive_abs_ov32$25 \core_final_stage_dive_abs_ov32$45 + connect \dive_abs_ov64$26 \core_final_stage_dive_abs_ov64$46 + connect \div_by_zero$27 \core_final_stage_div_by_zero$47 + connect \quotient_root$28 \core_final_stage_quotient_root$48 + connect \remainder \core_final_stage_remainder + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_stage_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_stage_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \output_stage_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_stage_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_stage_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_stage_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_stage_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_stage_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_stage_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_stage_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \output_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \output_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \output_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \output_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \output_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \output_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:209" + wire width 64 \output_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:210" + wire width 192 \output_stage_remainder + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_stage_muxid$49 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_stage_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_stage_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_stage_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_stage_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_stage_xer_so$68 + cell \output_stage \output_stage + connect \muxid \output_stage_muxid + connect \logical_op__insn_type \output_stage_logical_op__insn_type + connect \logical_op__fn_unit \output_stage_logical_op__fn_unit + connect \logical_op__imm_data__imm \output_stage_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \output_stage_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \output_stage_logical_op__rc__rc + connect \logical_op__rc__rc_ok \output_stage_logical_op__rc__rc_ok + connect \logical_op__oe__oe \output_stage_logical_op__oe__oe + connect \logical_op__oe__oe_ok \output_stage_logical_op__oe__oe_ok + connect \logical_op__invert_in \output_stage_logical_op__invert_in + connect \logical_op__zero_a \output_stage_logical_op__zero_a + connect \logical_op__input_carry \output_stage_logical_op__input_carry + connect \logical_op__invert_out \output_stage_logical_op__invert_out + connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 + connect \logical_op__output_carry \output_stage_logical_op__output_carry + connect \logical_op__is_32bit \output_stage_logical_op__is_32bit + connect \logical_op__is_signed \output_stage_logical_op__is_signed + connect \logical_op__data_len \output_stage_logical_op__data_len + connect \logical_op__insn \output_stage_logical_op__insn + connect \xer_so \output_stage_xer_so + connect \divisor_neg \output_stage_divisor_neg + connect \dividend_neg \output_stage_dividend_neg + connect \dive_abs_ov32 \output_stage_dive_abs_ov32 + connect \dive_abs_ov64 \output_stage_dive_abs_ov64 + connect \div_by_zero \output_stage_div_by_zero + connect \quotient_root \output_stage_quotient_root + connect \remainder \output_stage_remainder + connect \muxid$1 \output_stage_muxid$49 + connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$50 + connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$51 + connect \logical_op__imm_data__imm$4 \output_stage_logical_op__imm_data__imm$52 + connect \logical_op__imm_data__imm_ok$5 \output_stage_logical_op__imm_data__imm_ok$53 + connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$54 + connect \logical_op__rc__rc_ok$7 \output_stage_logical_op__rc__rc_ok$55 + connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$56 + connect \logical_op__oe__oe_ok$9 \output_stage_logical_op__oe__oe_ok$57 + connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$58 + connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$59 + connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$60 + connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$61 + connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$62 + connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$63 + connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$64 + connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$65 + connect \logical_op__data_len$18 \output_stage_logical_op__data_len$66 + connect \logical_op__insn$19 \output_stage_logical_op__insn$67 + connect \o \output_stage_o + connect \o_ok \output_stage_o_ok + connect \xer_ov \output_stage_xer_ov + connect \xer_ov_ok \output_stage_xer_ov_ok + connect \xer_so$20 \output_stage_xer_so$68 + end + attribute \src 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\enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$70 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \output_logical_op__fn_unit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__imm$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__imm_data__imm_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__rc__rc$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__rc__rc_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__oe__oe$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__oe__oe_ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__invert_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__zero_a$79 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__invert_out$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__write_cr0$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__output_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__is_32bit$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_logical_op__is_signed$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so_ok + cell \output$365 \output + connect \muxid \output_muxid + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__imm_data__imm \output_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc_ok \output_logical_op__rc__rc_ok + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe_ok \output_logical_op__oe__oe_ok + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__insn \output_logical_op__insn + connect \o \output_o + connect \o_ok \output_o_ok + connect \cr_a \output_cr_a + connect \xer_ov \output_xer_ov + connect \xer_so \output_xer_so + connect \muxid$1 \output_muxid$69 + connect \logical_op__insn_type$2 \output_logical_op__insn_type$70 + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$71 + connect \logical_op__imm_data__imm$4 \output_logical_op__imm_data__imm$72 + connect \logical_op__imm_data__imm_ok$5 \output_logical_op__imm_data__imm_ok$73 + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$74 + connect \logical_op__rc__rc_ok$7 \output_logical_op__rc__rc_ok$75 + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$76 + connect \logical_op__oe__oe_ok$9 \output_logical_op__oe__oe_ok$77 + connect \logical_op__invert_in$10 \output_logical_op__invert_in$78 + connect \logical_op__zero_a$11 \output_logical_op__zero_a$79 + connect \logical_op__input_carry$12 \output_logical_op__input_carry$80 + connect \logical_op__invert_out$13 \output_logical_op__invert_out$81 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$82 + connect \logical_op__output_carry$15 \output_logical_op__output_carry$83 + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$84 + connect \logical_op__is_signed$17 \output_logical_op__is_signed$85 + connect \logical_op__data_len$18 \output_logical_op__data_len$86 + connect \logical_op__insn$19 \output_logical_op__insn$87 + connect \o$20 \output_o$88 + connect \o_ok$21 \output_o_ok$89 + connect \cr_a$22 \output_cr_a$90 + connect \cr_a_ok \output_cr_a_ok + connect \xer_ov$23 \output_xer_ov$91 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so$24 \output_xer_so$92 + connect \xer_so_ok \output_xer_so_ok + end + process $group_0 + assign \core_final_stage_muxid 2'00 + assign \core_final_stage_muxid \muxid + sync init + end + process $group_1 + assign \core_final_stage_logical_op__insn_type 7'0000000 + assign \core_final_stage_logical_op__fn_unit 11'00000000000 + assign \core_final_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_logical_op__imm_data__imm_ok 1'0 + assign \core_final_stage_logical_op__rc__rc 1'0 + assign \core_final_stage_logical_op__rc__rc_ok 1'0 + assign \core_final_stage_logical_op__oe__oe 1'0 + assign \core_final_stage_logical_op__oe__oe_ok 1'0 + assign \core_final_stage_logical_op__invert_in 1'0 + assign \core_final_stage_logical_op__zero_a 1'0 + assign \core_final_stage_logical_op__input_carry 2'00 + assign \core_final_stage_logical_op__invert_out 1'0 + assign \core_final_stage_logical_op__write_cr0 1'0 + assign \core_final_stage_logical_op__output_carry 1'0 + assign \core_final_stage_logical_op__is_32bit 1'0 + assign \core_final_stage_logical_op__is_signed 1'0 + assign \core_final_stage_logical_op__data_len 4'0000 + assign \core_final_stage_logical_op__insn 32'00000000000000000000000000000000 + assign { \core_final_stage_logical_op__insn \core_final_stage_logical_op__data_len \core_final_stage_logical_op__is_signed \core_final_stage_logical_op__is_32bit \core_final_stage_logical_op__output_carry \core_final_stage_logical_op__write_cr0 \core_final_stage_logical_op__invert_out \core_final_stage_logical_op__input_carry \core_final_stage_logical_op__zero_a \core_final_stage_logical_op__invert_in { \core_final_stage_logical_op__oe__oe_ok \core_final_stage_logical_op__oe__oe } { \core_final_stage_logical_op__rc__rc_ok \core_final_stage_logical_op__rc__rc } { \core_final_stage_logical_op__imm_data__imm_ok \core_final_stage_logical_op__imm_data__imm } \core_final_stage_logical_op__fn_unit \core_final_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_19 + assign \core_final_stage_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_ra \ra + sync init + end + process $group_20 + assign \core_final_stage_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_rb \rb + sync init + end + process $group_21 + assign \core_final_stage_xer_so 1'0 + assign \core_final_stage_xer_so \xer_so + sync init + end + process $group_22 + assign \core_final_stage_divisor_neg 1'0 + assign \core_final_stage_divisor_neg \divisor_neg + sync init + end + process $group_23 + assign \core_final_stage_dividend_neg 1'0 + assign \core_final_stage_dividend_neg \dividend_neg + sync init + end + process $group_24 + assign \core_final_stage_dive_abs_ov32 1'0 + assign \core_final_stage_dive_abs_ov32 \dive_abs_ov32 + sync init + end + process $group_25 + assign \core_final_stage_dive_abs_ov64 1'0 + assign \core_final_stage_dive_abs_ov64 \dive_abs_ov64 + sync init + end + process $group_26 + assign \core_final_stage_div_by_zero 1'0 + assign \core_final_stage_div_by_zero \div_by_zero + sync init + end + process $group_27 + assign \core_final_stage_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_final_stage_operation 2'00 + assign \core_final_stage_operation \operation + sync init + end + process $group_29 + assign \core_final_stage_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_quotient_root \quotient_root + sync init + end + process $group_30 + assign \core_final_stage_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_root_times_radicand \root_times_radicand + sync init + end + process $group_31 + assign \core_final_stage_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_compare_lhs \compare_lhs + sync init + end + process $group_32 + assign \core_final_stage_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_compare_rhs \compare_rhs + sync init + end + process $group_33 + assign \output_stage_muxid 2'00 + assign \output_stage_muxid \core_final_stage_muxid$21 + sync init + end + process $group_34 + assign \output_stage_logical_op__insn_type 7'0000000 + assign \output_stage_logical_op__fn_unit 11'00000000000 + assign \output_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_stage_logical_op__imm_data__imm_ok 1'0 + assign \output_stage_logical_op__rc__rc 1'0 + assign \output_stage_logical_op__rc__rc_ok 1'0 + assign \output_stage_logical_op__oe__oe 1'0 + assign \output_stage_logical_op__oe__oe_ok 1'0 + assign \output_stage_logical_op__invert_in 1'0 + assign \output_stage_logical_op__zero_a 1'0 + assign \output_stage_logical_op__input_carry 2'00 + assign \output_stage_logical_op__invert_out 1'0 + assign \output_stage_logical_op__write_cr0 1'0 + assign \output_stage_logical_op__output_carry 1'0 + assign \output_stage_logical_op__is_32bit 1'0 + assign \output_stage_logical_op__is_signed 1'0 + assign \output_stage_logical_op__data_len 4'0000 + assign \output_stage_logical_op__insn 32'00000000000000000000000000000000 + assign { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in { \output_stage_logical_op__oe__oe_ok \output_stage_logical_op__oe__oe } { \output_stage_logical_op__rc__rc_ok \output_stage_logical_op__rc__rc } { \output_stage_logical_op__imm_data__imm_ok \output_stage_logical_op__imm_data__imm } \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \core_final_stage_logical_op__insn$39 \core_final_stage_logical_op__data_len$38 \core_final_stage_logical_op__is_signed$37 \core_final_stage_logical_op__is_32bit$36 \core_final_stage_logical_op__output_carry$35 \core_final_stage_logical_op__write_cr0$34 \core_final_stage_logical_op__invert_out$33 \core_final_stage_logical_op__input_carry$32 \core_final_stage_logical_op__zero_a$31 \core_final_stage_logical_op__invert_in$30 { \core_final_stage_logical_op__oe__oe_ok$29 \core_final_stage_logical_op__oe__oe$28 } { \core_final_stage_logical_op__rc__rc_ok$27 \core_final_stage_logical_op__rc__rc$26 } { \core_final_stage_logical_op__imm_data__imm_ok$25 \core_final_stage_logical_op__imm_data__imm$24 } \core_final_stage_logical_op__fn_unit$23 \core_final_stage_logical_op__insn_type$22 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$93 + process $group_52 + assign \ra$93 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$93 \core_final_stage_ra$40 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$94 + process $group_53 + assign \rb$94 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$94 \core_final_stage_rb$41 + sync init + end + process $group_54 + assign \output_stage_xer_so 1'0 + assign \output_stage_xer_so \core_final_stage_xer_so$42 + sync init + end + process $group_55 + assign \output_stage_divisor_neg 1'0 + assign \output_stage_divisor_neg \core_final_stage_divisor_neg$43 + sync init + end + process $group_56 + assign \output_stage_dividend_neg 1'0 + assign \output_stage_dividend_neg \core_final_stage_dividend_neg$44 + sync init + end + process $group_57 + assign \output_stage_dive_abs_ov32 1'0 + assign \output_stage_dive_abs_ov32 \core_final_stage_dive_abs_ov32$45 + sync init + end + process $group_58 + assign \output_stage_dive_abs_ov64 1'0 + assign \output_stage_dive_abs_ov64 \core_final_stage_dive_abs_ov64$46 + sync init + end + process $group_59 + assign \output_stage_div_by_zero 1'0 + assign \output_stage_div_by_zero \core_final_stage_div_by_zero$47 + sync init + end + process $group_60 + assign \output_stage_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_stage_quotient_root \core_final_stage_quotient_root$48 + sync init + end + process $group_61 + assign \output_stage_remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \output_stage_remainder \core_final_stage_remainder + sync init + end + process $group_62 + assign \output_muxid 2'00 + assign \output_muxid \output_stage_muxid$49 + sync init + end + process $group_63 + assign \output_logical_op__insn_type 7'0000000 + assign \output_logical_op__fn_unit 11'00000000000 + assign \output_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_logical_op__imm_data__imm_ok 1'0 + assign \output_logical_op__rc__rc 1'0 + assign \output_logical_op__rc__rc_ok 1'0 + assign \output_logical_op__oe__oe 1'0 + assign \output_logical_op__oe__oe_ok 1'0 + assign \output_logical_op__invert_in 1'0 + assign \output_logical_op__zero_a 1'0 + assign \output_logical_op__input_carry 2'00 + assign \output_logical_op__invert_out 1'0 + assign \output_logical_op__write_cr0 1'0 + assign \output_logical_op__output_carry 1'0 + assign \output_logical_op__is_32bit 1'0 + assign \output_logical_op__is_signed 1'0 + assign \output_logical_op__data_len 4'0000 + assign \output_logical_op__insn 32'00000000000000000000000000000000 + assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in { \output_logical_op__oe__oe_ok \output_logical_op__oe__oe } { \output_logical_op__rc__rc_ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm } \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$67 \output_stage_logical_op__data_len$66 \output_stage_logical_op__is_signed$65 \output_stage_logical_op__is_32bit$64 \output_stage_logical_op__output_carry$63 \output_stage_logical_op__write_cr0$62 \output_stage_logical_op__invert_out$61 \output_stage_logical_op__input_carry$60 \output_stage_logical_op__zero_a$59 \output_stage_logical_op__invert_in$58 { \output_stage_logical_op__oe__oe_ok$57 \output_stage_logical_op__oe__oe$56 } { \output_stage_logical_op__rc__rc_ok$55 \output_stage_logical_op__rc__rc$54 } { \output_stage_logical_op__imm_data__imm_ok$53 \output_stage_logical_op__imm_data__imm$52 } \output_stage_logical_op__fn_unit$51 \output_stage_logical_op__insn_type$50 } + sync init + end + process $group_81 + assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_o_ok 1'0 + assign { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$97 + process $group_83 + assign \output_cr_a 4'0000 + assign \cr_a_ok$95 1'0 + assign { \cr_a_ok$95 \output_cr_a } { \cr_a_ok$97 \cr_a$96 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$98 + process $group_85 + assign \output_xer_ov 2'00 + assign \xer_ov_ok$98 1'0 + assign { \xer_ov_ok$98 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$100 + process $group_87 + assign \output_xer_so 1'0 + assign \xer_so_ok$99 1'0 + assign { \xer_so_ok$99 \output_xer_so } { \xer_so_ok$100 \output_stage_xer_so$68 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$101 + process $group_89 + assign \p_valid_i$101 1'0 + assign \p_valid_i$101 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_90 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $102 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$101 + connect \B \p_ready_o + connect \Y $102 + end + process $group_91 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $102 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$104 + process $group_92 + assign \muxid$104 2'00 + assign \muxid$104 \output_muxid$69 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$105 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$114 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$122 + process $group_93 + assign \logical_op__insn_type$105 7'0000000 + assign \logical_op__fn_unit$106 11'00000000000 + assign \logical_op__imm_data__imm$107 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$108 1'0 + assign \logical_op__rc__rc$109 1'0 + assign \logical_op__rc__rc_ok$110 1'0 + assign \logical_op__oe__oe$111 1'0 + assign \logical_op__oe__oe_ok$112 1'0 + assign \logical_op__invert_in$113 1'0 + assign \logical_op__zero_a$114 1'0 + assign \logical_op__input_carry$115 2'00 + assign \logical_op__invert_out$116 1'0 + assign \logical_op__write_cr0$117 1'0 + assign \logical_op__output_carry$118 1'0 + assign \logical_op__is_32bit$119 1'0 + assign \logical_op__is_signed$120 1'0 + assign \logical_op__data_len$121 4'0000 + assign \logical_op__insn$122 32'00000000000000000000000000000000 + assign { \logical_op__insn$122 \logical_op__data_len$121 \logical_op__is_signed$120 \logical_op__is_32bit$119 \logical_op__output_carry$118 \logical_op__write_cr0$117 \logical_op__invert_out$116 \logical_op__input_carry$115 \logical_op__zero_a$114 \logical_op__invert_in$113 { \logical_op__oe__oe_ok$112 \logical_op__oe__oe$111 } { \logical_op__rc__rc_ok$110 \logical_op__rc__rc$109 } { \logical_op__imm_data__imm_ok$108 \logical_op__imm_data__imm$107 } \logical_op__fn_unit$106 \logical_op__insn_type$105 } { \output_logical_op__insn$87 \output_logical_op__data_len$86 \output_logical_op__is_signed$85 \output_logical_op__is_32bit$84 \output_logical_op__output_carry$83 \output_logical_op__write_cr0$82 \output_logical_op__invert_out$81 \output_logical_op__input_carry$80 \output_logical_op__zero_a$79 \output_logical_op__invert_in$78 { \output_logical_op__oe__oe_ok$77 \output_logical_op__oe__oe$76 } { \output_logical_op__rc__rc_ok$75 \output_logical_op__rc__rc$74 } { \output_logical_op__imm_data__imm_ok$73 \output_logical_op__imm_data__imm$72 } \output_logical_op__fn_unit$71 \output_logical_op__insn_type$70 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$124 + process $group_111 + assign \o$123 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$124 1'0 + assign { \o_ok$124 \o$123 } { \output_o_ok$89 \output_o$88 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$126 + process $group_113 + assign \cr_a$125 4'0000 + assign \cr_a_ok$126 1'0 + assign { \cr_a_ok$126 \cr_a$125 } { \output_cr_a_ok \output_cr_a$90 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$128 + process $group_115 + assign \xer_ov$127 2'00 + assign \xer_ov_ok$128 1'0 + assign { \xer_ov_ok$128 \xer_ov$127 } { \output_xer_ov_ok \output_xer_ov$91 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$130 + process $group_117 + assign \xer_so$129 1'0 + assign \xer_so_ok$130 1'0 + assign { \xer_so_ok$130 \xer_so$129 } { \output_xer_so_ok \output_xer_so$92 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_119 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_120 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$104 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$104 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_121 + assign \logical_op__insn_type$2$next \logical_op__insn_type$2 + assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 + assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4 + assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5 + assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 + assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7 + assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 + assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9 + assign \logical_op__invert_in$10$next \logical_op__invert_in$10 + assign \logical_op__zero_a$11$next \logical_op__zero_a$11 + assign \logical_op__input_carry$12$next \logical_op__input_carry$12 + assign \logical_op__invert_out$13$next \logical_op__invert_out$13 + assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 + assign \logical_op__output_carry$15$next \logical_op__output_carry$15 + assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 + assign \logical_op__is_signed$17$next \logical_op__is_signed$17 + assign \logical_op__data_len$18$next \logical_op__data_len$18 + assign \logical_op__insn$19$next \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$122 \logical_op__data_len$121 \logical_op__is_signed$120 \logical_op__is_32bit$119 \logical_op__output_carry$118 \logical_op__write_cr0$117 \logical_op__invert_out$116 \logical_op__input_carry$115 \logical_op__zero_a$114 \logical_op__invert_in$113 { \logical_op__oe__oe_ok$112 \logical_op__oe__oe$111 } { \logical_op__rc__rc_ok$110 \logical_op__rc__rc$109 } { \logical_op__imm_data__imm_ok$108 \logical_op__imm_data__imm$107 } \logical_op__fn_unit$106 \logical_op__insn_type$105 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$122 \logical_op__data_len$121 \logical_op__is_signed$120 \logical_op__is_32bit$119 \logical_op__output_carry$118 \logical_op__write_cr0$117 \logical_op__invert_out$116 \logical_op__input_carry$115 \logical_op__zero_a$114 \logical_op__invert_in$113 { \logical_op__oe__oe_ok$112 \logical_op__oe__oe$111 } { \logical_op__rc__rc_ok$110 \logical_op__rc__rc$109 } { \logical_op__imm_data__imm_ok$108 \logical_op__imm_data__imm$107 } \logical_op__fn_unit$106 \logical_op__insn_type$105 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$5$next 1'0 + assign \logical_op__rc__rc$6$next 1'0 + assign \logical_op__rc__rc_ok$7$next 1'0 + assign \logical_op__oe__oe$8$next 1'0 + assign \logical_op__oe__oe_ok$9$next 1'0 + end + sync init + update \logical_op__insn_type$2 7'0000000 + update \logical_op__fn_unit$3 11'00000000000 + update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \logical_op__imm_data__imm_ok$5 1'0 + update \logical_op__rc__rc$6 1'0 + update \logical_op__rc__rc_ok$7 1'0 + update \logical_op__oe__oe$8 1'0 + update \logical_op__oe__oe_ok$9 1'0 + update \logical_op__invert_in$10 1'0 + update \logical_op__zero_a$11 1'0 + update \logical_op__input_carry$12 2'00 + update \logical_op__invert_out$13 1'0 + update \logical_op__write_cr0$14 1'0 + update \logical_op__output_carry$15 1'0 + update \logical_op__is_32bit$16 1'0 + update \logical_op__is_signed$17 1'0 + update \logical_op__data_len$18 4'0000 + update \logical_op__insn$19 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \logical_op__insn_type$2 \logical_op__insn_type$2$next + update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next + update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next + update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next + update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next + update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next + update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next + update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next + update \logical_op__invert_in$10 \logical_op__invert_in$10$next + update \logical_op__zero_a$11 \logical_op__zero_a$11$next + update \logical_op__input_carry$12 \logical_op__input_carry$12$next + update \logical_op__invert_out$13 \logical_op__invert_out$13$next + update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next + update \logical_op__output_carry$15 \logical_op__output_carry$15$next + update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next + update \logical_op__is_signed$17 \logical_op__is_signed$17$next + update \logical_op__data_len$18 \logical_op__data_len$18$next + update \logical_op__insn$19 \logical_op__insn$19$next + end + process $group_139 + assign \o$next \o + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$next } { \o_ok$124 \o$123 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$next } { \o_ok$124 \o$123 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \o_ok$next 1'0 + end + sync init + update \o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 + sync posedge \coresync_clk + update \o \o$next + update \o_ok \o_ok$next + end + process $group_141 + assign \cr_a$next \cr_a + assign \cr_a_ok$next \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$126 \cr_a$125 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$126 \cr_a$125 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cr_a_ok$next 1'0 + end + sync init + update \cr_a 4'0000 + update \cr_a_ok 1'0 + sync posedge \coresync_clk + update \cr_a \cr_a$next + update \cr_a_ok \cr_a_ok$next + end + process $group_143 + assign \xer_ov$next \xer_ov + assign \xer_ov_ok$next \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$128 \xer_ov$127 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$128 \xer_ov$127 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ov_ok$next 1'0 + end + sync init + update \xer_ov 2'00 + update \xer_ov_ok 1'0 + sync posedge \coresync_clk + update \xer_ov \xer_ov$next + update \xer_ov_ok \xer_ov_ok$next + end + process $group_145 + assign \xer_so$20$next \xer_so$20 + assign \xer_so_ok$next \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$130 \xer_so$129 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$130 \xer_so$129 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_so_ok$next 1'0 + end + sync init + update \xer_so$20 1'0 + update \xer_so_ok 1'0 + sync posedge \coresync_clk + update \xer_so$20 \xer_so$20$next + update \xer_so_ok \xer_so_ok$next + end + process $group_147 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_148 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \cr_a$96 4'0000 + connect \cr_a_ok$97 1'0 + connect \xer_so_ok$100 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0" +module \alu_div0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \xer_so_ok + attribute \src "simple/issuer.py:102" + wire width 1 input 5 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 7 \n_ready_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 9 \logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 20 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 21 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 22 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 23 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 24 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 25 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 26 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 27 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 28 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 29 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 30 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 31 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 32 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 34 \p_ready_o + cell \p$71 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$72 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_start_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_start_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_start_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_start_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_start_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_start_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_start_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_start_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_start_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_start_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_start_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_start_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_start_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_start_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_start_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_start_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_start_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_start_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_start_muxid$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_start_logical_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__imm$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__imm_data__imm_ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__output_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__is_32bit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_start_logical_op__is_signed$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_start_xer_so$23 + cell \pipe_start \pipe_start + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \n_valid_o \pipe_start_n_valid_o + connect \n_ready_i \pipe_start_n_ready_i + connect \muxid \pipe_start_muxid + connect \logical_op__insn_type \pipe_start_logical_op__insn_type + connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_start_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_start_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_start_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_start_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_start_logical_op__invert_in + connect \logical_op__zero_a \pipe_start_logical_op__zero_a + connect \logical_op__input_carry \pipe_start_logical_op__input_carry + connect \logical_op__invert_out \pipe_start_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_start_logical_op__output_carry + connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit + connect \logical_op__is_signed \pipe_start_logical_op__is_signed + connect \logical_op__data_len \pipe_start_logical_op__data_len + connect \logical_op__insn \pipe_start_logical_op__insn + connect \ra \pipe_start_ra + connect \rb \pipe_start_rb + connect \xer_so \pipe_start_xer_so + connect \divisor_neg \pipe_start_divisor_neg + connect \dividend_neg \pipe_start_dividend_neg + connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \div_by_zero \pipe_start_div_by_zero + connect \divisor_radicand \pipe_start_divisor_radicand + connect \operation \pipe_start_operation + connect \quotient_root \pipe_start_quotient_root + connect \root_times_radicand \pipe_start_root_times_radicand + connect \compare_lhs \pipe_start_compare_lhs + connect \compare_rhs \pipe_start_compare_rhs + connect \p_valid_i \pipe_start_p_valid_i + connect \p_ready_o \pipe_start_p_ready_o + connect \muxid$1 \pipe_start_muxid$2 + connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 + connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 + connect \logical_op__imm_data__imm$4 \pipe_start_logical_op__imm_data__imm$5 + connect \logical_op__imm_data__imm_ok$5 \pipe_start_logical_op__imm_data__imm_ok$6 + connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 + connect \logical_op__rc__rc_ok$7 \pipe_start_logical_op__rc__rc_ok$8 + connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 + connect \logical_op__oe__oe_ok$9 \pipe_start_logical_op__oe__oe_ok$10 + connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 + connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 + connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 + connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 + connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 + connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 + connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 + connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 + connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 + connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 + connect \ra$20 \pipe_start_ra$21 + connect \rb$21 \pipe_start_rb$22 + connect \xer_so$22 \pipe_start_xer_so$23 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_0_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_0_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_0_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_0_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_0_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_0_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_0_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_0_muxid$24 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type$25 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_0_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__imm$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__rc__rc_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__oe__oe_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__zero_a$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_0_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_0_xer_so$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_0_divisor_neg$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_0_dividend_neg$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_0_dive_abs_ov32$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_0_dive_abs_ov64$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_0_div_by_zero$50 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_0_divisor_radicand$51 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_0_operation$52 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_0_quotient_root$53 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_0_root_times_radicand$54 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_0_compare_lhs$55 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_0_compare_rhs$56 + cell \pipe_middle_0 \pipe_middle_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_0_p_valid_i + connect \p_ready_o \pipe_middle_0_p_ready_o + connect \muxid \pipe_middle_0_muxid + connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_0_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_0_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_0_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_0_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_0_logical_op__data_len + connect \logical_op__insn \pipe_middle_0_logical_op__insn + connect \ra \pipe_middle_0_ra + connect \rb \pipe_middle_0_rb + connect \xer_so \pipe_middle_0_xer_so + connect \divisor_neg \pipe_middle_0_divisor_neg + connect \dividend_neg \pipe_middle_0_dividend_neg + connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 + connect \div_by_zero \pipe_middle_0_div_by_zero + connect \divisor_radicand \pipe_middle_0_divisor_radicand + connect \operation \pipe_middle_0_operation + connect \quotient_root \pipe_middle_0_quotient_root + connect \root_times_radicand \pipe_middle_0_root_times_radicand + connect \compare_lhs \pipe_middle_0_compare_lhs + connect \compare_rhs \pipe_middle_0_compare_rhs + connect \n_valid_o \pipe_middle_0_n_valid_o + connect \n_ready_i \pipe_middle_0_n_ready_i + connect \muxid$1 \pipe_middle_0_muxid$24 + connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 + connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 + connect \logical_op__imm_data__imm$4 \pipe_middle_0_logical_op__imm_data__imm$27 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_0_logical_op__imm_data__imm_ok$28 + connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 + connect \logical_op__rc__rc_ok$7 \pipe_middle_0_logical_op__rc__rc_ok$30 + connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 + connect \logical_op__oe__oe_ok$9 \pipe_middle_0_logical_op__oe__oe_ok$32 + connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 + connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 + connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 + connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 + connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 + connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 + connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 + connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 + connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 + connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 + connect \ra$20 \pipe_middle_0_ra$43 + connect \rb$21 \pipe_middle_0_rb$44 + connect \xer_so$22 \pipe_middle_0_xer_so$45 + connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 + connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 + connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 + connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 + connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 + connect \divisor_radicand$28 \pipe_middle_0_divisor_radicand$51 + connect \operation$29 \pipe_middle_0_operation$52 + connect \quotient_root$30 \pipe_middle_0_quotient_root$53 + connect \root_times_radicand$31 \pipe_middle_0_root_times_radicand$54 + connect \compare_lhs$32 \pipe_middle_0_compare_lhs$55 + connect \compare_rhs$33 \pipe_middle_0_compare_rhs$56 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_1_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_1_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_1_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_1_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_1_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_1_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_1_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_1_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_1_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_1_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_1_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_1_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_1_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_1_muxid$57 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_1_logical_op__insn_type$58 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_1_logical_op__fn_unit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_1_logical_op__imm_data__imm$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__imm_data__imm_ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__rc__rc$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__rc__rc_ok$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__oe__oe$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__oe__oe_ok$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__invert_in$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__zero_a$67 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_1_logical_op__input_carry$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__invert_out$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__write_cr0$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__output_carry$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__is_32bit$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_1_logical_op__is_signed$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_1_logical_op__data_len$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_1_logical_op__insn$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_1_ra$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_1_rb$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_1_xer_so$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_1_divisor_neg$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_1_dividend_neg$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_1_dive_abs_ov32$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_1_dive_abs_ov64$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_1_div_by_zero$83 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_1_divisor_radicand$84 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_1_operation$85 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_1_quotient_root$86 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_1_root_times_radicand$87 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_1_compare_lhs$88 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_1_compare_rhs$89 + cell \pipe_middle_1 \pipe_middle_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_1_p_valid_i + connect \p_ready_o \pipe_middle_1_p_ready_o + connect \muxid \pipe_middle_1_muxid + connect \logical_op__insn_type \pipe_middle_1_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_1_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_1_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_1_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_1_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_1_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_1_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_1_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_1_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_1_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_1_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_1_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_1_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_1_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_1_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_1_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_1_logical_op__data_len + connect \logical_op__insn \pipe_middle_1_logical_op__insn + connect \ra \pipe_middle_1_ra + connect \rb \pipe_middle_1_rb + connect \xer_so \pipe_middle_1_xer_so + connect \divisor_neg \pipe_middle_1_divisor_neg + connect \dividend_neg \pipe_middle_1_dividend_neg + connect \dive_abs_ov32 \pipe_middle_1_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_1_dive_abs_ov64 + connect \div_by_zero \pipe_middle_1_div_by_zero + connect \divisor_radicand \pipe_middle_1_divisor_radicand + connect \operation \pipe_middle_1_operation + connect \quotient_root \pipe_middle_1_quotient_root + connect \root_times_radicand \pipe_middle_1_root_times_radicand + connect \compare_lhs \pipe_middle_1_compare_lhs + connect \compare_rhs \pipe_middle_1_compare_rhs + connect \n_valid_o \pipe_middle_1_n_valid_o + connect \n_ready_i \pipe_middle_1_n_ready_i + connect \muxid$1 \pipe_middle_1_muxid$57 + connect \logical_op__insn_type$2 \pipe_middle_1_logical_op__insn_type$58 + connect \logical_op__fn_unit$3 \pipe_middle_1_logical_op__fn_unit$59 + connect \logical_op__imm_data__imm$4 \pipe_middle_1_logical_op__imm_data__imm$60 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_1_logical_op__imm_data__imm_ok$61 + connect \logical_op__rc__rc$6 \pipe_middle_1_logical_op__rc__rc$62 + connect \logical_op__rc__rc_ok$7 \pipe_middle_1_logical_op__rc__rc_ok$63 + connect \logical_op__oe__oe$8 \pipe_middle_1_logical_op__oe__oe$64 + connect \logical_op__oe__oe_ok$9 \pipe_middle_1_logical_op__oe__oe_ok$65 + connect \logical_op__invert_in$10 \pipe_middle_1_logical_op__invert_in$66 + connect \logical_op__zero_a$11 \pipe_middle_1_logical_op__zero_a$67 + connect \logical_op__input_carry$12 \pipe_middle_1_logical_op__input_carry$68 + connect \logical_op__invert_out$13 \pipe_middle_1_logical_op__invert_out$69 + connect \logical_op__write_cr0$14 \pipe_middle_1_logical_op__write_cr0$70 + connect \logical_op__output_carry$15 \pipe_middle_1_logical_op__output_carry$71 + connect \logical_op__is_32bit$16 \pipe_middle_1_logical_op__is_32bit$72 + connect \logical_op__is_signed$17 \pipe_middle_1_logical_op__is_signed$73 + connect \logical_op__data_len$18 \pipe_middle_1_logical_op__data_len$74 + connect \logical_op__insn$19 \pipe_middle_1_logical_op__insn$75 + connect \ra$20 \pipe_middle_1_ra$76 + connect \rb$21 \pipe_middle_1_rb$77 + connect \xer_so$22 \pipe_middle_1_xer_so$78 + connect \divisor_neg$23 \pipe_middle_1_divisor_neg$79 + connect \dividend_neg$24 \pipe_middle_1_dividend_neg$80 + connect \dive_abs_ov32$25 \pipe_middle_1_dive_abs_ov32$81 + connect \dive_abs_ov64$26 \pipe_middle_1_dive_abs_ov64$82 + connect \div_by_zero$27 \pipe_middle_1_div_by_zero$83 + connect \divisor_radicand$28 \pipe_middle_1_divisor_radicand$84 + connect \operation$29 \pipe_middle_1_operation$85 + connect \quotient_root$30 \pipe_middle_1_quotient_root$86 + connect \root_times_radicand$31 \pipe_middle_1_root_times_radicand$87 + connect \compare_lhs$32 \pipe_middle_1_compare_lhs$88 + connect \compare_rhs$33 \pipe_middle_1_compare_rhs$89 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_2_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_2_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_2_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_2_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_2_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_2_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_2_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_2_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_2_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_2_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_2_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_2_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_2_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_2_muxid$90 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_2_logical_op__insn_type$91 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_2_logical_op__fn_unit$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_2_logical_op__imm_data__imm$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__imm_data__imm_ok$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__rc__rc$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__rc__rc_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__oe__oe$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__oe__oe_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__invert_in$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__zero_a$100 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_2_logical_op__input_carry$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__invert_out$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__write_cr0$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__output_carry$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__is_32bit$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_2_logical_op__is_signed$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_2_logical_op__data_len$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_2_logical_op__insn$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_2_ra$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_2_rb$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_2_xer_so$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_2_divisor_neg$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_2_dividend_neg$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_2_dive_abs_ov32$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_2_dive_abs_ov64$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_2_div_by_zero$116 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_2_divisor_radicand$117 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_2_operation$118 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_2_quotient_root$119 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_2_root_times_radicand$120 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_2_compare_lhs$121 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_2_compare_rhs$122 + cell \pipe_middle_2 \pipe_middle_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_2_p_valid_i + connect \p_ready_o \pipe_middle_2_p_ready_o + connect \muxid \pipe_middle_2_muxid + connect \logical_op__insn_type \pipe_middle_2_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_2_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_2_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_2_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_2_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_2_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_2_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_2_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_2_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_2_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_2_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_2_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_2_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_2_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_2_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_2_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_2_logical_op__data_len + connect \logical_op__insn \pipe_middle_2_logical_op__insn + connect \ra \pipe_middle_2_ra + connect \rb \pipe_middle_2_rb + connect \xer_so \pipe_middle_2_xer_so + connect \divisor_neg \pipe_middle_2_divisor_neg + connect \dividend_neg \pipe_middle_2_dividend_neg + connect \dive_abs_ov32 \pipe_middle_2_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_2_dive_abs_ov64 + connect \div_by_zero \pipe_middle_2_div_by_zero + connect \divisor_radicand \pipe_middle_2_divisor_radicand + connect \operation \pipe_middle_2_operation + connect \quotient_root \pipe_middle_2_quotient_root + connect \root_times_radicand \pipe_middle_2_root_times_radicand + connect \compare_lhs \pipe_middle_2_compare_lhs + connect \compare_rhs \pipe_middle_2_compare_rhs + connect \n_valid_o \pipe_middle_2_n_valid_o + connect \n_ready_i \pipe_middle_2_n_ready_i + connect \muxid$1 \pipe_middle_2_muxid$90 + connect \logical_op__insn_type$2 \pipe_middle_2_logical_op__insn_type$91 + connect \logical_op__fn_unit$3 \pipe_middle_2_logical_op__fn_unit$92 + connect \logical_op__imm_data__imm$4 \pipe_middle_2_logical_op__imm_data__imm$93 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_2_logical_op__imm_data__imm_ok$94 + connect \logical_op__rc__rc$6 \pipe_middle_2_logical_op__rc__rc$95 + connect \logical_op__rc__rc_ok$7 \pipe_middle_2_logical_op__rc__rc_ok$96 + connect \logical_op__oe__oe$8 \pipe_middle_2_logical_op__oe__oe$97 + connect \logical_op__oe__oe_ok$9 \pipe_middle_2_logical_op__oe__oe_ok$98 + connect \logical_op__invert_in$10 \pipe_middle_2_logical_op__invert_in$99 + connect \logical_op__zero_a$11 \pipe_middle_2_logical_op__zero_a$100 + connect \logical_op__input_carry$12 \pipe_middle_2_logical_op__input_carry$101 + connect \logical_op__invert_out$13 \pipe_middle_2_logical_op__invert_out$102 + connect \logical_op__write_cr0$14 \pipe_middle_2_logical_op__write_cr0$103 + connect \logical_op__output_carry$15 \pipe_middle_2_logical_op__output_carry$104 + connect \logical_op__is_32bit$16 \pipe_middle_2_logical_op__is_32bit$105 + connect \logical_op__is_signed$17 \pipe_middle_2_logical_op__is_signed$106 + connect \logical_op__data_len$18 \pipe_middle_2_logical_op__data_len$107 + connect \logical_op__insn$19 \pipe_middle_2_logical_op__insn$108 + connect \ra$20 \pipe_middle_2_ra$109 + connect \rb$21 \pipe_middle_2_rb$110 + connect \xer_so$22 \pipe_middle_2_xer_so$111 + connect \divisor_neg$23 \pipe_middle_2_divisor_neg$112 + connect \dividend_neg$24 \pipe_middle_2_dividend_neg$113 + connect \dive_abs_ov32$25 \pipe_middle_2_dive_abs_ov32$114 + connect \dive_abs_ov64$26 \pipe_middle_2_dive_abs_ov64$115 + connect \div_by_zero$27 \pipe_middle_2_div_by_zero$116 + connect \divisor_radicand$28 \pipe_middle_2_divisor_radicand$117 + connect \operation$29 \pipe_middle_2_operation$118 + connect \quotient_root$30 \pipe_middle_2_quotient_root$119 + connect \root_times_radicand$31 \pipe_middle_2_root_times_radicand$120 + connect \compare_lhs$32 \pipe_middle_2_compare_lhs$121 + connect \compare_rhs$33 \pipe_middle_2_compare_rhs$122 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_3_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_3_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_3_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_3_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_3_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_3_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_3_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_3_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_3_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_3_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_3_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_3_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_3_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_3_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_3_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_3_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_3_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_3_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_3_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_3_muxid$123 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_3_logical_op__insn_type$124 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_3_logical_op__fn_unit$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_3_logical_op__imm_data__imm$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__imm_data__imm_ok$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__rc__rc$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__rc__rc_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__oe__oe$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__oe__oe_ok$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__invert_in$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__zero_a$133 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_3_logical_op__input_carry$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__invert_out$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__write_cr0$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__output_carry$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__is_32bit$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_3_logical_op__is_signed$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_3_logical_op__data_len$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_3_logical_op__insn$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_3_ra$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_3_rb$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_3_xer_so$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_3_divisor_neg$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_3_dividend_neg$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_3_dive_abs_ov32$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_3_dive_abs_ov64$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_3_div_by_zero$149 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_3_divisor_radicand$150 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_3_operation$151 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_3_quotient_root$152 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_3_root_times_radicand$153 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_3_compare_lhs$154 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_3_compare_rhs$155 + cell \pipe_middle_3 \pipe_middle_3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_3_p_valid_i + connect \p_ready_o \pipe_middle_3_p_ready_o + connect \muxid \pipe_middle_3_muxid + connect \logical_op__insn_type \pipe_middle_3_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_3_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_3_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_3_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_3_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_3_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_3_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_3_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_3_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_3_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_3_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_3_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_3_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_3_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_3_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_3_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_3_logical_op__data_len + connect \logical_op__insn \pipe_middle_3_logical_op__insn + connect \ra \pipe_middle_3_ra + connect \rb \pipe_middle_3_rb + connect \xer_so \pipe_middle_3_xer_so + connect \divisor_neg \pipe_middle_3_divisor_neg + connect \dividend_neg \pipe_middle_3_dividend_neg + connect \dive_abs_ov32 \pipe_middle_3_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_3_dive_abs_ov64 + connect \div_by_zero \pipe_middle_3_div_by_zero + connect \divisor_radicand \pipe_middle_3_divisor_radicand + connect \operation \pipe_middle_3_operation + connect \quotient_root \pipe_middle_3_quotient_root + connect \root_times_radicand \pipe_middle_3_root_times_radicand + connect \compare_lhs \pipe_middle_3_compare_lhs + connect \compare_rhs \pipe_middle_3_compare_rhs + connect \n_valid_o \pipe_middle_3_n_valid_o + connect \n_ready_i \pipe_middle_3_n_ready_i + connect \muxid$1 \pipe_middle_3_muxid$123 + connect \logical_op__insn_type$2 \pipe_middle_3_logical_op__insn_type$124 + connect \logical_op__fn_unit$3 \pipe_middle_3_logical_op__fn_unit$125 + connect \logical_op__imm_data__imm$4 \pipe_middle_3_logical_op__imm_data__imm$126 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_3_logical_op__imm_data__imm_ok$127 + connect \logical_op__rc__rc$6 \pipe_middle_3_logical_op__rc__rc$128 + connect \logical_op__rc__rc_ok$7 \pipe_middle_3_logical_op__rc__rc_ok$129 + connect \logical_op__oe__oe$8 \pipe_middle_3_logical_op__oe__oe$130 + connect \logical_op__oe__oe_ok$9 \pipe_middle_3_logical_op__oe__oe_ok$131 + connect \logical_op__invert_in$10 \pipe_middle_3_logical_op__invert_in$132 + connect \logical_op__zero_a$11 \pipe_middle_3_logical_op__zero_a$133 + connect \logical_op__input_carry$12 \pipe_middle_3_logical_op__input_carry$134 + connect \logical_op__invert_out$13 \pipe_middle_3_logical_op__invert_out$135 + connect \logical_op__write_cr0$14 \pipe_middle_3_logical_op__write_cr0$136 + connect \logical_op__output_carry$15 \pipe_middle_3_logical_op__output_carry$137 + connect \logical_op__is_32bit$16 \pipe_middle_3_logical_op__is_32bit$138 + connect \logical_op__is_signed$17 \pipe_middle_3_logical_op__is_signed$139 + connect \logical_op__data_len$18 \pipe_middle_3_logical_op__data_len$140 + connect \logical_op__insn$19 \pipe_middle_3_logical_op__insn$141 + connect \ra$20 \pipe_middle_3_ra$142 + connect \rb$21 \pipe_middle_3_rb$143 + connect \xer_so$22 \pipe_middle_3_xer_so$144 + connect \divisor_neg$23 \pipe_middle_3_divisor_neg$145 + connect \dividend_neg$24 \pipe_middle_3_dividend_neg$146 + connect \dive_abs_ov32$25 \pipe_middle_3_dive_abs_ov32$147 + connect \dive_abs_ov64$26 \pipe_middle_3_dive_abs_ov64$148 + connect \div_by_zero$27 \pipe_middle_3_div_by_zero$149 + connect \divisor_radicand$28 \pipe_middle_3_divisor_radicand$150 + connect \operation$29 \pipe_middle_3_operation$151 + connect \quotient_root$30 \pipe_middle_3_quotient_root$152 + connect \root_times_radicand$31 \pipe_middle_3_root_times_radicand$153 + connect \compare_lhs$32 \pipe_middle_3_compare_lhs$154 + connect \compare_rhs$33 \pipe_middle_3_compare_rhs$155 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_4_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_4_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_4_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_4_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_4_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_4_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_4_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_4_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_4_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_4_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_4_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_4_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_4_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_4_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_4_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_4_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_4_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_4_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_4_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_4_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_4_muxid$156 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_4_logical_op__insn_type$157 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_4_logical_op__fn_unit$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_4_logical_op__imm_data__imm$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__imm_data__imm_ok$160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__rc__rc$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__rc__rc_ok$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__oe__oe$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__oe__oe_ok$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__invert_in$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__zero_a$166 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_4_logical_op__input_carry$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__invert_out$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__write_cr0$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__output_carry$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__is_32bit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_4_logical_op__is_signed$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_4_logical_op__data_len$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_4_logical_op__insn$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_4_ra$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_4_rb$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_4_xer_so$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_4_divisor_neg$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_4_dividend_neg$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_4_dive_abs_ov32$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_4_dive_abs_ov64$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_4_div_by_zero$182 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_4_divisor_radicand$183 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_4_operation$184 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_4_quotient_root$185 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_4_root_times_radicand$186 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_4_compare_lhs$187 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_4_compare_rhs$188 + cell \pipe_middle_4 \pipe_middle_4 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_4_p_valid_i + connect \p_ready_o \pipe_middle_4_p_ready_o + connect \muxid \pipe_middle_4_muxid + connect \logical_op__insn_type \pipe_middle_4_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_4_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_4_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_4_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_4_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_4_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_4_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_4_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_4_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_4_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_4_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_4_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_4_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_4_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_4_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_4_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_4_logical_op__data_len + connect \logical_op__insn \pipe_middle_4_logical_op__insn + connect \ra \pipe_middle_4_ra + connect \rb \pipe_middle_4_rb + connect \xer_so \pipe_middle_4_xer_so + connect \divisor_neg \pipe_middle_4_divisor_neg + connect \dividend_neg \pipe_middle_4_dividend_neg + connect \dive_abs_ov32 \pipe_middle_4_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_4_dive_abs_ov64 + connect \div_by_zero \pipe_middle_4_div_by_zero + connect \divisor_radicand \pipe_middle_4_divisor_radicand + connect \operation \pipe_middle_4_operation + connect \quotient_root \pipe_middle_4_quotient_root + connect \root_times_radicand \pipe_middle_4_root_times_radicand + connect \compare_lhs \pipe_middle_4_compare_lhs + connect \compare_rhs \pipe_middle_4_compare_rhs + connect \n_valid_o \pipe_middle_4_n_valid_o + connect \n_ready_i \pipe_middle_4_n_ready_i + connect \muxid$1 \pipe_middle_4_muxid$156 + connect \logical_op__insn_type$2 \pipe_middle_4_logical_op__insn_type$157 + connect \logical_op__fn_unit$3 \pipe_middle_4_logical_op__fn_unit$158 + connect \logical_op__imm_data__imm$4 \pipe_middle_4_logical_op__imm_data__imm$159 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_4_logical_op__imm_data__imm_ok$160 + connect \logical_op__rc__rc$6 \pipe_middle_4_logical_op__rc__rc$161 + connect \logical_op__rc__rc_ok$7 \pipe_middle_4_logical_op__rc__rc_ok$162 + connect \logical_op__oe__oe$8 \pipe_middle_4_logical_op__oe__oe$163 + connect \logical_op__oe__oe_ok$9 \pipe_middle_4_logical_op__oe__oe_ok$164 + connect \logical_op__invert_in$10 \pipe_middle_4_logical_op__invert_in$165 + connect \logical_op__zero_a$11 \pipe_middle_4_logical_op__zero_a$166 + connect \logical_op__input_carry$12 \pipe_middle_4_logical_op__input_carry$167 + connect \logical_op__invert_out$13 \pipe_middle_4_logical_op__invert_out$168 + connect \logical_op__write_cr0$14 \pipe_middle_4_logical_op__write_cr0$169 + connect \logical_op__output_carry$15 \pipe_middle_4_logical_op__output_carry$170 + connect \logical_op__is_32bit$16 \pipe_middle_4_logical_op__is_32bit$171 + connect \logical_op__is_signed$17 \pipe_middle_4_logical_op__is_signed$172 + connect \logical_op__data_len$18 \pipe_middle_4_logical_op__data_len$173 + connect \logical_op__insn$19 \pipe_middle_4_logical_op__insn$174 + connect \ra$20 \pipe_middle_4_ra$175 + connect \rb$21 \pipe_middle_4_rb$176 + connect \xer_so$22 \pipe_middle_4_xer_so$177 + connect \divisor_neg$23 \pipe_middle_4_divisor_neg$178 + connect \dividend_neg$24 \pipe_middle_4_dividend_neg$179 + connect \dive_abs_ov32$25 \pipe_middle_4_dive_abs_ov32$180 + connect \dive_abs_ov64$26 \pipe_middle_4_dive_abs_ov64$181 + connect \div_by_zero$27 \pipe_middle_4_div_by_zero$182 + connect \divisor_radicand$28 \pipe_middle_4_divisor_radicand$183 + connect \operation$29 \pipe_middle_4_operation$184 + connect \quotient_root$30 \pipe_middle_4_quotient_root$185 + connect \root_times_radicand$31 \pipe_middle_4_root_times_radicand$186 + connect \compare_lhs$32 \pipe_middle_4_compare_lhs$187 + connect \compare_rhs$33 \pipe_middle_4_compare_rhs$188 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_5_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_5_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_5_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_5_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_5_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_5_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_5_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_5_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_5_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_5_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_5_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_5_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_5_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_5_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_5_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_5_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_5_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_5_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_5_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_5_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_5_muxid$189 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_5_logical_op__insn_type$190 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_5_logical_op__fn_unit$191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_5_logical_op__imm_data__imm$192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__imm_data__imm_ok$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__rc__rc$194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__rc__rc_ok$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__oe__oe$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__oe__oe_ok$197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__invert_in$198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__zero_a$199 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_5_logical_op__input_carry$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__invert_out$201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__write_cr0$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__output_carry$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__is_32bit$204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_5_logical_op__is_signed$205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_5_logical_op__data_len$206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_5_logical_op__insn$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_5_ra$208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_5_rb$209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_5_xer_so$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_5_divisor_neg$211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_5_dividend_neg$212 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_5_dive_abs_ov32$213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_5_dive_abs_ov64$214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_5_div_by_zero$215 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_5_divisor_radicand$216 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_5_operation$217 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_5_quotient_root$218 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_5_root_times_radicand$219 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_5_compare_lhs$220 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_5_compare_rhs$221 + cell \pipe_middle_5 \pipe_middle_5 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_5_p_valid_i + connect \p_ready_o \pipe_middle_5_p_ready_o + connect \muxid \pipe_middle_5_muxid + connect \logical_op__insn_type \pipe_middle_5_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_5_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_5_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_5_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_5_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_5_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_5_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_5_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_5_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_5_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_5_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_5_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_5_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_5_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_5_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_5_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_5_logical_op__data_len + connect \logical_op__insn \pipe_middle_5_logical_op__insn + connect \ra \pipe_middle_5_ra + connect \rb \pipe_middle_5_rb + connect \xer_so \pipe_middle_5_xer_so + connect \divisor_neg \pipe_middle_5_divisor_neg + connect \dividend_neg \pipe_middle_5_dividend_neg + connect \dive_abs_ov32 \pipe_middle_5_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_5_dive_abs_ov64 + connect \div_by_zero \pipe_middle_5_div_by_zero + connect \divisor_radicand \pipe_middle_5_divisor_radicand + connect \operation \pipe_middle_5_operation + connect \quotient_root \pipe_middle_5_quotient_root + connect \root_times_radicand \pipe_middle_5_root_times_radicand + connect \compare_lhs \pipe_middle_5_compare_lhs + connect \compare_rhs \pipe_middle_5_compare_rhs + connect \n_valid_o \pipe_middle_5_n_valid_o + connect \n_ready_i \pipe_middle_5_n_ready_i + connect \muxid$1 \pipe_middle_5_muxid$189 + connect \logical_op__insn_type$2 \pipe_middle_5_logical_op__insn_type$190 + connect \logical_op__fn_unit$3 \pipe_middle_5_logical_op__fn_unit$191 + connect \logical_op__imm_data__imm$4 \pipe_middle_5_logical_op__imm_data__imm$192 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_5_logical_op__imm_data__imm_ok$193 + connect \logical_op__rc__rc$6 \pipe_middle_5_logical_op__rc__rc$194 + connect \logical_op__rc__rc_ok$7 \pipe_middle_5_logical_op__rc__rc_ok$195 + connect \logical_op__oe__oe$8 \pipe_middle_5_logical_op__oe__oe$196 + connect \logical_op__oe__oe_ok$9 \pipe_middle_5_logical_op__oe__oe_ok$197 + connect \logical_op__invert_in$10 \pipe_middle_5_logical_op__invert_in$198 + connect \logical_op__zero_a$11 \pipe_middle_5_logical_op__zero_a$199 + connect \logical_op__input_carry$12 \pipe_middle_5_logical_op__input_carry$200 + connect \logical_op__invert_out$13 \pipe_middle_5_logical_op__invert_out$201 + connect \logical_op__write_cr0$14 \pipe_middle_5_logical_op__write_cr0$202 + connect \logical_op__output_carry$15 \pipe_middle_5_logical_op__output_carry$203 + connect \logical_op__is_32bit$16 \pipe_middle_5_logical_op__is_32bit$204 + connect \logical_op__is_signed$17 \pipe_middle_5_logical_op__is_signed$205 + connect \logical_op__data_len$18 \pipe_middle_5_logical_op__data_len$206 + connect \logical_op__insn$19 \pipe_middle_5_logical_op__insn$207 + connect \ra$20 \pipe_middle_5_ra$208 + connect \rb$21 \pipe_middle_5_rb$209 + connect \xer_so$22 \pipe_middle_5_xer_so$210 + connect \divisor_neg$23 \pipe_middle_5_divisor_neg$211 + connect \dividend_neg$24 \pipe_middle_5_dividend_neg$212 + connect \dive_abs_ov32$25 \pipe_middle_5_dive_abs_ov32$213 + connect \dive_abs_ov64$26 \pipe_middle_5_dive_abs_ov64$214 + connect \div_by_zero$27 \pipe_middle_5_div_by_zero$215 + connect \divisor_radicand$28 \pipe_middle_5_divisor_radicand$216 + connect \operation$29 \pipe_middle_5_operation$217 + connect \quotient_root$30 \pipe_middle_5_quotient_root$218 + connect \root_times_radicand$31 \pipe_middle_5_root_times_radicand$219 + connect \compare_lhs$32 \pipe_middle_5_compare_lhs$220 + connect \compare_rhs$33 \pipe_middle_5_compare_rhs$221 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_6_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_6_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_6_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_6_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_6_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_6_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_6_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_6_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_6_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_6_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_6_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_6_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_6_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_6_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_6_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_6_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_6_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_6_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_6_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_6_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_6_muxid$222 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_6_logical_op__insn_type$223 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_6_logical_op__fn_unit$224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_6_logical_op__imm_data__imm$225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__imm_data__imm_ok$226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__rc__rc$227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__rc__rc_ok$228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__oe__oe$229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__oe__oe_ok$230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__invert_in$231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__zero_a$232 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_6_logical_op__input_carry$233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__invert_out$234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__write_cr0$235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__output_carry$236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__is_32bit$237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_6_logical_op__is_signed$238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_6_logical_op__data_len$239 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_6_logical_op__insn$240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_6_ra$241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_6_rb$242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_6_xer_so$243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_6_divisor_neg$244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_6_dividend_neg$245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_6_dive_abs_ov32$246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_6_dive_abs_ov64$247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_6_div_by_zero$248 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_6_divisor_radicand$249 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_6_operation$250 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_6_quotient_root$251 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_6_root_times_radicand$252 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_6_compare_lhs$253 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_6_compare_rhs$254 + cell \pipe_middle_6 \pipe_middle_6 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_6_p_valid_i + connect \p_ready_o \pipe_middle_6_p_ready_o + connect \muxid \pipe_middle_6_muxid + connect \logical_op__insn_type \pipe_middle_6_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_6_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_6_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_6_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_6_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_6_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_6_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_6_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_6_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_6_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_6_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_6_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_6_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_6_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_6_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_6_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_6_logical_op__data_len + connect \logical_op__insn \pipe_middle_6_logical_op__insn + connect \ra \pipe_middle_6_ra + connect \rb \pipe_middle_6_rb + connect \xer_so \pipe_middle_6_xer_so + connect \divisor_neg \pipe_middle_6_divisor_neg + connect \dividend_neg \pipe_middle_6_dividend_neg + connect \dive_abs_ov32 \pipe_middle_6_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_6_dive_abs_ov64 + connect \div_by_zero \pipe_middle_6_div_by_zero + connect \divisor_radicand \pipe_middle_6_divisor_radicand + connect \operation \pipe_middle_6_operation + connect \quotient_root \pipe_middle_6_quotient_root + connect \root_times_radicand \pipe_middle_6_root_times_radicand + connect \compare_lhs \pipe_middle_6_compare_lhs + connect \compare_rhs \pipe_middle_6_compare_rhs + connect \n_valid_o \pipe_middle_6_n_valid_o + connect \n_ready_i \pipe_middle_6_n_ready_i + connect \muxid$1 \pipe_middle_6_muxid$222 + connect \logical_op__insn_type$2 \pipe_middle_6_logical_op__insn_type$223 + connect \logical_op__fn_unit$3 \pipe_middle_6_logical_op__fn_unit$224 + connect \logical_op__imm_data__imm$4 \pipe_middle_6_logical_op__imm_data__imm$225 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_6_logical_op__imm_data__imm_ok$226 + connect \logical_op__rc__rc$6 \pipe_middle_6_logical_op__rc__rc$227 + connect \logical_op__rc__rc_ok$7 \pipe_middle_6_logical_op__rc__rc_ok$228 + connect \logical_op__oe__oe$8 \pipe_middle_6_logical_op__oe__oe$229 + connect \logical_op__oe__oe_ok$9 \pipe_middle_6_logical_op__oe__oe_ok$230 + connect \logical_op__invert_in$10 \pipe_middle_6_logical_op__invert_in$231 + connect \logical_op__zero_a$11 \pipe_middle_6_logical_op__zero_a$232 + connect \logical_op__input_carry$12 \pipe_middle_6_logical_op__input_carry$233 + connect \logical_op__invert_out$13 \pipe_middle_6_logical_op__invert_out$234 + connect \logical_op__write_cr0$14 \pipe_middle_6_logical_op__write_cr0$235 + connect \logical_op__output_carry$15 \pipe_middle_6_logical_op__output_carry$236 + connect \logical_op__is_32bit$16 \pipe_middle_6_logical_op__is_32bit$237 + connect \logical_op__is_signed$17 \pipe_middle_6_logical_op__is_signed$238 + connect \logical_op__data_len$18 \pipe_middle_6_logical_op__data_len$239 + connect \logical_op__insn$19 \pipe_middle_6_logical_op__insn$240 + connect \ra$20 \pipe_middle_6_ra$241 + connect \rb$21 \pipe_middle_6_rb$242 + connect \xer_so$22 \pipe_middle_6_xer_so$243 + connect \divisor_neg$23 \pipe_middle_6_divisor_neg$244 + connect \dividend_neg$24 \pipe_middle_6_dividend_neg$245 + connect \dive_abs_ov32$25 \pipe_middle_6_dive_abs_ov32$246 + connect \dive_abs_ov64$26 \pipe_middle_6_dive_abs_ov64$247 + connect \div_by_zero$27 \pipe_middle_6_div_by_zero$248 + connect \divisor_radicand$28 \pipe_middle_6_divisor_radicand$249 + connect \operation$29 \pipe_middle_6_operation$250 + connect \quotient_root$30 \pipe_middle_6_quotient_root$251 + connect \root_times_radicand$31 \pipe_middle_6_root_times_radicand$252 + connect \compare_lhs$32 \pipe_middle_6_compare_lhs$253 + connect \compare_rhs$33 \pipe_middle_6_compare_rhs$254 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_7_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_7_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_7_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_7_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_7_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_7_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_7_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_7_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_7_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_7_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_7_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_7_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_7_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_7_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_7_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_7_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_7_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_7_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_7_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_7_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_7_muxid$255 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_7_logical_op__insn_type$256 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_7_logical_op__fn_unit$257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_7_logical_op__imm_data__imm$258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__imm_data__imm_ok$259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__rc__rc$260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__rc__rc_ok$261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__oe__oe$262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__oe__oe_ok$263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__invert_in$264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__zero_a$265 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_7_logical_op__input_carry$266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__invert_out$267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__write_cr0$268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__output_carry$269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__is_32bit$270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_7_logical_op__is_signed$271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_7_logical_op__data_len$272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_7_logical_op__insn$273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_7_ra$274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_7_rb$275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_7_xer_so$276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_7_divisor_neg$277 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_7_dividend_neg$278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_7_dive_abs_ov32$279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_7_dive_abs_ov64$280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_7_div_by_zero$281 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_7_divisor_radicand$282 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_7_operation$283 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_7_quotient_root$284 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_7_root_times_radicand$285 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_7_compare_lhs$286 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_7_compare_rhs$287 + cell \pipe_middle_7 \pipe_middle_7 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_7_p_valid_i + connect \p_ready_o \pipe_middle_7_p_ready_o + connect \muxid \pipe_middle_7_muxid + connect \logical_op__insn_type \pipe_middle_7_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_7_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_7_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_7_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_7_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_7_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_7_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_7_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_7_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_7_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_7_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_7_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_7_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_7_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_7_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_7_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_7_logical_op__data_len + connect \logical_op__insn \pipe_middle_7_logical_op__insn + connect \ra \pipe_middle_7_ra + connect \rb \pipe_middle_7_rb + connect \xer_so \pipe_middle_7_xer_so + connect \divisor_neg \pipe_middle_7_divisor_neg + connect \dividend_neg \pipe_middle_7_dividend_neg + connect \dive_abs_ov32 \pipe_middle_7_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_7_dive_abs_ov64 + connect \div_by_zero \pipe_middle_7_div_by_zero + connect \divisor_radicand \pipe_middle_7_divisor_radicand + connect \operation \pipe_middle_7_operation + connect \quotient_root \pipe_middle_7_quotient_root + connect \root_times_radicand \pipe_middle_7_root_times_radicand + connect \compare_lhs \pipe_middle_7_compare_lhs + connect \compare_rhs \pipe_middle_7_compare_rhs + connect \n_valid_o \pipe_middle_7_n_valid_o + connect \n_ready_i \pipe_middle_7_n_ready_i + connect \muxid$1 \pipe_middle_7_muxid$255 + connect \logical_op__insn_type$2 \pipe_middle_7_logical_op__insn_type$256 + connect \logical_op__fn_unit$3 \pipe_middle_7_logical_op__fn_unit$257 + connect \logical_op__imm_data__imm$4 \pipe_middle_7_logical_op__imm_data__imm$258 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_7_logical_op__imm_data__imm_ok$259 + connect \logical_op__rc__rc$6 \pipe_middle_7_logical_op__rc__rc$260 + connect \logical_op__rc__rc_ok$7 \pipe_middle_7_logical_op__rc__rc_ok$261 + connect \logical_op__oe__oe$8 \pipe_middle_7_logical_op__oe__oe$262 + connect \logical_op__oe__oe_ok$9 \pipe_middle_7_logical_op__oe__oe_ok$263 + connect \logical_op__invert_in$10 \pipe_middle_7_logical_op__invert_in$264 + connect \logical_op__zero_a$11 \pipe_middle_7_logical_op__zero_a$265 + connect \logical_op__input_carry$12 \pipe_middle_7_logical_op__input_carry$266 + connect \logical_op__invert_out$13 \pipe_middle_7_logical_op__invert_out$267 + connect \logical_op__write_cr0$14 \pipe_middle_7_logical_op__write_cr0$268 + connect \logical_op__output_carry$15 \pipe_middle_7_logical_op__output_carry$269 + connect \logical_op__is_32bit$16 \pipe_middle_7_logical_op__is_32bit$270 + connect \logical_op__is_signed$17 \pipe_middle_7_logical_op__is_signed$271 + connect \logical_op__data_len$18 \pipe_middle_7_logical_op__data_len$272 + connect \logical_op__insn$19 \pipe_middle_7_logical_op__insn$273 + connect \ra$20 \pipe_middle_7_ra$274 + connect \rb$21 \pipe_middle_7_rb$275 + connect \xer_so$22 \pipe_middle_7_xer_so$276 + connect \divisor_neg$23 \pipe_middle_7_divisor_neg$277 + connect \dividend_neg$24 \pipe_middle_7_dividend_neg$278 + connect \dive_abs_ov32$25 \pipe_middle_7_dive_abs_ov32$279 + connect \dive_abs_ov64$26 \pipe_middle_7_dive_abs_ov64$280 + connect \div_by_zero$27 \pipe_middle_7_div_by_zero$281 + connect \divisor_radicand$28 \pipe_middle_7_divisor_radicand$282 + connect \operation$29 \pipe_middle_7_operation$283 + connect \quotient_root$30 \pipe_middle_7_quotient_root$284 + connect \root_times_radicand$31 \pipe_middle_7_root_times_radicand$285 + connect \compare_lhs$32 \pipe_middle_7_compare_lhs$286 + connect \compare_rhs$33 \pipe_middle_7_compare_rhs$287 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_8_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_8_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_8_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_8_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_8_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_8_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_8_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_8_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_8_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_8_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_8_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_8_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_8_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_8_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_8_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_8_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_8_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_8_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_8_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_8_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_8_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_8_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_8_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_8_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_8_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_8_muxid$288 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_8_logical_op__insn_type$289 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_8_logical_op__fn_unit$290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_8_logical_op__imm_data__imm$291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__imm_data__imm_ok$292 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__rc__rc$293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__rc__rc_ok$294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__oe__oe$295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__oe__oe_ok$296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__invert_in$297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__zero_a$298 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_8_logical_op__input_carry$299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__invert_out$300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__write_cr0$301 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__output_carry$302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__is_32bit$303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_8_logical_op__is_signed$304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_8_logical_op__data_len$305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_8_logical_op__insn$306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_8_ra$307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_8_rb$308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_8_xer_so$309 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_8_divisor_neg$310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_8_dividend_neg$311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_8_dive_abs_ov32$312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_8_dive_abs_ov64$313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_8_div_by_zero$314 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_8_divisor_radicand$315 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_8_operation$316 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_8_quotient_root$317 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_8_root_times_radicand$318 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_8_compare_lhs$319 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_8_compare_rhs$320 + cell \pipe_middle_8 \pipe_middle_8 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_8_p_valid_i + connect \p_ready_o \pipe_middle_8_p_ready_o + connect \muxid \pipe_middle_8_muxid + connect \logical_op__insn_type \pipe_middle_8_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_8_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_8_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_8_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_8_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_8_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_8_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_8_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_8_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_8_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_8_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_8_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_8_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_8_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_8_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_8_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_8_logical_op__data_len + connect \logical_op__insn \pipe_middle_8_logical_op__insn + connect \ra \pipe_middle_8_ra + connect \rb \pipe_middle_8_rb + connect \xer_so \pipe_middle_8_xer_so + connect \divisor_neg \pipe_middle_8_divisor_neg + connect \dividend_neg \pipe_middle_8_dividend_neg + connect \dive_abs_ov32 \pipe_middle_8_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_8_dive_abs_ov64 + connect \div_by_zero \pipe_middle_8_div_by_zero + connect \divisor_radicand \pipe_middle_8_divisor_radicand + connect \operation \pipe_middle_8_operation + connect \quotient_root \pipe_middle_8_quotient_root + connect \root_times_radicand \pipe_middle_8_root_times_radicand + connect \compare_lhs \pipe_middle_8_compare_lhs + connect \compare_rhs \pipe_middle_8_compare_rhs + connect \n_valid_o \pipe_middle_8_n_valid_o + connect \n_ready_i \pipe_middle_8_n_ready_i + connect \muxid$1 \pipe_middle_8_muxid$288 + connect \logical_op__insn_type$2 \pipe_middle_8_logical_op__insn_type$289 + connect \logical_op__fn_unit$3 \pipe_middle_8_logical_op__fn_unit$290 + connect \logical_op__imm_data__imm$4 \pipe_middle_8_logical_op__imm_data__imm$291 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_8_logical_op__imm_data__imm_ok$292 + connect \logical_op__rc__rc$6 \pipe_middle_8_logical_op__rc__rc$293 + connect \logical_op__rc__rc_ok$7 \pipe_middle_8_logical_op__rc__rc_ok$294 + connect \logical_op__oe__oe$8 \pipe_middle_8_logical_op__oe__oe$295 + connect \logical_op__oe__oe_ok$9 \pipe_middle_8_logical_op__oe__oe_ok$296 + connect \logical_op__invert_in$10 \pipe_middle_8_logical_op__invert_in$297 + connect \logical_op__zero_a$11 \pipe_middle_8_logical_op__zero_a$298 + connect \logical_op__input_carry$12 \pipe_middle_8_logical_op__input_carry$299 + connect \logical_op__invert_out$13 \pipe_middle_8_logical_op__invert_out$300 + connect \logical_op__write_cr0$14 \pipe_middle_8_logical_op__write_cr0$301 + connect \logical_op__output_carry$15 \pipe_middle_8_logical_op__output_carry$302 + connect \logical_op__is_32bit$16 \pipe_middle_8_logical_op__is_32bit$303 + connect \logical_op__is_signed$17 \pipe_middle_8_logical_op__is_signed$304 + connect \logical_op__data_len$18 \pipe_middle_8_logical_op__data_len$305 + connect \logical_op__insn$19 \pipe_middle_8_logical_op__insn$306 + connect \ra$20 \pipe_middle_8_ra$307 + connect \rb$21 \pipe_middle_8_rb$308 + connect \xer_so$22 \pipe_middle_8_xer_so$309 + connect \divisor_neg$23 \pipe_middle_8_divisor_neg$310 + connect \dividend_neg$24 \pipe_middle_8_dividend_neg$311 + connect \dive_abs_ov32$25 \pipe_middle_8_dive_abs_ov32$312 + connect \dive_abs_ov64$26 \pipe_middle_8_dive_abs_ov64$313 + connect \div_by_zero$27 \pipe_middle_8_div_by_zero$314 + connect \divisor_radicand$28 \pipe_middle_8_divisor_radicand$315 + connect \operation$29 \pipe_middle_8_operation$316 + connect \quotient_root$30 \pipe_middle_8_quotient_root$317 + connect \root_times_radicand$31 \pipe_middle_8_root_times_radicand$318 + connect \compare_lhs$32 \pipe_middle_8_compare_lhs$319 + connect \compare_rhs$33 \pipe_middle_8_compare_rhs$320 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_9_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_9_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_9_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_9_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_9_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_9_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_9_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_9_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_9_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_9_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_9_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_9_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_9_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_9_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_9_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_9_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_9_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_9_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_9_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_9_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_9_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_9_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_9_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_9_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_9_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_9_muxid$321 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_9_logical_op__insn_type$322 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_9_logical_op__fn_unit$323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_9_logical_op__imm_data__imm$324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__imm_data__imm_ok$325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__rc__rc$326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__rc__rc_ok$327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__oe__oe$328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__oe__oe_ok$329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__invert_in$330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__zero_a$331 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_9_logical_op__input_carry$332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__invert_out$333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__write_cr0$334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__output_carry$335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__is_32bit$336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_9_logical_op__is_signed$337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_9_logical_op__data_len$338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_9_logical_op__insn$339 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_9_ra$340 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_9_rb$341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_9_xer_so$342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_9_divisor_neg$343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_9_dividend_neg$344 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_9_dive_abs_ov32$345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_9_dive_abs_ov64$346 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_9_div_by_zero$347 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_9_divisor_radicand$348 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_9_operation$349 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_9_quotient_root$350 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_9_root_times_radicand$351 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_9_compare_lhs$352 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_9_compare_rhs$353 + cell \pipe_middle_9 \pipe_middle_9 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_9_p_valid_i + connect \p_ready_o \pipe_middle_9_p_ready_o + connect \muxid \pipe_middle_9_muxid + connect \logical_op__insn_type \pipe_middle_9_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_9_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_9_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_9_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_9_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_9_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_9_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_9_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_9_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_9_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_9_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_9_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_9_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_9_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_9_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_9_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_9_logical_op__data_len + connect \logical_op__insn \pipe_middle_9_logical_op__insn + connect \ra \pipe_middle_9_ra + connect \rb \pipe_middle_9_rb + connect \xer_so \pipe_middle_9_xer_so + connect \divisor_neg \pipe_middle_9_divisor_neg + connect \dividend_neg \pipe_middle_9_dividend_neg + connect \dive_abs_ov32 \pipe_middle_9_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_9_dive_abs_ov64 + connect \div_by_zero \pipe_middle_9_div_by_zero + connect \divisor_radicand \pipe_middle_9_divisor_radicand + connect \operation \pipe_middle_9_operation + connect \quotient_root \pipe_middle_9_quotient_root + connect \root_times_radicand \pipe_middle_9_root_times_radicand + connect \compare_lhs \pipe_middle_9_compare_lhs + connect \compare_rhs \pipe_middle_9_compare_rhs + connect \n_valid_o \pipe_middle_9_n_valid_o + connect \n_ready_i \pipe_middle_9_n_ready_i + connect \muxid$1 \pipe_middle_9_muxid$321 + connect \logical_op__insn_type$2 \pipe_middle_9_logical_op__insn_type$322 + connect \logical_op__fn_unit$3 \pipe_middle_9_logical_op__fn_unit$323 + connect \logical_op__imm_data__imm$4 \pipe_middle_9_logical_op__imm_data__imm$324 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_9_logical_op__imm_data__imm_ok$325 + connect \logical_op__rc__rc$6 \pipe_middle_9_logical_op__rc__rc$326 + connect \logical_op__rc__rc_ok$7 \pipe_middle_9_logical_op__rc__rc_ok$327 + connect \logical_op__oe__oe$8 \pipe_middle_9_logical_op__oe__oe$328 + connect \logical_op__oe__oe_ok$9 \pipe_middle_9_logical_op__oe__oe_ok$329 + connect \logical_op__invert_in$10 \pipe_middle_9_logical_op__invert_in$330 + connect \logical_op__zero_a$11 \pipe_middle_9_logical_op__zero_a$331 + connect \logical_op__input_carry$12 \pipe_middle_9_logical_op__input_carry$332 + connect \logical_op__invert_out$13 \pipe_middle_9_logical_op__invert_out$333 + connect \logical_op__write_cr0$14 \pipe_middle_9_logical_op__write_cr0$334 + connect \logical_op__output_carry$15 \pipe_middle_9_logical_op__output_carry$335 + connect \logical_op__is_32bit$16 \pipe_middle_9_logical_op__is_32bit$336 + connect \logical_op__is_signed$17 \pipe_middle_9_logical_op__is_signed$337 + connect \logical_op__data_len$18 \pipe_middle_9_logical_op__data_len$338 + connect \logical_op__insn$19 \pipe_middle_9_logical_op__insn$339 + connect \ra$20 \pipe_middle_9_ra$340 + connect \rb$21 \pipe_middle_9_rb$341 + connect \xer_so$22 \pipe_middle_9_xer_so$342 + connect \divisor_neg$23 \pipe_middle_9_divisor_neg$343 + connect \dividend_neg$24 \pipe_middle_9_dividend_neg$344 + connect \dive_abs_ov32$25 \pipe_middle_9_dive_abs_ov32$345 + connect \dive_abs_ov64$26 \pipe_middle_9_dive_abs_ov64$346 + connect \div_by_zero$27 \pipe_middle_9_div_by_zero$347 + connect \divisor_radicand$28 \pipe_middle_9_divisor_radicand$348 + connect \operation$29 \pipe_middle_9_operation$349 + connect \quotient_root$30 \pipe_middle_9_quotient_root$350 + connect \root_times_radicand$31 \pipe_middle_9_root_times_radicand$351 + connect \compare_lhs$32 \pipe_middle_9_compare_lhs$352 + connect \compare_rhs$33 \pipe_middle_9_compare_rhs$353 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_10_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_10_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_10_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_10_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_10_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_10_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_10_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_10_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_10_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_10_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_10_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_10_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_10_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_10_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_10_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_10_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_10_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_10_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_10_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_10_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_10_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_10_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_10_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_10_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_10_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_10_muxid$354 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_10_logical_op__insn_type$355 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_10_logical_op__fn_unit$356 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_10_logical_op__imm_data__imm$357 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__imm_data__imm_ok$358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__rc__rc$359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__rc__rc_ok$360 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__oe__oe$361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__oe__oe_ok$362 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__invert_in$363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__zero_a$364 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_10_logical_op__input_carry$365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__invert_out$366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__write_cr0$367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__output_carry$368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__is_32bit$369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_10_logical_op__is_signed$370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_10_logical_op__data_len$371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_10_logical_op__insn$372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_10_ra$373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_10_rb$374 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_10_xer_so$375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_10_divisor_neg$376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_10_dividend_neg$377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_10_dive_abs_ov32$378 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_10_dive_abs_ov64$379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_10_div_by_zero$380 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_10_divisor_radicand$381 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_10_operation$382 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_10_quotient_root$383 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_10_root_times_radicand$384 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_10_compare_lhs$385 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_10_compare_rhs$386 + cell \pipe_middle_10 \pipe_middle_10 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_10_p_valid_i + connect \p_ready_o \pipe_middle_10_p_ready_o + connect \muxid \pipe_middle_10_muxid + connect \logical_op__insn_type \pipe_middle_10_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_10_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_10_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_10_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_10_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_10_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_10_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_10_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_10_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_10_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_10_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_10_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_10_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_10_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_10_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_10_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_10_logical_op__data_len + connect \logical_op__insn \pipe_middle_10_logical_op__insn + connect \ra \pipe_middle_10_ra + connect \rb \pipe_middle_10_rb + connect \xer_so \pipe_middle_10_xer_so + connect \divisor_neg \pipe_middle_10_divisor_neg + connect \dividend_neg \pipe_middle_10_dividend_neg + connect \dive_abs_ov32 \pipe_middle_10_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_10_dive_abs_ov64 + connect \div_by_zero \pipe_middle_10_div_by_zero + connect \divisor_radicand \pipe_middle_10_divisor_radicand + connect \operation \pipe_middle_10_operation + connect \quotient_root \pipe_middle_10_quotient_root + connect \root_times_radicand \pipe_middle_10_root_times_radicand + connect \compare_lhs \pipe_middle_10_compare_lhs + connect \compare_rhs \pipe_middle_10_compare_rhs + connect \n_valid_o \pipe_middle_10_n_valid_o + connect \n_ready_i \pipe_middle_10_n_ready_i + connect \muxid$1 \pipe_middle_10_muxid$354 + connect \logical_op__insn_type$2 \pipe_middle_10_logical_op__insn_type$355 + connect \logical_op__fn_unit$3 \pipe_middle_10_logical_op__fn_unit$356 + connect \logical_op__imm_data__imm$4 \pipe_middle_10_logical_op__imm_data__imm$357 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_10_logical_op__imm_data__imm_ok$358 + connect \logical_op__rc__rc$6 \pipe_middle_10_logical_op__rc__rc$359 + connect \logical_op__rc__rc_ok$7 \pipe_middle_10_logical_op__rc__rc_ok$360 + connect \logical_op__oe__oe$8 \pipe_middle_10_logical_op__oe__oe$361 + connect \logical_op__oe__oe_ok$9 \pipe_middle_10_logical_op__oe__oe_ok$362 + connect \logical_op__invert_in$10 \pipe_middle_10_logical_op__invert_in$363 + connect \logical_op__zero_a$11 \pipe_middle_10_logical_op__zero_a$364 + connect \logical_op__input_carry$12 \pipe_middle_10_logical_op__input_carry$365 + connect \logical_op__invert_out$13 \pipe_middle_10_logical_op__invert_out$366 + connect \logical_op__write_cr0$14 \pipe_middle_10_logical_op__write_cr0$367 + connect \logical_op__output_carry$15 \pipe_middle_10_logical_op__output_carry$368 + connect \logical_op__is_32bit$16 \pipe_middle_10_logical_op__is_32bit$369 + connect \logical_op__is_signed$17 \pipe_middle_10_logical_op__is_signed$370 + connect \logical_op__data_len$18 \pipe_middle_10_logical_op__data_len$371 + connect \logical_op__insn$19 \pipe_middle_10_logical_op__insn$372 + connect \ra$20 \pipe_middle_10_ra$373 + connect \rb$21 \pipe_middle_10_rb$374 + connect \xer_so$22 \pipe_middle_10_xer_so$375 + connect \divisor_neg$23 \pipe_middle_10_divisor_neg$376 + connect \dividend_neg$24 \pipe_middle_10_dividend_neg$377 + connect \dive_abs_ov32$25 \pipe_middle_10_dive_abs_ov32$378 + connect \dive_abs_ov64$26 \pipe_middle_10_dive_abs_ov64$379 + connect \div_by_zero$27 \pipe_middle_10_div_by_zero$380 + connect \divisor_radicand$28 \pipe_middle_10_divisor_radicand$381 + connect \operation$29 \pipe_middle_10_operation$382 + connect \quotient_root$30 \pipe_middle_10_quotient_root$383 + connect \root_times_radicand$31 \pipe_middle_10_root_times_radicand$384 + connect \compare_lhs$32 \pipe_middle_10_compare_lhs$385 + connect \compare_rhs$33 \pipe_middle_10_compare_rhs$386 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_11_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_11_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_11_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_11_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_11_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_11_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_11_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_11_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_11_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_11_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_11_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_11_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_11_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_11_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_11_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_11_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_11_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_11_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_11_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_11_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_11_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_11_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_11_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_11_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_11_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_11_muxid$387 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_11_logical_op__insn_type$388 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_11_logical_op__fn_unit$389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_11_logical_op__imm_data__imm$390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__imm_data__imm_ok$391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__rc__rc$392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__rc__rc_ok$393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__oe__oe$394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__oe__oe_ok$395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__invert_in$396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__zero_a$397 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_11_logical_op__input_carry$398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__invert_out$399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__write_cr0$400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__output_carry$401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__is_32bit$402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_11_logical_op__is_signed$403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_11_logical_op__data_len$404 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_11_logical_op__insn$405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_11_ra$406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_11_rb$407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_11_xer_so$408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_11_divisor_neg$409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_11_dividend_neg$410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_11_dive_abs_ov32$411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_11_dive_abs_ov64$412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_11_div_by_zero$413 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_11_divisor_radicand$414 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_11_operation$415 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_11_quotient_root$416 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_11_root_times_radicand$417 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_11_compare_lhs$418 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_11_compare_rhs$419 + cell \pipe_middle_11 \pipe_middle_11 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_11_p_valid_i + connect \p_ready_o \pipe_middle_11_p_ready_o + connect \muxid \pipe_middle_11_muxid + connect \logical_op__insn_type \pipe_middle_11_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_11_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_11_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_11_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_11_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_11_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_11_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_11_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_11_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_11_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_11_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_11_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_11_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_11_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_11_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_11_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_11_logical_op__data_len + connect \logical_op__insn \pipe_middle_11_logical_op__insn + connect \ra \pipe_middle_11_ra + connect \rb \pipe_middle_11_rb + connect \xer_so \pipe_middle_11_xer_so + connect \divisor_neg \pipe_middle_11_divisor_neg + connect \dividend_neg \pipe_middle_11_dividend_neg + connect \dive_abs_ov32 \pipe_middle_11_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_11_dive_abs_ov64 + connect \div_by_zero \pipe_middle_11_div_by_zero + connect \divisor_radicand \pipe_middle_11_divisor_radicand + connect \operation \pipe_middle_11_operation + connect \quotient_root \pipe_middle_11_quotient_root + connect \root_times_radicand \pipe_middle_11_root_times_radicand + connect \compare_lhs \pipe_middle_11_compare_lhs + connect \compare_rhs \pipe_middle_11_compare_rhs + connect \n_valid_o \pipe_middle_11_n_valid_o + connect \n_ready_i \pipe_middle_11_n_ready_i + connect \muxid$1 \pipe_middle_11_muxid$387 + connect \logical_op__insn_type$2 \pipe_middle_11_logical_op__insn_type$388 + connect \logical_op__fn_unit$3 \pipe_middle_11_logical_op__fn_unit$389 + connect \logical_op__imm_data__imm$4 \pipe_middle_11_logical_op__imm_data__imm$390 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_11_logical_op__imm_data__imm_ok$391 + connect \logical_op__rc__rc$6 \pipe_middle_11_logical_op__rc__rc$392 + connect \logical_op__rc__rc_ok$7 \pipe_middle_11_logical_op__rc__rc_ok$393 + connect \logical_op__oe__oe$8 \pipe_middle_11_logical_op__oe__oe$394 + connect \logical_op__oe__oe_ok$9 \pipe_middle_11_logical_op__oe__oe_ok$395 + connect \logical_op__invert_in$10 \pipe_middle_11_logical_op__invert_in$396 + connect \logical_op__zero_a$11 \pipe_middle_11_logical_op__zero_a$397 + connect \logical_op__input_carry$12 \pipe_middle_11_logical_op__input_carry$398 + connect \logical_op__invert_out$13 \pipe_middle_11_logical_op__invert_out$399 + connect \logical_op__write_cr0$14 \pipe_middle_11_logical_op__write_cr0$400 + connect \logical_op__output_carry$15 \pipe_middle_11_logical_op__output_carry$401 + connect \logical_op__is_32bit$16 \pipe_middle_11_logical_op__is_32bit$402 + connect \logical_op__is_signed$17 \pipe_middle_11_logical_op__is_signed$403 + connect \logical_op__data_len$18 \pipe_middle_11_logical_op__data_len$404 + connect \logical_op__insn$19 \pipe_middle_11_logical_op__insn$405 + connect \ra$20 \pipe_middle_11_ra$406 + connect \rb$21 \pipe_middle_11_rb$407 + connect \xer_so$22 \pipe_middle_11_xer_so$408 + connect \divisor_neg$23 \pipe_middle_11_divisor_neg$409 + connect \dividend_neg$24 \pipe_middle_11_dividend_neg$410 + connect \dive_abs_ov32$25 \pipe_middle_11_dive_abs_ov32$411 + connect \dive_abs_ov64$26 \pipe_middle_11_dive_abs_ov64$412 + connect \div_by_zero$27 \pipe_middle_11_div_by_zero$413 + connect \divisor_radicand$28 \pipe_middle_11_divisor_radicand$414 + connect \operation$29 \pipe_middle_11_operation$415 + connect \quotient_root$30 \pipe_middle_11_quotient_root$416 + connect \root_times_radicand$31 \pipe_middle_11_root_times_radicand$417 + connect \compare_lhs$32 \pipe_middle_11_compare_lhs$418 + connect \compare_rhs$33 \pipe_middle_11_compare_rhs$419 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_12_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_12_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_12_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_12_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_12_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_12_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_12_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_12_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_12_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_12_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_12_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_12_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_12_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_12_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_12_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_12_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_12_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_12_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_12_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_12_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_12_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_12_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_12_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_12_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_12_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_12_muxid$420 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_12_logical_op__insn_type$421 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_12_logical_op__fn_unit$422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_12_logical_op__imm_data__imm$423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__imm_data__imm_ok$424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__rc__rc$425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__rc__rc_ok$426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__oe__oe$427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__oe__oe_ok$428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__invert_in$429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__zero_a$430 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_12_logical_op__input_carry$431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__invert_out$432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__write_cr0$433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__output_carry$434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__is_32bit$435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_12_logical_op__is_signed$436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_12_logical_op__data_len$437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_12_logical_op__insn$438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_12_ra$439 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_12_rb$440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_12_xer_so$441 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_12_divisor_neg$442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_12_dividend_neg$443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_12_dive_abs_ov32$444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_12_dive_abs_ov64$445 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_12_div_by_zero$446 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_12_divisor_radicand$447 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_12_operation$448 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_12_quotient_root$449 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_12_root_times_radicand$450 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_12_compare_lhs$451 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_12_compare_rhs$452 + cell \pipe_middle_12 \pipe_middle_12 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_12_p_valid_i + connect \p_ready_o \pipe_middle_12_p_ready_o + connect \muxid \pipe_middle_12_muxid + connect \logical_op__insn_type \pipe_middle_12_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_12_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_12_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_12_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_12_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_12_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_12_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_12_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_12_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_12_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_12_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_12_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_12_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_12_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_12_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_12_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_12_logical_op__data_len + connect \logical_op__insn \pipe_middle_12_logical_op__insn + connect \ra \pipe_middle_12_ra + connect \rb \pipe_middle_12_rb + connect \xer_so \pipe_middle_12_xer_so + connect \divisor_neg \pipe_middle_12_divisor_neg + connect \dividend_neg \pipe_middle_12_dividend_neg + connect \dive_abs_ov32 \pipe_middle_12_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_12_dive_abs_ov64 + connect \div_by_zero \pipe_middle_12_div_by_zero + connect \divisor_radicand \pipe_middle_12_divisor_radicand + connect \operation \pipe_middle_12_operation + connect \quotient_root \pipe_middle_12_quotient_root + connect \root_times_radicand \pipe_middle_12_root_times_radicand + connect \compare_lhs \pipe_middle_12_compare_lhs + connect \compare_rhs \pipe_middle_12_compare_rhs + connect \n_valid_o \pipe_middle_12_n_valid_o + connect \n_ready_i \pipe_middle_12_n_ready_i + connect \muxid$1 \pipe_middle_12_muxid$420 + connect \logical_op__insn_type$2 \pipe_middle_12_logical_op__insn_type$421 + connect \logical_op__fn_unit$3 \pipe_middle_12_logical_op__fn_unit$422 + connect \logical_op__imm_data__imm$4 \pipe_middle_12_logical_op__imm_data__imm$423 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_12_logical_op__imm_data__imm_ok$424 + connect \logical_op__rc__rc$6 \pipe_middle_12_logical_op__rc__rc$425 + connect \logical_op__rc__rc_ok$7 \pipe_middle_12_logical_op__rc__rc_ok$426 + connect \logical_op__oe__oe$8 \pipe_middle_12_logical_op__oe__oe$427 + connect \logical_op__oe__oe_ok$9 \pipe_middle_12_logical_op__oe__oe_ok$428 + connect \logical_op__invert_in$10 \pipe_middle_12_logical_op__invert_in$429 + connect \logical_op__zero_a$11 \pipe_middle_12_logical_op__zero_a$430 + connect \logical_op__input_carry$12 \pipe_middle_12_logical_op__input_carry$431 + connect \logical_op__invert_out$13 \pipe_middle_12_logical_op__invert_out$432 + connect \logical_op__write_cr0$14 \pipe_middle_12_logical_op__write_cr0$433 + connect \logical_op__output_carry$15 \pipe_middle_12_logical_op__output_carry$434 + connect \logical_op__is_32bit$16 \pipe_middle_12_logical_op__is_32bit$435 + connect \logical_op__is_signed$17 \pipe_middle_12_logical_op__is_signed$436 + connect \logical_op__data_len$18 \pipe_middle_12_logical_op__data_len$437 + connect \logical_op__insn$19 \pipe_middle_12_logical_op__insn$438 + connect \ra$20 \pipe_middle_12_ra$439 + connect \rb$21 \pipe_middle_12_rb$440 + connect \xer_so$22 \pipe_middle_12_xer_so$441 + connect \divisor_neg$23 \pipe_middle_12_divisor_neg$442 + connect \dividend_neg$24 \pipe_middle_12_dividend_neg$443 + connect \dive_abs_ov32$25 \pipe_middle_12_dive_abs_ov32$444 + connect \dive_abs_ov64$26 \pipe_middle_12_dive_abs_ov64$445 + connect \div_by_zero$27 \pipe_middle_12_div_by_zero$446 + connect \divisor_radicand$28 \pipe_middle_12_divisor_radicand$447 + connect \operation$29 \pipe_middle_12_operation$448 + connect \quotient_root$30 \pipe_middle_12_quotient_root$449 + connect \root_times_radicand$31 \pipe_middle_12_root_times_radicand$450 + connect \compare_lhs$32 \pipe_middle_12_compare_lhs$451 + connect \compare_rhs$33 \pipe_middle_12_compare_rhs$452 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_13_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_13_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_13_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_13_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_13_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_13_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_13_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_13_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_13_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_13_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_13_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_13_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_13_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_13_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_13_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_13_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_13_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_13_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_13_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_13_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_13_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_13_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_13_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_13_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_13_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_13_muxid$453 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_13_logical_op__insn_type$454 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_13_logical_op__fn_unit$455 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_13_logical_op__imm_data__imm$456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__imm_data__imm_ok$457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__rc__rc$458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__rc__rc_ok$459 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__oe__oe$460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__oe__oe_ok$461 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__invert_in$462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__zero_a$463 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_13_logical_op__input_carry$464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__invert_out$465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__write_cr0$466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__output_carry$467 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__is_32bit$468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_13_logical_op__is_signed$469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_13_logical_op__data_len$470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_13_logical_op__insn$471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_13_ra$472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_13_rb$473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_13_xer_so$474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_13_divisor_neg$475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_13_dividend_neg$476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_13_dive_abs_ov32$477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_13_dive_abs_ov64$478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_13_div_by_zero$479 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_13_divisor_radicand$480 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_13_operation$481 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_13_quotient_root$482 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_13_root_times_radicand$483 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_13_compare_lhs$484 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_13_compare_rhs$485 + cell \pipe_middle_13 \pipe_middle_13 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_13_p_valid_i + connect \p_ready_o \pipe_middle_13_p_ready_o + connect \muxid \pipe_middle_13_muxid + connect \logical_op__insn_type \pipe_middle_13_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_13_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_13_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_13_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_13_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_13_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_13_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_13_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_13_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_13_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_13_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_13_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_13_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_13_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_13_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_13_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_13_logical_op__data_len + connect \logical_op__insn \pipe_middle_13_logical_op__insn + connect \ra \pipe_middle_13_ra + connect \rb \pipe_middle_13_rb + connect \xer_so \pipe_middle_13_xer_so + connect \divisor_neg \pipe_middle_13_divisor_neg + connect \dividend_neg \pipe_middle_13_dividend_neg + connect \dive_abs_ov32 \pipe_middle_13_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_13_dive_abs_ov64 + connect \div_by_zero \pipe_middle_13_div_by_zero + connect \divisor_radicand \pipe_middle_13_divisor_radicand + connect \operation \pipe_middle_13_operation + connect \quotient_root \pipe_middle_13_quotient_root + connect \root_times_radicand \pipe_middle_13_root_times_radicand + connect \compare_lhs \pipe_middle_13_compare_lhs + connect \compare_rhs \pipe_middle_13_compare_rhs + connect \n_valid_o \pipe_middle_13_n_valid_o + connect \n_ready_i \pipe_middle_13_n_ready_i + connect \muxid$1 \pipe_middle_13_muxid$453 + connect \logical_op__insn_type$2 \pipe_middle_13_logical_op__insn_type$454 + connect \logical_op__fn_unit$3 \pipe_middle_13_logical_op__fn_unit$455 + connect \logical_op__imm_data__imm$4 \pipe_middle_13_logical_op__imm_data__imm$456 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_13_logical_op__imm_data__imm_ok$457 + connect \logical_op__rc__rc$6 \pipe_middle_13_logical_op__rc__rc$458 + connect \logical_op__rc__rc_ok$7 \pipe_middle_13_logical_op__rc__rc_ok$459 + connect \logical_op__oe__oe$8 \pipe_middle_13_logical_op__oe__oe$460 + connect \logical_op__oe__oe_ok$9 \pipe_middle_13_logical_op__oe__oe_ok$461 + connect \logical_op__invert_in$10 \pipe_middle_13_logical_op__invert_in$462 + connect \logical_op__zero_a$11 \pipe_middle_13_logical_op__zero_a$463 + connect \logical_op__input_carry$12 \pipe_middle_13_logical_op__input_carry$464 + connect \logical_op__invert_out$13 \pipe_middle_13_logical_op__invert_out$465 + connect \logical_op__write_cr0$14 \pipe_middle_13_logical_op__write_cr0$466 + connect \logical_op__output_carry$15 \pipe_middle_13_logical_op__output_carry$467 + connect \logical_op__is_32bit$16 \pipe_middle_13_logical_op__is_32bit$468 + connect \logical_op__is_signed$17 \pipe_middle_13_logical_op__is_signed$469 + connect \logical_op__data_len$18 \pipe_middle_13_logical_op__data_len$470 + connect \logical_op__insn$19 \pipe_middle_13_logical_op__insn$471 + connect \ra$20 \pipe_middle_13_ra$472 + connect \rb$21 \pipe_middle_13_rb$473 + connect \xer_so$22 \pipe_middle_13_xer_so$474 + connect \divisor_neg$23 \pipe_middle_13_divisor_neg$475 + connect \dividend_neg$24 \pipe_middle_13_dividend_neg$476 + connect \dive_abs_ov32$25 \pipe_middle_13_dive_abs_ov32$477 + connect \dive_abs_ov64$26 \pipe_middle_13_dive_abs_ov64$478 + connect \div_by_zero$27 \pipe_middle_13_div_by_zero$479 + connect \divisor_radicand$28 \pipe_middle_13_divisor_radicand$480 + connect \operation$29 \pipe_middle_13_operation$481 + connect \quotient_root$30 \pipe_middle_13_quotient_root$482 + connect \root_times_radicand$31 \pipe_middle_13_root_times_radicand$483 + connect \compare_lhs$32 \pipe_middle_13_compare_lhs$484 + connect \compare_rhs$33 \pipe_middle_13_compare_rhs$485 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_14_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_14_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_14_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_14_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_14_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_14_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_14_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_14_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_14_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_14_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_14_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_14_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_14_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_14_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_14_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_14_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_14_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_14_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_14_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_14_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_14_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_14_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_14_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_14_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_14_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_14_muxid$486 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_14_logical_op__insn_type$487 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_14_logical_op__fn_unit$488 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_14_logical_op__imm_data__imm$489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__imm_data__imm_ok$490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__rc__rc$491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__rc__rc_ok$492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__oe__oe$493 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__oe__oe_ok$494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__invert_in$495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__zero_a$496 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_14_logical_op__input_carry$497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__invert_out$498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__write_cr0$499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__output_carry$500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__is_32bit$501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_14_logical_op__is_signed$502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_14_logical_op__data_len$503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_14_logical_op__insn$504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_14_ra$505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_14_rb$506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_14_xer_so$507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_14_divisor_neg$508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_14_dividend_neg$509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_14_dive_abs_ov32$510 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_14_dive_abs_ov64$511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_14_div_by_zero$512 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_14_divisor_radicand$513 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_14_operation$514 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_14_quotient_root$515 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_14_root_times_radicand$516 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_14_compare_lhs$517 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_14_compare_rhs$518 + cell \pipe_middle_14 \pipe_middle_14 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_14_p_valid_i + connect \p_ready_o \pipe_middle_14_p_ready_o + connect \muxid \pipe_middle_14_muxid + connect \logical_op__insn_type \pipe_middle_14_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_14_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_14_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_14_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_14_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_14_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_14_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_14_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_14_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_14_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_14_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_14_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_14_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_14_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_14_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_14_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_14_logical_op__data_len + connect \logical_op__insn \pipe_middle_14_logical_op__insn + connect \ra \pipe_middle_14_ra + connect \rb \pipe_middle_14_rb + connect \xer_so \pipe_middle_14_xer_so + connect \divisor_neg \pipe_middle_14_divisor_neg + connect \dividend_neg \pipe_middle_14_dividend_neg + connect \dive_abs_ov32 \pipe_middle_14_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_14_dive_abs_ov64 + connect \div_by_zero \pipe_middle_14_div_by_zero + connect \divisor_radicand \pipe_middle_14_divisor_radicand + connect \operation \pipe_middle_14_operation + connect \quotient_root \pipe_middle_14_quotient_root + connect \root_times_radicand \pipe_middle_14_root_times_radicand + connect \compare_lhs \pipe_middle_14_compare_lhs + connect \compare_rhs \pipe_middle_14_compare_rhs + connect \n_valid_o \pipe_middle_14_n_valid_o + connect \n_ready_i \pipe_middle_14_n_ready_i + connect \muxid$1 \pipe_middle_14_muxid$486 + connect \logical_op__insn_type$2 \pipe_middle_14_logical_op__insn_type$487 + connect \logical_op__fn_unit$3 \pipe_middle_14_logical_op__fn_unit$488 + connect \logical_op__imm_data__imm$4 \pipe_middle_14_logical_op__imm_data__imm$489 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_14_logical_op__imm_data__imm_ok$490 + connect \logical_op__rc__rc$6 \pipe_middle_14_logical_op__rc__rc$491 + connect \logical_op__rc__rc_ok$7 \pipe_middle_14_logical_op__rc__rc_ok$492 + connect \logical_op__oe__oe$8 \pipe_middle_14_logical_op__oe__oe$493 + connect \logical_op__oe__oe_ok$9 \pipe_middle_14_logical_op__oe__oe_ok$494 + connect \logical_op__invert_in$10 \pipe_middle_14_logical_op__invert_in$495 + connect \logical_op__zero_a$11 \pipe_middle_14_logical_op__zero_a$496 + connect \logical_op__input_carry$12 \pipe_middle_14_logical_op__input_carry$497 + connect \logical_op__invert_out$13 \pipe_middle_14_logical_op__invert_out$498 + connect \logical_op__write_cr0$14 \pipe_middle_14_logical_op__write_cr0$499 + connect \logical_op__output_carry$15 \pipe_middle_14_logical_op__output_carry$500 + connect \logical_op__is_32bit$16 \pipe_middle_14_logical_op__is_32bit$501 + connect \logical_op__is_signed$17 \pipe_middle_14_logical_op__is_signed$502 + connect \logical_op__data_len$18 \pipe_middle_14_logical_op__data_len$503 + connect \logical_op__insn$19 \pipe_middle_14_logical_op__insn$504 + connect \ra$20 \pipe_middle_14_ra$505 + connect \rb$21 \pipe_middle_14_rb$506 + connect \xer_so$22 \pipe_middle_14_xer_so$507 + connect \divisor_neg$23 \pipe_middle_14_divisor_neg$508 + connect \dividend_neg$24 \pipe_middle_14_dividend_neg$509 + connect \dive_abs_ov32$25 \pipe_middle_14_dive_abs_ov32$510 + connect \dive_abs_ov64$26 \pipe_middle_14_dive_abs_ov64$511 + connect \div_by_zero$27 \pipe_middle_14_div_by_zero$512 + connect \divisor_radicand$28 \pipe_middle_14_divisor_radicand$513 + connect \operation$29 \pipe_middle_14_operation$514 + connect \quotient_root$30 \pipe_middle_14_quotient_root$515 + connect \root_times_radicand$31 \pipe_middle_14_root_times_radicand$516 + connect \compare_lhs$32 \pipe_middle_14_compare_lhs$517 + connect \compare_rhs$33 \pipe_middle_14_compare_rhs$518 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_middle_15_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_middle_15_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_15_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_15_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_15_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_15_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_15_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_15_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_15_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_15_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_15_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_15_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_15_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_15_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_15_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_15_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_15_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_15_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_15_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_15_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_15_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_15_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_15_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_middle_15_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_middle_15_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_15_muxid$519 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_15_logical_op__insn_type$520 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_middle_15_logical_op__fn_unit$521 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_15_logical_op__imm_data__imm$522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__imm_data__imm_ok$523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__rc__rc$524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__rc__rc_ok$525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__oe__oe$526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__oe__oe_ok$527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__invert_in$528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__zero_a$529 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_15_logical_op__input_carry$530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__invert_out$531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__write_cr0$532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__output_carry$533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__is_32bit$534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_middle_15_logical_op__is_signed$535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_15_logical_op__data_len$536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_15_logical_op__insn$537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_15_ra$538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_15_rb$539 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_middle_15_xer_so$540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_middle_15_divisor_neg$541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_middle_15_dividend_neg$542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_middle_15_dive_abs_ov32$543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_middle_15_dive_abs_ov64$544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_middle_15_div_by_zero$545 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_middle_15_divisor_radicand$546 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_middle_15_operation$547 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_middle_15_quotient_root$548 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_middle_15_root_times_radicand$549 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_middle_15_compare_lhs$550 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_middle_15_compare_rhs$551 + cell \pipe_middle_15 \pipe_middle_15 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_middle_15_p_valid_i + connect \p_ready_o \pipe_middle_15_p_ready_o + connect \muxid \pipe_middle_15_muxid + connect \logical_op__insn_type \pipe_middle_15_logical_op__insn_type + connect \logical_op__fn_unit \pipe_middle_15_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_middle_15_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_middle_15_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_middle_15_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_middle_15_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_middle_15_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_middle_15_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_middle_15_logical_op__invert_in + connect \logical_op__zero_a \pipe_middle_15_logical_op__zero_a + connect \logical_op__input_carry \pipe_middle_15_logical_op__input_carry + connect \logical_op__invert_out \pipe_middle_15_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_middle_15_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_middle_15_logical_op__output_carry + connect \logical_op__is_32bit \pipe_middle_15_logical_op__is_32bit + connect \logical_op__is_signed \pipe_middle_15_logical_op__is_signed + connect \logical_op__data_len \pipe_middle_15_logical_op__data_len + connect \logical_op__insn \pipe_middle_15_logical_op__insn + connect \ra \pipe_middle_15_ra + connect \rb \pipe_middle_15_rb + connect \xer_so \pipe_middle_15_xer_so + connect \divisor_neg \pipe_middle_15_divisor_neg + connect \dividend_neg \pipe_middle_15_dividend_neg + connect \dive_abs_ov32 \pipe_middle_15_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_middle_15_dive_abs_ov64 + connect \div_by_zero \pipe_middle_15_div_by_zero + connect \divisor_radicand \pipe_middle_15_divisor_radicand + connect \operation \pipe_middle_15_operation + connect \quotient_root \pipe_middle_15_quotient_root + connect \root_times_radicand \pipe_middle_15_root_times_radicand + connect \compare_lhs \pipe_middle_15_compare_lhs + connect \compare_rhs \pipe_middle_15_compare_rhs + connect \n_valid_o \pipe_middle_15_n_valid_o + connect \n_ready_i \pipe_middle_15_n_ready_i + connect \muxid$1 \pipe_middle_15_muxid$519 + connect \logical_op__insn_type$2 \pipe_middle_15_logical_op__insn_type$520 + connect \logical_op__fn_unit$3 \pipe_middle_15_logical_op__fn_unit$521 + connect \logical_op__imm_data__imm$4 \pipe_middle_15_logical_op__imm_data__imm$522 + connect \logical_op__imm_data__imm_ok$5 \pipe_middle_15_logical_op__imm_data__imm_ok$523 + connect \logical_op__rc__rc$6 \pipe_middle_15_logical_op__rc__rc$524 + connect \logical_op__rc__rc_ok$7 \pipe_middle_15_logical_op__rc__rc_ok$525 + connect \logical_op__oe__oe$8 \pipe_middle_15_logical_op__oe__oe$526 + connect \logical_op__oe__oe_ok$9 \pipe_middle_15_logical_op__oe__oe_ok$527 + connect \logical_op__invert_in$10 \pipe_middle_15_logical_op__invert_in$528 + connect \logical_op__zero_a$11 \pipe_middle_15_logical_op__zero_a$529 + connect \logical_op__input_carry$12 \pipe_middle_15_logical_op__input_carry$530 + connect \logical_op__invert_out$13 \pipe_middle_15_logical_op__invert_out$531 + connect \logical_op__write_cr0$14 \pipe_middle_15_logical_op__write_cr0$532 + connect \logical_op__output_carry$15 \pipe_middle_15_logical_op__output_carry$533 + connect \logical_op__is_32bit$16 \pipe_middle_15_logical_op__is_32bit$534 + connect \logical_op__is_signed$17 \pipe_middle_15_logical_op__is_signed$535 + connect \logical_op__data_len$18 \pipe_middle_15_logical_op__data_len$536 + connect \logical_op__insn$19 \pipe_middle_15_logical_op__insn$537 + connect \ra$20 \pipe_middle_15_ra$538 + connect \rb$21 \pipe_middle_15_rb$539 + connect \xer_so$22 \pipe_middle_15_xer_so$540 + connect \divisor_neg$23 \pipe_middle_15_divisor_neg$541 + connect \dividend_neg$24 \pipe_middle_15_dividend_neg$542 + connect \dive_abs_ov32$25 \pipe_middle_15_dive_abs_ov32$543 + connect \dive_abs_ov64$26 \pipe_middle_15_dive_abs_ov64$544 + connect \div_by_zero$27 \pipe_middle_15_div_by_zero$545 + connect \divisor_radicand$28 \pipe_middle_15_divisor_radicand$546 + connect \operation$29 \pipe_middle_15_operation$547 + connect \quotient_root$30 \pipe_middle_15_quotient_root$548 + connect \root_times_radicand$31 \pipe_middle_15_root_times_radicand$549 + connect \compare_lhs$32 \pipe_middle_15_compare_lhs$550 + connect \compare_rhs$33 \pipe_middle_15_compare_rhs$551 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe_end_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe_end_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_end_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_end_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \pipe_end_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire width 1 \pipe_end_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire width 1 \pipe_end_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire width 1 \pipe_end_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire width 1 \pipe_end_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire width 1 \pipe_end_div_by_zero + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:161" + wire width 64 \pipe_end_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:162" + wire width 2 \pipe_end_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:163" + wire width 64 \pipe_end_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:164" + wire width 128 \pipe_end_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:165" + wire width 192 \pipe_end_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:166" + wire width 192 \pipe_end_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe_end_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe_end_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_end_muxid$552 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type$553 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe_end_logical_op__fn_unit$554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__imm$555 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__imm_data__imm_ok$556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__rc__rc$557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__rc__rc_ok$558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__oe__oe$559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__oe__oe_ok$560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__invert_in$561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__zero_a$562 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry$563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__invert_out$564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__write_cr0$565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__output_carry$566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__is_32bit$567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe_end_logical_op__is_signed$568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len$569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn$570 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_end_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_end_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe_end_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_end_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe_end_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_end_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_end_xer_so$571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe_end_xer_so_ok + cell \pipe_end \pipe_end + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe_end_p_valid_i + connect \p_ready_o \pipe_end_p_ready_o + connect \muxid \pipe_end_muxid + connect \logical_op__insn_type \pipe_end_logical_op__insn_type + connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit + connect \logical_op__imm_data__imm \pipe_end_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \pipe_end_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc + connect \logical_op__rc__rc_ok \pipe_end_logical_op__rc__rc_ok + connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe + connect \logical_op__oe__oe_ok \pipe_end_logical_op__oe__oe_ok + connect \logical_op__invert_in \pipe_end_logical_op__invert_in + connect \logical_op__zero_a \pipe_end_logical_op__zero_a + connect \logical_op__input_carry \pipe_end_logical_op__input_carry + connect \logical_op__invert_out \pipe_end_logical_op__invert_out + connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 + connect \logical_op__output_carry \pipe_end_logical_op__output_carry + connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit + connect \logical_op__is_signed \pipe_end_logical_op__is_signed + connect \logical_op__data_len \pipe_end_logical_op__data_len + connect \logical_op__insn \pipe_end_logical_op__insn + connect \ra \pipe_end_ra + connect \rb \pipe_end_rb + connect \xer_so \pipe_end_xer_so + connect \divisor_neg \pipe_end_divisor_neg + connect \dividend_neg \pipe_end_dividend_neg + connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 + connect \div_by_zero \pipe_end_div_by_zero + connect \divisor_radicand \pipe_end_divisor_radicand + connect \operation \pipe_end_operation + connect \quotient_root \pipe_end_quotient_root + connect \root_times_radicand \pipe_end_root_times_radicand + connect \compare_lhs \pipe_end_compare_lhs + connect \compare_rhs \pipe_end_compare_rhs + connect \n_valid_o \pipe_end_n_valid_o + connect \n_ready_i \pipe_end_n_ready_i + connect \muxid$1 \pipe_end_muxid$552 + connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$553 + connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$554 + connect \logical_op__imm_data__imm$4 \pipe_end_logical_op__imm_data__imm$555 + connect \logical_op__imm_data__imm_ok$5 \pipe_end_logical_op__imm_data__imm_ok$556 + connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$557 + connect \logical_op__rc__rc_ok$7 \pipe_end_logical_op__rc__rc_ok$558 + connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$559 + connect \logical_op__oe__oe_ok$9 \pipe_end_logical_op__oe__oe_ok$560 + connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$561 + connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$562 + connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$563 + connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$564 + connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$565 + connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$566 + connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$567 + connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$568 + connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$569 + connect \logical_op__insn$19 \pipe_end_logical_op__insn$570 + connect \o \pipe_end_o + connect \o_ok \pipe_end_o_ok + connect \cr_a \pipe_end_cr_a + connect \cr_a_ok \pipe_end_cr_a_ok + connect \xer_ov \pipe_end_xer_ov + connect \xer_ov_ok \pipe_end_xer_ov_ok + connect \xer_so$20 \pipe_end_xer_so$571 + connect \xer_so_ok \pipe_end_xer_so_ok + end + process $group_0 + assign \pipe_middle_0_p_valid_i 1'0 + assign \pipe_middle_0_p_valid_i \pipe_start_n_valid_o + sync init + end + process $group_1 + assign \pipe_start_n_ready_i 1'0 + assign \pipe_start_n_ready_i \pipe_middle_0_p_ready_o + sync init + end + process $group_2 + assign \pipe_middle_0_muxid 2'00 + assign \pipe_middle_0_muxid \pipe_start_muxid + sync init + end + process $group_3 + assign \pipe_middle_0_logical_op__insn_type 7'0000000 + assign \pipe_middle_0_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_0_logical_op__rc__rc 1'0 + assign \pipe_middle_0_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_0_logical_op__oe__oe 1'0 + assign \pipe_middle_0_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_0_logical_op__invert_in 1'0 + assign \pipe_middle_0_logical_op__zero_a 1'0 + assign \pipe_middle_0_logical_op__input_carry 2'00 + assign \pipe_middle_0_logical_op__invert_out 1'0 + assign \pipe_middle_0_logical_op__write_cr0 1'0 + assign \pipe_middle_0_logical_op__output_carry 1'0 + assign \pipe_middle_0_logical_op__is_32bit 1'0 + assign \pipe_middle_0_logical_op__is_signed 1'0 + assign \pipe_middle_0_logical_op__data_len 4'0000 + assign \pipe_middle_0_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in { \pipe_middle_0_logical_op__oe__oe_ok \pipe_middle_0_logical_op__oe__oe } { \pipe_middle_0_logical_op__rc__rc_ok \pipe_middle_0_logical_op__rc__rc } { \pipe_middle_0_logical_op__imm_data__imm_ok \pipe_middle_0_logical_op__imm_data__imm } \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in { \pipe_start_logical_op__oe__oe_ok \pipe_start_logical_op__oe__oe } { \pipe_start_logical_op__rc__rc_ok \pipe_start_logical_op__rc__rc } { \pipe_start_logical_op__imm_data__imm_ok \pipe_start_logical_op__imm_data__imm } \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } + sync init + end + process $group_21 + assign \pipe_middle_0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_ra \pipe_start_ra + sync init + end + process $group_22 + assign \pipe_middle_0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_rb \pipe_start_rb + sync init + end + process $group_23 + assign \pipe_middle_0_xer_so 1'0 + assign \pipe_middle_0_xer_so \pipe_start_xer_so + sync init + end + process $group_24 + assign \pipe_middle_0_divisor_neg 1'0 + assign \pipe_middle_0_divisor_neg \pipe_start_divisor_neg + sync init + end + process $group_25 + assign \pipe_middle_0_dividend_neg 1'0 + assign \pipe_middle_0_dividend_neg \pipe_start_dividend_neg + sync init + end + process $group_26 + assign \pipe_middle_0_dive_abs_ov32 1'0 + assign \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 + sync init + end + process $group_27 + assign \pipe_middle_0_dive_abs_ov64 1'0 + assign \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 + sync init + end + process $group_28 + assign \pipe_middle_0_div_by_zero 1'0 + assign \pipe_middle_0_div_by_zero \pipe_start_div_by_zero + sync init + end + process $group_29 + assign \pipe_middle_0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand + sync init + end + process $group_30 + assign \pipe_middle_0_operation 2'00 + assign \pipe_middle_0_operation \pipe_start_operation + sync init + end + process $group_31 + assign \pipe_middle_0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_quotient_root \pipe_start_quotient_root + sync init + end + process $group_32 + assign \pipe_middle_0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_root_times_radicand \pipe_start_root_times_radicand + sync init + end + process $group_33 + assign \pipe_middle_0_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_compare_lhs \pipe_start_compare_lhs + sync init + end + process $group_34 + assign \pipe_middle_0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_0_compare_rhs \pipe_start_compare_rhs + sync init + end + process $group_35 + assign \pipe_middle_1_p_valid_i 1'0 + assign \pipe_middle_1_p_valid_i \pipe_middle_0_n_valid_o + sync init + end + process $group_36 + assign \pipe_middle_0_n_ready_i 1'0 + assign \pipe_middle_0_n_ready_i \pipe_middle_1_p_ready_o + sync init + end + process $group_37 + assign \pipe_middle_1_muxid 2'00 + assign \pipe_middle_1_muxid \pipe_middle_0_muxid$24 + sync init + end + process $group_38 + assign \pipe_middle_1_logical_op__insn_type 7'0000000 + assign \pipe_middle_1_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_1_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_1_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_1_logical_op__rc__rc 1'0 + assign \pipe_middle_1_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_1_logical_op__oe__oe 1'0 + assign \pipe_middle_1_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_1_logical_op__invert_in 1'0 + assign \pipe_middle_1_logical_op__zero_a 1'0 + assign \pipe_middle_1_logical_op__input_carry 2'00 + assign \pipe_middle_1_logical_op__invert_out 1'0 + assign \pipe_middle_1_logical_op__write_cr0 1'0 + assign \pipe_middle_1_logical_op__output_carry 1'0 + assign \pipe_middle_1_logical_op__is_32bit 1'0 + assign \pipe_middle_1_logical_op__is_signed 1'0 + assign \pipe_middle_1_logical_op__data_len 4'0000 + assign \pipe_middle_1_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_1_logical_op__insn \pipe_middle_1_logical_op__data_len \pipe_middle_1_logical_op__is_signed \pipe_middle_1_logical_op__is_32bit \pipe_middle_1_logical_op__output_carry \pipe_middle_1_logical_op__write_cr0 \pipe_middle_1_logical_op__invert_out \pipe_middle_1_logical_op__input_carry \pipe_middle_1_logical_op__zero_a \pipe_middle_1_logical_op__invert_in { \pipe_middle_1_logical_op__oe__oe_ok \pipe_middle_1_logical_op__oe__oe } { \pipe_middle_1_logical_op__rc__rc_ok \pipe_middle_1_logical_op__rc__rc } { \pipe_middle_1_logical_op__imm_data__imm_ok \pipe_middle_1_logical_op__imm_data__imm } \pipe_middle_1_logical_op__fn_unit \pipe_middle_1_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 { \pipe_middle_0_logical_op__oe__oe_ok$32 \pipe_middle_0_logical_op__oe__oe$31 } { \pipe_middle_0_logical_op__rc__rc_ok$30 \pipe_middle_0_logical_op__rc__rc$29 } { \pipe_middle_0_logical_op__imm_data__imm_ok$28 \pipe_middle_0_logical_op__imm_data__imm$27 } \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } + sync init + end + process $group_56 + assign \pipe_middle_1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_1_ra \pipe_middle_0_ra$43 + sync init + end + process $group_57 + assign \pipe_middle_1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_1_rb \pipe_middle_0_rb$44 + sync init + end + process $group_58 + assign \pipe_middle_1_xer_so 1'0 + assign \pipe_middle_1_xer_so \pipe_middle_0_xer_so$45 + sync init + end + process $group_59 + assign \pipe_middle_1_divisor_neg 1'0 + assign \pipe_middle_1_divisor_neg \pipe_middle_0_divisor_neg$46 + sync init + end + process $group_60 + assign \pipe_middle_1_dividend_neg 1'0 + assign \pipe_middle_1_dividend_neg \pipe_middle_0_dividend_neg$47 + sync init + end + process $group_61 + assign \pipe_middle_1_dive_abs_ov32 1'0 + assign \pipe_middle_1_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 + sync init + end + process $group_62 + assign \pipe_middle_1_dive_abs_ov64 1'0 + assign \pipe_middle_1_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 + sync init + end + process $group_63 + assign \pipe_middle_1_div_by_zero 1'0 + assign \pipe_middle_1_div_by_zero \pipe_middle_0_div_by_zero$50 + sync init + end + process $group_64 + assign \pipe_middle_1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_1_divisor_radicand \pipe_middle_0_divisor_radicand$51 + sync init + end + process $group_65 + assign \pipe_middle_1_operation 2'00 + assign \pipe_middle_1_operation \pipe_middle_0_operation$52 + sync init + end + process $group_66 + assign \pipe_middle_1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_1_quotient_root \pipe_middle_0_quotient_root$53 + sync init + end + process $group_67 + assign \pipe_middle_1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_1_root_times_radicand \pipe_middle_0_root_times_radicand$54 + sync init + end + process $group_68 + assign \pipe_middle_1_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_1_compare_lhs \pipe_middle_0_compare_lhs$55 + sync init + end + process $group_69 + assign \pipe_middle_1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_1_compare_rhs \pipe_middle_0_compare_rhs$56 + sync init + end + process $group_70 + assign \pipe_middle_2_p_valid_i 1'0 + assign \pipe_middle_2_p_valid_i \pipe_middle_1_n_valid_o + sync init + end + process $group_71 + assign \pipe_middle_1_n_ready_i 1'0 + assign \pipe_middle_1_n_ready_i \pipe_middle_2_p_ready_o + sync init + end + process $group_72 + assign \pipe_middle_2_muxid 2'00 + assign \pipe_middle_2_muxid \pipe_middle_1_muxid$57 + sync init + end + process $group_73 + assign \pipe_middle_2_logical_op__insn_type 7'0000000 + assign \pipe_middle_2_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_2_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_2_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_2_logical_op__rc__rc 1'0 + assign \pipe_middle_2_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_2_logical_op__oe__oe 1'0 + assign \pipe_middle_2_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_2_logical_op__invert_in 1'0 + assign \pipe_middle_2_logical_op__zero_a 1'0 + assign \pipe_middle_2_logical_op__input_carry 2'00 + assign \pipe_middle_2_logical_op__invert_out 1'0 + assign \pipe_middle_2_logical_op__write_cr0 1'0 + assign \pipe_middle_2_logical_op__output_carry 1'0 + assign \pipe_middle_2_logical_op__is_32bit 1'0 + assign \pipe_middle_2_logical_op__is_signed 1'0 + assign \pipe_middle_2_logical_op__data_len 4'0000 + assign \pipe_middle_2_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_2_logical_op__insn \pipe_middle_2_logical_op__data_len \pipe_middle_2_logical_op__is_signed \pipe_middle_2_logical_op__is_32bit \pipe_middle_2_logical_op__output_carry \pipe_middle_2_logical_op__write_cr0 \pipe_middle_2_logical_op__invert_out \pipe_middle_2_logical_op__input_carry \pipe_middle_2_logical_op__zero_a \pipe_middle_2_logical_op__invert_in { \pipe_middle_2_logical_op__oe__oe_ok \pipe_middle_2_logical_op__oe__oe } { \pipe_middle_2_logical_op__rc__rc_ok \pipe_middle_2_logical_op__rc__rc } { \pipe_middle_2_logical_op__imm_data__imm_ok \pipe_middle_2_logical_op__imm_data__imm } \pipe_middle_2_logical_op__fn_unit \pipe_middle_2_logical_op__insn_type } { \pipe_middle_1_logical_op__insn$75 \pipe_middle_1_logical_op__data_len$74 \pipe_middle_1_logical_op__is_signed$73 \pipe_middle_1_logical_op__is_32bit$72 \pipe_middle_1_logical_op__output_carry$71 \pipe_middle_1_logical_op__write_cr0$70 \pipe_middle_1_logical_op__invert_out$69 \pipe_middle_1_logical_op__input_carry$68 \pipe_middle_1_logical_op__zero_a$67 \pipe_middle_1_logical_op__invert_in$66 { \pipe_middle_1_logical_op__oe__oe_ok$65 \pipe_middle_1_logical_op__oe__oe$64 } { \pipe_middle_1_logical_op__rc__rc_ok$63 \pipe_middle_1_logical_op__rc__rc$62 } { \pipe_middle_1_logical_op__imm_data__imm_ok$61 \pipe_middle_1_logical_op__imm_data__imm$60 } \pipe_middle_1_logical_op__fn_unit$59 \pipe_middle_1_logical_op__insn_type$58 } + sync init + end + process $group_91 + assign \pipe_middle_2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_2_ra \pipe_middle_1_ra$76 + sync init + end + process $group_92 + assign \pipe_middle_2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_2_rb \pipe_middle_1_rb$77 + sync init + end + process $group_93 + assign \pipe_middle_2_xer_so 1'0 + assign \pipe_middle_2_xer_so \pipe_middle_1_xer_so$78 + sync init + end + process $group_94 + assign \pipe_middle_2_divisor_neg 1'0 + assign \pipe_middle_2_divisor_neg \pipe_middle_1_divisor_neg$79 + sync init + end + process $group_95 + assign \pipe_middle_2_dividend_neg 1'0 + assign \pipe_middle_2_dividend_neg \pipe_middle_1_dividend_neg$80 + sync init + end + process $group_96 + assign \pipe_middle_2_dive_abs_ov32 1'0 + assign \pipe_middle_2_dive_abs_ov32 \pipe_middle_1_dive_abs_ov32$81 + sync init + end + process $group_97 + assign \pipe_middle_2_dive_abs_ov64 1'0 + assign \pipe_middle_2_dive_abs_ov64 \pipe_middle_1_dive_abs_ov64$82 + sync init + end + process $group_98 + assign \pipe_middle_2_div_by_zero 1'0 + assign \pipe_middle_2_div_by_zero \pipe_middle_1_div_by_zero$83 + sync init + end + process $group_99 + assign \pipe_middle_2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_2_divisor_radicand \pipe_middle_1_divisor_radicand$84 + sync init + end + process $group_100 + assign \pipe_middle_2_operation 2'00 + assign \pipe_middle_2_operation \pipe_middle_1_operation$85 + sync init + end + process $group_101 + assign \pipe_middle_2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_2_quotient_root \pipe_middle_1_quotient_root$86 + sync init + end + process $group_102 + assign \pipe_middle_2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_2_root_times_radicand \pipe_middle_1_root_times_radicand$87 + sync init + end + process $group_103 + assign \pipe_middle_2_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_2_compare_lhs \pipe_middle_1_compare_lhs$88 + sync init + end + process $group_104 + assign \pipe_middle_2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_2_compare_rhs \pipe_middle_1_compare_rhs$89 + sync init + end + process $group_105 + assign \pipe_middle_3_p_valid_i 1'0 + assign \pipe_middle_3_p_valid_i \pipe_middle_2_n_valid_o + sync init + end + process $group_106 + assign \pipe_middle_2_n_ready_i 1'0 + assign \pipe_middle_2_n_ready_i \pipe_middle_3_p_ready_o + sync init + end + process $group_107 + assign \pipe_middle_3_muxid 2'00 + assign \pipe_middle_3_muxid \pipe_middle_2_muxid$90 + sync init + end + process $group_108 + assign \pipe_middle_3_logical_op__insn_type 7'0000000 + assign \pipe_middle_3_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_3_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_3_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_3_logical_op__rc__rc 1'0 + assign \pipe_middle_3_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_3_logical_op__oe__oe 1'0 + assign \pipe_middle_3_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_3_logical_op__invert_in 1'0 + assign \pipe_middle_3_logical_op__zero_a 1'0 + assign \pipe_middle_3_logical_op__input_carry 2'00 + assign \pipe_middle_3_logical_op__invert_out 1'0 + assign \pipe_middle_3_logical_op__write_cr0 1'0 + assign \pipe_middle_3_logical_op__output_carry 1'0 + assign \pipe_middle_3_logical_op__is_32bit 1'0 + assign \pipe_middle_3_logical_op__is_signed 1'0 + assign \pipe_middle_3_logical_op__data_len 4'0000 + assign \pipe_middle_3_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_3_logical_op__insn \pipe_middle_3_logical_op__data_len \pipe_middle_3_logical_op__is_signed \pipe_middle_3_logical_op__is_32bit \pipe_middle_3_logical_op__output_carry \pipe_middle_3_logical_op__write_cr0 \pipe_middle_3_logical_op__invert_out \pipe_middle_3_logical_op__input_carry \pipe_middle_3_logical_op__zero_a \pipe_middle_3_logical_op__invert_in { \pipe_middle_3_logical_op__oe__oe_ok \pipe_middle_3_logical_op__oe__oe } { \pipe_middle_3_logical_op__rc__rc_ok \pipe_middle_3_logical_op__rc__rc } { \pipe_middle_3_logical_op__imm_data__imm_ok \pipe_middle_3_logical_op__imm_data__imm } \pipe_middle_3_logical_op__fn_unit \pipe_middle_3_logical_op__insn_type } { \pipe_middle_2_logical_op__insn$108 \pipe_middle_2_logical_op__data_len$107 \pipe_middle_2_logical_op__is_signed$106 \pipe_middle_2_logical_op__is_32bit$105 \pipe_middle_2_logical_op__output_carry$104 \pipe_middle_2_logical_op__write_cr0$103 \pipe_middle_2_logical_op__invert_out$102 \pipe_middle_2_logical_op__input_carry$101 \pipe_middle_2_logical_op__zero_a$100 \pipe_middle_2_logical_op__invert_in$99 { \pipe_middle_2_logical_op__oe__oe_ok$98 \pipe_middle_2_logical_op__oe__oe$97 } { \pipe_middle_2_logical_op__rc__rc_ok$96 \pipe_middle_2_logical_op__rc__rc$95 } { \pipe_middle_2_logical_op__imm_data__imm_ok$94 \pipe_middle_2_logical_op__imm_data__imm$93 } \pipe_middle_2_logical_op__fn_unit$92 \pipe_middle_2_logical_op__insn_type$91 } + sync init + end + process $group_126 + assign \pipe_middle_3_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_3_ra \pipe_middle_2_ra$109 + sync init + end + process $group_127 + assign \pipe_middle_3_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_3_rb \pipe_middle_2_rb$110 + sync init + end + process $group_128 + assign \pipe_middle_3_xer_so 1'0 + assign \pipe_middle_3_xer_so \pipe_middle_2_xer_so$111 + sync init + end + process $group_129 + assign \pipe_middle_3_divisor_neg 1'0 + assign \pipe_middle_3_divisor_neg \pipe_middle_2_divisor_neg$112 + sync init + end + process $group_130 + assign \pipe_middle_3_dividend_neg 1'0 + assign \pipe_middle_3_dividend_neg \pipe_middle_2_dividend_neg$113 + sync init + end + process $group_131 + assign \pipe_middle_3_dive_abs_ov32 1'0 + assign \pipe_middle_3_dive_abs_ov32 \pipe_middle_2_dive_abs_ov32$114 + sync init + end + process $group_132 + assign \pipe_middle_3_dive_abs_ov64 1'0 + assign \pipe_middle_3_dive_abs_ov64 \pipe_middle_2_dive_abs_ov64$115 + sync init + end + process $group_133 + assign \pipe_middle_3_div_by_zero 1'0 + assign \pipe_middle_3_div_by_zero \pipe_middle_2_div_by_zero$116 + sync init + end + process $group_134 + assign \pipe_middle_3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_3_divisor_radicand \pipe_middle_2_divisor_radicand$117 + sync init + end + process $group_135 + assign \pipe_middle_3_operation 2'00 + assign \pipe_middle_3_operation \pipe_middle_2_operation$118 + sync init + end + process $group_136 + assign \pipe_middle_3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_3_quotient_root \pipe_middle_2_quotient_root$119 + sync init + end + process $group_137 + assign \pipe_middle_3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_3_root_times_radicand \pipe_middle_2_root_times_radicand$120 + sync init + end + process $group_138 + assign \pipe_middle_3_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_3_compare_lhs \pipe_middle_2_compare_lhs$121 + sync init + end + process $group_139 + assign \pipe_middle_3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_3_compare_rhs \pipe_middle_2_compare_rhs$122 + sync init + end + process $group_140 + assign \pipe_middle_4_p_valid_i 1'0 + assign \pipe_middle_4_p_valid_i \pipe_middle_3_n_valid_o + sync init + end + process $group_141 + assign \pipe_middle_3_n_ready_i 1'0 + assign \pipe_middle_3_n_ready_i \pipe_middle_4_p_ready_o + sync init + end + process $group_142 + assign \pipe_middle_4_muxid 2'00 + assign \pipe_middle_4_muxid \pipe_middle_3_muxid$123 + sync init + end + process $group_143 + assign \pipe_middle_4_logical_op__insn_type 7'0000000 + assign \pipe_middle_4_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_4_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_4_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_4_logical_op__rc__rc 1'0 + assign \pipe_middle_4_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_4_logical_op__oe__oe 1'0 + assign \pipe_middle_4_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_4_logical_op__invert_in 1'0 + assign \pipe_middle_4_logical_op__zero_a 1'0 + assign \pipe_middle_4_logical_op__input_carry 2'00 + assign \pipe_middle_4_logical_op__invert_out 1'0 + assign \pipe_middle_4_logical_op__write_cr0 1'0 + assign \pipe_middle_4_logical_op__output_carry 1'0 + assign \pipe_middle_4_logical_op__is_32bit 1'0 + assign \pipe_middle_4_logical_op__is_signed 1'0 + assign \pipe_middle_4_logical_op__data_len 4'0000 + assign \pipe_middle_4_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_4_logical_op__insn \pipe_middle_4_logical_op__data_len \pipe_middle_4_logical_op__is_signed \pipe_middle_4_logical_op__is_32bit \pipe_middle_4_logical_op__output_carry \pipe_middle_4_logical_op__write_cr0 \pipe_middle_4_logical_op__invert_out \pipe_middle_4_logical_op__input_carry \pipe_middle_4_logical_op__zero_a \pipe_middle_4_logical_op__invert_in { \pipe_middle_4_logical_op__oe__oe_ok \pipe_middle_4_logical_op__oe__oe } { \pipe_middle_4_logical_op__rc__rc_ok \pipe_middle_4_logical_op__rc__rc } { \pipe_middle_4_logical_op__imm_data__imm_ok \pipe_middle_4_logical_op__imm_data__imm } \pipe_middle_4_logical_op__fn_unit \pipe_middle_4_logical_op__insn_type } { \pipe_middle_3_logical_op__insn$141 \pipe_middle_3_logical_op__data_len$140 \pipe_middle_3_logical_op__is_signed$139 \pipe_middle_3_logical_op__is_32bit$138 \pipe_middle_3_logical_op__output_carry$137 \pipe_middle_3_logical_op__write_cr0$136 \pipe_middle_3_logical_op__invert_out$135 \pipe_middle_3_logical_op__input_carry$134 \pipe_middle_3_logical_op__zero_a$133 \pipe_middle_3_logical_op__invert_in$132 { \pipe_middle_3_logical_op__oe__oe_ok$131 \pipe_middle_3_logical_op__oe__oe$130 } { \pipe_middle_3_logical_op__rc__rc_ok$129 \pipe_middle_3_logical_op__rc__rc$128 } { \pipe_middle_3_logical_op__imm_data__imm_ok$127 \pipe_middle_3_logical_op__imm_data__imm$126 } \pipe_middle_3_logical_op__fn_unit$125 \pipe_middle_3_logical_op__insn_type$124 } + sync init + end + process $group_161 + assign \pipe_middle_4_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_4_ra \pipe_middle_3_ra$142 + sync init + end + process $group_162 + assign \pipe_middle_4_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_4_rb \pipe_middle_3_rb$143 + sync init + end + process $group_163 + assign \pipe_middle_4_xer_so 1'0 + assign \pipe_middle_4_xer_so \pipe_middle_3_xer_so$144 + sync init + end + process $group_164 + assign \pipe_middle_4_divisor_neg 1'0 + assign \pipe_middle_4_divisor_neg \pipe_middle_3_divisor_neg$145 + sync init + end + process $group_165 + assign \pipe_middle_4_dividend_neg 1'0 + assign \pipe_middle_4_dividend_neg \pipe_middle_3_dividend_neg$146 + sync init + end + process $group_166 + assign \pipe_middle_4_dive_abs_ov32 1'0 + assign \pipe_middle_4_dive_abs_ov32 \pipe_middle_3_dive_abs_ov32$147 + sync init + end + process $group_167 + assign \pipe_middle_4_dive_abs_ov64 1'0 + assign \pipe_middle_4_dive_abs_ov64 \pipe_middle_3_dive_abs_ov64$148 + sync init + end + process $group_168 + assign \pipe_middle_4_div_by_zero 1'0 + assign \pipe_middle_4_div_by_zero \pipe_middle_3_div_by_zero$149 + sync init + end + process $group_169 + assign \pipe_middle_4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_4_divisor_radicand \pipe_middle_3_divisor_radicand$150 + sync init + end + process $group_170 + assign \pipe_middle_4_operation 2'00 + assign \pipe_middle_4_operation \pipe_middle_3_operation$151 + sync init + end + process $group_171 + assign \pipe_middle_4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_4_quotient_root \pipe_middle_3_quotient_root$152 + sync init + end + process $group_172 + assign \pipe_middle_4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_4_root_times_radicand \pipe_middle_3_root_times_radicand$153 + sync init + end + process $group_173 + assign \pipe_middle_4_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_4_compare_lhs \pipe_middle_3_compare_lhs$154 + sync init + end + process $group_174 + assign \pipe_middle_4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_4_compare_rhs \pipe_middle_3_compare_rhs$155 + sync init + end + process $group_175 + assign \pipe_middle_5_p_valid_i 1'0 + assign \pipe_middle_5_p_valid_i \pipe_middle_4_n_valid_o + sync init + end + process $group_176 + assign \pipe_middle_4_n_ready_i 1'0 + assign \pipe_middle_4_n_ready_i \pipe_middle_5_p_ready_o + sync init + end + process $group_177 + assign \pipe_middle_5_muxid 2'00 + assign \pipe_middle_5_muxid \pipe_middle_4_muxid$156 + sync init + end + process $group_178 + assign \pipe_middle_5_logical_op__insn_type 7'0000000 + assign \pipe_middle_5_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_5_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_5_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_5_logical_op__rc__rc 1'0 + assign \pipe_middle_5_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_5_logical_op__oe__oe 1'0 + assign \pipe_middle_5_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_5_logical_op__invert_in 1'0 + assign \pipe_middle_5_logical_op__zero_a 1'0 + assign \pipe_middle_5_logical_op__input_carry 2'00 + assign \pipe_middle_5_logical_op__invert_out 1'0 + assign \pipe_middle_5_logical_op__write_cr0 1'0 + assign \pipe_middle_5_logical_op__output_carry 1'0 + assign \pipe_middle_5_logical_op__is_32bit 1'0 + assign \pipe_middle_5_logical_op__is_signed 1'0 + assign \pipe_middle_5_logical_op__data_len 4'0000 + assign \pipe_middle_5_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_5_logical_op__insn \pipe_middle_5_logical_op__data_len \pipe_middle_5_logical_op__is_signed \pipe_middle_5_logical_op__is_32bit \pipe_middle_5_logical_op__output_carry \pipe_middle_5_logical_op__write_cr0 \pipe_middle_5_logical_op__invert_out \pipe_middle_5_logical_op__input_carry \pipe_middle_5_logical_op__zero_a \pipe_middle_5_logical_op__invert_in { \pipe_middle_5_logical_op__oe__oe_ok \pipe_middle_5_logical_op__oe__oe } { \pipe_middle_5_logical_op__rc__rc_ok \pipe_middle_5_logical_op__rc__rc } { \pipe_middle_5_logical_op__imm_data__imm_ok \pipe_middle_5_logical_op__imm_data__imm } \pipe_middle_5_logical_op__fn_unit \pipe_middle_5_logical_op__insn_type } { \pipe_middle_4_logical_op__insn$174 \pipe_middle_4_logical_op__data_len$173 \pipe_middle_4_logical_op__is_signed$172 \pipe_middle_4_logical_op__is_32bit$171 \pipe_middle_4_logical_op__output_carry$170 \pipe_middle_4_logical_op__write_cr0$169 \pipe_middle_4_logical_op__invert_out$168 \pipe_middle_4_logical_op__input_carry$167 \pipe_middle_4_logical_op__zero_a$166 \pipe_middle_4_logical_op__invert_in$165 { \pipe_middle_4_logical_op__oe__oe_ok$164 \pipe_middle_4_logical_op__oe__oe$163 } { \pipe_middle_4_logical_op__rc__rc_ok$162 \pipe_middle_4_logical_op__rc__rc$161 } { \pipe_middle_4_logical_op__imm_data__imm_ok$160 \pipe_middle_4_logical_op__imm_data__imm$159 } \pipe_middle_4_logical_op__fn_unit$158 \pipe_middle_4_logical_op__insn_type$157 } + sync init + end + process $group_196 + assign \pipe_middle_5_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_5_ra \pipe_middle_4_ra$175 + sync init + end + process $group_197 + assign \pipe_middle_5_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_5_rb \pipe_middle_4_rb$176 + sync init + end + process $group_198 + assign \pipe_middle_5_xer_so 1'0 + assign \pipe_middle_5_xer_so \pipe_middle_4_xer_so$177 + sync init + end + process $group_199 + assign \pipe_middle_5_divisor_neg 1'0 + assign \pipe_middle_5_divisor_neg \pipe_middle_4_divisor_neg$178 + sync init + end + process $group_200 + assign \pipe_middle_5_dividend_neg 1'0 + assign \pipe_middle_5_dividend_neg \pipe_middle_4_dividend_neg$179 + sync init + end + process $group_201 + assign \pipe_middle_5_dive_abs_ov32 1'0 + assign \pipe_middle_5_dive_abs_ov32 \pipe_middle_4_dive_abs_ov32$180 + sync init + end + process $group_202 + assign \pipe_middle_5_dive_abs_ov64 1'0 + assign \pipe_middle_5_dive_abs_ov64 \pipe_middle_4_dive_abs_ov64$181 + sync init + end + process $group_203 + assign \pipe_middle_5_div_by_zero 1'0 + assign \pipe_middle_5_div_by_zero \pipe_middle_4_div_by_zero$182 + sync init + end + process $group_204 + assign \pipe_middle_5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_5_divisor_radicand \pipe_middle_4_divisor_radicand$183 + sync init + end + process $group_205 + assign \pipe_middle_5_operation 2'00 + assign \pipe_middle_5_operation \pipe_middle_4_operation$184 + sync init + end + process $group_206 + assign \pipe_middle_5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_5_quotient_root \pipe_middle_4_quotient_root$185 + sync init + end + process $group_207 + assign \pipe_middle_5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_5_root_times_radicand \pipe_middle_4_root_times_radicand$186 + sync init + end + process $group_208 + assign \pipe_middle_5_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_5_compare_lhs \pipe_middle_4_compare_lhs$187 + sync init + end + process $group_209 + assign \pipe_middle_5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_5_compare_rhs \pipe_middle_4_compare_rhs$188 + sync init + end + process $group_210 + assign \pipe_middle_6_p_valid_i 1'0 + assign \pipe_middle_6_p_valid_i \pipe_middle_5_n_valid_o + sync init + end + process $group_211 + assign \pipe_middle_5_n_ready_i 1'0 + assign \pipe_middle_5_n_ready_i \pipe_middle_6_p_ready_o + sync init + end + process $group_212 + assign \pipe_middle_6_muxid 2'00 + assign \pipe_middle_6_muxid \pipe_middle_5_muxid$189 + sync init + end + process $group_213 + assign \pipe_middle_6_logical_op__insn_type 7'0000000 + assign \pipe_middle_6_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_6_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_6_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_6_logical_op__rc__rc 1'0 + assign \pipe_middle_6_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_6_logical_op__oe__oe 1'0 + assign \pipe_middle_6_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_6_logical_op__invert_in 1'0 + assign \pipe_middle_6_logical_op__zero_a 1'0 + assign \pipe_middle_6_logical_op__input_carry 2'00 + assign \pipe_middle_6_logical_op__invert_out 1'0 + assign \pipe_middle_6_logical_op__write_cr0 1'0 + assign \pipe_middle_6_logical_op__output_carry 1'0 + assign \pipe_middle_6_logical_op__is_32bit 1'0 + assign \pipe_middle_6_logical_op__is_signed 1'0 + assign \pipe_middle_6_logical_op__data_len 4'0000 + assign \pipe_middle_6_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_6_logical_op__insn \pipe_middle_6_logical_op__data_len \pipe_middle_6_logical_op__is_signed \pipe_middle_6_logical_op__is_32bit \pipe_middle_6_logical_op__output_carry \pipe_middle_6_logical_op__write_cr0 \pipe_middle_6_logical_op__invert_out \pipe_middle_6_logical_op__input_carry \pipe_middle_6_logical_op__zero_a \pipe_middle_6_logical_op__invert_in { \pipe_middle_6_logical_op__oe__oe_ok \pipe_middle_6_logical_op__oe__oe } { \pipe_middle_6_logical_op__rc__rc_ok \pipe_middle_6_logical_op__rc__rc } { \pipe_middle_6_logical_op__imm_data__imm_ok \pipe_middle_6_logical_op__imm_data__imm } \pipe_middle_6_logical_op__fn_unit \pipe_middle_6_logical_op__insn_type } { \pipe_middle_5_logical_op__insn$207 \pipe_middle_5_logical_op__data_len$206 \pipe_middle_5_logical_op__is_signed$205 \pipe_middle_5_logical_op__is_32bit$204 \pipe_middle_5_logical_op__output_carry$203 \pipe_middle_5_logical_op__write_cr0$202 \pipe_middle_5_logical_op__invert_out$201 \pipe_middle_5_logical_op__input_carry$200 \pipe_middle_5_logical_op__zero_a$199 \pipe_middle_5_logical_op__invert_in$198 { \pipe_middle_5_logical_op__oe__oe_ok$197 \pipe_middle_5_logical_op__oe__oe$196 } { \pipe_middle_5_logical_op__rc__rc_ok$195 \pipe_middle_5_logical_op__rc__rc$194 } { \pipe_middle_5_logical_op__imm_data__imm_ok$193 \pipe_middle_5_logical_op__imm_data__imm$192 } \pipe_middle_5_logical_op__fn_unit$191 \pipe_middle_5_logical_op__insn_type$190 } + sync init + end + process $group_231 + assign \pipe_middle_6_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_6_ra \pipe_middle_5_ra$208 + sync init + end + process $group_232 + assign \pipe_middle_6_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_6_rb \pipe_middle_5_rb$209 + sync init + end + process $group_233 + assign \pipe_middle_6_xer_so 1'0 + assign \pipe_middle_6_xer_so \pipe_middle_5_xer_so$210 + sync init + end + process $group_234 + assign \pipe_middle_6_divisor_neg 1'0 + assign \pipe_middle_6_divisor_neg \pipe_middle_5_divisor_neg$211 + sync init + end + process $group_235 + assign \pipe_middle_6_dividend_neg 1'0 + assign \pipe_middle_6_dividend_neg \pipe_middle_5_dividend_neg$212 + sync init + end + process $group_236 + assign \pipe_middle_6_dive_abs_ov32 1'0 + assign \pipe_middle_6_dive_abs_ov32 \pipe_middle_5_dive_abs_ov32$213 + sync init + end + process $group_237 + assign \pipe_middle_6_dive_abs_ov64 1'0 + assign \pipe_middle_6_dive_abs_ov64 \pipe_middle_5_dive_abs_ov64$214 + sync init + end + process $group_238 + assign \pipe_middle_6_div_by_zero 1'0 + assign \pipe_middle_6_div_by_zero \pipe_middle_5_div_by_zero$215 + sync init + end + process $group_239 + assign \pipe_middle_6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_6_divisor_radicand \pipe_middle_5_divisor_radicand$216 + sync init + end + process $group_240 + assign \pipe_middle_6_operation 2'00 + assign \pipe_middle_6_operation \pipe_middle_5_operation$217 + sync init + end + process $group_241 + assign \pipe_middle_6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_6_quotient_root \pipe_middle_5_quotient_root$218 + sync init + end + process $group_242 + assign \pipe_middle_6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_6_root_times_radicand \pipe_middle_5_root_times_radicand$219 + sync init + end + process $group_243 + assign \pipe_middle_6_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_6_compare_lhs \pipe_middle_5_compare_lhs$220 + sync init + end + process $group_244 + assign \pipe_middle_6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_6_compare_rhs \pipe_middle_5_compare_rhs$221 + sync init + end + process $group_245 + assign \pipe_middle_7_p_valid_i 1'0 + assign \pipe_middle_7_p_valid_i \pipe_middle_6_n_valid_o + sync init + end + process $group_246 + assign \pipe_middle_6_n_ready_i 1'0 + assign \pipe_middle_6_n_ready_i \pipe_middle_7_p_ready_o + sync init + end + process $group_247 + assign \pipe_middle_7_muxid 2'00 + assign \pipe_middle_7_muxid \pipe_middle_6_muxid$222 + sync init + end + process $group_248 + assign \pipe_middle_7_logical_op__insn_type 7'0000000 + assign \pipe_middle_7_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_7_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_7_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_7_logical_op__rc__rc 1'0 + assign \pipe_middle_7_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_7_logical_op__oe__oe 1'0 + assign \pipe_middle_7_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_7_logical_op__invert_in 1'0 + assign \pipe_middle_7_logical_op__zero_a 1'0 + assign \pipe_middle_7_logical_op__input_carry 2'00 + assign \pipe_middle_7_logical_op__invert_out 1'0 + assign \pipe_middle_7_logical_op__write_cr0 1'0 + assign \pipe_middle_7_logical_op__output_carry 1'0 + assign \pipe_middle_7_logical_op__is_32bit 1'0 + assign \pipe_middle_7_logical_op__is_signed 1'0 + assign \pipe_middle_7_logical_op__data_len 4'0000 + assign \pipe_middle_7_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_7_logical_op__insn \pipe_middle_7_logical_op__data_len \pipe_middle_7_logical_op__is_signed \pipe_middle_7_logical_op__is_32bit \pipe_middle_7_logical_op__output_carry \pipe_middle_7_logical_op__write_cr0 \pipe_middle_7_logical_op__invert_out \pipe_middle_7_logical_op__input_carry \pipe_middle_7_logical_op__zero_a \pipe_middle_7_logical_op__invert_in { \pipe_middle_7_logical_op__oe__oe_ok \pipe_middle_7_logical_op__oe__oe } { \pipe_middle_7_logical_op__rc__rc_ok \pipe_middle_7_logical_op__rc__rc } { \pipe_middle_7_logical_op__imm_data__imm_ok \pipe_middle_7_logical_op__imm_data__imm } \pipe_middle_7_logical_op__fn_unit \pipe_middle_7_logical_op__insn_type } { \pipe_middle_6_logical_op__insn$240 \pipe_middle_6_logical_op__data_len$239 \pipe_middle_6_logical_op__is_signed$238 \pipe_middle_6_logical_op__is_32bit$237 \pipe_middle_6_logical_op__output_carry$236 \pipe_middle_6_logical_op__write_cr0$235 \pipe_middle_6_logical_op__invert_out$234 \pipe_middle_6_logical_op__input_carry$233 \pipe_middle_6_logical_op__zero_a$232 \pipe_middle_6_logical_op__invert_in$231 { \pipe_middle_6_logical_op__oe__oe_ok$230 \pipe_middle_6_logical_op__oe__oe$229 } { \pipe_middle_6_logical_op__rc__rc_ok$228 \pipe_middle_6_logical_op__rc__rc$227 } { \pipe_middle_6_logical_op__imm_data__imm_ok$226 \pipe_middle_6_logical_op__imm_data__imm$225 } \pipe_middle_6_logical_op__fn_unit$224 \pipe_middle_6_logical_op__insn_type$223 } + sync init + end + process $group_266 + assign \pipe_middle_7_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_7_ra \pipe_middle_6_ra$241 + sync init + end + process $group_267 + assign \pipe_middle_7_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_7_rb \pipe_middle_6_rb$242 + sync init + end + process $group_268 + assign \pipe_middle_7_xer_so 1'0 + assign \pipe_middle_7_xer_so \pipe_middle_6_xer_so$243 + sync init + end + process $group_269 + assign \pipe_middle_7_divisor_neg 1'0 + assign \pipe_middle_7_divisor_neg \pipe_middle_6_divisor_neg$244 + sync init + end + process $group_270 + assign \pipe_middle_7_dividend_neg 1'0 + assign \pipe_middle_7_dividend_neg \pipe_middle_6_dividend_neg$245 + sync init + end + process $group_271 + assign \pipe_middle_7_dive_abs_ov32 1'0 + assign \pipe_middle_7_dive_abs_ov32 \pipe_middle_6_dive_abs_ov32$246 + sync init + end + process $group_272 + assign \pipe_middle_7_dive_abs_ov64 1'0 + assign \pipe_middle_7_dive_abs_ov64 \pipe_middle_6_dive_abs_ov64$247 + sync init + end + process $group_273 + assign \pipe_middle_7_div_by_zero 1'0 + assign \pipe_middle_7_div_by_zero \pipe_middle_6_div_by_zero$248 + sync init + end + process $group_274 + assign \pipe_middle_7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_7_divisor_radicand \pipe_middle_6_divisor_radicand$249 + sync init + end + process $group_275 + assign \pipe_middle_7_operation 2'00 + assign \pipe_middle_7_operation \pipe_middle_6_operation$250 + sync init + end + process $group_276 + assign \pipe_middle_7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_7_quotient_root \pipe_middle_6_quotient_root$251 + sync init + end + process $group_277 + assign \pipe_middle_7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_7_root_times_radicand \pipe_middle_6_root_times_radicand$252 + sync init + end + process $group_278 + assign \pipe_middle_7_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_7_compare_lhs \pipe_middle_6_compare_lhs$253 + sync init + end + process $group_279 + assign \pipe_middle_7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_7_compare_rhs \pipe_middle_6_compare_rhs$254 + sync init + end + process $group_280 + assign \pipe_middle_8_p_valid_i 1'0 + assign \pipe_middle_8_p_valid_i \pipe_middle_7_n_valid_o + sync init + end + process $group_281 + assign \pipe_middle_7_n_ready_i 1'0 + assign \pipe_middle_7_n_ready_i \pipe_middle_8_p_ready_o + sync init + end + process $group_282 + assign \pipe_middle_8_muxid 2'00 + assign \pipe_middle_8_muxid \pipe_middle_7_muxid$255 + sync init + end + process $group_283 + assign \pipe_middle_8_logical_op__insn_type 7'0000000 + assign \pipe_middle_8_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_8_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_8_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_8_logical_op__rc__rc 1'0 + assign \pipe_middle_8_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_8_logical_op__oe__oe 1'0 + assign \pipe_middle_8_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_8_logical_op__invert_in 1'0 + assign \pipe_middle_8_logical_op__zero_a 1'0 + assign \pipe_middle_8_logical_op__input_carry 2'00 + assign \pipe_middle_8_logical_op__invert_out 1'0 + assign \pipe_middle_8_logical_op__write_cr0 1'0 + assign \pipe_middle_8_logical_op__output_carry 1'0 + assign \pipe_middle_8_logical_op__is_32bit 1'0 + assign \pipe_middle_8_logical_op__is_signed 1'0 + assign \pipe_middle_8_logical_op__data_len 4'0000 + assign \pipe_middle_8_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_8_logical_op__insn \pipe_middle_8_logical_op__data_len \pipe_middle_8_logical_op__is_signed \pipe_middle_8_logical_op__is_32bit \pipe_middle_8_logical_op__output_carry \pipe_middle_8_logical_op__write_cr0 \pipe_middle_8_logical_op__invert_out \pipe_middle_8_logical_op__input_carry \pipe_middle_8_logical_op__zero_a \pipe_middle_8_logical_op__invert_in { \pipe_middle_8_logical_op__oe__oe_ok \pipe_middle_8_logical_op__oe__oe } { \pipe_middle_8_logical_op__rc__rc_ok \pipe_middle_8_logical_op__rc__rc } { \pipe_middle_8_logical_op__imm_data__imm_ok \pipe_middle_8_logical_op__imm_data__imm } \pipe_middle_8_logical_op__fn_unit \pipe_middle_8_logical_op__insn_type } { \pipe_middle_7_logical_op__insn$273 \pipe_middle_7_logical_op__data_len$272 \pipe_middle_7_logical_op__is_signed$271 \pipe_middle_7_logical_op__is_32bit$270 \pipe_middle_7_logical_op__output_carry$269 \pipe_middle_7_logical_op__write_cr0$268 \pipe_middle_7_logical_op__invert_out$267 \pipe_middle_7_logical_op__input_carry$266 \pipe_middle_7_logical_op__zero_a$265 \pipe_middle_7_logical_op__invert_in$264 { \pipe_middle_7_logical_op__oe__oe_ok$263 \pipe_middle_7_logical_op__oe__oe$262 } { \pipe_middle_7_logical_op__rc__rc_ok$261 \pipe_middle_7_logical_op__rc__rc$260 } { \pipe_middle_7_logical_op__imm_data__imm_ok$259 \pipe_middle_7_logical_op__imm_data__imm$258 } \pipe_middle_7_logical_op__fn_unit$257 \pipe_middle_7_logical_op__insn_type$256 } + sync init + end + process $group_301 + assign \pipe_middle_8_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_8_ra \pipe_middle_7_ra$274 + sync init + end + process $group_302 + assign \pipe_middle_8_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_8_rb \pipe_middle_7_rb$275 + sync init + end + process $group_303 + assign \pipe_middle_8_xer_so 1'0 + assign \pipe_middle_8_xer_so \pipe_middle_7_xer_so$276 + sync init + end + process $group_304 + assign \pipe_middle_8_divisor_neg 1'0 + assign \pipe_middle_8_divisor_neg \pipe_middle_7_divisor_neg$277 + sync init + end + process $group_305 + assign \pipe_middle_8_dividend_neg 1'0 + assign \pipe_middle_8_dividend_neg \pipe_middle_7_dividend_neg$278 + sync init + end + process $group_306 + assign \pipe_middle_8_dive_abs_ov32 1'0 + assign \pipe_middle_8_dive_abs_ov32 \pipe_middle_7_dive_abs_ov32$279 + sync init + end + process $group_307 + assign \pipe_middle_8_dive_abs_ov64 1'0 + assign \pipe_middle_8_dive_abs_ov64 \pipe_middle_7_dive_abs_ov64$280 + sync init + end + process $group_308 + assign \pipe_middle_8_div_by_zero 1'0 + assign \pipe_middle_8_div_by_zero \pipe_middle_7_div_by_zero$281 + sync init + end + process $group_309 + assign \pipe_middle_8_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_8_divisor_radicand \pipe_middle_7_divisor_radicand$282 + sync init + end + process $group_310 + assign \pipe_middle_8_operation 2'00 + assign \pipe_middle_8_operation \pipe_middle_7_operation$283 + sync init + end + process $group_311 + assign \pipe_middle_8_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_8_quotient_root \pipe_middle_7_quotient_root$284 + sync init + end + process $group_312 + assign \pipe_middle_8_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_8_root_times_radicand \pipe_middle_7_root_times_radicand$285 + sync init + end + process $group_313 + assign \pipe_middle_8_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_8_compare_lhs \pipe_middle_7_compare_lhs$286 + sync init + end + process $group_314 + assign \pipe_middle_8_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_8_compare_rhs \pipe_middle_7_compare_rhs$287 + sync init + end + process $group_315 + assign \pipe_middle_9_p_valid_i 1'0 + assign \pipe_middle_9_p_valid_i \pipe_middle_8_n_valid_o + sync init + end + process $group_316 + assign \pipe_middle_8_n_ready_i 1'0 + assign \pipe_middle_8_n_ready_i \pipe_middle_9_p_ready_o + sync init + end + process $group_317 + assign \pipe_middle_9_muxid 2'00 + assign \pipe_middle_9_muxid \pipe_middle_8_muxid$288 + sync init + end + process $group_318 + assign \pipe_middle_9_logical_op__insn_type 7'0000000 + assign \pipe_middle_9_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_9_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_9_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_9_logical_op__rc__rc 1'0 + assign \pipe_middle_9_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_9_logical_op__oe__oe 1'0 + assign \pipe_middle_9_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_9_logical_op__invert_in 1'0 + assign \pipe_middle_9_logical_op__zero_a 1'0 + assign \pipe_middle_9_logical_op__input_carry 2'00 + assign \pipe_middle_9_logical_op__invert_out 1'0 + assign \pipe_middle_9_logical_op__write_cr0 1'0 + assign \pipe_middle_9_logical_op__output_carry 1'0 + assign \pipe_middle_9_logical_op__is_32bit 1'0 + assign \pipe_middle_9_logical_op__is_signed 1'0 + assign \pipe_middle_9_logical_op__data_len 4'0000 + assign \pipe_middle_9_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_9_logical_op__insn \pipe_middle_9_logical_op__data_len \pipe_middle_9_logical_op__is_signed \pipe_middle_9_logical_op__is_32bit \pipe_middle_9_logical_op__output_carry \pipe_middle_9_logical_op__write_cr0 \pipe_middle_9_logical_op__invert_out \pipe_middle_9_logical_op__input_carry \pipe_middle_9_logical_op__zero_a \pipe_middle_9_logical_op__invert_in { \pipe_middle_9_logical_op__oe__oe_ok \pipe_middle_9_logical_op__oe__oe } { \pipe_middle_9_logical_op__rc__rc_ok \pipe_middle_9_logical_op__rc__rc } { \pipe_middle_9_logical_op__imm_data__imm_ok \pipe_middle_9_logical_op__imm_data__imm } \pipe_middle_9_logical_op__fn_unit \pipe_middle_9_logical_op__insn_type } { \pipe_middle_8_logical_op__insn$306 \pipe_middle_8_logical_op__data_len$305 \pipe_middle_8_logical_op__is_signed$304 \pipe_middle_8_logical_op__is_32bit$303 \pipe_middle_8_logical_op__output_carry$302 \pipe_middle_8_logical_op__write_cr0$301 \pipe_middle_8_logical_op__invert_out$300 \pipe_middle_8_logical_op__input_carry$299 \pipe_middle_8_logical_op__zero_a$298 \pipe_middle_8_logical_op__invert_in$297 { \pipe_middle_8_logical_op__oe__oe_ok$296 \pipe_middle_8_logical_op__oe__oe$295 } { \pipe_middle_8_logical_op__rc__rc_ok$294 \pipe_middle_8_logical_op__rc__rc$293 } { \pipe_middle_8_logical_op__imm_data__imm_ok$292 \pipe_middle_8_logical_op__imm_data__imm$291 } \pipe_middle_8_logical_op__fn_unit$290 \pipe_middle_8_logical_op__insn_type$289 } + sync init + end + process $group_336 + assign \pipe_middle_9_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_9_ra \pipe_middle_8_ra$307 + sync init + end + process $group_337 + assign \pipe_middle_9_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_9_rb \pipe_middle_8_rb$308 + sync init + end + process $group_338 + assign \pipe_middle_9_xer_so 1'0 + assign \pipe_middle_9_xer_so \pipe_middle_8_xer_so$309 + sync init + end + process $group_339 + assign \pipe_middle_9_divisor_neg 1'0 + assign \pipe_middle_9_divisor_neg \pipe_middle_8_divisor_neg$310 + sync init + end + process $group_340 + assign \pipe_middle_9_dividend_neg 1'0 + assign \pipe_middle_9_dividend_neg \pipe_middle_8_dividend_neg$311 + sync init + end + process $group_341 + assign \pipe_middle_9_dive_abs_ov32 1'0 + assign \pipe_middle_9_dive_abs_ov32 \pipe_middle_8_dive_abs_ov32$312 + sync init + end + process $group_342 + assign \pipe_middle_9_dive_abs_ov64 1'0 + assign \pipe_middle_9_dive_abs_ov64 \pipe_middle_8_dive_abs_ov64$313 + sync init + end + process $group_343 + assign \pipe_middle_9_div_by_zero 1'0 + assign \pipe_middle_9_div_by_zero \pipe_middle_8_div_by_zero$314 + sync init + end + process $group_344 + assign \pipe_middle_9_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_9_divisor_radicand \pipe_middle_8_divisor_radicand$315 + sync init + end + process $group_345 + assign \pipe_middle_9_operation 2'00 + assign \pipe_middle_9_operation \pipe_middle_8_operation$316 + sync init + end + process $group_346 + assign \pipe_middle_9_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_9_quotient_root \pipe_middle_8_quotient_root$317 + sync init + end + process $group_347 + assign \pipe_middle_9_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_9_root_times_radicand \pipe_middle_8_root_times_radicand$318 + sync init + end + process $group_348 + assign \pipe_middle_9_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_9_compare_lhs \pipe_middle_8_compare_lhs$319 + sync init + end + process $group_349 + assign \pipe_middle_9_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_9_compare_rhs \pipe_middle_8_compare_rhs$320 + sync init + end + process $group_350 + assign \pipe_middle_10_p_valid_i 1'0 + assign \pipe_middle_10_p_valid_i \pipe_middle_9_n_valid_o + sync init + end + process $group_351 + assign \pipe_middle_9_n_ready_i 1'0 + assign \pipe_middle_9_n_ready_i \pipe_middle_10_p_ready_o + sync init + end + process $group_352 + assign \pipe_middle_10_muxid 2'00 + assign \pipe_middle_10_muxid \pipe_middle_9_muxid$321 + sync init + end + process $group_353 + assign \pipe_middle_10_logical_op__insn_type 7'0000000 + assign \pipe_middle_10_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_10_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_10_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_10_logical_op__rc__rc 1'0 + assign \pipe_middle_10_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_10_logical_op__oe__oe 1'0 + assign \pipe_middle_10_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_10_logical_op__invert_in 1'0 + assign \pipe_middle_10_logical_op__zero_a 1'0 + assign \pipe_middle_10_logical_op__input_carry 2'00 + assign \pipe_middle_10_logical_op__invert_out 1'0 + assign \pipe_middle_10_logical_op__write_cr0 1'0 + assign \pipe_middle_10_logical_op__output_carry 1'0 + assign \pipe_middle_10_logical_op__is_32bit 1'0 + assign \pipe_middle_10_logical_op__is_signed 1'0 + assign \pipe_middle_10_logical_op__data_len 4'0000 + assign \pipe_middle_10_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_10_logical_op__insn \pipe_middle_10_logical_op__data_len \pipe_middle_10_logical_op__is_signed \pipe_middle_10_logical_op__is_32bit \pipe_middle_10_logical_op__output_carry \pipe_middle_10_logical_op__write_cr0 \pipe_middle_10_logical_op__invert_out \pipe_middle_10_logical_op__input_carry \pipe_middle_10_logical_op__zero_a \pipe_middle_10_logical_op__invert_in { \pipe_middle_10_logical_op__oe__oe_ok \pipe_middle_10_logical_op__oe__oe } { \pipe_middle_10_logical_op__rc__rc_ok \pipe_middle_10_logical_op__rc__rc } { \pipe_middle_10_logical_op__imm_data__imm_ok \pipe_middle_10_logical_op__imm_data__imm } \pipe_middle_10_logical_op__fn_unit \pipe_middle_10_logical_op__insn_type } { \pipe_middle_9_logical_op__insn$339 \pipe_middle_9_logical_op__data_len$338 \pipe_middle_9_logical_op__is_signed$337 \pipe_middle_9_logical_op__is_32bit$336 \pipe_middle_9_logical_op__output_carry$335 \pipe_middle_9_logical_op__write_cr0$334 \pipe_middle_9_logical_op__invert_out$333 \pipe_middle_9_logical_op__input_carry$332 \pipe_middle_9_logical_op__zero_a$331 \pipe_middle_9_logical_op__invert_in$330 { \pipe_middle_9_logical_op__oe__oe_ok$329 \pipe_middle_9_logical_op__oe__oe$328 } { \pipe_middle_9_logical_op__rc__rc_ok$327 \pipe_middle_9_logical_op__rc__rc$326 } { \pipe_middle_9_logical_op__imm_data__imm_ok$325 \pipe_middle_9_logical_op__imm_data__imm$324 } \pipe_middle_9_logical_op__fn_unit$323 \pipe_middle_9_logical_op__insn_type$322 } + sync init + end + process $group_371 + assign \pipe_middle_10_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_10_ra \pipe_middle_9_ra$340 + sync init + end + process $group_372 + assign \pipe_middle_10_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_10_rb \pipe_middle_9_rb$341 + sync init + end + process $group_373 + assign \pipe_middle_10_xer_so 1'0 + assign \pipe_middle_10_xer_so \pipe_middle_9_xer_so$342 + sync init + end + process $group_374 + assign \pipe_middle_10_divisor_neg 1'0 + assign \pipe_middle_10_divisor_neg \pipe_middle_9_divisor_neg$343 + sync init + end + process $group_375 + assign \pipe_middle_10_dividend_neg 1'0 + assign \pipe_middle_10_dividend_neg \pipe_middle_9_dividend_neg$344 + sync init + end + process $group_376 + assign \pipe_middle_10_dive_abs_ov32 1'0 + assign \pipe_middle_10_dive_abs_ov32 \pipe_middle_9_dive_abs_ov32$345 + sync init + end + process $group_377 + assign \pipe_middle_10_dive_abs_ov64 1'0 + assign \pipe_middle_10_dive_abs_ov64 \pipe_middle_9_dive_abs_ov64$346 + sync init + end + process $group_378 + assign \pipe_middle_10_div_by_zero 1'0 + assign \pipe_middle_10_div_by_zero \pipe_middle_9_div_by_zero$347 + sync init + end + process $group_379 + assign \pipe_middle_10_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_10_divisor_radicand \pipe_middle_9_divisor_radicand$348 + sync init + end + process $group_380 + assign \pipe_middle_10_operation 2'00 + assign \pipe_middle_10_operation \pipe_middle_9_operation$349 + sync init + end + process $group_381 + assign \pipe_middle_10_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_10_quotient_root \pipe_middle_9_quotient_root$350 + sync init + end + process $group_382 + assign \pipe_middle_10_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_10_root_times_radicand \pipe_middle_9_root_times_radicand$351 + sync init + end + process $group_383 + assign \pipe_middle_10_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_10_compare_lhs \pipe_middle_9_compare_lhs$352 + sync init + end + process $group_384 + assign \pipe_middle_10_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_10_compare_rhs \pipe_middle_9_compare_rhs$353 + sync init + end + process $group_385 + assign \pipe_middle_11_p_valid_i 1'0 + assign \pipe_middle_11_p_valid_i \pipe_middle_10_n_valid_o + sync init + end + process $group_386 + assign \pipe_middle_10_n_ready_i 1'0 + assign \pipe_middle_10_n_ready_i \pipe_middle_11_p_ready_o + sync init + end + process $group_387 + assign \pipe_middle_11_muxid 2'00 + assign \pipe_middle_11_muxid \pipe_middle_10_muxid$354 + sync init + end + process $group_388 + assign \pipe_middle_11_logical_op__insn_type 7'0000000 + assign \pipe_middle_11_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_11_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_11_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_11_logical_op__rc__rc 1'0 + assign \pipe_middle_11_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_11_logical_op__oe__oe 1'0 + assign \pipe_middle_11_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_11_logical_op__invert_in 1'0 + assign \pipe_middle_11_logical_op__zero_a 1'0 + assign \pipe_middle_11_logical_op__input_carry 2'00 + assign \pipe_middle_11_logical_op__invert_out 1'0 + assign \pipe_middle_11_logical_op__write_cr0 1'0 + assign \pipe_middle_11_logical_op__output_carry 1'0 + assign \pipe_middle_11_logical_op__is_32bit 1'0 + assign \pipe_middle_11_logical_op__is_signed 1'0 + assign \pipe_middle_11_logical_op__data_len 4'0000 + assign \pipe_middle_11_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_11_logical_op__insn \pipe_middle_11_logical_op__data_len \pipe_middle_11_logical_op__is_signed \pipe_middle_11_logical_op__is_32bit \pipe_middle_11_logical_op__output_carry \pipe_middle_11_logical_op__write_cr0 \pipe_middle_11_logical_op__invert_out \pipe_middle_11_logical_op__input_carry \pipe_middle_11_logical_op__zero_a \pipe_middle_11_logical_op__invert_in { \pipe_middle_11_logical_op__oe__oe_ok \pipe_middle_11_logical_op__oe__oe } { \pipe_middle_11_logical_op__rc__rc_ok \pipe_middle_11_logical_op__rc__rc } { \pipe_middle_11_logical_op__imm_data__imm_ok \pipe_middle_11_logical_op__imm_data__imm } \pipe_middle_11_logical_op__fn_unit \pipe_middle_11_logical_op__insn_type } { \pipe_middle_10_logical_op__insn$372 \pipe_middle_10_logical_op__data_len$371 \pipe_middle_10_logical_op__is_signed$370 \pipe_middle_10_logical_op__is_32bit$369 \pipe_middle_10_logical_op__output_carry$368 \pipe_middle_10_logical_op__write_cr0$367 \pipe_middle_10_logical_op__invert_out$366 \pipe_middle_10_logical_op__input_carry$365 \pipe_middle_10_logical_op__zero_a$364 \pipe_middle_10_logical_op__invert_in$363 { \pipe_middle_10_logical_op__oe__oe_ok$362 \pipe_middle_10_logical_op__oe__oe$361 } { \pipe_middle_10_logical_op__rc__rc_ok$360 \pipe_middle_10_logical_op__rc__rc$359 } { \pipe_middle_10_logical_op__imm_data__imm_ok$358 \pipe_middle_10_logical_op__imm_data__imm$357 } \pipe_middle_10_logical_op__fn_unit$356 \pipe_middle_10_logical_op__insn_type$355 } + sync init + end + process $group_406 + assign \pipe_middle_11_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_11_ra \pipe_middle_10_ra$373 + sync init + end + process $group_407 + assign \pipe_middle_11_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_11_rb \pipe_middle_10_rb$374 + sync init + end + process $group_408 + assign \pipe_middle_11_xer_so 1'0 + assign \pipe_middle_11_xer_so \pipe_middle_10_xer_so$375 + sync init + end + process $group_409 + assign \pipe_middle_11_divisor_neg 1'0 + assign \pipe_middle_11_divisor_neg \pipe_middle_10_divisor_neg$376 + sync init + end + process $group_410 + assign \pipe_middle_11_dividend_neg 1'0 + assign \pipe_middle_11_dividend_neg \pipe_middle_10_dividend_neg$377 + sync init + end + process $group_411 + assign \pipe_middle_11_dive_abs_ov32 1'0 + assign \pipe_middle_11_dive_abs_ov32 \pipe_middle_10_dive_abs_ov32$378 + sync init + end + process $group_412 + assign \pipe_middle_11_dive_abs_ov64 1'0 + assign \pipe_middle_11_dive_abs_ov64 \pipe_middle_10_dive_abs_ov64$379 + sync init + end + process $group_413 + assign \pipe_middle_11_div_by_zero 1'0 + assign \pipe_middle_11_div_by_zero \pipe_middle_10_div_by_zero$380 + sync init + end + process $group_414 + assign \pipe_middle_11_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_11_divisor_radicand \pipe_middle_10_divisor_radicand$381 + sync init + end + process $group_415 + assign \pipe_middle_11_operation 2'00 + assign \pipe_middle_11_operation \pipe_middle_10_operation$382 + sync init + end + process $group_416 + assign \pipe_middle_11_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_11_quotient_root \pipe_middle_10_quotient_root$383 + sync init + end + process $group_417 + assign \pipe_middle_11_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_11_root_times_radicand \pipe_middle_10_root_times_radicand$384 + sync init + end + process $group_418 + assign \pipe_middle_11_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_11_compare_lhs \pipe_middle_10_compare_lhs$385 + sync init + end + process $group_419 + assign \pipe_middle_11_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_11_compare_rhs \pipe_middle_10_compare_rhs$386 + sync init + end + process $group_420 + assign \pipe_middle_12_p_valid_i 1'0 + assign \pipe_middle_12_p_valid_i \pipe_middle_11_n_valid_o + sync init + end + process $group_421 + assign \pipe_middle_11_n_ready_i 1'0 + assign \pipe_middle_11_n_ready_i \pipe_middle_12_p_ready_o + sync init + end + process $group_422 + assign \pipe_middle_12_muxid 2'00 + assign \pipe_middle_12_muxid \pipe_middle_11_muxid$387 + sync init + end + process $group_423 + assign \pipe_middle_12_logical_op__insn_type 7'0000000 + assign \pipe_middle_12_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_12_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_12_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_12_logical_op__rc__rc 1'0 + assign \pipe_middle_12_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_12_logical_op__oe__oe 1'0 + assign \pipe_middle_12_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_12_logical_op__invert_in 1'0 + assign \pipe_middle_12_logical_op__zero_a 1'0 + assign \pipe_middle_12_logical_op__input_carry 2'00 + assign \pipe_middle_12_logical_op__invert_out 1'0 + assign \pipe_middle_12_logical_op__write_cr0 1'0 + assign \pipe_middle_12_logical_op__output_carry 1'0 + assign \pipe_middle_12_logical_op__is_32bit 1'0 + assign \pipe_middle_12_logical_op__is_signed 1'0 + assign \pipe_middle_12_logical_op__data_len 4'0000 + assign \pipe_middle_12_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_12_logical_op__insn \pipe_middle_12_logical_op__data_len \pipe_middle_12_logical_op__is_signed \pipe_middle_12_logical_op__is_32bit \pipe_middle_12_logical_op__output_carry \pipe_middle_12_logical_op__write_cr0 \pipe_middle_12_logical_op__invert_out \pipe_middle_12_logical_op__input_carry \pipe_middle_12_logical_op__zero_a \pipe_middle_12_logical_op__invert_in { \pipe_middle_12_logical_op__oe__oe_ok \pipe_middle_12_logical_op__oe__oe } { \pipe_middle_12_logical_op__rc__rc_ok \pipe_middle_12_logical_op__rc__rc } { \pipe_middle_12_logical_op__imm_data__imm_ok \pipe_middle_12_logical_op__imm_data__imm } \pipe_middle_12_logical_op__fn_unit \pipe_middle_12_logical_op__insn_type } { \pipe_middle_11_logical_op__insn$405 \pipe_middle_11_logical_op__data_len$404 \pipe_middle_11_logical_op__is_signed$403 \pipe_middle_11_logical_op__is_32bit$402 \pipe_middle_11_logical_op__output_carry$401 \pipe_middle_11_logical_op__write_cr0$400 \pipe_middle_11_logical_op__invert_out$399 \pipe_middle_11_logical_op__input_carry$398 \pipe_middle_11_logical_op__zero_a$397 \pipe_middle_11_logical_op__invert_in$396 { \pipe_middle_11_logical_op__oe__oe_ok$395 \pipe_middle_11_logical_op__oe__oe$394 } { \pipe_middle_11_logical_op__rc__rc_ok$393 \pipe_middle_11_logical_op__rc__rc$392 } { \pipe_middle_11_logical_op__imm_data__imm_ok$391 \pipe_middle_11_logical_op__imm_data__imm$390 } \pipe_middle_11_logical_op__fn_unit$389 \pipe_middle_11_logical_op__insn_type$388 } + sync init + end + process $group_441 + assign \pipe_middle_12_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_12_ra \pipe_middle_11_ra$406 + sync init + end + process $group_442 + assign \pipe_middle_12_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_12_rb \pipe_middle_11_rb$407 + sync init + end + process $group_443 + assign \pipe_middle_12_xer_so 1'0 + assign \pipe_middle_12_xer_so \pipe_middle_11_xer_so$408 + sync init + end + process $group_444 + assign \pipe_middle_12_divisor_neg 1'0 + assign \pipe_middle_12_divisor_neg \pipe_middle_11_divisor_neg$409 + sync init + end + process $group_445 + assign \pipe_middle_12_dividend_neg 1'0 + assign \pipe_middle_12_dividend_neg \pipe_middle_11_dividend_neg$410 + sync init + end + process $group_446 + assign \pipe_middle_12_dive_abs_ov32 1'0 + assign \pipe_middle_12_dive_abs_ov32 \pipe_middle_11_dive_abs_ov32$411 + sync init + end + process $group_447 + assign \pipe_middle_12_dive_abs_ov64 1'0 + assign \pipe_middle_12_dive_abs_ov64 \pipe_middle_11_dive_abs_ov64$412 + sync init + end + process $group_448 + assign \pipe_middle_12_div_by_zero 1'0 + assign \pipe_middle_12_div_by_zero \pipe_middle_11_div_by_zero$413 + sync init + end + process $group_449 + assign \pipe_middle_12_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_12_divisor_radicand \pipe_middle_11_divisor_radicand$414 + sync init + end + process $group_450 + assign \pipe_middle_12_operation 2'00 + assign \pipe_middle_12_operation \pipe_middle_11_operation$415 + sync init + end + process $group_451 + assign \pipe_middle_12_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_12_quotient_root \pipe_middle_11_quotient_root$416 + sync init + end + process $group_452 + assign \pipe_middle_12_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_12_root_times_radicand \pipe_middle_11_root_times_radicand$417 + sync init + end + process $group_453 + assign \pipe_middle_12_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_12_compare_lhs \pipe_middle_11_compare_lhs$418 + sync init + end + process $group_454 + assign \pipe_middle_12_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_12_compare_rhs \pipe_middle_11_compare_rhs$419 + sync init + end + process $group_455 + assign \pipe_middle_13_p_valid_i 1'0 + assign \pipe_middle_13_p_valid_i \pipe_middle_12_n_valid_o + sync init + end + process $group_456 + assign \pipe_middle_12_n_ready_i 1'0 + assign \pipe_middle_12_n_ready_i \pipe_middle_13_p_ready_o + sync init + end + process $group_457 + assign \pipe_middle_13_muxid 2'00 + assign \pipe_middle_13_muxid \pipe_middle_12_muxid$420 + sync init + end + process $group_458 + assign \pipe_middle_13_logical_op__insn_type 7'0000000 + assign \pipe_middle_13_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_13_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_13_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_13_logical_op__rc__rc 1'0 + assign \pipe_middle_13_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_13_logical_op__oe__oe 1'0 + assign \pipe_middle_13_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_13_logical_op__invert_in 1'0 + assign \pipe_middle_13_logical_op__zero_a 1'0 + assign \pipe_middle_13_logical_op__input_carry 2'00 + assign \pipe_middle_13_logical_op__invert_out 1'0 + assign \pipe_middle_13_logical_op__write_cr0 1'0 + assign \pipe_middle_13_logical_op__output_carry 1'0 + assign \pipe_middle_13_logical_op__is_32bit 1'0 + assign \pipe_middle_13_logical_op__is_signed 1'0 + assign \pipe_middle_13_logical_op__data_len 4'0000 + assign \pipe_middle_13_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_13_logical_op__insn \pipe_middle_13_logical_op__data_len \pipe_middle_13_logical_op__is_signed \pipe_middle_13_logical_op__is_32bit \pipe_middle_13_logical_op__output_carry \pipe_middle_13_logical_op__write_cr0 \pipe_middle_13_logical_op__invert_out \pipe_middle_13_logical_op__input_carry \pipe_middle_13_logical_op__zero_a \pipe_middle_13_logical_op__invert_in { \pipe_middle_13_logical_op__oe__oe_ok \pipe_middle_13_logical_op__oe__oe } { \pipe_middle_13_logical_op__rc__rc_ok \pipe_middle_13_logical_op__rc__rc } { \pipe_middle_13_logical_op__imm_data__imm_ok \pipe_middle_13_logical_op__imm_data__imm } \pipe_middle_13_logical_op__fn_unit \pipe_middle_13_logical_op__insn_type } { \pipe_middle_12_logical_op__insn$438 \pipe_middle_12_logical_op__data_len$437 \pipe_middle_12_logical_op__is_signed$436 \pipe_middle_12_logical_op__is_32bit$435 \pipe_middle_12_logical_op__output_carry$434 \pipe_middle_12_logical_op__write_cr0$433 \pipe_middle_12_logical_op__invert_out$432 \pipe_middle_12_logical_op__input_carry$431 \pipe_middle_12_logical_op__zero_a$430 \pipe_middle_12_logical_op__invert_in$429 { \pipe_middle_12_logical_op__oe__oe_ok$428 \pipe_middle_12_logical_op__oe__oe$427 } { \pipe_middle_12_logical_op__rc__rc_ok$426 \pipe_middle_12_logical_op__rc__rc$425 } { \pipe_middle_12_logical_op__imm_data__imm_ok$424 \pipe_middle_12_logical_op__imm_data__imm$423 } \pipe_middle_12_logical_op__fn_unit$422 \pipe_middle_12_logical_op__insn_type$421 } + sync init + end + process $group_476 + assign \pipe_middle_13_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_13_ra \pipe_middle_12_ra$439 + sync init + end + process $group_477 + assign \pipe_middle_13_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_13_rb \pipe_middle_12_rb$440 + sync init + end + process $group_478 + assign \pipe_middle_13_xer_so 1'0 + assign \pipe_middle_13_xer_so \pipe_middle_12_xer_so$441 + sync init + end + process $group_479 + assign \pipe_middle_13_divisor_neg 1'0 + assign \pipe_middle_13_divisor_neg \pipe_middle_12_divisor_neg$442 + sync init + end + process $group_480 + assign \pipe_middle_13_dividend_neg 1'0 + assign \pipe_middle_13_dividend_neg \pipe_middle_12_dividend_neg$443 + sync init + end + process $group_481 + assign \pipe_middle_13_dive_abs_ov32 1'0 + assign \pipe_middle_13_dive_abs_ov32 \pipe_middle_12_dive_abs_ov32$444 + sync init + end + process $group_482 + assign \pipe_middle_13_dive_abs_ov64 1'0 + assign \pipe_middle_13_dive_abs_ov64 \pipe_middle_12_dive_abs_ov64$445 + sync init + end + process $group_483 + assign \pipe_middle_13_div_by_zero 1'0 + assign \pipe_middle_13_div_by_zero \pipe_middle_12_div_by_zero$446 + sync init + end + process $group_484 + assign \pipe_middle_13_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_13_divisor_radicand \pipe_middle_12_divisor_radicand$447 + sync init + end + process $group_485 + assign \pipe_middle_13_operation 2'00 + assign \pipe_middle_13_operation \pipe_middle_12_operation$448 + sync init + end + process $group_486 + assign \pipe_middle_13_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_13_quotient_root \pipe_middle_12_quotient_root$449 + sync init + end + process $group_487 + assign \pipe_middle_13_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_13_root_times_radicand \pipe_middle_12_root_times_radicand$450 + sync init + end + process $group_488 + assign \pipe_middle_13_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_13_compare_lhs \pipe_middle_12_compare_lhs$451 + sync init + end + process $group_489 + assign \pipe_middle_13_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_13_compare_rhs \pipe_middle_12_compare_rhs$452 + sync init + end + process $group_490 + assign \pipe_middle_14_p_valid_i 1'0 + assign \pipe_middle_14_p_valid_i \pipe_middle_13_n_valid_o + sync init + end + process $group_491 + assign \pipe_middle_13_n_ready_i 1'0 + assign \pipe_middle_13_n_ready_i \pipe_middle_14_p_ready_o + sync init + end + process $group_492 + assign \pipe_middle_14_muxid 2'00 + assign \pipe_middle_14_muxid \pipe_middle_13_muxid$453 + sync init + end + process $group_493 + assign \pipe_middle_14_logical_op__insn_type 7'0000000 + assign \pipe_middle_14_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_14_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_14_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_14_logical_op__rc__rc 1'0 + assign \pipe_middle_14_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_14_logical_op__oe__oe 1'0 + assign \pipe_middle_14_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_14_logical_op__invert_in 1'0 + assign \pipe_middle_14_logical_op__zero_a 1'0 + assign \pipe_middle_14_logical_op__input_carry 2'00 + assign \pipe_middle_14_logical_op__invert_out 1'0 + assign \pipe_middle_14_logical_op__write_cr0 1'0 + assign \pipe_middle_14_logical_op__output_carry 1'0 + assign \pipe_middle_14_logical_op__is_32bit 1'0 + assign \pipe_middle_14_logical_op__is_signed 1'0 + assign \pipe_middle_14_logical_op__data_len 4'0000 + assign \pipe_middle_14_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_14_logical_op__insn \pipe_middle_14_logical_op__data_len \pipe_middle_14_logical_op__is_signed \pipe_middle_14_logical_op__is_32bit \pipe_middle_14_logical_op__output_carry \pipe_middle_14_logical_op__write_cr0 \pipe_middle_14_logical_op__invert_out \pipe_middle_14_logical_op__input_carry \pipe_middle_14_logical_op__zero_a \pipe_middle_14_logical_op__invert_in { \pipe_middle_14_logical_op__oe__oe_ok \pipe_middle_14_logical_op__oe__oe } { \pipe_middle_14_logical_op__rc__rc_ok \pipe_middle_14_logical_op__rc__rc } { \pipe_middle_14_logical_op__imm_data__imm_ok \pipe_middle_14_logical_op__imm_data__imm } \pipe_middle_14_logical_op__fn_unit \pipe_middle_14_logical_op__insn_type } { \pipe_middle_13_logical_op__insn$471 \pipe_middle_13_logical_op__data_len$470 \pipe_middle_13_logical_op__is_signed$469 \pipe_middle_13_logical_op__is_32bit$468 \pipe_middle_13_logical_op__output_carry$467 \pipe_middle_13_logical_op__write_cr0$466 \pipe_middle_13_logical_op__invert_out$465 \pipe_middle_13_logical_op__input_carry$464 \pipe_middle_13_logical_op__zero_a$463 \pipe_middle_13_logical_op__invert_in$462 { \pipe_middle_13_logical_op__oe__oe_ok$461 \pipe_middle_13_logical_op__oe__oe$460 } { \pipe_middle_13_logical_op__rc__rc_ok$459 \pipe_middle_13_logical_op__rc__rc$458 } { \pipe_middle_13_logical_op__imm_data__imm_ok$457 \pipe_middle_13_logical_op__imm_data__imm$456 } \pipe_middle_13_logical_op__fn_unit$455 \pipe_middle_13_logical_op__insn_type$454 } + sync init + end + process $group_511 + assign \pipe_middle_14_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_14_ra \pipe_middle_13_ra$472 + sync init + end + process $group_512 + assign \pipe_middle_14_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_14_rb \pipe_middle_13_rb$473 + sync init + end + process $group_513 + assign \pipe_middle_14_xer_so 1'0 + assign \pipe_middle_14_xer_so \pipe_middle_13_xer_so$474 + sync init + end + process $group_514 + assign \pipe_middle_14_divisor_neg 1'0 + assign \pipe_middle_14_divisor_neg \pipe_middle_13_divisor_neg$475 + sync init + end + process $group_515 + assign \pipe_middle_14_dividend_neg 1'0 + assign \pipe_middle_14_dividend_neg \pipe_middle_13_dividend_neg$476 + sync init + end + process $group_516 + assign \pipe_middle_14_dive_abs_ov32 1'0 + assign \pipe_middle_14_dive_abs_ov32 \pipe_middle_13_dive_abs_ov32$477 + sync init + end + process $group_517 + assign \pipe_middle_14_dive_abs_ov64 1'0 + assign \pipe_middle_14_dive_abs_ov64 \pipe_middle_13_dive_abs_ov64$478 + sync init + end + process $group_518 + assign \pipe_middle_14_div_by_zero 1'0 + assign \pipe_middle_14_div_by_zero \pipe_middle_13_div_by_zero$479 + sync init + end + process $group_519 + assign \pipe_middle_14_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_14_divisor_radicand \pipe_middle_13_divisor_radicand$480 + sync init + end + process $group_520 + assign \pipe_middle_14_operation 2'00 + assign \pipe_middle_14_operation \pipe_middle_13_operation$481 + sync init + end + process $group_521 + assign \pipe_middle_14_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_14_quotient_root \pipe_middle_13_quotient_root$482 + sync init + end + process $group_522 + assign \pipe_middle_14_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_14_root_times_radicand \pipe_middle_13_root_times_radicand$483 + sync init + end + process $group_523 + assign \pipe_middle_14_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_14_compare_lhs \pipe_middle_13_compare_lhs$484 + sync init + end + process $group_524 + assign \pipe_middle_14_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_14_compare_rhs \pipe_middle_13_compare_rhs$485 + sync init + end + process $group_525 + assign \pipe_middle_15_p_valid_i 1'0 + assign \pipe_middle_15_p_valid_i \pipe_middle_14_n_valid_o + sync init + end + process $group_526 + assign \pipe_middle_14_n_ready_i 1'0 + assign \pipe_middle_14_n_ready_i \pipe_middle_15_p_ready_o + sync init + end + process $group_527 + assign \pipe_middle_15_muxid 2'00 + assign \pipe_middle_15_muxid \pipe_middle_14_muxid$486 + sync init + end + process $group_528 + assign \pipe_middle_15_logical_op__insn_type 7'0000000 + assign \pipe_middle_15_logical_op__fn_unit 11'00000000000 + assign \pipe_middle_15_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_15_logical_op__imm_data__imm_ok 1'0 + assign \pipe_middle_15_logical_op__rc__rc 1'0 + assign \pipe_middle_15_logical_op__rc__rc_ok 1'0 + assign \pipe_middle_15_logical_op__oe__oe 1'0 + assign \pipe_middle_15_logical_op__oe__oe_ok 1'0 + assign \pipe_middle_15_logical_op__invert_in 1'0 + assign \pipe_middle_15_logical_op__zero_a 1'0 + assign \pipe_middle_15_logical_op__input_carry 2'00 + assign \pipe_middle_15_logical_op__invert_out 1'0 + assign \pipe_middle_15_logical_op__write_cr0 1'0 + assign \pipe_middle_15_logical_op__output_carry 1'0 + assign \pipe_middle_15_logical_op__is_32bit 1'0 + assign \pipe_middle_15_logical_op__is_signed 1'0 + assign \pipe_middle_15_logical_op__data_len 4'0000 + assign \pipe_middle_15_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_middle_15_logical_op__insn \pipe_middle_15_logical_op__data_len \pipe_middle_15_logical_op__is_signed \pipe_middle_15_logical_op__is_32bit \pipe_middle_15_logical_op__output_carry \pipe_middle_15_logical_op__write_cr0 \pipe_middle_15_logical_op__invert_out \pipe_middle_15_logical_op__input_carry \pipe_middle_15_logical_op__zero_a \pipe_middle_15_logical_op__invert_in { \pipe_middle_15_logical_op__oe__oe_ok \pipe_middle_15_logical_op__oe__oe } { \pipe_middle_15_logical_op__rc__rc_ok \pipe_middle_15_logical_op__rc__rc } { \pipe_middle_15_logical_op__imm_data__imm_ok \pipe_middle_15_logical_op__imm_data__imm } \pipe_middle_15_logical_op__fn_unit \pipe_middle_15_logical_op__insn_type } { \pipe_middle_14_logical_op__insn$504 \pipe_middle_14_logical_op__data_len$503 \pipe_middle_14_logical_op__is_signed$502 \pipe_middle_14_logical_op__is_32bit$501 \pipe_middle_14_logical_op__output_carry$500 \pipe_middle_14_logical_op__write_cr0$499 \pipe_middle_14_logical_op__invert_out$498 \pipe_middle_14_logical_op__input_carry$497 \pipe_middle_14_logical_op__zero_a$496 \pipe_middle_14_logical_op__invert_in$495 { \pipe_middle_14_logical_op__oe__oe_ok$494 \pipe_middle_14_logical_op__oe__oe$493 } { \pipe_middle_14_logical_op__rc__rc_ok$492 \pipe_middle_14_logical_op__rc__rc$491 } { \pipe_middle_14_logical_op__imm_data__imm_ok$490 \pipe_middle_14_logical_op__imm_data__imm$489 } \pipe_middle_14_logical_op__fn_unit$488 \pipe_middle_14_logical_op__insn_type$487 } + sync init + end + process $group_546 + assign \pipe_middle_15_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_15_ra \pipe_middle_14_ra$505 + sync init + end + process $group_547 + assign \pipe_middle_15_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_15_rb \pipe_middle_14_rb$506 + sync init + end + process $group_548 + assign \pipe_middle_15_xer_so 1'0 + assign \pipe_middle_15_xer_so \pipe_middle_14_xer_so$507 + sync init + end + process $group_549 + assign \pipe_middle_15_divisor_neg 1'0 + assign \pipe_middle_15_divisor_neg \pipe_middle_14_divisor_neg$508 + sync init + end + process $group_550 + assign \pipe_middle_15_dividend_neg 1'0 + assign \pipe_middle_15_dividend_neg \pipe_middle_14_dividend_neg$509 + sync init + end + process $group_551 + assign \pipe_middle_15_dive_abs_ov32 1'0 + assign \pipe_middle_15_dive_abs_ov32 \pipe_middle_14_dive_abs_ov32$510 + sync init + end + process $group_552 + assign \pipe_middle_15_dive_abs_ov64 1'0 + assign \pipe_middle_15_dive_abs_ov64 \pipe_middle_14_dive_abs_ov64$511 + sync init + end + process $group_553 + assign \pipe_middle_15_div_by_zero 1'0 + assign \pipe_middle_15_div_by_zero \pipe_middle_14_div_by_zero$512 + sync init + end + process $group_554 + assign \pipe_middle_15_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_15_divisor_radicand \pipe_middle_14_divisor_radicand$513 + sync init + end + process $group_555 + assign \pipe_middle_15_operation 2'00 + assign \pipe_middle_15_operation \pipe_middle_14_operation$514 + sync init + end + process $group_556 + assign \pipe_middle_15_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_15_quotient_root \pipe_middle_14_quotient_root$515 + sync init + end + process $group_557 + assign \pipe_middle_15_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_15_root_times_radicand \pipe_middle_14_root_times_radicand$516 + sync init + end + process $group_558 + assign \pipe_middle_15_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_15_compare_lhs \pipe_middle_14_compare_lhs$517 + sync init + end + process $group_559 + assign \pipe_middle_15_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_middle_15_compare_rhs \pipe_middle_14_compare_rhs$518 + sync init + end + process $group_560 + assign \pipe_end_p_valid_i 1'0 + assign \pipe_end_p_valid_i \pipe_middle_15_n_valid_o + sync init + end + process $group_561 + assign \pipe_middle_15_n_ready_i 1'0 + assign \pipe_middle_15_n_ready_i \pipe_end_p_ready_o + sync init + end + process $group_562 + assign \pipe_end_muxid 2'00 + assign \pipe_end_muxid \pipe_middle_15_muxid$519 + sync init + end + process $group_563 + assign \pipe_end_logical_op__insn_type 7'0000000 + assign \pipe_end_logical_op__fn_unit 11'00000000000 + assign \pipe_end_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_logical_op__imm_data__imm_ok 1'0 + assign \pipe_end_logical_op__rc__rc 1'0 + assign \pipe_end_logical_op__rc__rc_ok 1'0 + assign \pipe_end_logical_op__oe__oe 1'0 + assign \pipe_end_logical_op__oe__oe_ok 1'0 + assign \pipe_end_logical_op__invert_in 1'0 + assign \pipe_end_logical_op__zero_a 1'0 + assign \pipe_end_logical_op__input_carry 2'00 + assign \pipe_end_logical_op__invert_out 1'0 + assign \pipe_end_logical_op__write_cr0 1'0 + assign \pipe_end_logical_op__output_carry 1'0 + assign \pipe_end_logical_op__is_32bit 1'0 + assign \pipe_end_logical_op__is_signed 1'0 + assign \pipe_end_logical_op__data_len 4'0000 + assign \pipe_end_logical_op__insn 32'00000000000000000000000000000000 + assign { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in { \pipe_end_logical_op__oe__oe_ok \pipe_end_logical_op__oe__oe } { \pipe_end_logical_op__rc__rc_ok \pipe_end_logical_op__rc__rc } { \pipe_end_logical_op__imm_data__imm_ok \pipe_end_logical_op__imm_data__imm } \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_15_logical_op__insn$537 \pipe_middle_15_logical_op__data_len$536 \pipe_middle_15_logical_op__is_signed$535 \pipe_middle_15_logical_op__is_32bit$534 \pipe_middle_15_logical_op__output_carry$533 \pipe_middle_15_logical_op__write_cr0$532 \pipe_middle_15_logical_op__invert_out$531 \pipe_middle_15_logical_op__input_carry$530 \pipe_middle_15_logical_op__zero_a$529 \pipe_middle_15_logical_op__invert_in$528 { \pipe_middle_15_logical_op__oe__oe_ok$527 \pipe_middle_15_logical_op__oe__oe$526 } { \pipe_middle_15_logical_op__rc__rc_ok$525 \pipe_middle_15_logical_op__rc__rc$524 } { \pipe_middle_15_logical_op__imm_data__imm_ok$523 \pipe_middle_15_logical_op__imm_data__imm$522 } \pipe_middle_15_logical_op__fn_unit$521 \pipe_middle_15_logical_op__insn_type$520 } + sync init + end + process $group_581 + assign \pipe_end_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_ra \pipe_middle_15_ra$538 + sync init + end + process $group_582 + assign \pipe_end_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_rb \pipe_middle_15_rb$539 + sync init + end + process $group_583 + assign \pipe_end_xer_so 1'0 + assign \pipe_end_xer_so \pipe_middle_15_xer_so$540 + sync init + end + process $group_584 + assign \pipe_end_divisor_neg 1'0 + assign \pipe_end_divisor_neg \pipe_middle_15_divisor_neg$541 + sync init + end + process $group_585 + assign \pipe_end_dividend_neg 1'0 + assign \pipe_end_dividend_neg \pipe_middle_15_dividend_neg$542 + sync init + end + process $group_586 + assign \pipe_end_dive_abs_ov32 1'0 + assign \pipe_end_dive_abs_ov32 \pipe_middle_15_dive_abs_ov32$543 + sync init + end + process $group_587 + assign \pipe_end_dive_abs_ov64 1'0 + assign \pipe_end_dive_abs_ov64 \pipe_middle_15_dive_abs_ov64$544 + sync init + end + process $group_588 + assign \pipe_end_div_by_zero 1'0 + assign \pipe_end_div_by_zero \pipe_middle_15_div_by_zero$545 + sync init + end + process $group_589 + assign \pipe_end_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_divisor_radicand \pipe_middle_15_divisor_radicand$546 + sync init + end + process $group_590 + assign \pipe_end_operation 2'00 + assign \pipe_end_operation \pipe_middle_15_operation$547 + sync init + end + process $group_591 + assign \pipe_end_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_quotient_root \pipe_middle_15_quotient_root$548 + sync init + end + process $group_592 + assign \pipe_end_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_root_times_radicand \pipe_middle_15_root_times_radicand$549 + sync init + end + process $group_593 + assign \pipe_end_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_compare_lhs \pipe_middle_15_compare_lhs$550 + sync init + end + process $group_594 + assign \pipe_end_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_compare_rhs \pipe_middle_15_compare_rhs$551 + sync init + end + process $group_595 + assign \pipe_start_p_valid_i 1'0 + assign \pipe_start_p_valid_i \p_valid_i + sync init + end + process $group_596 + assign \p_ready_o 1'0 + assign \p_ready_o \pipe_start_p_ready_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + process $group_597 + assign \pipe_start_muxid$2 2'00 + assign \pipe_start_muxid$2 \muxid + sync init + end + process $group_598 + assign \pipe_start_logical_op__insn_type$3 7'0000000 + assign \pipe_start_logical_op__fn_unit$4 11'00000000000 + assign \pipe_start_logical_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_start_logical_op__imm_data__imm_ok$6 1'0 + assign \pipe_start_logical_op__rc__rc$7 1'0 + assign \pipe_start_logical_op__rc__rc_ok$8 1'0 + assign \pipe_start_logical_op__oe__oe$9 1'0 + assign \pipe_start_logical_op__oe__oe_ok$10 1'0 + assign \pipe_start_logical_op__invert_in$11 1'0 + assign \pipe_start_logical_op__zero_a$12 1'0 + assign \pipe_start_logical_op__input_carry$13 2'00 + assign \pipe_start_logical_op__invert_out$14 1'0 + assign \pipe_start_logical_op__write_cr0$15 1'0 + assign \pipe_start_logical_op__output_carry$16 1'0 + assign \pipe_start_logical_op__is_32bit$17 1'0 + assign \pipe_start_logical_op__is_signed$18 1'0 + assign \pipe_start_logical_op__data_len$19 4'0000 + assign \pipe_start_logical_op__insn$20 32'00000000000000000000000000000000 + assign { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 { \pipe_start_logical_op__oe__oe_ok$10 \pipe_start_logical_op__oe__oe$9 } { \pipe_start_logical_op__rc__rc_ok$8 \pipe_start_logical_op__rc__rc$7 } { \pipe_start_logical_op__imm_data__imm_ok$6 \pipe_start_logical_op__imm_data__imm$5 } \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type } + sync init + end + process $group_616 + assign \pipe_start_ra$21 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_start_ra$21 \ra + sync init + end + process $group_617 + assign \pipe_start_rb$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_start_rb$22 \rb + sync init + end + process $group_618 + assign \pipe_start_xer_so$23 1'0 + assign \pipe_start_xer_so$23 \xer_so$1 + sync init + end + process $group_619 + assign \n_valid_o 1'0 + assign \n_valid_o \pipe_end_n_valid_o + sync init + end + process $group_620 + assign \pipe_end_n_ready_i 1'0 + assign \pipe_end_n_ready_i \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$572 + process $group_621 + assign \muxid$572 2'00 + assign \muxid$572 \pipe_end_muxid$552 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$573 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \logical_op__fn_unit$574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__imm$575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__imm_data__imm_ok$576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc$577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__rc__rc_ok$578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe$579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__oe__oe_ok$580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_in$581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__zero_a$582 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__invert_out$584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__write_cr0$585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__output_carry$586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_32bit$587 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \logical_op__is_signed$588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$589 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$590 + process $group_622 + assign \logical_op__insn_type$573 7'0000000 + assign \logical_op__fn_unit$574 11'00000000000 + assign \logical_op__imm_data__imm$575 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \logical_op__imm_data__imm_ok$576 1'0 + assign \logical_op__rc__rc$577 1'0 + assign \logical_op__rc__rc_ok$578 1'0 + assign \logical_op__oe__oe$579 1'0 + assign \logical_op__oe__oe_ok$580 1'0 + assign \logical_op__invert_in$581 1'0 + assign \logical_op__zero_a$582 1'0 + assign \logical_op__input_carry$583 2'00 + assign \logical_op__invert_out$584 1'0 + assign \logical_op__write_cr0$585 1'0 + assign \logical_op__output_carry$586 1'0 + assign \logical_op__is_32bit$587 1'0 + assign \logical_op__is_signed$588 1'0 + assign \logical_op__data_len$589 4'0000 + assign \logical_op__insn$590 32'00000000000000000000000000000000 + assign { \logical_op__insn$590 \logical_op__data_len$589 \logical_op__is_signed$588 \logical_op__is_32bit$587 \logical_op__output_carry$586 \logical_op__write_cr0$585 \logical_op__invert_out$584 \logical_op__input_carry$583 \logical_op__zero_a$582 \logical_op__invert_in$581 { \logical_op__oe__oe_ok$580 \logical_op__oe__oe$579 } { \logical_op__rc__rc_ok$578 \logical_op__rc__rc$577 } { \logical_op__imm_data__imm_ok$576 \logical_op__imm_data__imm$575 } \logical_op__fn_unit$574 \logical_op__insn_type$573 } { \pipe_end_logical_op__insn$570 \pipe_end_logical_op__data_len$569 \pipe_end_logical_op__is_signed$568 \pipe_end_logical_op__is_32bit$567 \pipe_end_logical_op__output_carry$566 \pipe_end_logical_op__write_cr0$565 \pipe_end_logical_op__invert_out$564 \pipe_end_logical_op__input_carry$563 \pipe_end_logical_op__zero_a$562 \pipe_end_logical_op__invert_in$561 { \pipe_end_logical_op__oe__oe_ok$560 \pipe_end_logical_op__oe__oe$559 } { \pipe_end_logical_op__rc__rc_ok$558 \pipe_end_logical_op__rc__rc$557 } { \pipe_end_logical_op__imm_data__imm_ok$556 \pipe_end_logical_op__imm_data__imm$555 } \pipe_end_logical_op__fn_unit$554 \pipe_end_logical_op__insn_type$553 } + sync init + end + process $group_640 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'0 + assign { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } + sync init + end + process $group_642 + assign \cr_a 4'0000 + assign \cr_a_ok 1'0 + assign { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } + sync init + end + process $group_644 + assign \xer_ov 2'00 + assign \xer_ov_ok 1'0 + assign { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } + sync init + end + process $group_646 + assign \xer_so 1'0 + assign \xer_so_ok 1'0 + assign { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$571 } + sync init + end + connect \muxid 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l" +module \src_l$366 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $3 + connect \B \s_src + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 3'000 + end + sync init + update \q_int 3'000 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $9 + connect \B \s_src + connect \Y $11 + end + process $group_1 + assign \q_src 3'000 + assign \q_src $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $13 + end + process $group_2 + assign \qn_src 3'000 + assign \qn_src $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_src 3'000 + assign \qlq_src $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l" +module \opc_l$367 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_opc + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_opc + connect \Y $11 + end + process $group_1 + assign \q_opc 1'0 + assign \q_opc $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $13 + end + process $group_2 + assign \qn_opc 1'0 + assign \qn_opc $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_opc 1'0 + assign \qlq_opc $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l" +module \req_l$368 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $3 + connect \B \s_req + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 4'0000 + end + sync init + update \q_int 4'0000 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $9 + connect \B \s_req + connect \Y $11 + end + process $group_1 + assign \q_req 4'0000 + assign \q_req $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $13 + end + process $group_2 + assign \qn_req 4'0000 + assign \qn_req $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_req 4'0000 + assign \qlq_req $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l" +module \rst_l$369 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rst + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rst + connect \Y $11 + end + process $group_1 + assign \q_rst 1'0 + assign \q_rst $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $13 + end + process $group_2 + assign \qn_rst 1'0 + assign \qn_rst $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rst 1'0 + assign \qlq_rst $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l" +module \rok_l$370 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rdok + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rdok + connect \Y $11 + end + process $group_1 + assign \q_rdok 1'0 + assign \q_rdok $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $13 + end + process $group_2 + assign \qn_rdok 1'0 + assign \qn_rdok $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rdok 1'0 + assign \qlq_rdok $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l" +module \alui_l$371 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alui + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alui + connect \Y $11 + end + process $group_1 + assign \q_alui 1'0 + assign \q_alui $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $13 + end + process $group_2 + assign \qn_alui 1'0 + assign \qn_alui $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alui 1'0 + assign \qlq_alui $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l" +module \alu_l$372 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alu + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alu + connect \Y $11 + end + process $group_1 + assign \q_alu 1'0 + assign \q_alu $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $13 + end + process $group_2 + assign \qn_alu 1'0 + assign \qn_alu $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alu 1'0 + assign \qlq_alu $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0" +module \div0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_div0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_div0__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \oper_i_alu_div0__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \oper_i_alu_div0__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \oper_i_alu_div0__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \oper_i_alu_div0__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_alu_div0__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_div0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 24 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 input 26 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 27 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 28 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 29 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 30 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 31 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 32 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 33 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 34 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 35 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 output 36 \dest4_o + attribute \src "simple/issuer.py:102" + wire width 1 input 37 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \alu_div0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \alu_div0_n_ready_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_div0_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_div0_logical_op__insn_type$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_div0_logical_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_div0_logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_div0_logical_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_div0_logical_op__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__zero_a$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_div0_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_div0_logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_div0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_div0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_div0_logical_op__data_len$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_div0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_div0_logical_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_div0_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_div0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_div0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \alu_div0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \alu_div0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \alu_div0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \alu_div0_p_ready_o + cell \alu_div0 \alu_div0 + connect \coresync_clk \coresync_clk + connect \o_ok \o_ok + connect \cr_a_ok \cr_a_ok + connect \xer_ov_ok \xer_ov_ok + connect \xer_so_ok \xer_so_ok + connect \coresync_rst \coresync_rst + connect \n_valid_o \alu_div0_n_valid_o + connect \n_ready_i \alu_div0_n_ready_i + connect \logical_op__insn_type \alu_div0_logical_op__insn_type + connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit + connect \logical_op__imm_data__imm \alu_div0_logical_op__imm_data__imm + connect \logical_op__imm_data__imm_ok \alu_div0_logical_op__imm_data__imm_ok + connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc + connect \logical_op__rc__rc_ok \alu_div0_logical_op__rc__rc_ok + connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe + connect \logical_op__oe__oe_ok \alu_div0_logical_op__oe__oe_ok + connect \logical_op__invert_in \alu_div0_logical_op__invert_in + connect \logical_op__zero_a \alu_div0_logical_op__zero_a + connect \logical_op__input_carry \alu_div0_logical_op__input_carry + connect \logical_op__invert_out \alu_div0_logical_op__invert_out + connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 + connect \logical_op__output_carry \alu_div0_logical_op__output_carry + connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit + connect \logical_op__is_signed \alu_div0_logical_op__is_signed + connect \logical_op__data_len \alu_div0_logical_op__data_len + connect \logical_op__insn \alu_div0_logical_op__insn + connect \o \alu_div0_o + connect \cr_a \alu_div0_cr_a + connect \xer_ov \alu_div0_xer_ov + connect \xer_so \alu_div0_xer_so + connect \ra \alu_div0_ra + connect \rb \alu_div0_rb + connect \xer_so$1 \alu_div0_xer_so$1 + connect \p_valid_i \alu_div0_p_valid_i + connect \p_ready_o \alu_div0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + cell \src_l$366 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_src \src_l_s_src + connect \r_src \src_l_r_src + connect \q_src \src_l_q_src + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \opc_l_q_opc + cell \opc_l$367 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_opc \opc_l_s_opc + connect \r_opc \opc_l_r_opc + connect \q_opc \opc_l_q_opc + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \req_l_r_req$next + cell \req_l$368 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \s_req \req_l_s_req + connect \r_req \req_l_r_req + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst$next + cell \rst_l$369 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_rst \rst_l_s_rst + connect \r_rst \rst_l_r_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok$next + cell \rok_l$370 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \s_rdok \rok_l_s_rdok + connect \r_rdok \rok_l_r_rdok + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alui_l_s_alui + cell \alui_l$371 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_s_alu + cell \alu_l$372 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire width 1 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $5 + connect \B \cu_rd__go_i + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $7 + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $2 + connect \B $4 + connect \Y $10 + end + process $group_0 + assign \all_rd 1'0 + assign \all_rd $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly$next + process $group_1 + assign \all_rd_dly$next \all_rd_dly + assign \all_rd_dly$next \all_rd + sync init + update \all_rd_dly 1'0 + sync posedge \coresync_clk + update \all_rd_dly \all_rd_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B $12 + connect \Y $14 + end + process $group_2 + assign \all_rd_rise 1'0 + assign \all_rd_rise $14 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire width 1 \all_rd_pulse + process $group_3 + assign \all_rd_pulse 1'0 + assign \all_rd_pulse \all_rd_rise + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire width 1 \alu_done + process $group_4 + assign \alu_done 1'0 + assign \alu_done \alu_div0_n_valid_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly$next + process $group_5 + assign \alu_done_dly$next \alu_done_dly + assign \alu_done_dly$next \alu_done + sync init + update \alu_done_dly 1'0 + sync posedge \coresync_clk + update \alu_done_dly \alu_done_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B $16 + connect \Y $18 + end + process $group_6 + assign \alu_done_rise 1'0 + assign \alu_done_rise $18 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire width 1 \alu_pulse + process $group_7 + assign \alu_pulse 1'0 + assign \alu_pulse \alu_done_rise + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + process $group_8 + assign \alu_pulsem 4'0000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 4 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $20 + end + process $group_9 + assign \prev_wr_go$next \prev_wr_go + assign \prev_wr_go$next $20 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \prev_wr_go$next 4'0000 + end + sync init + update \prev_wr_go 4'0000 + sync posedge \coresync_clk + update \prev_wr_go \prev_wr_go$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire width 1 \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 4 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 4 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__rel_o + connect \B $24 + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_bool $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A $26 + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $23 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B $22 + connect \Y $30 + end + process $group_10 + assign \cu_done_o 1'0 + assign \cu_done_o $30 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $32 + connect \B $34 + connect \Y $36 + end + process $group_11 + assign \wr_any 1'0 + assign \wr_any $36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire width 1 \req_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_ready_i + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B $38 + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 4 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $42 + connect \B 1'0 + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $40 + connect \B $44 + connect \Y $46 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $48 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $48 + connect \B \alu_div0_n_ready_i + connect \Y $50 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $50 + connect \B \alu_div0_n_valid_o + connect \Y $52 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $52 + connect \B \cu_busy_o + connect \Y $54 + end + process $group_12 + assign \req_done 1'0 + assign \req_done $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch { $54 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + case 1'1 + assign \req_done 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire width 1 \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire width 1 \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire width 1 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $56 + end + process $group_13 + assign \reset 1'0 + assign \reset $56 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire width 1 \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire width 1 $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $58 + end + process $group_14 + assign \rst_r 1'0 + assign \rst_r $58 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 4 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 4 $60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $60 + end + process $group_15 + assign \reset_w 4'0000 + assign \reset_w $60 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 3 $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $62 + end + process $group_16 + assign \reset_r 3'000 + assign \reset_r $62 + sync init + end + process $group_17 + assign \rok_l_s_rdok$next \rok_l_s_rdok + assign \rok_l_s_rdok$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_s_rdok$next 1'0 + end + sync init + update \rok_l_s_rdok 1'0 + sync posedge \coresync_clk + update \rok_l_s_rdok \rok_l_s_rdok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire width 1 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $65 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_valid_o + connect \B \cu_busy_o + connect \Y $64 + end + process $group_18 + assign \rok_l_r_rdok$next \rok_l_r_rdok + assign \rok_l_r_rdok$next $64 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_r_rdok$next 1'1 + end + sync init + update \rok_l_r_rdok 1'1 + sync posedge \coresync_clk + update \rok_l_r_rdok \rok_l_r_rdok$next + end + process $group_19 + assign \rst_l_s_rst$next \rst_l_s_rst + assign \rst_l_s_rst$next \all_rd + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_s_rst$next 1'0 + end + sync init + update \rst_l_s_rst 1'0 + sync posedge \coresync_clk + update \rst_l_s_rst \rst_l_s_rst$next + end + process $group_20 + assign \rst_l_r_rst$next \rst_l_r_rst + assign \rst_l_r_rst$next \rst_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_r_rst$next 1'1 + end + sync init + update \rst_l_r_rst 1'1 + sync posedge \coresync_clk + update \rst_l_r_rst \rst_l_r_rst$next + end + process $group_21 + assign \opc_l_s_opc$next \opc_l_s_opc + assign \opc_l_s_opc$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_s_opc$next 1'0 + end + sync init + update \opc_l_s_opc 1'0 + sync posedge \coresync_clk + update \opc_l_s_opc \opc_l_s_opc$next + end + process $group_22 + assign \opc_l_r_opc$next \opc_l_r_opc + assign \opc_l_r_opc$next \req_done + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_r_opc$next 1'1 + end + sync init + update \opc_l_r_opc 1'1 + sync posedge \coresync_clk + update \opc_l_r_opc \opc_l_r_opc$next + end + process $group_23 + assign \src_l_s_src$next \src_l_s_src + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_s_src$next 3'000 + end + sync init + update \src_l_s_src 3'000 + sync posedge \coresync_clk + update \src_l_s_src \src_l_s_src$next + end + process $group_24 + assign \src_l_r_src$next \src_l_r_src + assign \src_l_r_src$next \reset_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_r_src$next 3'111 + end + sync init + update \src_l_r_src 3'111 + sync posedge \coresync_clk + update \src_l_r_src \src_l_r_src$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 4 $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $66 + end + process $group_25 + assign \req_l_s_req$next \req_l_s_req + assign \req_l_s_req$next $66 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_s_req$next 4'0000 + end + sync init + update \req_l_s_req 4'0000 + sync posedge \coresync_clk + update \req_l_s_req \req_l_s_req$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 4 $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $68 + end + process $group_26 + assign \req_l_r_req$next \req_l_r_req + assign \req_l_r_req$next $68 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_r_req$next 4'1111 + end + sync init + update \req_l_r_req 4'1111 + sync posedge \coresync_clk + update \req_l_r_req \req_l_r_req$next + end + process $group_27 + assign \alu_div0_logical_op__insn_type$next \alu_div0_logical_op__insn_type + assign \alu_div0_logical_op__fn_unit$next \alu_div0_logical_op__fn_unit + assign \alu_div0_logical_op__imm_data__imm$next \alu_div0_logical_op__imm_data__imm + assign \alu_div0_logical_op__imm_data__imm_ok$next \alu_div0_logical_op__imm_data__imm_ok + assign \alu_div0_logical_op__rc__rc$next \alu_div0_logical_op__rc__rc + assign \alu_div0_logical_op__rc__rc_ok$next \alu_div0_logical_op__rc__rc_ok + assign \alu_div0_logical_op__oe__oe$next \alu_div0_logical_op__oe__oe + assign \alu_div0_logical_op__oe__oe_ok$next \alu_div0_logical_op__oe__oe_ok + assign \alu_div0_logical_op__invert_in$next \alu_div0_logical_op__invert_in + assign \alu_div0_logical_op__zero_a$next \alu_div0_logical_op__zero_a + assign \alu_div0_logical_op__input_carry$next \alu_div0_logical_op__input_carry + assign \alu_div0_logical_op__invert_out$next \alu_div0_logical_op__invert_out + assign \alu_div0_logical_op__write_cr0$next \alu_div0_logical_op__write_cr0 + assign \alu_div0_logical_op__output_carry$next \alu_div0_logical_op__output_carry + assign \alu_div0_logical_op__is_32bit$next \alu_div0_logical_op__is_32bit + assign \alu_div0_logical_op__is_signed$next \alu_div0_logical_op__is_signed + assign \alu_div0_logical_op__data_len$next \alu_div0_logical_op__data_len + assign \alu_div0_logical_op__insn$next \alu_div0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + case 1'1 + assign { \alu_div0_logical_op__insn$next \alu_div0_logical_op__data_len$next \alu_div0_logical_op__is_signed$next \alu_div0_logical_op__is_32bit$next \alu_div0_logical_op__output_carry$next \alu_div0_logical_op__write_cr0$next \alu_div0_logical_op__invert_out$next \alu_div0_logical_op__input_carry$next \alu_div0_logical_op__zero_a$next \alu_div0_logical_op__invert_in$next { \alu_div0_logical_op__oe__oe_ok$next \alu_div0_logical_op__oe__oe$next } { \alu_div0_logical_op__rc__rc_ok$next \alu_div0_logical_op__rc__rc$next } { \alu_div0_logical_op__imm_data__imm_ok$next \alu_div0_logical_op__imm_data__imm$next } \alu_div0_logical_op__fn_unit$next \alu_div0_logical_op__insn_type$next } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in { \oper_i_alu_div0__oe__oe_ok \oper_i_alu_div0__oe__oe } { \oper_i_alu_div0__rc__rc_ok \oper_i_alu_div0__rc__rc } { \oper_i_alu_div0__imm_data__imm_ok \oper_i_alu_div0__imm_data__imm } \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_div0_logical_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_div0_logical_op__imm_data__imm_ok$next 1'0 + assign \alu_div0_logical_op__rc__rc$next 1'0 + assign \alu_div0_logical_op__rc__rc_ok$next 1'0 + assign \alu_div0_logical_op__oe__oe$next 1'0 + assign \alu_div0_logical_op__oe__oe_ok$next 1'0 + end + sync init + update \alu_div0_logical_op__insn_type 7'0000000 + update \alu_div0_logical_op__fn_unit 11'00000000000 + update \alu_div0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_div0_logical_op__imm_data__imm_ok 1'0 + update \alu_div0_logical_op__rc__rc 1'0 + update \alu_div0_logical_op__rc__rc_ok 1'0 + update \alu_div0_logical_op__oe__oe 1'0 + update \alu_div0_logical_op__oe__oe_ok 1'0 + update \alu_div0_logical_op__invert_in 1'0 + update \alu_div0_logical_op__zero_a 1'0 + update \alu_div0_logical_op__input_carry 2'00 + update \alu_div0_logical_op__invert_out 1'0 + update \alu_div0_logical_op__write_cr0 1'0 + update \alu_div0_logical_op__output_carry 1'0 + update \alu_div0_logical_op__is_32bit 1'0 + update \alu_div0_logical_op__is_signed 1'0 + update \alu_div0_logical_op__data_len 4'0000 + update \alu_div0_logical_op__insn 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \alu_div0_logical_op__insn_type \alu_div0_logical_op__insn_type$next + update \alu_div0_logical_op__fn_unit \alu_div0_logical_op__fn_unit$next + update \alu_div0_logical_op__imm_data__imm \alu_div0_logical_op__imm_data__imm$next + update \alu_div0_logical_op__imm_data__imm_ok \alu_div0_logical_op__imm_data__imm_ok$next + update \alu_div0_logical_op__rc__rc \alu_div0_logical_op__rc__rc$next + update \alu_div0_logical_op__rc__rc_ok \alu_div0_logical_op__rc__rc_ok$next + update \alu_div0_logical_op__oe__oe \alu_div0_logical_op__oe__oe$next + update \alu_div0_logical_op__oe__oe_ok \alu_div0_logical_op__oe__oe_ok$next + update \alu_div0_logical_op__invert_in \alu_div0_logical_op__invert_in$next + update \alu_div0_logical_op__zero_a \alu_div0_logical_op__zero_a$next + update \alu_div0_logical_op__input_carry \alu_div0_logical_op__input_carry$next + update \alu_div0_logical_op__invert_out \alu_div0_logical_op__invert_out$next + update \alu_div0_logical_op__write_cr0 \alu_div0_logical_op__write_cr0$next + update \alu_div0_logical_op__output_carry \alu_div0_logical_op__output_carry$next + update \alu_div0_logical_op__is_32bit \alu_div0_logical_op__is_32bit$next + update \alu_div0_logical_op__is_signed \alu_div0_logical_op__is_signed$next + update \alu_div0_logical_op__data_len \alu_div0_logical_op__data_len$next + update \alu_div0_logical_op__insn \alu_div0_logical_op__insn$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok$next + process $group_45 + assign \data_r0__o$next \data_r0__o + assign \data_r0__o_ok$next \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_div0_o } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r0__o_ok$next 1'0 + end + sync init + update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0__o_ok 1'0 + sync posedge \coresync_clk + update \data_r0__o \data_r0__o$next + update \data_r0__o_ok \data_r0__o_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__cr_a_ok$next + process $group_47 + assign \data_r1__cr_a$next \data_r1__cr_a + assign \data_r1__cr_a_ok$next \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } { \cr_a_ok \alu_div0_cr_a } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r1__cr_a_ok$next 1'0 + end + sync init + update \data_r1__cr_a 4'0000 + update \data_r1__cr_a_ok 1'0 + sync posedge \coresync_clk + update \data_r1__cr_a \data_r1__cr_a$next + update \data_r1__cr_a_ok \data_r1__cr_a_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__xer_ov_ok$next + process $group_49 + assign \data_r2__xer_ov$next \data_r2__xer_ov + assign \data_r2__xer_ov_ok$next \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r2__xer_ov_ok$next \data_r2__xer_ov$next } { \xer_ov_ok \alu_div0_xer_ov } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r2__xer_ov_ok$next \data_r2__xer_ov$next } 3'000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r2__xer_ov_ok$next 1'0 + end + sync init + update \data_r2__xer_ov 2'00 + update \data_r2__xer_ov_ok 1'0 + sync posedge \coresync_clk + update \data_r2__xer_ov \data_r2__xer_ov$next + update \data_r2__xer_ov_ok \data_r2__xer_ov_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so_ok$next + process $group_51 + assign \data_r3__xer_so$next \data_r3__xer_so + assign \data_r3__xer_so_ok$next \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } { \xer_so_ok \alu_div0_xer_so } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r3__xer_so_ok$next 1'0 + end + sync init + update \data_r3__xer_so 1'0 + update \data_r3__xer_so_ok 1'0 + sync posedge \coresync_clk + update \data_r3__xer_so \data_r3__xer_so$next + update \data_r3__xer_so_ok \data_r3__xer_so_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $70 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $74 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $76 + end + process $group_53 + assign \cu_wrmask_o 4'0000 + assign \cu_wrmask_o { $76 $74 $72 $70 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $79 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__zero_a + connect \Y $78 + end + process $group_54 + assign \src_sel 1'0 + assign \src_sel $78 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $81 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_div0_logical_op__zero_a + connect \Y $80 + end + process $group_55 + assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm $80 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire width 1 \src_sel$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $84 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__imm_data__imm_ok + connect \Y $83 + end + process $group_56 + assign \src_sel$82 1'0 + assign \src_sel$82 $83 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $87 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_div0_logical_op__imm_data__imm + connect \S \alu_div0_logical_op__imm_data__imm_ok + connect \Y $86 + end + process $group_57 + assign \src_or_imm$85 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm$85 $86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $88 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $89 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $88 + end + process $group_58 + assign \alu_div0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_div0_ra $88 + sync init + end + process $group_59 + assign \src_r0$next \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r0$next \src_or_imm + end + sync init + update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r0 \src_r0$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $90 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $91 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$85 + connect \S \src_sel$82 + connect \Y $90 + end + process $group_60 + assign \alu_div0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_div0_rb $90 + sync init + end + process $group_61 + assign \src_r1$next \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel$82 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r1$next \src_or_imm$85 + end + sync init + update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r1 \src_r1$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $92 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $93 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $92 + end + process $group_62 + assign \alu_div0_xer_so$1 1'0 + assign \alu_div0_xer_so$1 $92 + sync init + end + process $group_63 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r2$next \src3_i + end + sync init + update \src_r2 1'0 + sync posedge \coresync_clk + update \src_r2 \src_r2$next + end + process $group_64 + assign \alu_div0_p_valid_i 1'0 + assign \alu_div0_p_valid_i \alui_l_q_alui + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire width 1 $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $94 + end + process $group_65 + assign \alui_l_r_alui$next \alui_l_r_alui + assign \alui_l_r_alui$next $94 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alui_l_r_alui$next 1'1 + end + sync init + update \alui_l_r_alui 1'1 + sync posedge \coresync_clk + update \alui_l_r_alui \alui_l_r_alui$next + end + process $group_66 + assign \alui_l_s_alui 1'0 + assign \alui_l_s_alui \all_rd_pulse + sync init + end + process $group_67 + assign \alu_div0_n_ready_i 1'0 + assign \alu_div0_n_ready_i \alu_l_q_alu + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire width 1 $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $96 + end + process $group_68 + assign \alu_l_r_alu$next \alu_l_r_alu + assign \alu_l_r_alu$next $96 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_l_r_alu$next 1'1 + end + sync init + update \alu_l_r_alu 1'1 + sync posedge \coresync_clk + update \alu_l_r_alu \alu_l_r_alu$next + end + process $group_69 + assign \alu_l_s_alu 1'0 + assign \alu_l_s_alu \all_rd_pulse + sync init + end + process $group_70 + assign \cu_busy_o 1'0 + assign \cu_busy_o \opc_l_q_opc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $98 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire width 1 $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__zero_a + connect \Y $100 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire width 1 $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__imm_data__imm_ok + connect \Y $102 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $98 + connect \B { 1'1 $102 $100 } + connect \Y $104 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $106 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $104 + connect \B $106 + connect \Y $108 + end + process $group_71 + assign \cu_rd__rel_o 3'000 + assign \cu_rd__rel_o $108 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire width 1 \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $110 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $112 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $114 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $116 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 4 $118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B { $110 $112 $114 $116 } + connect \Y $118 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 4 $120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $118 + connect \B \cu_wrmask_o + connect \Y $120 + end + process $group_72 + assign \cu_wr__rel_o 4'0000 + assign \cu_wr__rel_o $120 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $122 + end + process $group_73 + assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $122 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $124 + end + process $group_74 + assign \dest2_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $124 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $126 + end + process $group_75 + assign \dest3_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $126 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest3_o { \data_r2__xer_ov_ok \data_r2__xer_ov } [1:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $128 + end + process $group_76 + assign \dest4_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $128 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0] + end + sync init + end + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.p" +module \p$373 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.n" +module \n$374 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.p" +module \p$375 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.n" +module \n$376 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input" +module \input$377 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 20 \mul_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 22 \mul_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 24 \mul_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 31 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + process $group_0 + assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \a \ra + sync init + end + process $group_1 + assign \ra$14 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$14 \a + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + process $group_2 + assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \b \rb + sync init + end + process $group_3 + assign \rb$15 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$15 \b + assign \rb$15 \rb + sync init + end + process $group_4 + assign \xer_so$16 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" + switch { \mul_op__oe__oe_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:69" + case 1'1 + assign \xer_so$16 \xer_so + end + sync init + end + process $group_5 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_6 + assign \mul_op__insn_type$2 7'0000000 + assign \mul_op__fn_unit$3 11'00000000000 + assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$5 1'0 + assign \mul_op__rc__rc$6 1'0 + assign \mul_op__rc__rc_ok$7 1'0 + assign \mul_op__oe__oe$8 1'0 + assign \mul_op__oe__oe_ok$9 1'0 + assign \mul_op__write_cr0$10 1'0 + assign \mul_op__is_32bit$11 1'0 + assign \mul_op__is_signed$12 1'0 + assign \mul_op__insn$13 32'00000000000000000000000000000000 + assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.mul1" +module \mul1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 20 \mul_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 22 \mul_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 24 \mul_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 31 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire width 1 output 32 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire width 1 output 33 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30" + wire width 1 \is_32bit + process $group_0 + assign \is_32bit 1'0 + assign \is_32bit \mul_op__is_32bit + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" + wire width 1 \sign_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $mux $18 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \mul_op__is_32bit + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $and $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $17 + connect \B \mul_op__is_signed + connect \Y $19 + end + process $group_1 + assign \sign_a 1'0 + assign \sign_a $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" + wire width 1 \sign_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $mux $22 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \mul_op__is_32bit + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $and $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $21 + connect \B \mul_op__is_signed + connect \Y $23 + end + process $group_2 + assign \sign_b 1'0 + assign \sign_b $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" + wire width 1 \sign32_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" + cell $and $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ra [31] + connect \B \mul_op__is_signed + connect \Y $25 + end + process $group_3 + assign \sign32_a 1'0 + assign \sign32_a $25 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" + wire width 1 \sign32_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" + cell $and $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rb [31] + connect \B \mul_op__is_signed + connect \Y $27 + end + process $group_4 + assign \sign32_b 1'0 + assign \sign32_b $27 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" + cell $xor $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign_a + connect \B \sign_b + connect \Y $29 + end + process $group_5 + assign \neg_res 1'0 + assign \neg_res $29 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" + cell $xor $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign32_a + connect \B \sign32_b + connect \Y $31 + end + process $group_6 + assign \neg_res32 1'0 + assign \neg_res32 $31 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50" + wire width 64 \abs_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + wire width 65 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + wire width 65 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $neg $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 65 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + wire width 65 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $mux $39 + parameter \WIDTH 65 + connect \A $36 + connect \B $34 + connect \S \sign_a + connect \Y $38 + end + connect $33 $38 + process $group_7 + assign \abs_a 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \abs_a $33 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51" + wire width 64 \abs_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + wire width 65 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + wire width 65 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $neg $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 65 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + wire width 65 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $mux $46 + parameter \WIDTH 65 + connect \A $43 + connect \B $41 + connect \S \sign_b + connect \Y $45 + end + connect $40 $45 + process $group_8 + assign \abs_b 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \abs_b $40 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + wire width 32 $47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $48 + parameter \WIDTH 32 + connect \A \abs_a [63:32] + connect \B 32'00000000000000000000000000000000 + connect \S \is_32bit + connect \Y $47 + end + process $group_9 + assign \ra$14 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$14 [31:0] \abs_a [31:0] + assign \ra$14 [63:32] $47 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + wire width 32 $49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $50 + parameter \WIDTH 32 + connect \A \abs_b [63:32] + connect \B 32'00000000000000000000000000000000 + connect \S \is_32bit + connect \Y $49 + end + process $group_10 + assign \rb$15 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$15 [31:0] \abs_b [31:0] + assign \rb$15 [63:32] $49 + sync init + end + process $group_11 + assign \xer_so$16 1'0 + assign \xer_so$16 \xer_so + sync init + end + process $group_12 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_13 + assign \mul_op__insn_type$2 7'0000000 + assign \mul_op__fn_unit$3 11'00000000000 + assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$5 1'0 + assign \mul_op__rc__rc$6 1'0 + assign \mul_op__rc__rc_ok$7 1'0 + assign \mul_op__oe__oe$8 1'0 + assign \mul_op__oe__oe_ok$9 1'0 + assign \mul_op__write_cr0$10 1'0 + assign \mul_op__is_32bit$11 1'0 + assign \mul_op__is_signed$12 1'0 + assign \mul_op__insn$13 32'00000000000000000000000000000000 + assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1" +module \mul_pipe1 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 6 \mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 8 \mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 12 \mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire width 1 output 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire width 1 \neg_res$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire width 1 output 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire width 1 \neg_res32$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 22 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 23 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 24 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 25 \mul_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 26 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 27 \mul_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 28 \mul_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 30 \mul_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 32 \mul_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 37 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 38 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 39 \xer_so$16 + cell \p$375 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$376 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute 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\enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \input_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \input_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type$18 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \input_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__imm$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__imm_data__imm_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__rc__rc_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__oe__oe_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \input_xer_so$32 + cell \input$377 \input + connect \muxid \input_muxid + connect \mul_op__insn_type \input_mul_op__insn_type + connect \mul_op__fn_unit \input_mul_op__fn_unit + connect \mul_op__imm_data__imm \input_mul_op__imm_data__imm + connect \mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm_ok + connect \mul_op__rc__rc \input_mul_op__rc__rc + connect \mul_op__rc__rc_ok \input_mul_op__rc__rc_ok + connect \mul_op__oe__oe \input_mul_op__oe__oe + connect \mul_op__oe__oe_ok \input_mul_op__oe__oe_ok + connect \mul_op__write_cr0 \input_mul_op__write_cr0 + connect \mul_op__is_32bit \input_mul_op__is_32bit + connect \mul_op__is_signed \input_mul_op__is_signed + connect \mul_op__insn \input_mul_op__insn + connect \ra \input_ra + connect \rb \input_rb + connect \xer_so \input_xer_so + connect \muxid$1 \input_muxid$17 + connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 + connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 + connect \mul_op__imm_data__imm$4 \input_mul_op__imm_data__imm$20 + connect \mul_op__imm_data__imm_ok$5 \input_mul_op__imm_data__imm_ok$21 + connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 + connect \mul_op__rc__rc_ok$7 \input_mul_op__rc__rc_ok$23 + connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 + connect \mul_op__oe__oe_ok$9 \input_mul_op__oe__oe_ok$25 + connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 + connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 + connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 + connect \mul_op__insn$13 \input_mul_op__insn$29 + connect \ra$14 \input_ra$30 + connect \rb$15 \input_rb$31 + connect \xer_so$16 \input_xer_so$32 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul1_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul1_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \mul1_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul1_muxid$33 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul1_mul_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__rc__rc$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__rc__rc_ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__oe__oe$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__oe__oe_ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul1_mul_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \mul1_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire width 1 \mul1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire width 1 \mul1_neg_res32 + cell \mul1 \mul1 + connect \muxid \mul1_muxid + connect \mul_op__insn_type \mul1_mul_op__insn_type + connect \mul_op__fn_unit \mul1_mul_op__fn_unit + connect \mul_op__imm_data__imm \mul1_mul_op__imm_data__imm + connect \mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm_ok + connect \mul_op__rc__rc \mul1_mul_op__rc__rc + connect \mul_op__rc__rc_ok \mul1_mul_op__rc__rc_ok + connect \mul_op__oe__oe \mul1_mul_op__oe__oe + connect \mul_op__oe__oe_ok \mul1_mul_op__oe__oe_ok + connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 + connect \mul_op__is_32bit \mul1_mul_op__is_32bit + connect \mul_op__is_signed \mul1_mul_op__is_signed + connect \mul_op__insn \mul1_mul_op__insn + connect \ra \mul1_ra + connect \rb \mul1_rb + connect \xer_so \mul1_xer_so + connect \muxid$1 \mul1_muxid$33 + connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 + connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 + connect \mul_op__imm_data__imm$4 \mul1_mul_op__imm_data__imm$36 + connect \mul_op__imm_data__imm_ok$5 \mul1_mul_op__imm_data__imm_ok$37 + connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 + connect \mul_op__rc__rc_ok$7 \mul1_mul_op__rc__rc_ok$39 + connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 + connect \mul_op__oe__oe_ok$9 \mul1_mul_op__oe__oe_ok$41 + connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 + connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 + connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 + connect \mul_op__insn$13 \mul1_mul_op__insn$45 + connect \ra$14 \mul1_ra$46 + connect \rb$15 \mul1_rb$47 + connect \xer_so$16 \mul1_xer_so$48 + connect \neg_res \mul1_neg_res + connect \neg_res32 \mul1_neg_res32 + end + process $group_0 + assign \input_muxid 2'00 + assign \input_muxid \muxid$1 + sync init + end + process $group_1 + assign \input_mul_op__insn_type 7'0000000 + assign \input_mul_op__fn_unit 11'00000000000 + assign \input_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_mul_op__imm_data__imm_ok 1'0 + assign \input_mul_op__rc__rc 1'0 + assign \input_mul_op__rc__rc_ok 1'0 + assign \input_mul_op__oe__oe 1'0 + assign \input_mul_op__oe__oe_ok 1'0 + assign \input_mul_op__write_cr0 1'0 + assign \input_mul_op__is_32bit 1'0 + assign \input_mul_op__is_signed 1'0 + assign \input_mul_op__insn 32'00000000000000000000000000000000 + assign { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 { \input_mul_op__oe__oe_ok \input_mul_op__oe__oe } { \input_mul_op__rc__rc_ok \input_mul_op__rc__rc } { \input_mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm } \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } + sync init + end + process $group_13 + assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_ra \ra$14 + sync init + end + process $group_14 + assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_rb \rb$15 + sync init + end + process $group_15 + assign \input_xer_so 1'0 + assign \input_xer_so \xer_so$16 + sync init + end + process $group_16 + assign \mul1_muxid 2'00 + assign \mul1_muxid \input_muxid$17 + sync init + end + process $group_17 + assign \mul1_mul_op__insn_type 7'0000000 + assign \mul1_mul_op__fn_unit 11'00000000000 + assign \mul1_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul1_mul_op__imm_data__imm_ok 1'0 + assign \mul1_mul_op__rc__rc 1'0 + assign \mul1_mul_op__rc__rc_ok 1'0 + assign \mul1_mul_op__oe__oe 1'0 + assign \mul1_mul_op__oe__oe_ok 1'0 + assign \mul1_mul_op__write_cr0 1'0 + assign \mul1_mul_op__is_32bit 1'0 + assign \mul1_mul_op__is_signed 1'0 + assign \mul1_mul_op__insn 32'00000000000000000000000000000000 + assign { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 { \mul1_mul_op__oe__oe_ok \mul1_mul_op__oe__oe } { \mul1_mul_op__rc__rc_ok \mul1_mul_op__rc__rc } { \mul1_mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm } \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 { \input_mul_op__oe__oe_ok$25 \input_mul_op__oe__oe$24 } { \input_mul_op__rc__rc_ok$23 \input_mul_op__rc__rc$22 } { \input_mul_op__imm_data__imm_ok$21 \input_mul_op__imm_data__imm$20 } \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } + sync init + end + process $group_29 + assign \mul1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul1_ra \input_ra$30 + sync init + end + process $group_30 + assign \mul1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul1_rb \input_rb$31 + sync init + end + process $group_31 + assign \mul1_xer_so 1'0 + assign \mul1_xer_so \input_xer_so$32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$49 + process $group_32 + assign \p_valid_i$49 1'0 + assign \p_valid_i$49 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_33 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$49 + connect \B \p_ready_o + connect \Y $50 + end + process $group_34 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $50 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$52 + process $group_35 + assign \muxid$52 2'00 + assign \muxid$52 \mul1_muxid$33 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$53 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_op__fn_unit$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__imm$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__imm_data__imm_ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc_ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe_ok$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__write_cr0$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_32bit$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_signed$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$64 + process $group_36 + assign \mul_op__insn_type$53 7'0000000 + assign \mul_op__fn_unit$54 11'00000000000 + assign \mul_op__imm_data__imm$55 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$56 1'0 + assign \mul_op__rc__rc$57 1'0 + assign \mul_op__rc__rc_ok$58 1'0 + assign \mul_op__oe__oe$59 1'0 + assign \mul_op__oe__oe_ok$60 1'0 + assign \mul_op__write_cr0$61 1'0 + assign \mul_op__is_32bit$62 1'0 + assign \mul_op__is_signed$63 1'0 + assign \mul_op__insn$64 32'00000000000000000000000000000000 + assign { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__oe_ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__rc_ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__imm_ok$56 \mul_op__imm_data__imm$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 { \mul1_mul_op__oe__oe_ok$41 \mul1_mul_op__oe__oe$40 } { \mul1_mul_op__rc__rc_ok$39 \mul1_mul_op__rc__rc$38 } { \mul1_mul_op__imm_data__imm_ok$37 \mul1_mul_op__imm_data__imm$36 } \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + process $group_48 + assign \ra$65 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$65 \mul1_ra$46 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + process $group_49 + assign \rb$66 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$66 \mul1_rb$47 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$67 + process $group_50 + assign \xer_so$67 1'0 + assign \xer_so$67 \mul1_xer_so$48 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire width 1 \neg_res$68 + process $group_51 + assign \neg_res$68 1'0 + assign \neg_res$68 \mul1_neg_res + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire width 1 \neg_res32$69 + process $group_52 + assign \neg_res32$69 1'0 + assign \neg_res32$69 \mul1_neg_res32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_53 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_54 + assign \muxid$next \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$next \muxid$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$next \muxid$52 + end + sync init + update \muxid 2'00 + sync posedge \coresync_clk + update \muxid \muxid$next + end + process $group_55 + assign \mul_op__insn_type$next \mul_op__insn_type + assign \mul_op__fn_unit$next \mul_op__fn_unit + assign \mul_op__imm_data__imm$next \mul_op__imm_data__imm + assign \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm_ok + assign \mul_op__rc__rc$next \mul_op__rc__rc + assign \mul_op__rc__rc_ok$next \mul_op__rc__rc_ok + assign \mul_op__oe__oe$next \mul_op__oe__oe + assign \mul_op__oe__oe_ok$next \mul_op__oe__oe_ok + assign \mul_op__write_cr0$next \mul_op__write_cr0 + assign \mul_op__is_32bit$next \mul_op__is_32bit + assign \mul_op__is_signed$next \mul_op__is_signed + assign \mul_op__insn$next \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__oe_ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__rc_ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__imm_ok$56 \mul_op__imm_data__imm$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__oe_ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__rc_ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__imm_ok$56 \mul_op__imm_data__imm$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \mul_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$next 1'0 + assign \mul_op__rc__rc$next 1'0 + assign \mul_op__rc__rc_ok$next 1'0 + assign \mul_op__oe__oe$next 1'0 + assign \mul_op__oe__oe_ok$next 1'0 + end + sync init + update \mul_op__insn_type 7'0000000 + update \mul_op__fn_unit 11'00000000000 + update \mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \mul_op__imm_data__imm_ok 1'0 + update \mul_op__rc__rc 1'0 + update \mul_op__rc__rc_ok 1'0 + update \mul_op__oe__oe 1'0 + update \mul_op__oe__oe_ok 1'0 + update \mul_op__write_cr0 1'0 + update \mul_op__is_32bit 1'0 + update \mul_op__is_signed 1'0 + update \mul_op__insn 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \mul_op__insn_type \mul_op__insn_type$next + update \mul_op__fn_unit \mul_op__fn_unit$next + update \mul_op__imm_data__imm \mul_op__imm_data__imm$next + update \mul_op__imm_data__imm_ok \mul_op__imm_data__imm_ok$next + update \mul_op__rc__rc \mul_op__rc__rc$next + update \mul_op__rc__rc_ok \mul_op__rc__rc_ok$next + update \mul_op__oe__oe \mul_op__oe__oe$next + update \mul_op__oe__oe_ok \mul_op__oe__oe_ok$next + update \mul_op__write_cr0 \mul_op__write_cr0$next + update \mul_op__is_32bit \mul_op__is_32bit$next + update \mul_op__is_signed \mul_op__is_signed$next + update \mul_op__insn \mul_op__insn$next + end + process $group_67 + assign \ra$next \ra + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$next \ra$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$next \ra$65 + end + sync init + update \ra 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ra \ra$next + end + process $group_68 + assign \rb$next \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$next \rb$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$next \rb$66 + end + sync init + update \rb 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \rb \rb$next + end + process $group_69 + assign \xer_so$next \xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$next \xer_so$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$next \xer_so$67 + end + sync init + update \xer_so 1'0 + sync posedge \coresync_clk + update \xer_so \xer_so$next + end + process $group_70 + assign \neg_res$next \neg_res + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \neg_res$next \neg_res$68 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \neg_res$next \neg_res$68 + end + sync init + update \neg_res 1'0 + sync posedge \coresync_clk + update \neg_res \neg_res$next + end + process $group_71 + assign \neg_res32$next \neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \neg_res32$next \neg_res32$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \neg_res32$next \neg_res32$69 + end + sync init + update \neg_res32 1'0 + sync posedge \coresync_clk + update \neg_res32 \neg_res32$next + end + process $group_72 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_73 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p" +module \p$378 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.n" +module \n$379 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.mul2" +module \mul2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire width 1 input 16 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire width 1 input 17 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 22 \mul_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 24 \mul_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 26 \mul_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 31 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 32 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire width 1 output 33 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire width 1 output 34 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 129 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 128 $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $mul $19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 128 + connect \A \ra + connect \B \rb + connect \Y $18 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \Y_WIDTH 129 + connect \A $18 + connect \Y $17 + end + process $group_0 + assign \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \o $17 + sync init + end + process $group_1 + assign \neg_res$15 1'0 + assign \neg_res$15 \neg_res + sync init + end + process $group_2 + assign \neg_res32$16 1'0 + assign \neg_res32$16 \neg_res32 + sync init + end + process $group_3 + assign \xer_so$14 1'0 + assign \xer_so$14 \xer_so + sync init + end + process $group_4 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_5 + assign \mul_op__insn_type$2 7'0000000 + assign \mul_op__fn_unit$3 11'00000000000 + assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$5 1'0 + assign \mul_op__rc__rc$6 1'0 + assign \mul_op__rc__rc_ok$7 1'0 + assign \mul_op__oe__oe$8 1'0 + assign \mul_op__oe__oe_ok$9 1'0 + assign \mul_op__write_cr0$10 1'0 + assign \mul_op__is_32bit$11 1'0 + assign \mul_op__is_signed$12 1'0 + assign \mul_op__insn$13 32'00000000000000000000000000000000 + assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2" +module \mul_pipe2 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire width 1 input 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire width 1 input 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 22 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 23 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 25 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 26 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 27 \mul_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \mul_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \mul_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \mul_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 37 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 output 38 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire width 1 output 39 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire width 1 \neg_res$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire width 1 output 40 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire width 1 \neg_res32$16$next + cell \p$378 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$379 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul2_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul2_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \mul2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire width 1 \mul2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire width 1 \mul2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul2_muxid$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type$18 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul2_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__imm$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__imm_data__imm_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__rc__rc_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__oe__oe_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul2_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \mul2_xer_so$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire width 1 \mul2_neg_res$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire width 1 \mul2_neg_res32$32 + cell \mul2 \mul2 + connect \muxid \mul2_muxid + connect \mul_op__insn_type \mul2_mul_op__insn_type + connect \mul_op__fn_unit \mul2_mul_op__fn_unit + connect \mul_op__imm_data__imm \mul2_mul_op__imm_data__imm + connect \mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm_ok + connect \mul_op__rc__rc \mul2_mul_op__rc__rc + connect \mul_op__rc__rc_ok \mul2_mul_op__rc__rc_ok + connect \mul_op__oe__oe \mul2_mul_op__oe__oe + connect \mul_op__oe__oe_ok \mul2_mul_op__oe__oe_ok + connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 + connect \mul_op__is_32bit \mul2_mul_op__is_32bit + connect \mul_op__is_signed \mul2_mul_op__is_signed + connect \mul_op__insn \mul2_mul_op__insn + connect \ra \mul2_ra + connect \rb \mul2_rb + connect \xer_so \mul2_xer_so + connect \neg_res \mul2_neg_res + connect \neg_res32 \mul2_neg_res32 + connect \muxid$1 \mul2_muxid$17 + connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 + connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 + connect \mul_op__imm_data__imm$4 \mul2_mul_op__imm_data__imm$20 + connect \mul_op__imm_data__imm_ok$5 \mul2_mul_op__imm_data__imm_ok$21 + connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 + connect \mul_op__rc__rc_ok$7 \mul2_mul_op__rc__rc_ok$23 + connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 + connect \mul_op__oe__oe_ok$9 \mul2_mul_op__oe__oe_ok$25 + connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 + connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 + connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 + connect \mul_op__insn$13 \mul2_mul_op__insn$29 + connect \o \mul2_o + connect \xer_so$14 \mul2_xer_so$30 + connect \neg_res$15 \mul2_neg_res$31 + connect \neg_res32$16 \mul2_neg_res32$32 + end + process $group_0 + assign \mul2_muxid 2'00 + assign \mul2_muxid \muxid + sync init + end + process $group_1 + assign \mul2_mul_op__insn_type 7'0000000 + assign \mul2_mul_op__fn_unit 11'00000000000 + assign \mul2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul2_mul_op__imm_data__imm_ok 1'0 + assign \mul2_mul_op__rc__rc 1'0 + assign \mul2_mul_op__rc__rc_ok 1'0 + assign \mul2_mul_op__oe__oe 1'0 + assign \mul2_mul_op__oe__oe_ok 1'0 + assign \mul2_mul_op__write_cr0 1'0 + assign \mul2_mul_op__is_32bit 1'0 + assign \mul2_mul_op__is_signed 1'0 + assign \mul2_mul_op__insn 32'00000000000000000000000000000000 + assign { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 { \mul2_mul_op__oe__oe_ok \mul2_mul_op__oe__oe } { \mul2_mul_op__rc__rc_ok \mul2_mul_op__rc__rc } { \mul2_mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm } \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + sync init + end + process $group_13 + assign \mul2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul2_ra \ra + sync init + end + process $group_14 + assign \mul2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul2_rb \rb + sync init + end + process $group_15 + assign \mul2_xer_so 1'0 + assign \mul2_xer_so \xer_so + sync init + end + process $group_16 + assign \mul2_neg_res 1'0 + assign \mul2_neg_res \neg_res + sync init + end + process $group_17 + assign \mul2_neg_res32 1'0 + assign \mul2_neg_res32 \neg_res32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$33 + process $group_18 + assign \p_valid_i$33 1'0 + assign \p_valid_i$33 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_19 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$33 + connect \B \p_ready_o + connect \Y $34 + end + process $group_20 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $34 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$36 + process $group_21 + assign \muxid$36 2'00 + assign \muxid$36 \mul2_muxid$17 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$37 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_op__fn_unit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__imm$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__imm_data__imm_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe_ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__write_cr0$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_32bit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_signed$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$48 + process $group_22 + assign \mul_op__insn_type$37 7'0000000 + assign \mul_op__fn_unit$38 11'00000000000 + assign \mul_op__imm_data__imm$39 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$40 1'0 + assign \mul_op__rc__rc$41 1'0 + assign \mul_op__rc__rc_ok$42 1'0 + assign \mul_op__oe__oe$43 1'0 + assign \mul_op__oe__oe_ok$44 1'0 + assign \mul_op__write_cr0$45 1'0 + assign \mul_op__is_32bit$46 1'0 + assign \mul_op__is_signed$47 1'0 + assign \mul_op__insn$48 32'00000000000000000000000000000000 + assign { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__oe_ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__rc_ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__imm_ok$40 \mul_op__imm_data__imm$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 { \mul2_mul_op__oe__oe_ok$25 \mul2_mul_op__oe__oe$24 } { \mul2_mul_op__rc__rc_ok$23 \mul2_mul_op__rc__rc$22 } { \mul2_mul_op__imm_data__imm_ok$21 \mul2_mul_op__imm_data__imm$20 } \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$49 + process $group_34 + assign \o$49 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \o$49 \mul2_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \xer_so$50 + process $group_35 + assign \xer_so$50 1'0 + assign \xer_so$50 \mul2_xer_so$30 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire width 1 \neg_res$51 + process $group_36 + assign \neg_res$51 1'0 + assign \neg_res$51 \mul2_neg_res$31 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire width 1 \neg_res32$52 + process $group_37 + assign \neg_res32$52 1'0 + assign \neg_res32$52 \mul2_neg_res32$32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_38 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_39 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$36 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_40 + assign \mul_op__insn_type$2$next \mul_op__insn_type$2 + assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3 + assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4 + assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5 + assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6 + assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7 + assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8 + assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9 + assign \mul_op__write_cr0$10$next \mul_op__write_cr0$10 + assign \mul_op__is_32bit$11$next \mul_op__is_32bit$11 + assign \mul_op__is_signed$12$next \mul_op__is_signed$12 + assign \mul_op__insn$13$next \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__oe_ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__rc_ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__imm_ok$40 \mul_op__imm_data__imm$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__oe_ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__rc_ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__imm_ok$40 \mul_op__imm_data__imm$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$5$next 1'0 + assign \mul_op__rc__rc$6$next 1'0 + assign \mul_op__rc__rc_ok$7$next 1'0 + assign \mul_op__oe__oe$8$next 1'0 + assign \mul_op__oe__oe_ok$9$next 1'0 + end + sync init + update \mul_op__insn_type$2 7'0000000 + update \mul_op__fn_unit$3 11'00000000000 + update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \mul_op__imm_data__imm_ok$5 1'0 + update \mul_op__rc__rc$6 1'0 + update \mul_op__rc__rc_ok$7 1'0 + update \mul_op__oe__oe$8 1'0 + update \mul_op__oe__oe_ok$9 1'0 + update \mul_op__write_cr0$10 1'0 + update \mul_op__is_32bit$11 1'0 + update \mul_op__is_signed$12 1'0 + update \mul_op__insn$13 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \mul_op__insn_type$2 \mul_op__insn_type$2$next + update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next + update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next + update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next + update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next + update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next + update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next + update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next + update \mul_op__write_cr0$10 \mul_op__write_cr0$10$next + update \mul_op__is_32bit$11 \mul_op__is_32bit$11$next + update \mul_op__is_signed$12 \mul_op__is_signed$12$next + update \mul_op__insn$13 \mul_op__insn$13$next + end + process $group_52 + assign \o$next \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \o$next \o$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \o$next \o$49 + end + sync init + update \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \o \o$next + end + process $group_53 + assign \xer_so$14$next \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$14$next \xer_so$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$14$next \xer_so$50 + end + sync init + update \xer_so$14 1'0 + sync posedge \coresync_clk + update \xer_so$14 \xer_so$14$next + end + process $group_54 + assign \neg_res$15$next \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \neg_res$15$next \neg_res$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \neg_res$15$next \neg_res$51 + end + sync init + update \neg_res$15 1'0 + sync posedge \coresync_clk + update \neg_res$15 \neg_res$15$next + end + process $group_55 + assign \neg_res32$16$next \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \neg_res32$16$next \neg_res32$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \neg_res32$16$next \neg_res32$52 + end + sync init + update \neg_res32$16 1'0 + sync posedge \coresync_clk + update \neg_res32$16 \neg_res32$16$next + end + process $group_56 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_57 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.p" +module \p$380 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n" +module \n$381 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3" +module \mul3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 14 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire width 1 input 15 \neg_res + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 20 \mul_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 22 \mul_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 24 \mul_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 29 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 30 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 31 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 32 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 33 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" + wire width 1 \is_32bit + process $group_0 + assign \is_32bit 1'0 + assign \is_32bit \mul_op__is_32bit + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" + wire width 129 \mul_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $neg $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 130 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $19 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $mux $22 + parameter \WIDTH 130 + connect \A $19 + connect \B $17 + connect \S \neg_res + connect \Y $21 + end + connect $16 $21 + process $group_1 + assign \mul_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \mul_o $16 [128:0] + sync init + end + wire width 1 $verilog_initial_trigger + process $group_2 + assign \o_ok 1'0 + assign \o_ok 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_3 + assign \o$14 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" + switch \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" + attribute \nmigen.decoding "OP_MUL_H32/52" + case 7'0110100 + assign \o$14 { \mul_o [63:32] \mul_o [63:32] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" + attribute \nmigen.decoding "OP_MUL_H64/51" + case 7'0110011 + assign \o$14 \mul_o [127:64] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" + attribute \nmigen.decoding "" + case + assign \o$14 \mul_o [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:58" + wire width 1 \mul_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + cell $reduce_bool $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + wire width 1 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + cell $reduce_and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + cell $not $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $26 + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63" + cell $and $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $23 + connect \B $25 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + cell $reduce_and $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + cell $not $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $34 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68" + cell $and $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $31 + connect \B $33 + connect \Y $37 + end + process $group_4 + assign \mul_ov 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" + switch \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" + attribute \nmigen.decoding "OP_MUL_H32/52" + case 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" + attribute \nmigen.decoding "OP_MUL_H64/51" + case 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59" + switch { \is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59" + case 1'1 + assign \mul_ov $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:64" + case + assign \mul_ov $37 + end + end + sync init + end + process $group_5 + assign \xer_ov 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" + switch \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" + attribute \nmigen.decoding "OP_MUL_H32/52" + case 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" + attribute \nmigen.decoding "OP_MUL_H64/51" + case 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" + attribute \nmigen.decoding "" + case + assign \xer_ov { \mul_ov \mul_ov } + end + sync init + end + process $group_6 + assign \xer_ov_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45" + switch \mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47" + attribute \nmigen.decoding "OP_MUL_H32/52" + case 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" + attribute \nmigen.decoding "OP_MUL_H64/51" + case 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53" + attribute \nmigen.decoding "" + case + assign \xer_ov_ok 1'1 + end + sync init + end + process $group_7 + assign \xer_so$15 1'0 + assign \xer_so$15 \xer_so + sync init + end + process $group_8 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_9 + assign \mul_op__insn_type$2 7'0000000 + assign \mul_op__fn_unit$3 11'00000000000 + assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$5 1'0 + assign \mul_op__rc__rc$6 1'0 + assign \mul_op__rc__rc_ok$7 1'0 + assign \mul_op__oe__oe$8 1'0 + assign \mul_op__oe__oe_ok$9 1'0 + assign \mul_op__write_cr0$10 1'0 + assign \mul_op__is_32bit$11 1'0 + assign \mul_op__is_signed$12 1'0 + assign \mul_op__insn$13 32'00000000000000000000000000000000 + assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output" +module \output$382 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 14 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 16 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 22 \mul_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 24 \mul_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 26 \mul_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 31 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 32 \o_ok$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 33 \cr_a$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 34 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 35 \xer_ov$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 36 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 37 \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" + wire width 65 \o$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $20 + end + process $group_0 + assign \o$19 65'00000000000000000000000000000000000000000000000000000000000000000 + assign \o$19 $20 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + wire width 64 \target + process $group_1 + assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \target \o$19 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + wire width 1 \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + cell $eq $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001010 + connect \Y $22 + end + process $group_2 + assign \is_cmp 1'0 + assign \is_cmp $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + wire width 1 \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + cell $eq $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001100 + connect \Y $24 + end + process $group_3 + assign \is_cmpeqb 1'0 + assign \is_cmpeqb $24 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + wire width 1 \msb_test + process $group_4 + assign \msb_test 1'0 + assign \msb_test \target [63] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 1 \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 1 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + cell $reduce_bool $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $26 + end + process $group_5 + assign \is_nzero 1'0 + assign \is_nzero $26 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + wire width 1 \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $not $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $and $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $28 + connect \Y $30 + end + process $group_6 + assign \is_positive 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_positive \msb_test + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_positive $30 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" + wire width 1 \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $not $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $and $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $32 + connect \Y $34 + end + process $group_7 + assign \is_negative 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_negative $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_negative \msb_test + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + cell $not $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $36 + end + process $group_8 + assign \cr0 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + switch { \is_cmpeqb } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + case 1'1 + assign \cr0 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + case + assign \cr0 { \is_negative \is_positive $36 \xer_so$18 } + end + sync init + end + process $group_9 + assign \o$14 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o$14 \o$19 [63:0] + sync init + end + process $group_10 + assign \o_ok$15 1'0 + assign \o_ok$15 \o_ok + sync init + end + process $group_11 + assign \cr_a$16 4'0000 + assign \cr_a$16 \cr0 + sync init + end + process $group_12 + assign \cr_a_ok 1'0 + assign \cr_a_ok \mul_op__write_cr0 + sync init + end + process $group_13 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_14 + assign \mul_op__insn_type$2 7'0000000 + assign \mul_op__fn_unit$3 11'00000000000 + assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$5 1'0 + assign \mul_op__rc__rc$6 1'0 + assign \mul_op__rc__rc_ok$7 1'0 + assign \mul_op__oe__oe$8 1'0 + assign \mul_op__oe__oe_ok$9 1'0 + assign \mul_op__write_cr0$10 1'0 + assign \mul_op__is_32bit$11 1'0 + assign \mul_op__is_signed$12 1'0 + assign \mul_op__insn$13 32'00000000000000000000000000000000 + assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28" + wire width 1 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + cell $and $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__oe_ok + connect \Y $38 + end + process $group_26 + assign \oe 1'0 + assign \oe $38 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" + wire width 1 \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" + cell $or $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $40 + end + process $group_27 + assign \so 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \so $40 + end + sync init + end + process $group_28 + assign \xer_so$18 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_so$18 \so + end + sync init + end + process $group_29 + assign \xer_so_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_so_ok 1'1 + end + sync init + end + process $group_30 + assign \xer_ov$17 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_ov$17 \xer_ov + end + sync init + end + process $group_31 + assign \xer_ov_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + switch { \oe } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + case 1'1 + assign \xer_ov_ok 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3" +module \mul_pipe3 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 18 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire width 1 input 19 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire width 1 input 20 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 21 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 22 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 25 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \mul_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \mul_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \mul_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 30 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 31 \mul_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe_ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 35 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 36 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 37 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 38 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 39 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 40 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 41 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 42 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 43 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$next + cell \p$380 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$381 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul3_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul3_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \mul3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire width 1 \mul3_neg_res + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul3_muxid$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type$17 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul3_mul_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__imm$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__imm_data__imm_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__rc__rc$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__rc__rc_ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__oe__oe$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__oe__oe_ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__write_cr0$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__is_32bit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul3_mul_op__is_signed$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \mul3_o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \mul3_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \mul3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \mul3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \mul3_xer_so$30 + cell \mul3 \mul3 + connect \muxid \mul3_muxid + connect \mul_op__insn_type \mul3_mul_op__insn_type + connect \mul_op__fn_unit \mul3_mul_op__fn_unit + connect \mul_op__imm_data__imm \mul3_mul_op__imm_data__imm + connect \mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm_ok + connect \mul_op__rc__rc \mul3_mul_op__rc__rc + connect \mul_op__rc__rc_ok \mul3_mul_op__rc__rc_ok + connect \mul_op__oe__oe \mul3_mul_op__oe__oe + connect \mul_op__oe__oe_ok \mul3_mul_op__oe__oe_ok + connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 + connect \mul_op__is_32bit \mul3_mul_op__is_32bit + connect \mul_op__is_signed \mul3_mul_op__is_signed + connect \mul_op__insn \mul3_mul_op__insn + connect \o \mul3_o + connect \xer_so \mul3_xer_so + connect \neg_res \mul3_neg_res + connect \muxid$1 \mul3_muxid$16 + connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 + connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 + connect \mul_op__imm_data__imm$4 \mul3_mul_op__imm_data__imm$19 + connect \mul_op__imm_data__imm_ok$5 \mul3_mul_op__imm_data__imm_ok$20 + connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 + connect \mul_op__rc__rc_ok$7 \mul3_mul_op__rc__rc_ok$22 + connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 + connect \mul_op__oe__oe_ok$9 \mul3_mul_op__oe__oe_ok$24 + connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 + connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 + connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 + connect \mul_op__insn$13 \mul3_mul_op__insn$28 + connect \o$14 \mul3_o$29 + connect \o_ok \mul3_o_ok + connect \xer_ov \mul3_xer_ov + connect \xer_ov_ok \mul3_xer_ov_ok + connect \xer_so$15 \mul3_xer_so$30 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \output_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$31 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type$32 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \output_mul_op__fn_unit$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__imm$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__imm_data__imm_ok$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__rc__rc$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__rc__rc_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__oe__oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__oe__oe_ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__write_cr0$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__is_32bit$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_mul_op__is_signed$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_o_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_so_ok + cell \output$382 \output + connect \muxid \output_muxid + connect \mul_op__insn_type \output_mul_op__insn_type + connect \mul_op__fn_unit \output_mul_op__fn_unit + connect \mul_op__imm_data__imm \output_mul_op__imm_data__imm + connect \mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm_ok + connect \mul_op__rc__rc \output_mul_op__rc__rc + connect \mul_op__rc__rc_ok \output_mul_op__rc__rc_ok + connect \mul_op__oe__oe \output_mul_op__oe__oe + connect \mul_op__oe__oe_ok \output_mul_op__oe__oe_ok + connect \mul_op__write_cr0 \output_mul_op__write_cr0 + connect \mul_op__is_32bit \output_mul_op__is_32bit + connect \mul_op__is_signed \output_mul_op__is_signed + connect \mul_op__insn \output_mul_op__insn + connect \o \output_o + connect \o_ok \output_o_ok + connect \cr_a \output_cr_a + connect \xer_ov \output_xer_ov + connect \xer_so \output_xer_so + connect \muxid$1 \output_muxid$31 + connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 + connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 + connect \mul_op__imm_data__imm$4 \output_mul_op__imm_data__imm$34 + connect \mul_op__imm_data__imm_ok$5 \output_mul_op__imm_data__imm_ok$35 + connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 + connect \mul_op__rc__rc_ok$7 \output_mul_op__rc__rc_ok$37 + connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 + connect \mul_op__oe__oe_ok$9 \output_mul_op__oe__oe_ok$39 + connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 + connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 + connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 + connect \mul_op__insn$13 \output_mul_op__insn$43 + connect \o$14 \output_o$44 + connect \o_ok$15 \output_o_ok$45 + connect \cr_a$16 \output_cr_a$46 + connect \cr_a_ok \output_cr_a_ok + connect \xer_ov$17 \output_xer_ov$47 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so$18 \output_xer_so$48 + connect \xer_so_ok \output_xer_so_ok + end + process $group_0 + assign \mul3_muxid 2'00 + assign \mul3_muxid \muxid + sync init + end + process $group_1 + assign \mul3_mul_op__insn_type 7'0000000 + assign \mul3_mul_op__fn_unit 11'00000000000 + assign \mul3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul3_mul_op__imm_data__imm_ok 1'0 + assign \mul3_mul_op__rc__rc 1'0 + assign \mul3_mul_op__rc__rc_ok 1'0 + assign \mul3_mul_op__oe__oe 1'0 + assign \mul3_mul_op__oe__oe_ok 1'0 + assign \mul3_mul_op__write_cr0 1'0 + assign \mul3_mul_op__is_32bit 1'0 + assign \mul3_mul_op__is_signed 1'0 + assign \mul3_mul_op__insn 32'00000000000000000000000000000000 + assign { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 { \mul3_mul_op__oe__oe_ok \mul3_mul_op__oe__oe } { \mul3_mul_op__rc__rc_ok \mul3_mul_op__rc__rc } { \mul3_mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm } \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + sync init + end + process $group_13 + assign \mul3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \mul3_o \o + sync init + end + process $group_14 + assign \mul3_xer_so 1'0 + assign \mul3_xer_so \xer_so + sync init + end + process $group_15 + assign \mul3_neg_res 1'0 + assign \mul3_neg_res \neg_res + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire width 1 \neg_res32$49 + process $group_16 + assign \neg_res32$49 1'0 + assign \neg_res32$49 \neg_res32 + sync init + end + process $group_17 + assign \output_muxid 2'00 + assign \output_muxid \mul3_muxid$16 + sync init + end + process $group_18 + assign \output_mul_op__insn_type 7'0000000 + assign \output_mul_op__fn_unit 11'00000000000 + assign \output_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_mul_op__imm_data__imm_ok 1'0 + assign \output_mul_op__rc__rc 1'0 + assign \output_mul_op__rc__rc_ok 1'0 + assign \output_mul_op__oe__oe 1'0 + assign \output_mul_op__oe__oe_ok 1'0 + assign \output_mul_op__write_cr0 1'0 + assign \output_mul_op__is_32bit 1'0 + assign \output_mul_op__is_signed 1'0 + assign \output_mul_op__insn 32'00000000000000000000000000000000 + assign { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 { \output_mul_op__oe__oe_ok \output_mul_op__oe__oe } { \output_mul_op__rc__rc_ok \output_mul_op__rc__rc } { \output_mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm } \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 { \mul3_mul_op__oe__oe_ok$24 \mul3_mul_op__oe__oe$23 } { \mul3_mul_op__rc__rc_ok$22 \mul3_mul_op__rc__rc$21 } { \mul3_mul_op__imm_data__imm_ok$20 \mul3_mul_op__imm_data__imm$19 } \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } + sync init + end + process $group_30 + assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_o_ok 1'0 + assign { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$52 + process $group_32 + assign \output_cr_a 4'0000 + assign \cr_a_ok$50 1'0 + assign { \cr_a_ok$50 \output_cr_a } { \cr_a_ok$52 \cr_a$51 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$53 + process $group_34 + assign \output_xer_ov 2'00 + assign \xer_ov_ok$53 1'0 + assign { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$55 + process $group_36 + assign \output_xer_so 1'0 + assign \xer_so_ok$54 1'0 + assign { \xer_so_ok$54 \output_xer_so } { \xer_so_ok$55 \mul3_xer_so$30 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$56 + process $group_38 + assign \p_valid_i$56 1'0 + assign \p_valid_i$56 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_39 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$56 + connect \B \p_ready_o + connect \Y $57 + end + process $group_40 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $57 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$59 + process $group_41 + assign \muxid$59 2'00 + assign \muxid$59 \output_muxid$31 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$60 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_op__fn_unit$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__imm$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__imm_data__imm_ok$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc_ok$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe_ok$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__write_cr0$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_32bit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_signed$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$71 + process $group_42 + assign \mul_op__insn_type$60 7'0000000 + assign \mul_op__fn_unit$61 11'00000000000 + assign \mul_op__imm_data__imm$62 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$63 1'0 + assign \mul_op__rc__rc$64 1'0 + assign \mul_op__rc__rc_ok$65 1'0 + assign \mul_op__oe__oe$66 1'0 + assign \mul_op__oe__oe_ok$67 1'0 + assign \mul_op__write_cr0$68 1'0 + assign \mul_op__is_32bit$69 1'0 + assign \mul_op__is_signed$70 1'0 + assign \mul_op__insn$71 32'00000000000000000000000000000000 + assign { \mul_op__insn$71 \mul_op__is_signed$70 \mul_op__is_32bit$69 \mul_op__write_cr0$68 { \mul_op__oe__oe_ok$67 \mul_op__oe__oe$66 } { \mul_op__rc__rc_ok$65 \mul_op__rc__rc$64 } { \mul_op__imm_data__imm_ok$63 \mul_op__imm_data__imm$62 } \mul_op__fn_unit$61 \mul_op__insn_type$60 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 { \output_mul_op__oe__oe_ok$39 \output_mul_op__oe__oe$38 } { \output_mul_op__rc__rc_ok$37 \output_mul_op__rc__rc$36 } { \output_mul_op__imm_data__imm_ok$35 \output_mul_op__imm_data__imm$34 } \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$73 + process $group_54 + assign \o$72 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$73 1'0 + assign { \o_ok$73 \o$72 } { \output_o_ok$45 \output_o$44 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$75 + process $group_56 + assign \cr_a$74 4'0000 + assign \cr_a_ok$75 1'0 + assign { \cr_a_ok$75 \cr_a$74 } { \output_cr_a_ok \output_cr_a$46 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ov_ok$77 + process $group_58 + assign \xer_ov$76 2'00 + assign \xer_ov_ok$77 1'0 + assign { \xer_ov_ok$77 \xer_ov$76 } { \output_xer_ov_ok \output_xer_ov$47 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_so_ok$79 + process $group_60 + assign \xer_so$78 1'0 + assign \xer_so_ok$79 1'0 + assign { \xer_so_ok$79 \xer_so$78 } { \output_xer_so_ok \output_xer_so$48 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_62 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_63 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$59 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_64 + assign \mul_op__insn_type$2$next \mul_op__insn_type$2 + assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3 + assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4 + assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5 + assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6 + assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7 + assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8 + assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9 + assign \mul_op__write_cr0$10$next \mul_op__write_cr0$10 + assign \mul_op__is_32bit$11$next \mul_op__is_32bit$11 + assign \mul_op__is_signed$12$next \mul_op__is_signed$12 + assign \mul_op__insn$13$next \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$71 \mul_op__is_signed$70 \mul_op__is_32bit$69 \mul_op__write_cr0$68 { \mul_op__oe__oe_ok$67 \mul_op__oe__oe$66 } { \mul_op__rc__rc_ok$65 \mul_op__rc__rc$64 } { \mul_op__imm_data__imm_ok$63 \mul_op__imm_data__imm$62 } \mul_op__fn_unit$61 \mul_op__insn_type$60 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$71 \mul_op__is_signed$70 \mul_op__is_32bit$69 \mul_op__write_cr0$68 { \mul_op__oe__oe_ok$67 \mul_op__oe__oe$66 } { \mul_op__rc__rc_ok$65 \mul_op__rc__rc$64 } { \mul_op__imm_data__imm_ok$63 \mul_op__imm_data__imm$62 } \mul_op__fn_unit$61 \mul_op__insn_type$60 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$5$next 1'0 + assign \mul_op__rc__rc$6$next 1'0 + assign \mul_op__rc__rc_ok$7$next 1'0 + assign \mul_op__oe__oe$8$next 1'0 + assign \mul_op__oe__oe_ok$9$next 1'0 + end + sync init + update \mul_op__insn_type$2 7'0000000 + update \mul_op__fn_unit$3 11'00000000000 + update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \mul_op__imm_data__imm_ok$5 1'0 + update \mul_op__rc__rc$6 1'0 + update \mul_op__rc__rc_ok$7 1'0 + update \mul_op__oe__oe$8 1'0 + update \mul_op__oe__oe_ok$9 1'0 + update \mul_op__write_cr0$10 1'0 + update \mul_op__is_32bit$11 1'0 + update \mul_op__is_signed$12 1'0 + update \mul_op__insn$13 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \mul_op__insn_type$2 \mul_op__insn_type$2$next + update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next + update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next + update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next + update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next + update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next + update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next + update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next + update \mul_op__write_cr0$10 \mul_op__write_cr0$10$next + update \mul_op__is_32bit$11 \mul_op__is_32bit$11$next + update \mul_op__is_signed$12 \mul_op__is_signed$12$next + update \mul_op__insn$13 \mul_op__insn$13$next + end + process $group_76 + assign \o$14$next \o$14 + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$14$next } { \o_ok$73 \o$72 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$14$next } { \o_ok$73 \o$72 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \o_ok$next 1'0 + end + sync init + update \o$14 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 + sync posedge \coresync_clk + update \o$14 \o$14$next + update \o_ok \o_ok$next + end + process $group_78 + assign \cr_a$next \cr_a + assign \cr_a_ok$next \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$75 \cr_a$74 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$75 \cr_a$74 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cr_a_ok$next 1'0 + end + sync init + update \cr_a 4'0000 + update \cr_a_ok 1'0 + sync posedge \coresync_clk + update \cr_a \cr_a$next + update \cr_a_ok \cr_a_ok$next + end + process $group_80 + assign \xer_ov$next \xer_ov + assign \xer_ov_ok$next \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$77 \xer_ov$76 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$77 \xer_ov$76 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ov_ok$next 1'0 + end + sync init + update \xer_ov 2'00 + update \xer_ov_ok 1'0 + sync posedge \coresync_clk + update \xer_ov \xer_ov$next + update \xer_ov_ok \xer_ov_ok$next + end + process $group_82 + assign \xer_so$15$next \xer_so$15 + assign \xer_so_ok$next \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_so_ok$next \xer_so$15$next } { \xer_so_ok$79 \xer_so$78 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_so_ok$next \xer_so$15$next } { \xer_so_ok$79 \xer_so$78 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_so_ok$next 1'0 + end + sync init + update \xer_so$15 1'0 + update \xer_so_ok 1'0 + sync posedge \coresync_clk + update \xer_so$15 \xer_so$15$next + update \xer_so_ok \xer_so_ok$next + end + process $group_84 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_85 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \cr_a$51 4'0000 + connect \cr_a_ok$52 1'0 + connect \xer_so_ok$55 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0" +module \alu_mul0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \xer_so_ok + attribute \src "simple/issuer.py:102" + wire width 1 input 5 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 7 \n_ready_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 9 \mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 input 26 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 27 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 28 \p_ready_o + cell \p$373 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$374 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \mul_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \mul_pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe1_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_pipe1_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \mul_pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire width 1 \mul_pipe1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire width 1 \mul_pipe1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \mul_pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \mul_pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe1_muxid$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type$3 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_pipe1_mul_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__imm$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__is_32bit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe1_mul_op__is_signed$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \mul_pipe1_xer_so$17 + cell \mul_pipe1 \mul_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \n_valid_o \mul_pipe1_n_valid_o + connect \n_ready_i \mul_pipe1_n_ready_i + connect \muxid \mul_pipe1_muxid + connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type + connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit + connect \mul_op__imm_data__imm \mul_pipe1_mul_op__imm_data__imm + connect \mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm_ok + connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc + connect \mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc_ok + connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe + connect \mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe_ok + connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 + connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit + connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed + connect \mul_op__insn \mul_pipe1_mul_op__insn + connect \ra \mul_pipe1_ra + connect \rb \mul_pipe1_rb + connect \xer_so \mul_pipe1_xer_so + connect \neg_res \mul_pipe1_neg_res + connect \neg_res32 \mul_pipe1_neg_res32 + connect \p_valid_i \mul_pipe1_p_valid_i + connect \p_ready_o \mul_pipe1_p_ready_o + connect \muxid$1 \mul_pipe1_muxid$2 + connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 + connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 + connect \mul_op__imm_data__imm$4 \mul_pipe1_mul_op__imm_data__imm$5 + connect \mul_op__imm_data__imm_ok$5 \mul_pipe1_mul_op__imm_data__imm_ok$6 + connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 + connect \mul_op__rc__rc_ok$7 \mul_pipe1_mul_op__rc__rc_ok$8 + connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 + connect \mul_op__oe__oe_ok$9 \mul_pipe1_mul_op__oe__oe_ok$10 + connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 + connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 + connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 + connect \mul_op__insn$13 \mul_pipe1_mul_op__insn$14 + connect \ra$14 \mul_pipe1_ra$15 + connect \rb$15 \mul_pipe1_rb$16 + connect \xer_so$16 \mul_pipe1_xer_so$17 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \mul_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \mul_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe2_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_pipe2_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \mul_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire width 1 \mul_pipe2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire width 1 \mul_pipe2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \mul_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \mul_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe2_muxid$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type$19 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_pipe2_mul_op__fn_unit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__imm$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__rc__rc$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__rc__rc_ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__oe__oe$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__oe__oe_ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__write_cr0$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe2_mul_op__is_signed$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \mul_pipe2_xer_so$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire width 1 \mul_pipe2_neg_res$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire width 1 \mul_pipe2_neg_res32$33 + cell \mul_pipe2 \mul_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \mul_pipe2_p_valid_i + connect \p_ready_o \mul_pipe2_p_ready_o + connect \muxid \mul_pipe2_muxid + connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type + connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit + connect \mul_op__imm_data__imm \mul_pipe2_mul_op__imm_data__imm + connect \mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm_ok + connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc + connect \mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc_ok + connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe + connect \mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe_ok + connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 + connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit + connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed + connect \mul_op__insn \mul_pipe2_mul_op__insn + connect \ra \mul_pipe2_ra + connect \rb \mul_pipe2_rb + connect \xer_so \mul_pipe2_xer_so + connect \neg_res \mul_pipe2_neg_res + connect \neg_res32 \mul_pipe2_neg_res32 + connect \n_valid_o \mul_pipe2_n_valid_o + connect \n_ready_i \mul_pipe2_n_ready_i + connect \muxid$1 \mul_pipe2_muxid$18 + connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 + connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 + connect \mul_op__imm_data__imm$4 \mul_pipe2_mul_op__imm_data__imm$21 + connect \mul_op__imm_data__imm_ok$5 \mul_pipe2_mul_op__imm_data__imm_ok$22 + connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 + connect \mul_op__rc__rc_ok$7 \mul_pipe2_mul_op__rc__rc_ok$24 + connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 + connect \mul_op__oe__oe_ok$9 \mul_pipe2_mul_op__oe__oe_ok$26 + connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 + connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 + connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 + connect \mul_op__insn$13 \mul_pipe2_mul_op__insn$30 + connect \o \mul_pipe2_o + connect \xer_so$14 \mul_pipe2_xer_so$31 + connect \neg_res$15 \mul_pipe2_neg_res$32 + connect \neg_res32$16 \mul_pipe2_neg_res32$33 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \mul_pipe3_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \mul_pipe3_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe3_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_pipe3_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \mul_pipe3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire width 1 \mul_pipe3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire width 1 \mul_pipe3_neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \mul_pipe3_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \mul_pipe3_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe3_muxid$34 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type$35 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_pipe3_mul_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__imm$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__write_cr0$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__is_32bit$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_pipe3_mul_op__is_signed$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \mul_pipe3_o$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \mul_pipe3_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \mul_pipe3_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \mul_pipe3_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \mul_pipe3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \mul_pipe3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \mul_pipe3_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \mul_pipe3_xer_so_ok + cell \mul_pipe3 \mul_pipe3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \mul_pipe3_p_valid_i + connect \p_ready_o \mul_pipe3_p_ready_o + connect \muxid \mul_pipe3_muxid + connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type + connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit + connect \mul_op__imm_data__imm \mul_pipe3_mul_op__imm_data__imm + connect \mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm_ok + connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc + connect \mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc_ok + connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe + connect \mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe_ok + connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 + connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit + connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed + connect \mul_op__insn \mul_pipe3_mul_op__insn + connect \o \mul_pipe3_o + connect \xer_so \mul_pipe3_xer_so + connect \neg_res \mul_pipe3_neg_res + connect \neg_res32 \mul_pipe3_neg_res32 + connect \n_valid_o \mul_pipe3_n_valid_o + connect \n_ready_i \mul_pipe3_n_ready_i + connect \muxid$1 \mul_pipe3_muxid$34 + connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 + connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 + connect \mul_op__imm_data__imm$4 \mul_pipe3_mul_op__imm_data__imm$37 + connect \mul_op__imm_data__imm_ok$5 \mul_pipe3_mul_op__imm_data__imm_ok$38 + connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 + connect \mul_op__rc__rc_ok$7 \mul_pipe3_mul_op__rc__rc_ok$40 + connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 + connect \mul_op__oe__oe_ok$9 \mul_pipe3_mul_op__oe__oe_ok$42 + connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 + connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 + connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 + connect \mul_op__insn$13 \mul_pipe3_mul_op__insn$46 + connect \o$14 \mul_pipe3_o$47 + connect \o_ok \mul_pipe3_o_ok + connect \cr_a \mul_pipe3_cr_a + connect \cr_a_ok \mul_pipe3_cr_a_ok + connect \xer_ov \mul_pipe3_xer_ov + connect \xer_ov_ok \mul_pipe3_xer_ov_ok + connect \xer_so$15 \mul_pipe3_xer_so$48 + connect \xer_so_ok \mul_pipe3_xer_so_ok + end + process $group_0 + assign \mul_pipe2_p_valid_i 1'0 + assign \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o + sync init + end + process $group_1 + assign \mul_pipe1_n_ready_i 1'0 + assign \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o + sync init + end + process $group_2 + assign \mul_pipe2_muxid 2'00 + assign \mul_pipe2_muxid \mul_pipe1_muxid + sync init + end + process $group_3 + assign \mul_pipe2_mul_op__insn_type 7'0000000 + assign \mul_pipe2_mul_op__fn_unit 11'00000000000 + assign \mul_pipe2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe2_mul_op__imm_data__imm_ok 1'0 + assign \mul_pipe2_mul_op__rc__rc 1'0 + assign \mul_pipe2_mul_op__rc__rc_ok 1'0 + assign \mul_pipe2_mul_op__oe__oe 1'0 + assign \mul_pipe2_mul_op__oe__oe_ok 1'0 + assign \mul_pipe2_mul_op__write_cr0 1'0 + assign \mul_pipe2_mul_op__is_32bit 1'0 + assign \mul_pipe2_mul_op__is_signed 1'0 + assign \mul_pipe2_mul_op__insn 32'00000000000000000000000000000000 + assign { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 { \mul_pipe2_mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe } { \mul_pipe2_mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc } { \mul_pipe2_mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm } \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 { \mul_pipe1_mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe } { \mul_pipe1_mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc } { \mul_pipe1_mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm } \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } + sync init + end + process $group_15 + assign \mul_pipe2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe2_ra \mul_pipe1_ra + sync init + end + process $group_16 + assign \mul_pipe2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe2_rb \mul_pipe1_rb + sync init + end + process $group_17 + assign \mul_pipe2_xer_so 1'0 + assign \mul_pipe2_xer_so \mul_pipe1_xer_so + sync init + end + process $group_18 + assign \mul_pipe2_neg_res 1'0 + assign \mul_pipe2_neg_res \mul_pipe1_neg_res + sync init + end + process $group_19 + assign \mul_pipe2_neg_res32 1'0 + assign \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 + sync init + end + process $group_20 + assign \mul_pipe3_p_valid_i 1'0 + assign \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o + sync init + end + process $group_21 + assign \mul_pipe2_n_ready_i 1'0 + assign \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o + sync init + end + process $group_22 + assign \mul_pipe3_muxid 2'00 + assign \mul_pipe3_muxid \mul_pipe2_muxid$18 + sync init + end + process $group_23 + assign \mul_pipe3_mul_op__insn_type 7'0000000 + assign \mul_pipe3_mul_op__fn_unit 11'00000000000 + assign \mul_pipe3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe3_mul_op__imm_data__imm_ok 1'0 + assign \mul_pipe3_mul_op__rc__rc 1'0 + assign \mul_pipe3_mul_op__rc__rc_ok 1'0 + assign \mul_pipe3_mul_op__oe__oe 1'0 + assign \mul_pipe3_mul_op__oe__oe_ok 1'0 + assign \mul_pipe3_mul_op__write_cr0 1'0 + assign \mul_pipe3_mul_op__is_32bit 1'0 + assign \mul_pipe3_mul_op__is_signed 1'0 + assign \mul_pipe3_mul_op__insn 32'00000000000000000000000000000000 + assign { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 { \mul_pipe3_mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe } { \mul_pipe3_mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc } { \mul_pipe3_mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm } \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 { \mul_pipe2_mul_op__oe__oe_ok$26 \mul_pipe2_mul_op__oe__oe$25 } { \mul_pipe2_mul_op__rc__rc_ok$24 \mul_pipe2_mul_op__rc__rc$23 } { \mul_pipe2_mul_op__imm_data__imm_ok$22 \mul_pipe2_mul_op__imm_data__imm$21 } \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } + sync init + end + process $group_35 + assign \mul_pipe3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe3_o \mul_pipe2_o + sync init + end + process $group_36 + assign \mul_pipe3_xer_so 1'0 + assign \mul_pipe3_xer_so \mul_pipe2_xer_so$31 + sync init + end + process $group_37 + assign \mul_pipe3_neg_res 1'0 + assign \mul_pipe3_neg_res \mul_pipe2_neg_res$32 + sync init + end + process $group_38 + assign \mul_pipe3_neg_res32 1'0 + assign \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$33 + sync init + end + process $group_39 + assign \mul_pipe1_p_valid_i 1'0 + assign \mul_pipe1_p_valid_i \p_valid_i + sync init + end + process $group_40 + assign \p_ready_o 1'0 + assign \p_ready_o \mul_pipe1_p_ready_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + process $group_41 + assign \mul_pipe1_muxid$2 2'00 + assign \mul_pipe1_muxid$2 \muxid + sync init + end + process $group_42 + assign \mul_pipe1_mul_op__insn_type$3 7'0000000 + assign \mul_pipe1_mul_op__fn_unit$4 11'00000000000 + assign \mul_pipe1_mul_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe1_mul_op__imm_data__imm_ok$6 1'0 + assign \mul_pipe1_mul_op__rc__rc$7 1'0 + assign \mul_pipe1_mul_op__rc__rc_ok$8 1'0 + assign \mul_pipe1_mul_op__oe__oe$9 1'0 + assign \mul_pipe1_mul_op__oe__oe_ok$10 1'0 + assign \mul_pipe1_mul_op__write_cr0$11 1'0 + assign \mul_pipe1_mul_op__is_32bit$12 1'0 + assign \mul_pipe1_mul_op__is_signed$13 1'0 + assign \mul_pipe1_mul_op__insn$14 32'00000000000000000000000000000000 + assign { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 { \mul_pipe1_mul_op__oe__oe_ok$10 \mul_pipe1_mul_op__oe__oe$9 } { \mul_pipe1_mul_op__rc__rc_ok$8 \mul_pipe1_mul_op__rc__rc$7 } { \mul_pipe1_mul_op__imm_data__imm_ok$6 \mul_pipe1_mul_op__imm_data__imm$5 } \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type } + sync init + end + process $group_54 + assign \mul_pipe1_ra$15 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe1_ra$15 \ra + sync init + end + process $group_55 + assign \mul_pipe1_rb$16 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_pipe1_rb$16 \rb + sync init + end + process $group_56 + assign \mul_pipe1_xer_so$17 1'0 + assign \mul_pipe1_xer_so$17 \xer_so$1 + sync init + end + process $group_57 + assign \n_valid_o 1'0 + assign \n_valid_o \mul_pipe3_n_valid_o + sync init + end + process $group_58 + assign \mul_pipe3_n_ready_i 1'0 + assign \mul_pipe3_n_ready_i \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$49 + process $group_59 + assign \muxid$49 2'00 + assign \muxid$49 \mul_pipe3_muxid$34 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$50 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \mul_op__fn_unit$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__imm$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__imm_data__imm_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__rc__rc_ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__oe__oe_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__write_cr0$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \mul_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$61 + process $group_60 + assign \mul_op__insn_type$50 7'0000000 + assign \mul_op__fn_unit$51 11'00000000000 + assign \mul_op__imm_data__imm$52 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul_op__imm_data__imm_ok$53 1'0 + assign \mul_op__rc__rc$54 1'0 + assign \mul_op__rc__rc_ok$55 1'0 + assign \mul_op__oe__oe$56 1'0 + assign \mul_op__oe__oe_ok$57 1'0 + assign \mul_op__write_cr0$58 1'0 + assign \mul_op__is_32bit$59 1'0 + assign \mul_op__is_signed$60 1'0 + assign \mul_op__insn$61 32'00000000000000000000000000000000 + assign { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 { \mul_op__oe__oe_ok$57 \mul_op__oe__oe$56 } { \mul_op__rc__rc_ok$55 \mul_op__rc__rc$54 } { \mul_op__imm_data__imm_ok$53 \mul_op__imm_data__imm$52 } \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 { \mul_pipe3_mul_op__oe__oe_ok$42 \mul_pipe3_mul_op__oe__oe$41 } { \mul_pipe3_mul_op__rc__rc_ok$40 \mul_pipe3_mul_op__rc__rc$39 } { \mul_pipe3_mul_op__imm_data__imm_ok$38 \mul_pipe3_mul_op__imm_data__imm$37 } \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } + sync init + end + process $group_72 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'0 + assign { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$47 } + sync init + end + process $group_74 + assign \cr_a 4'0000 + assign \cr_a_ok 1'0 + assign { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } + sync init + end + process $group_76 + assign \xer_ov 2'00 + assign \xer_ov_ok 1'0 + assign { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } + sync init + end + process $group_78 + assign \xer_so 1'0 + assign \xer_so_ok 1'0 + assign { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$48 } + sync init + end + connect \muxid 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l" +module \src_l$383 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $3 + connect \B \s_src + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 3'000 + end + sync init + update \q_int 3'000 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $9 + connect \B \s_src + connect \Y $11 + end + process $group_1 + assign \q_src 3'000 + assign \q_src $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $13 + end + process $group_2 + assign \qn_src 3'000 + assign \qn_src $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_src 3'000 + assign \qlq_src $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l" +module \opc_l$384 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_opc + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_opc + connect \Y $11 + end + process $group_1 + assign \q_opc 1'0 + assign \q_opc $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $13 + end + process $group_2 + assign \qn_opc 1'0 + assign \qn_opc $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_opc 1'0 + assign \qlq_opc $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l" +module \req_l$385 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $3 + connect \B \s_req + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 4'0000 + end + sync init + update \q_int 4'0000 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $9 + connect \B \s_req + connect \Y $11 + end + process $group_1 + assign \q_req 4'0000 + assign \q_req $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $13 + end + process $group_2 + assign \qn_req 4'0000 + assign \qn_req $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_req 4'0000 + assign \qlq_req $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l" +module \rst_l$386 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rst + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rst + connect \Y $11 + end + process $group_1 + assign \q_rst 1'0 + assign \q_rst $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $13 + end + process $group_2 + assign \qn_rst 1'0 + assign \qn_rst $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rst 1'0 + assign \qlq_rst $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l" +module \rok_l$387 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rdok + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rdok + connect \Y $11 + end + process $group_1 + assign \q_rdok 1'0 + assign \q_rdok $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $13 + end + process $group_2 + assign \qn_rdok 1'0 + assign \qn_rdok $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rdok 1'0 + assign \qlq_rdok $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l" +module \alui_l$388 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alui + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alui + connect \Y $11 + end + process $group_1 + assign \q_alui 1'0 + assign \q_alui $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $13 + end + process $group_2 + assign \qn_alui 1'0 + assign \qn_alui $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alui 1'0 + assign \qlq_alui $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l" +module \alu_l$389 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alu + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alu + connect \Y $11 + end + process $group_1 + assign \q_alu 1'0 + assign \q_alu $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $13 + end + process $group_2 + assign \qn_alu 1'0 + assign \qn_alu $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alu 1'0 + assign \qlq_alu $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0" +module \mul0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_mul0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_mul0__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \oper_i_alu_mul0__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \oper_i_alu_mul0__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \oper_i_alu_mul0__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \oper_i_alu_mul0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \oper_i_alu_mul0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 input 13 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 output 14 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 15 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 16 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 17 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 18 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 19 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 input 20 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 21 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 22 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 23 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 24 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 26 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 27 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 28 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 29 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 output 30 \dest4_o + attribute \src "simple/issuer.py:102" + wire width 1 input 31 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \alu_mul0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \alu_mul0_n_ready_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_mul0_mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_mul0_mul_op__insn_type$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_mul0_mul_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_mul0_mul_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_mul0_mul_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_mul0_mul_op__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_mul0_mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_mul0_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_mul0_mul_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_mul0_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_mul0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_mul0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \alu_mul0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 1 \alu_mul0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \alu_mul0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \alu_mul0_p_ready_o + cell \alu_mul0 \alu_mul0 + connect \coresync_clk \coresync_clk + connect \o_ok \o_ok + connect \cr_a_ok \cr_a_ok + connect \xer_ov_ok \xer_ov_ok + connect \xer_so_ok \xer_so_ok + connect \coresync_rst \coresync_rst + connect \n_valid_o \alu_mul0_n_valid_o + connect \n_ready_i \alu_mul0_n_ready_i + connect \mul_op__insn_type \alu_mul0_mul_op__insn_type + connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit + connect \mul_op__imm_data__imm \alu_mul0_mul_op__imm_data__imm + connect \mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm_ok + connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc + connect \mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc_ok + connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe + connect \mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe_ok + connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 + connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit + connect \mul_op__is_signed \alu_mul0_mul_op__is_signed + connect \mul_op__insn \alu_mul0_mul_op__insn + connect \o \alu_mul0_o + connect \cr_a \alu_mul0_cr_a + connect \xer_ov \alu_mul0_xer_ov + connect \xer_so \alu_mul0_xer_so + connect \ra \alu_mul0_ra + connect \rb \alu_mul0_rb + connect \xer_so$1 \alu_mul0_xer_so$1 + connect \p_valid_i \alu_mul0_p_valid_i + connect \p_ready_o \alu_mul0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + cell \src_l$383 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_src \src_l_s_src + connect \r_src \src_l_r_src + connect \q_src \src_l_q_src + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \opc_l_q_opc + cell \opc_l$384 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_opc \opc_l_s_opc + connect \r_opc \opc_l_r_opc + connect \q_opc \opc_l_q_opc + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \req_l_r_req$next + cell \req_l$385 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \s_req \req_l_s_req + connect \r_req \req_l_r_req + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst$next + cell \rst_l$386 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_rst \rst_l_s_rst + connect \r_rst \rst_l_r_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok$next + cell \rok_l$387 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \s_rdok \rok_l_s_rdok + connect \r_rdok \rok_l_r_rdok + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alui_l_s_alui + cell \alui_l$388 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_s_alu + cell \alu_l$389 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire width 1 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $5 + connect \B \cu_rd__go_i + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $7 + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $2 + connect \B $4 + connect \Y $10 + end + process $group_0 + assign \all_rd 1'0 + assign \all_rd $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly$next + process $group_1 + assign \all_rd_dly$next \all_rd_dly + assign \all_rd_dly$next \all_rd + sync init + update \all_rd_dly 1'0 + sync posedge \coresync_clk + update \all_rd_dly \all_rd_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B $12 + connect \Y $14 + end + process $group_2 + assign \all_rd_rise 1'0 + assign \all_rd_rise $14 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire width 1 \all_rd_pulse + process $group_3 + assign \all_rd_pulse 1'0 + assign \all_rd_pulse \all_rd_rise + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire width 1 \alu_done + process $group_4 + assign \alu_done 1'0 + assign \alu_done \alu_mul0_n_valid_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly$next + process $group_5 + assign \alu_done_dly$next \alu_done_dly + assign \alu_done_dly$next \alu_done + sync init + update \alu_done_dly 1'0 + sync posedge \coresync_clk + update \alu_done_dly \alu_done_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B $16 + connect \Y $18 + end + process $group_6 + assign \alu_done_rise 1'0 + assign \alu_done_rise $18 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire width 1 \alu_pulse + process $group_7 + assign \alu_pulse 1'0 + assign \alu_pulse \alu_done_rise + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + process $group_8 + assign \alu_pulsem 4'0000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 4 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $20 + end + process $group_9 + assign \prev_wr_go$next \prev_wr_go + assign \prev_wr_go$next $20 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \prev_wr_go$next 4'0000 + end + sync init + update \prev_wr_go 4'0000 + sync posedge \coresync_clk + update \prev_wr_go \prev_wr_go$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire width 1 \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 4 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 4 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__rel_o + connect \B $24 + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_bool $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A $26 + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $23 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B $22 + connect \Y $30 + end + process $group_10 + assign \cu_done_o 1'0 + assign \cu_done_o $30 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $32 + connect \B $34 + connect \Y $36 + end + process $group_11 + assign \wr_any 1'0 + assign \wr_any $36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire width 1 \req_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_ready_i + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B $38 + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 4 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $42 + connect \B 1'0 + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $40 + connect \B $44 + connect \Y $46 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $48 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $48 + connect \B \alu_mul0_n_ready_i + connect \Y $50 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $50 + connect \B \alu_mul0_n_valid_o + connect \Y $52 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $52 + connect \B \cu_busy_o + connect \Y $54 + end + process $group_12 + assign \req_done 1'0 + assign \req_done $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch { $54 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + case 1'1 + assign \req_done 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire width 1 \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire width 1 \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire width 1 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $56 + end + process $group_13 + assign \reset 1'0 + assign \reset $56 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire width 1 \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire width 1 $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $58 + end + process $group_14 + assign \rst_r 1'0 + assign \rst_r $58 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 4 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 4 $60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $60 + end + process $group_15 + assign \reset_w 4'0000 + assign \reset_w $60 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 3 $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $62 + end + process $group_16 + assign \reset_r 3'000 + assign \reset_r $62 + sync init + end + process $group_17 + assign \rok_l_s_rdok$next \rok_l_s_rdok + assign \rok_l_s_rdok$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_s_rdok$next 1'0 + end + sync init + update \rok_l_s_rdok 1'0 + sync posedge \coresync_clk + update \rok_l_s_rdok \rok_l_s_rdok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire width 1 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $65 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_valid_o + connect \B \cu_busy_o + connect \Y $64 + end + process $group_18 + assign \rok_l_r_rdok$next \rok_l_r_rdok + assign \rok_l_r_rdok$next $64 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_r_rdok$next 1'1 + end + sync init + update \rok_l_r_rdok 1'1 + sync posedge \coresync_clk + update \rok_l_r_rdok \rok_l_r_rdok$next + end + process $group_19 + assign \rst_l_s_rst$next \rst_l_s_rst + assign \rst_l_s_rst$next \all_rd + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_s_rst$next 1'0 + end + sync init + update \rst_l_s_rst 1'0 + sync posedge \coresync_clk + update \rst_l_s_rst \rst_l_s_rst$next + end + process $group_20 + assign \rst_l_r_rst$next \rst_l_r_rst + assign \rst_l_r_rst$next \rst_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_r_rst$next 1'1 + end + sync init + update \rst_l_r_rst 1'1 + sync posedge \coresync_clk + update \rst_l_r_rst \rst_l_r_rst$next + end + process $group_21 + assign \opc_l_s_opc$next \opc_l_s_opc + assign \opc_l_s_opc$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_s_opc$next 1'0 + end + sync init + update \opc_l_s_opc 1'0 + sync posedge \coresync_clk + update \opc_l_s_opc \opc_l_s_opc$next + end + process $group_22 + assign \opc_l_r_opc$next \opc_l_r_opc + assign \opc_l_r_opc$next \req_done + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_r_opc$next 1'1 + end + sync init + update \opc_l_r_opc 1'1 + sync posedge \coresync_clk + update \opc_l_r_opc \opc_l_r_opc$next + end + process $group_23 + assign \src_l_s_src$next \src_l_s_src + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_s_src$next 3'000 + end + sync init + update \src_l_s_src 3'000 + sync posedge \coresync_clk + update \src_l_s_src \src_l_s_src$next + end + process $group_24 + assign \src_l_r_src$next \src_l_r_src + assign \src_l_r_src$next \reset_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_r_src$next 3'111 + end + sync init + update \src_l_r_src 3'111 + sync posedge \coresync_clk + update \src_l_r_src \src_l_r_src$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 4 $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $66 + end + process $group_25 + assign \req_l_s_req$next \req_l_s_req + assign \req_l_s_req$next $66 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_s_req$next 4'0000 + end + sync init + update \req_l_s_req 4'0000 + sync posedge \coresync_clk + update \req_l_s_req \req_l_s_req$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 4 $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $68 + end + process $group_26 + assign \req_l_r_req$next \req_l_r_req + assign \req_l_r_req$next $68 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_r_req$next 4'1111 + end + sync init + update \req_l_r_req 4'1111 + sync posedge \coresync_clk + update \req_l_r_req \req_l_r_req$next + end + process $group_27 + assign \alu_mul0_mul_op__insn_type$next \alu_mul0_mul_op__insn_type + assign \alu_mul0_mul_op__fn_unit$next \alu_mul0_mul_op__fn_unit + assign \alu_mul0_mul_op__imm_data__imm$next \alu_mul0_mul_op__imm_data__imm + assign \alu_mul0_mul_op__imm_data__imm_ok$next \alu_mul0_mul_op__imm_data__imm_ok + assign \alu_mul0_mul_op__rc__rc$next \alu_mul0_mul_op__rc__rc + assign \alu_mul0_mul_op__rc__rc_ok$next \alu_mul0_mul_op__rc__rc_ok + assign \alu_mul0_mul_op__oe__oe$next \alu_mul0_mul_op__oe__oe + assign \alu_mul0_mul_op__oe__oe_ok$next \alu_mul0_mul_op__oe__oe_ok + assign \alu_mul0_mul_op__write_cr0$next \alu_mul0_mul_op__write_cr0 + assign \alu_mul0_mul_op__is_32bit$next \alu_mul0_mul_op__is_32bit + assign \alu_mul0_mul_op__is_signed$next \alu_mul0_mul_op__is_signed + assign \alu_mul0_mul_op__insn$next \alu_mul0_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + case 1'1 + assign { \alu_mul0_mul_op__insn$next \alu_mul0_mul_op__is_signed$next \alu_mul0_mul_op__is_32bit$next \alu_mul0_mul_op__write_cr0$next { \alu_mul0_mul_op__oe__oe_ok$next \alu_mul0_mul_op__oe__oe$next } { \alu_mul0_mul_op__rc__rc_ok$next \alu_mul0_mul_op__rc__rc$next } { \alu_mul0_mul_op__imm_data__imm_ok$next \alu_mul0_mul_op__imm_data__imm$next } \alu_mul0_mul_op__fn_unit$next \alu_mul0_mul_op__insn_type$next } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 { \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_mul0_mul_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_mul0_mul_op__imm_data__imm_ok$next 1'0 + assign \alu_mul0_mul_op__rc__rc$next 1'0 + assign \alu_mul0_mul_op__rc__rc_ok$next 1'0 + assign \alu_mul0_mul_op__oe__oe$next 1'0 + assign \alu_mul0_mul_op__oe__oe_ok$next 1'0 + end + sync init + update \alu_mul0_mul_op__insn_type 7'0000000 + update \alu_mul0_mul_op__fn_unit 11'00000000000 + update \alu_mul0_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_mul0_mul_op__imm_data__imm_ok 1'0 + update \alu_mul0_mul_op__rc__rc 1'0 + update \alu_mul0_mul_op__rc__rc_ok 1'0 + update \alu_mul0_mul_op__oe__oe 1'0 + update \alu_mul0_mul_op__oe__oe_ok 1'0 + update \alu_mul0_mul_op__write_cr0 1'0 + update \alu_mul0_mul_op__is_32bit 1'0 + update \alu_mul0_mul_op__is_signed 1'0 + update \alu_mul0_mul_op__insn 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn_type \alu_mul0_mul_op__insn_type$next + update \alu_mul0_mul_op__fn_unit \alu_mul0_mul_op__fn_unit$next + update \alu_mul0_mul_op__imm_data__imm \alu_mul0_mul_op__imm_data__imm$next + update \alu_mul0_mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm_ok$next + update \alu_mul0_mul_op__rc__rc \alu_mul0_mul_op__rc__rc$next + update \alu_mul0_mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc_ok$next + update \alu_mul0_mul_op__oe__oe \alu_mul0_mul_op__oe__oe$next + update \alu_mul0_mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe_ok$next + update \alu_mul0_mul_op__write_cr0 \alu_mul0_mul_op__write_cr0$next + update \alu_mul0_mul_op__is_32bit \alu_mul0_mul_op__is_32bit$next + update \alu_mul0_mul_op__is_signed \alu_mul0_mul_op__is_signed$next + update \alu_mul0_mul_op__insn \alu_mul0_mul_op__insn$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok$next + process $group_39 + assign \data_r0__o$next \data_r0__o + assign \data_r0__o_ok$next \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_mul0_o } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r0__o_ok$next 1'0 + end + sync init + update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0__o_ok 1'0 + sync posedge \coresync_clk + update \data_r0__o \data_r0__o$next + update \data_r0__o_ok \data_r0__o_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__cr_a_ok$next + process $group_41 + assign \data_r1__cr_a$next \data_r1__cr_a + assign \data_r1__cr_a_ok$next \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } { \cr_a_ok \alu_mul0_cr_a } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r1__cr_a_ok$next 1'0 + end + sync init + update \data_r1__cr_a 4'0000 + update \data_r1__cr_a_ok 1'0 + sync posedge \coresync_clk + update \data_r1__cr_a \data_r1__cr_a$next + update \data_r1__cr_a_ok \data_r1__cr_a_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__xer_ov_ok$next + process $group_43 + assign \data_r2__xer_ov$next \data_r2__xer_ov + assign \data_r2__xer_ov_ok$next \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r2__xer_ov_ok$next \data_r2__xer_ov$next } { \xer_ov_ok \alu_mul0_xer_ov } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r2__xer_ov_ok$next \data_r2__xer_ov$next } 3'000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r2__xer_ov_ok$next 1'0 + end + sync init + update \data_r2__xer_ov 2'00 + update \data_r2__xer_ov_ok 1'0 + sync posedge \coresync_clk + update \data_r2__xer_ov \data_r2__xer_ov$next + update \data_r2__xer_ov_ok \data_r2__xer_ov_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r3__xer_so_ok$next + process $group_45 + assign \data_r3__xer_so$next \data_r3__xer_so + assign \data_r3__xer_so_ok$next \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } { \xer_so_ok \alu_mul0_xer_so } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r3__xer_so_ok$next 1'0 + end + sync init + update \data_r3__xer_so 1'0 + update \data_r3__xer_so_ok 1'0 + sync posedge \coresync_clk + update \data_r3__xer_so \data_r3__xer_so$next + update \data_r3__xer_so_ok \data_r3__xer_so_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $70 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $74 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $76 + end + process $group_47 + assign \cu_wrmask_o 4'0000 + assign \cu_wrmask_o { $76 $74 $72 $70 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $79 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_mul0_mul_op__imm_data__imm_ok + connect \Y $78 + end + process $group_48 + assign \src_sel 1'0 + assign \src_sel $78 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $81 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_mul0_mul_op__imm_data__imm + connect \S \alu_mul0_mul_op__imm_data__imm_ok + connect \Y $80 + end + process $group_49 + assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm $80 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $82 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $83 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $82 + end + process $group_50 + assign \alu_mul0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_mul0_ra $82 + sync init + end + process $group_51 + assign \src_r0$next \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [0] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r0$next \src1_i + end + sync init + update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r0 \src_r0$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $84 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $85 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $84 + end + process $group_52 + assign \alu_mul0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_mul0_rb $84 + sync init + end + process $group_53 + assign \src_r1$next \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r1$next \src_or_imm + end + sync init + update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r1 \src_r1$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $87 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $86 + end + process $group_54 + assign \alu_mul0_xer_so$1 1'0 + assign \alu_mul0_xer_so$1 $86 + sync init + end + process $group_55 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r2$next \src3_i + end + sync init + update \src_r2 1'0 + sync posedge \coresync_clk + update \src_r2 \src_r2$next + end + process $group_56 + assign \alu_mul0_p_valid_i 1'0 + assign \alu_mul0_p_valid_i \alui_l_q_alui + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire width 1 $88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $88 + end + process $group_57 + assign \alui_l_r_alui$next \alui_l_r_alui + assign \alui_l_r_alui$next $88 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alui_l_r_alui$next 1'1 + end + sync init + update \alui_l_r_alui 1'1 + sync posedge \coresync_clk + update \alui_l_r_alui \alui_l_r_alui$next + end + process $group_58 + assign \alui_l_s_alui 1'0 + assign \alui_l_s_alui \all_rd_pulse + sync init + end + process $group_59 + assign \alu_mul0_n_ready_i 1'0 + assign \alu_mul0_n_ready_i \alu_l_q_alu + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire width 1 $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $90 + end + process $group_60 + assign \alu_l_r_alu$next \alu_l_r_alu + assign \alu_l_r_alu$next $90 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_l_r_alu$next 1'1 + end + sync init + update \alu_l_r_alu 1'1 + sync posedge \coresync_clk + update \alu_l_r_alu \alu_l_r_alu$next + end + process $group_61 + assign \alu_l_s_alu 1'0 + assign \alu_l_s_alu \all_rd_pulse + sync init + end + process $group_62 + assign \cu_busy_o 1'0 + assign \cu_busy_o \opc_l_q_opc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $92 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire width 1 $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_mul_op__imm_data__imm_ok + connect \Y $94 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $92 + connect \B { 1'1 $94 1'1 } + connect \Y $96 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $98 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 3 $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $96 + connect \B $98 + connect \Y $100 + end + process $group_63 + assign \cu_rd__rel_o 3'000 + assign \cu_rd__rel_o $100 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire width 1 \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $102 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $104 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $106 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $108 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 4 $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B { $102 $104 $106 $108 } + connect \Y $110 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 4 $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $110 + connect \B \cu_wrmask_o + connect \Y $112 + end + process $group_64 + assign \cu_wr__rel_o 4'0000 + assign \cu_wr__rel_o $112 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $114 + end + process $group_65 + assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $114 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $116 + end + process $group_66 + assign \dest2_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $116 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $118 + end + process $group_67 + assign \dest3_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $118 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest3_o { \data_r2__xer_ov_ok \data_r2__xer_ov } [1:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [3] + connect \B \cu_busy_o + connect \Y $120 + end + process $group_68 + assign \dest4_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $120 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0] + end + sync init + end + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p" +module \p$390 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n" +module \n$391 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" +module \p$393 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" +module \n$394 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" +module \input$395 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \sr_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \sr_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \sr_op__oe__oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 10 \sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 20 \xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 21 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 22 \sr_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 23 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 24 \sr_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 25 \sr_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 26 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \sr_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \sr_op__oe__oe_ok$9 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 31 \sr_op__input_carry$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \sr_op__output_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \sr_op__input_cr$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \sr_op__output_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \sr_op__is_32bit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 36 \sr_op__is_signed$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 37 \sr_op__insn$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 38 \ra$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 39 \rb$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 40 \rc$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 41 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + process $group_0 + assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \a \ra + sync init + end + process $group_1 + assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$17 \a + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + process $group_2 + assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \b \rb + sync init + end + process $group_3 + assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$18 \b + sync init + end + process $group_4 + assign \xer_ca$20 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:56" + attribute \nmigen.decoding "ZERO/0" + case 2'00 + assign \xer_ca$20 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:58" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \xer_ca$20 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:60" + attribute \nmigen.decoding "CA/2" + case 2'10 + assign \xer_ca$20 \xer_ca + end + sync init + end + process $group_5 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_6 + assign \sr_op__insn_type$2 7'0000000 + assign \sr_op__fn_unit$3 11'00000000000 + assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__imm_ok$5 1'0 + assign \sr_op__rc__rc$6 1'0 + assign \sr_op__rc__rc_ok$7 1'0 + assign \sr_op__oe__oe$8 1'0 + assign \sr_op__oe__oe_ok$9 1'0 + assign { } 0'0 + assign \sr_op__input_carry$10 2'00 + assign \sr_op__output_carry$11 1'0 + assign \sr_op__input_cr$12 1'0 + assign \sr_op__output_cr$13 1'0 + assign \sr_op__is_32bit$14 1'0 + assign \sr_op__is_signed$15 1'0 + assign \sr_op__insn$16 32'00000000000000000000000000000000 + assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + sync init + end + process $group_22 + assign \rc$19 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rc$19 \rc + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" +module \rotl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" + wire width 64 input 0 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" + wire width 6 input 1 \b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" + wire width 64 output 2 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" + wire width 64 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" + wire width 8 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" + cell $sub $3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \b + connect \Y $2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" + cell $shift $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A { \a \a } + connect \B $2 + connect \Y $1 + end + process $group_0 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" +module \right_mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:8" + wire width 7 input 0 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:9" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'0 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'10 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'111 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1000 + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1001 + connect \Y $19 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1010 + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1011 + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1100 + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1101 + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1111 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10001 + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10010 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10011 + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10100 + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10101 + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10110 + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10111 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11000 + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11001 + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11010 + connect \Y $53 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11011 + connect \Y $55 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11100 + connect \Y $57 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11101 + connect \Y $59 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11110 + connect \Y $61 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11111 + connect \Y $63 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100000 + connect \Y $65 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100001 + connect \Y $67 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100010 + connect \Y $69 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $71 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $75 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $77 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $79 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $81 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $83 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $85 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $87 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $89 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $91 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $93 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $95 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $97 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $99 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $101 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $103 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $105 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $107 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $109 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $111 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $113 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $115 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $117 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $119 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $121 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $123 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $125 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $127 + end + process $group_0 + assign \mask 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [0] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [1] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [2] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [3] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [4] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $11 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [5] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [6] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $15 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [7] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $17 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [8] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $19 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [9] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $21 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [10] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $23 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [11] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [12] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $27 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [13] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $29 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [14] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $31 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [15] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $33 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [16] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $35 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [17] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $37 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [18] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $39 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [19] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $41 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [20] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $43 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [21] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $45 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [22] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $47 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [23] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $49 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [24] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $51 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [25] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $53 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [26] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $55 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [27] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $57 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [28] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $59 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [29] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $61 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [30] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $63 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [31] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $65 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [32] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $67 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [33] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $69 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [34] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $71 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [35] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $73 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [36] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [37] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $77 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [38] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $79 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [39] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [40] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $83 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [41] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $85 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [42] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [43] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $89 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [44] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $91 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [45] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $93 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [46] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $95 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [47] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $97 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [48] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $99 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [49] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [50] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $103 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [51] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $105 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [52] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $107 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [53] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $109 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [54] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $111 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [55] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $113 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [56] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $115 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [57] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $117 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [58] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $119 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [59] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $121 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [60] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $123 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [61] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $125 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [62] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $127 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [63] 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" +module \left_mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:8" + wire width 7 input 0 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:9" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'0 + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'10 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'111 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1000 + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1001 + connect \Y $19 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1010 + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1011 + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1100 + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1101 + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1111 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10001 + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10010 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10011 + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10100 + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10101 + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10110 + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10111 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11000 + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11001 + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11010 + connect \Y $53 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11011 + connect \Y $55 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11100 + connect \Y $57 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11101 + connect \Y $59 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11110 + connect \Y $61 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11111 + connect \Y $63 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100000 + connect \Y $65 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100001 + connect \Y $67 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100010 + connect \Y $69 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $71 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $75 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $77 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $79 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $81 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $83 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $85 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $87 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $89 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $91 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $93 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $95 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $97 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $99 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $101 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $103 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $105 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $107 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $109 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $111 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $113 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $115 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $117 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $119 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $121 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $123 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $125 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + wire width 1 $127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + cell $gt $128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $127 + end + process $group_0 + assign \mask 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [0] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [1] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [2] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [3] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [4] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $11 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [5] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [6] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $15 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [7] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $17 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [8] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $19 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [9] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $21 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [10] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $23 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [11] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [12] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $27 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [13] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $29 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [14] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $31 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [15] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $33 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [16] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $35 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [17] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $37 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [18] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $39 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [19] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $41 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [20] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $43 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [21] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $45 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [22] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $47 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [23] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $49 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [24] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $51 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [25] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $53 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [26] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $55 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [27] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $57 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [28] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $59 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [29] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $61 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [30] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $63 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [31] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $65 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [32] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $67 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [33] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $69 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [34] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $71 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [35] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $73 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [36] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [37] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $77 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [38] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $79 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [39] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [40] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $83 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [41] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $85 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [42] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [43] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $89 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [44] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $91 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [45] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $93 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [46] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $95 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [47] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $97 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [48] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $99 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [49] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [50] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $103 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [51] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $105 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [52] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $107 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [53] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $109 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [54] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $111 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [55] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $113 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [56] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $115 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [57] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $117 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [58] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $119 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [59] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $121 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [60] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $123 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [61] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $125 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [62] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + switch { $127 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" + case 1'1 + assign \mask [63] 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" +module \rotator + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" + wire width 5 input 0 \me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + wire width 5 input 1 \mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" + wire width 1 input 2 \mb_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" + wire width 64 input 3 \rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" + wire width 64 input 4 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" + wire width 7 input 5 \shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" + wire width 1 input 6 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" + wire width 1 input 7 \arith + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" + wire width 1 input 8 \right_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" + wire width 1 input 9 \clear_left + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" + wire width 1 input 10 \clear_right + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" + wire width 1 input 11 \sign_ext_rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" + wire width 64 output 12 \result_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" + wire width 1 output 13 \carry_out_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" + wire width 64 \rotl_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" + wire width 6 \rotl_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" + wire width 64 \rotl_o + cell \rotl \rotl + connect \a \rotl_a + connect \b \rotl_b + connect \o \rotl_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:8" + wire width 7 \right_mask_shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:9" + wire width 64 \right_mask_mask + cell \right_mask \right_mask + connect \shift \right_mask_shift + connect \mask \right_mask_mask + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:8" + wire width 7 \left_mask_shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:9" + wire width 64 \left_mask_mask + cell \left_mask \left_mask + connect \shift \left_mask_shift + connect \mask \left_mask_mask + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" + wire width 32 \hi32 + process $group_0 + assign \hi32 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" + switch { \sign_ext_rs \is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" + case 2'-1 + assign \hi32 \rs [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:87" + case 2'1- + assign \hi32 { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:90" + case + assign \hi32 \rs [63:32] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82" + wire width 64 \repl32 + process $group_1 + assign \repl32 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \repl32 { \hi32 \rs [31:0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:94" + wire width 6 \shift_signed + process $group_2 + assign \shift_signed 6'000000 + assign \shift_signed \shift [5:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73" + wire width 6 \rot_count + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" + wire width 7 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" + wire width 7 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" + cell $neg $3 + parameter \A_SIGNED 1 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \shift_signed + connect \Y $2 + end + connect $1 $2 + process $group_3 + assign \rot_count 6'000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" + switch { \right_shift } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" + case 1'1 + assign \rot_count $1 [5:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:100" + case + assign \rot_count \shift [5:0] + end + sync init + end + process $group_4 + assign \rotl_a 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rotl_a \repl32 + sync init + end + process $group_5 + assign \rotl_b 6'000000 + assign \rotl_b \rot_count + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74" + wire width 64 \rot + process $group_6 + assign \rot 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rot \rotl_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75" + wire width 7 \sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" + cell $and $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift [6] + connect \B $4 + connect \Y $6 + end + process $group_7 + assign \sh 7'0000000 + assign \sh { $6 \shift [5:0] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76" + wire width 7 \mb$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + wire width 7 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 7 + connect \A \mb + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" + cell $not $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sh [5] + connect \Y $11 + end + process $group_8 + assign \mb$8 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" + switch { \right_shift \clear_left } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" + case 2'-1 + assign \mb$8 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" + switch { \is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" + case 1'1 + assign \mb$8 [6:5] 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:120" + case + assign \mb$8 [6:5] { 1'0 \mb_extra } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122" + case 2'1- + assign \mb$8 \sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" + switch { \is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" + case 1'1 + assign \mb$8 [6:5] { \sh [5] $11 } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:127" + case + assign \mb$8 { 1'0 \is_32bit 5'00000 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77" + wire width 7 \me$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" + cell $and $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_right + connect \B \is_32bit + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" + cell $not $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_left + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" + cell $and $19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_right + connect \B $16 + connect \Y $18 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" + wire width 6 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" + cell $not $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \sh [5:0] + connect \Y $20 + end + process $group_9 + assign \me$13 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" + switch { $18 $14 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" + case 2'-1 + assign \me$13 { 2'01 \me } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" + case 2'1- + assign \me$13 { 1'0 \mb_extra \mb } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:137" + case + assign \me$13 { \sh [6] $20 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + cell $le $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mb$8 + connect \B 7'1000000 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" + wire width 8 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" + wire width 8 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" + cell $sub $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \mb$8 + connect \Y $25 + end + connect $24 $25 + process $group_10 + assign \right_mask_shift 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + switch { $22 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + case 1'1 + assign \right_mask_shift $24 [6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:146" + case + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:78" + wire width 64 \mr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + cell $le $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mb$8 + connect \B 7'1000000 + connect \Y $27 + end + process $group_11 + assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + switch { $27 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + case 1'1 + assign \mr \right_mask_mask + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:146" + case + assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" + wire width 8 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" + wire width 8 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" + cell $sub $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 6'111111 + connect \B \me$13 + connect \Y $30 + end + connect $29 $30 + process $group_12 + assign \left_mask_shift 7'0000000 + assign \left_mask_shift $29 [6:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79" + wire width 64 \ml + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" + cell $not $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \left_mask_mask + connect \Y $32 + end + process $group_13 + assign \ml 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ml $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:80" + wire width 2 \output_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $not $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_right + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $and $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_left + connect \B $34 + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $or $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $36 + connect \B \right_shift + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" + cell $and $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \arith + connect \B \repl32 [63] + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" + cell $gt $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \mb$8 [5:0] + connect \B \me$13 [5:0] + connect \Y $42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" + cell $and $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_right + connect \B $42 + connect \Y $44 + end + process $group_14 + assign \output_mode 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + switch { $38 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + case 1'1 + assign \output_mode { 1'1 $40 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:163" + case + assign \output_mode { 1'0 $44 } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $and $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $46 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $and $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B $46 + connect \Y $48 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $and $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $not $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $51 + connect \Y $50 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $and $55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B $50 + connect \Y $54 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + wire width 64 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $or $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $48 + connect \B $54 + connect \Y $56 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + wire width 64 $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $58 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + wire width 64 $60 + attribute \src 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parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B \mr + connect \Y $70 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + wire width 64 $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $not $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + wire width 64 $74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $or $75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B $72 + connect \Y $74 + end + process $group_15 + assign \result_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src 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15 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 20 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute 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\sr_op__is_32bit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \sr_op__is_signed$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 36 \sr_op__insn$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 37 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 38 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 39 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" + wire width 5 \rotator_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + wire width 5 \rotator_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" + wire width 1 \rotator_mb_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" + wire width 64 \rotator_rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" + wire width 64 \rotator_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" + wire width 7 \rotator_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" + wire width 1 \rotator_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" + wire width 1 \rotator_arith + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" + wire width 1 \rotator_right_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" + wire width 1 \rotator_clear_left + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" + wire width 1 \rotator_clear_right + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" + wire width 1 \rotator_sign_ext_rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" + wire width 64 \rotator_result_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" + wire width 1 \rotator_carry_out_o + cell \rotator \rotator + connect \me \rotator_me + connect \mb \rotator_mb + connect \mb_extra \rotator_mb_extra + connect \rs \rotator_rs + connect \ra \rotator_ra + connect \shift \rotator_shift + connect \is_32bit \rotator_is_32bit + connect \arith \rotator_arith + connect \right_shift \rotator_right_shift + connect \clear_left \rotator_clear_left + connect \clear_right \rotator_clear_right + connect \sign_ext_rs \rotator_sign_ext_rs + connect \result_o \rotator_result_o + connect \carry_out_o \rotator_carry_out_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" + wire width 5 \mb + process $group_0 + assign \mb 5'00000 + assign \mb { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:47" + wire width 5 \me + process $group_1 + assign \me 5'00000 + assign \me { \sr_op__insn [5] \sr_op__insn [4] \sr_op__insn [3] \sr_op__insn [2] \sr_op__insn [1] } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:48" + wire width 1 \mb_extra + process $group_2 + assign \mb_extra 1'0 + assign \mb_extra { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] \sr_op__insn [5] } [0] + sync init + end + process $group_3 + assign \rotator_me 5'00000 + assign \rotator_me \me + sync init + end + process $group_4 + assign \rotator_mb 5'00000 + assign \rotator_mb \mb + sync init + end + process $group_5 + assign \rotator_mb_extra 1'0 + assign \rotator_mb_extra \mb_extra + sync init + end + process $group_6 + assign \rotator_rs 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rotator_rs \rc + sync init + end + process $group_7 + assign \rotator_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rotator_ra \ra + sync init + end + process $group_8 + assign \rotator_shift 7'0000000 + assign \rotator_shift \rb [6:0] + sync init + end + process $group_9 + assign \rotator_is_32bit 1'0 + assign \rotator_is_32bit \sr_op__is_32bit + sync init + end + process $group_10 + assign \rotator_arith 1'0 + assign \rotator_arith \sr_op__is_signed + sync init + end + process $group_11 + assign \o_ok 1'0 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" + switch \sr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71" + attribute \nmigen.decoding "OP_SHL/60" + case 7'0111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72" + attribute \nmigen.decoding "OP_SHR/61" + case 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73" + attribute \nmigen.decoding "OP_RLC/56" + case 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:74" + attribute \nmigen.decoding "OP_RLCL/57" + case 7'0111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:75" + attribute \nmigen.decoding "OP_RLCR/58" + case 7'0111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:76" + attribute \nmigen.decoding "OP_EXTSWSLI/32" + case 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:77" + attribute \nmigen.decoding "" + case + assign \o_ok 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" + wire width 4 \mode + process $group_12 + assign \mode 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" + switch \sr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71" + attribute \nmigen.decoding "OP_SHL/60" + case 7'0111100 + assign \mode 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72" + attribute \nmigen.decoding "OP_SHR/61" + case 7'0111101 + assign \mode 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73" + attribute \nmigen.decoding "OP_RLC/56" + case 7'0111000 + assign \mode 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:74" + attribute \nmigen.decoding "OP_RLCL/57" + case 7'0111001 + assign \mode 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:75" + attribute \nmigen.decoding "OP_RLCR/58" + case 7'0111010 + assign \mode 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:76" + attribute \nmigen.decoding "OP_EXTSWSLI/32" + case 7'0100000 + assign \mode 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:77" + attribute \nmigen.decoding "" + case + end + sync init + end + process $group_13 + assign \rotator_right_shift 1'0 + assign \rotator_clear_left 1'0 + assign \rotator_clear_right 1'0 + assign \rotator_sign_ext_rs 1'0 + assign { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode + sync init + end + process $group_17 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o \rotator_result_o + sync init + end + process $group_18 + assign \xer_ca 2'00 + assign \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } + sync init + end + process $group_19 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_20 + assign \sr_op__insn_type$2 7'0000000 + assign \sr_op__fn_unit$3 11'00000000000 + assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__imm_ok$5 1'0 + assign \sr_op__rc__rc$6 1'0 + assign \sr_op__rc__rc_ok$7 1'0 + assign \sr_op__oe__oe$8 1'0 + assign \sr_op__oe__oe_ok$9 1'0 + assign { } 0'0 + assign \sr_op__input_carry$10 2'00 + assign \sr_op__output_carry$11 1'0 + assign \sr_op__input_cr$12 1'0 + assign \sr_op__output_cr$13 1'0 + assign \sr_op__is_32bit$14 1'0 + assign \sr_op__is_signed$15 1'0 + assign \sr_op__insn$16 32'00000000000000000000000000000000 + assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1" +module \pipe1$392 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \sr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 6 \sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \sr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \sr_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 8 \sr_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 10 \sr_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 12 \sr_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__oe_ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 14 \sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 15 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 16 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 17 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 18 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 19 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 20 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 21 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 22 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 23 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 24 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 25 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 26 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 27 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 28 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 29 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute 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"CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 39 \sr_op__input_carry$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 40 \sr_op__output_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 41 \sr_op__input_cr$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 42 \sr_op__output_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 43 \sr_op__is_32bit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 44 \sr_op__is_signed$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 45 \sr_op__insn$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 46 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 47 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 48 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 49 \xer_ca$17 + cell \p$393 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$394 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__oe__oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type$19 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \input_sr_op__fn_unit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__imm$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__imm_data__imm_ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__rc__rc$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__rc__rc_ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__oe__oe$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__oe__oe_ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__output_carry$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__input_cr$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__output_cr$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__is_32bit$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \input_sr_op__is_signed$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$37 + cell \input$395 \input + connect \muxid \input_muxid + connect \sr_op__insn_type \input_sr_op__insn_type + connect \sr_op__fn_unit \input_sr_op__fn_unit + connect \sr_op__imm_data__imm \input_sr_op__imm_data__imm + connect \sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm_ok + connect \sr_op__rc__rc \input_sr_op__rc__rc + connect \sr_op__rc__rc_ok \input_sr_op__rc__rc_ok + connect \sr_op__oe__oe \input_sr_op__oe__oe + connect \sr_op__oe__oe_ok \input_sr_op__oe__oe_ok + connect \sr_op__input_carry \input_sr_op__input_carry + connect \sr_op__output_carry \input_sr_op__output_carry + connect \sr_op__input_cr \input_sr_op__input_cr + connect \sr_op__output_cr \input_sr_op__output_cr + connect \sr_op__is_32bit \input_sr_op__is_32bit + connect \sr_op__is_signed \input_sr_op__is_signed + connect \sr_op__insn \input_sr_op__insn + connect \ra \input_ra + connect \rb \input_rb + connect \rc \input_rc + connect \xer_ca \input_xer_ca + connect \muxid$1 \input_muxid$18 + connect \sr_op__insn_type$2 \input_sr_op__insn_type$19 + connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$20 + connect \sr_op__imm_data__imm$4 \input_sr_op__imm_data__imm$21 + connect \sr_op__imm_data__imm_ok$5 \input_sr_op__imm_data__imm_ok$22 + connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$23 + connect \sr_op__rc__rc_ok$7 \input_sr_op__rc__rc_ok$24 + connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$25 + connect \sr_op__oe__oe_ok$9 \input_sr_op__oe__oe_ok$26 + connect \sr_op__input_carry$10 \input_sr_op__input_carry$27 + connect \sr_op__output_carry$11 \input_sr_op__output_carry$28 + connect \sr_op__input_cr$12 \input_sr_op__input_cr$29 + connect \sr_op__output_cr$13 \input_sr_op__output_cr$30 + connect \sr_op__is_32bit$14 \input_sr_op__is_32bit$31 + connect \sr_op__is_signed$15 \input_sr_op__is_signed$32 + connect \sr_op__insn$16 \input_sr_op__insn$33 + connect \ra$17 \input_ra$34 + connect \rb$18 \input_rb$35 + connect \rc$19 \input_rc$36 + connect \xer_ca$20 \input_xer_ca$37 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_sr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \main_sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__oe__oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$38 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_sr_op__insn_type$39 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \main_sr_op__fn_unit$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__imm$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__imm_data__imm_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__rc__rc$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__rc__rc_ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__oe__oe$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__oe__oe_ok$46 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__output_carry$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__input_cr$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__output_cr$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__is_32bit$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \main_sr_op__is_signed$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \main_xer_ca + cell \main$396 \main + connect \muxid \main_muxid + connect \sr_op__insn_type \main_sr_op__insn_type + connect \sr_op__fn_unit \main_sr_op__fn_unit + connect \sr_op__imm_data__imm \main_sr_op__imm_data__imm + connect \sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm_ok + connect \sr_op__rc__rc \main_sr_op__rc__rc + connect \sr_op__rc__rc_ok \main_sr_op__rc__rc_ok + connect \sr_op__oe__oe \main_sr_op__oe__oe + connect \sr_op__oe__oe_ok \main_sr_op__oe__oe_ok + connect \sr_op__input_carry \main_sr_op__input_carry + connect \sr_op__output_carry \main_sr_op__output_carry + connect \sr_op__input_cr \main_sr_op__input_cr + connect \sr_op__output_cr \main_sr_op__output_cr + connect \sr_op__is_32bit \main_sr_op__is_32bit + connect \sr_op__is_signed \main_sr_op__is_signed + connect \sr_op__insn \main_sr_op__insn + connect \ra \main_ra + connect \rb \main_rb + connect \rc \main_rc + connect \muxid$1 \main_muxid$38 + connect \sr_op__insn_type$2 \main_sr_op__insn_type$39 + connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$40 + connect \sr_op__imm_data__imm$4 \main_sr_op__imm_data__imm$41 + connect \sr_op__imm_data__imm_ok$5 \main_sr_op__imm_data__imm_ok$42 + connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$43 + connect \sr_op__rc__rc_ok$7 \main_sr_op__rc__rc_ok$44 + connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$45 + connect \sr_op__oe__oe_ok$9 \main_sr_op__oe__oe_ok$46 + connect \sr_op__input_carry$10 \main_sr_op__input_carry$47 + connect \sr_op__output_carry$11 \main_sr_op__output_carry$48 + connect \sr_op__input_cr$12 \main_sr_op__input_cr$49 + connect \sr_op__output_cr$13 \main_sr_op__output_cr$50 + connect \sr_op__is_32bit$14 \main_sr_op__is_32bit$51 + connect \sr_op__is_signed$15 \main_sr_op__is_signed$52 + connect \sr_op__insn$16 \main_sr_op__insn$53 + connect \o \main_o + connect \o_ok \main_o_ok + connect \xer_ca \main_xer_ca + end + process $group_0 + assign \input_muxid 2'00 + assign \input_muxid \muxid$1 + sync init + end + process $group_1 + assign \input_sr_op__insn_type 7'0000000 + assign \input_sr_op__fn_unit 11'00000000000 + assign \input_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_sr_op__imm_data__imm_ok 1'0 + assign \input_sr_op__rc__rc 1'0 + assign \input_sr_op__rc__rc_ok 1'0 + assign \input_sr_op__oe__oe 1'0 + assign \input_sr_op__oe__oe_ok 1'0 + assign { } 0'0 + assign \input_sr_op__input_carry 2'00 + assign \input_sr_op__output_carry 1'0 + assign \input_sr_op__input_cr 1'0 + assign \input_sr_op__output_cr 1'0 + assign \input_sr_op__is_32bit 1'0 + assign \input_sr_op__is_signed 1'0 + assign \input_sr_op__insn 32'00000000000000000000000000000000 + assign { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry { } { \input_sr_op__oe__oe_ok \input_sr_op__oe__oe } { \input_sr_op__rc__rc_ok \input_sr_op__rc__rc } { \input_sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm } \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } + sync init + end + process $group_17 + assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_ra \ra + sync init + end + process $group_18 + assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_rb \rb + sync init + end + process $group_19 + assign \input_rc 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_rc \rc + sync init + end + process $group_20 + assign \input_xer_ca 2'00 + assign \input_xer_ca \xer_ca$17 + sync init + end + process $group_21 + assign \main_muxid 2'00 + assign \main_muxid \input_muxid$18 + sync init + end + process $group_22 + assign \main_sr_op__insn_type 7'0000000 + assign \main_sr_op__fn_unit 11'00000000000 + assign \main_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_sr_op__imm_data__imm_ok 1'0 + assign \main_sr_op__rc__rc 1'0 + assign \main_sr_op__rc__rc_ok 1'0 + assign \main_sr_op__oe__oe 1'0 + assign \main_sr_op__oe__oe_ok 1'0 + assign { } 0'0 + assign \main_sr_op__input_carry 2'00 + assign \main_sr_op__output_carry 1'0 + assign \main_sr_op__input_cr 1'0 + assign \main_sr_op__output_cr 1'0 + assign \main_sr_op__is_32bit 1'0 + assign \main_sr_op__is_signed 1'0 + assign \main_sr_op__insn 32'00000000000000000000000000000000 + assign { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry { } { \main_sr_op__oe__oe_ok \main_sr_op__oe__oe } { \main_sr_op__rc__rc_ok \main_sr_op__rc__rc } { \main_sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm } \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$33 \input_sr_op__is_signed$32 \input_sr_op__is_32bit$31 \input_sr_op__output_cr$30 \input_sr_op__input_cr$29 \input_sr_op__output_carry$28 \input_sr_op__input_carry$27 { } { \input_sr_op__oe__oe_ok$26 \input_sr_op__oe__oe$25 } { \input_sr_op__rc__rc_ok$24 \input_sr_op__rc__rc$23 } { \input_sr_op__imm_data__imm_ok$22 \input_sr_op__imm_data__imm$21 } \input_sr_op__fn_unit$20 \input_sr_op__insn_type$19 } + sync init + end + process $group_38 + assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_ra \input_ra$34 + sync init + end + process $group_39 + assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_rb \input_rb$35 + sync init + end + process $group_40 + assign \main_rc 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_rc \input_rc$36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \xer_ca$54 + process $group_41 + assign \xer_ca$54 2'00 + assign \xer_ca$54 \input_xer_ca$37 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$55 + process $group_42 + assign \p_valid_i$55 1'0 + assign \p_valid_i$55 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_43 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$55 + connect \B \p_ready_o + connect \Y $56 + end + process $group_44 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $56 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$58 + process $group_45 + assign \muxid$58 2'00 + assign \muxid$58 \main_muxid$38 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$59 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \sr_op__fn_unit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__imm$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__imm_data__imm_ok$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__rc__rc$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__rc__rc_ok$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__oe$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__oe_ok$66 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__output_carry$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__input_cr$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__output_cr$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__is_32bit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__is_signed$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$73 + process $group_46 + assign \sr_op__insn_type$59 7'0000000 + assign \sr_op__fn_unit$60 11'00000000000 + assign \sr_op__imm_data__imm$61 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__imm_ok$62 1'0 + assign \sr_op__rc__rc$63 1'0 + assign \sr_op__rc__rc_ok$64 1'0 + assign \sr_op__oe__oe$65 1'0 + assign \sr_op__oe__oe_ok$66 1'0 + assign { } 0'0 + assign \sr_op__input_carry$67 2'00 + assign \sr_op__output_carry$68 1'0 + assign \sr_op__input_cr$69 1'0 + assign \sr_op__output_cr$70 1'0 + assign \sr_op__is_32bit$71 1'0 + assign \sr_op__is_signed$72 1'0 + assign \sr_op__insn$73 32'00000000000000000000000000000000 + assign { \sr_op__insn$73 \sr_op__is_signed$72 \sr_op__is_32bit$71 \sr_op__output_cr$70 \sr_op__input_cr$69 \sr_op__output_carry$68 \sr_op__input_carry$67 { } { \sr_op__oe__oe_ok$66 \sr_op__oe__oe$65 } { \sr_op__rc__rc_ok$64 \sr_op__rc__rc$63 } { \sr_op__imm_data__imm_ok$62 \sr_op__imm_data__imm$61 } \sr_op__fn_unit$60 \sr_op__insn_type$59 } { \main_sr_op__insn$53 \main_sr_op__is_signed$52 \main_sr_op__is_32bit$51 \main_sr_op__output_cr$50 \main_sr_op__input_cr$49 \main_sr_op__output_carry$48 \main_sr_op__input_carry$47 { } { \main_sr_op__oe__oe_ok$46 \main_sr_op__oe__oe$45 } { \main_sr_op__rc__rc_ok$44 \main_sr_op__rc__rc$43 } { \main_sr_op__imm_data__imm_ok$42 \main_sr_op__imm_data__imm$41 } \main_sr_op__fn_unit$40 \main_sr_op__insn_type$39 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$75 + process $group_62 + assign \o$74 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$75 1'0 + assign { \o_ok$75 \o$74 } { \main_o_ok \main_o } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$79 + process $group_64 + assign \cr_a$76 4'0000 + assign \cr_a_ok$77 1'0 + assign { \cr_a_ok$77 \cr_a$76 } { \cr_a_ok$79 \cr_a$78 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$82 + process $group_66 + assign \xer_ca$80 2'00 + assign \xer_ca_ok$81 1'0 + assign { \xer_ca_ok$81 \xer_ca$80 } { \xer_ca_ok$82 \main_xer_ca } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_68 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_69 + assign \muxid$next \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$next \muxid$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$next \muxid$58 + end + sync init + update \muxid 2'00 + sync posedge \coresync_clk + update \muxid \muxid$next + end + process $group_70 + assign \sr_op__insn_type$next \sr_op__insn_type + assign \sr_op__fn_unit$next \sr_op__fn_unit + assign \sr_op__imm_data__imm$next \sr_op__imm_data__imm + assign \sr_op__imm_data__imm_ok$next \sr_op__imm_data__imm_ok + assign \sr_op__rc__rc$next \sr_op__rc__rc + assign \sr_op__rc__rc_ok$next \sr_op__rc__rc_ok + assign \sr_op__oe__oe$next \sr_op__oe__oe + assign \sr_op__oe__oe_ok$next \sr_op__oe__oe_ok + assign { } { } + assign \sr_op__input_carry$next \sr_op__input_carry + assign \sr_op__output_carry$next \sr_op__output_carry + assign \sr_op__input_cr$next \sr_op__input_cr + assign \sr_op__output_cr$next \sr_op__output_cr + assign \sr_op__is_32bit$next \sr_op__is_32bit + assign \sr_op__is_signed$next \sr_op__is_signed + assign \sr_op__insn$next \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \sr_op__insn$next \sr_op__is_signed$next \sr_op__is_32bit$next \sr_op__output_cr$next \sr_op__input_cr$next \sr_op__output_carry$next \sr_op__input_carry$next { } { \sr_op__oe__oe_ok$next \sr_op__oe__oe$next } { \sr_op__rc__rc_ok$next \sr_op__rc__rc$next } { \sr_op__imm_data__imm_ok$next \sr_op__imm_data__imm$next } \sr_op__fn_unit$next \sr_op__insn_type$next } { \sr_op__insn$73 \sr_op__is_signed$72 \sr_op__is_32bit$71 \sr_op__output_cr$70 \sr_op__input_cr$69 \sr_op__output_carry$68 \sr_op__input_carry$67 { } { \sr_op__oe__oe_ok$66 \sr_op__oe__oe$65 } { \sr_op__rc__rc_ok$64 \sr_op__rc__rc$63 } { \sr_op__imm_data__imm_ok$62 \sr_op__imm_data__imm$61 } \sr_op__fn_unit$60 \sr_op__insn_type$59 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \sr_op__insn$next \sr_op__is_signed$next \sr_op__is_32bit$next \sr_op__output_cr$next \sr_op__input_cr$next \sr_op__output_carry$next \sr_op__input_carry$next { } { \sr_op__oe__oe_ok$next \sr_op__oe__oe$next } { \sr_op__rc__rc_ok$next \sr_op__rc__rc$next } { \sr_op__imm_data__imm_ok$next \sr_op__imm_data__imm$next } \sr_op__fn_unit$next \sr_op__insn_type$next } { \sr_op__insn$73 \sr_op__is_signed$72 \sr_op__is_32bit$71 \sr_op__output_cr$70 \sr_op__input_cr$69 \sr_op__output_carry$68 \sr_op__input_carry$67 { } { \sr_op__oe__oe_ok$66 \sr_op__oe__oe$65 } { \sr_op__rc__rc_ok$64 \sr_op__rc__rc$63 } { \sr_op__imm_data__imm_ok$62 \sr_op__imm_data__imm$61 } \sr_op__fn_unit$60 \sr_op__insn_type$59 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \sr_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__imm_ok$next 1'0 + assign \sr_op__rc__rc$next 1'0 + assign \sr_op__rc__rc_ok$next 1'0 + assign \sr_op__oe__oe$next 1'0 + assign \sr_op__oe__oe_ok$next 1'0 + end + sync init + update \sr_op__insn_type 7'0000000 + update \sr_op__fn_unit 11'00000000000 + update \sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \sr_op__imm_data__imm_ok 1'0 + update \sr_op__rc__rc 1'0 + update \sr_op__rc__rc_ok 1'0 + update \sr_op__oe__oe 1'0 + update \sr_op__oe__oe_ok 1'0 + update { } 0'0 + update \sr_op__input_carry 2'00 + update \sr_op__output_carry 1'0 + update \sr_op__input_cr 1'0 + update \sr_op__output_cr 1'0 + update \sr_op__is_32bit 1'0 + update \sr_op__is_signed 1'0 + update \sr_op__insn 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \sr_op__insn_type \sr_op__insn_type$next + update \sr_op__fn_unit \sr_op__fn_unit$next + update \sr_op__imm_data__imm \sr_op__imm_data__imm$next + update \sr_op__imm_data__imm_ok \sr_op__imm_data__imm_ok$next + update \sr_op__rc__rc \sr_op__rc__rc$next + update \sr_op__rc__rc_ok \sr_op__rc__rc_ok$next + update \sr_op__oe__oe \sr_op__oe__oe$next + update \sr_op__oe__oe_ok \sr_op__oe__oe_ok$next + update { } { } + update \sr_op__input_carry \sr_op__input_carry$next + update \sr_op__output_carry \sr_op__output_carry$next + update \sr_op__input_cr \sr_op__input_cr$next + update \sr_op__output_cr \sr_op__output_cr$next + update \sr_op__is_32bit \sr_op__is_32bit$next + update \sr_op__is_signed \sr_op__is_signed$next + update \sr_op__insn \sr_op__insn$next + end + process $group_86 + assign \o$next \o + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$next } { \o_ok$75 \o$74 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$next } { \o_ok$75 \o$74 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \o_ok$next 1'0 + end + sync init + update \o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 + sync posedge \coresync_clk + update \o \o$next + update \o_ok \o_ok$next + end + process $group_88 + assign \cr_a$next \cr_a + assign \cr_a_ok$next \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$77 \cr_a$76 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$77 \cr_a$76 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cr_a_ok$next 1'0 + end + sync init + update \cr_a 4'0000 + update \cr_a_ok 1'0 + sync posedge \coresync_clk + update \cr_a \cr_a$next + update \cr_a_ok \cr_a_ok$next + end + process $group_90 + assign \xer_ca$next \xer_ca + assign \xer_ca_ok$next \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$81 \xer_ca$80 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$81 \xer_ca$80 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ca_ok$next 1'0 + end + sync init + update \xer_ca 2'00 + update \xer_ca_ok 1'0 + sync posedge \coresync_clk + update \xer_ca \xer_ca$next + update \xer_ca_ok \xer_ca_ok$next + end + process $group_92 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_93 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \cr_a$78 4'0000 + connect \cr_a_ok$79 1'0 + connect \xer_ca_ok$82 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" +module \p$398 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" +module \n$399 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" +module \output$400 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 0 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \sr_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \sr_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \sr_op__oe__oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 10 \sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 18 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 19 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 20 \xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 21 \muxid$1 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 22 \sr_op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 23 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 24 \sr_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 25 \sr_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 26 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 27 \sr_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 28 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 29 \sr_op__oe__oe_ok$9 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 31 \sr_op__input_carry$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 32 \sr_op__output_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \sr_op__input_cr$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \sr_op__output_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \sr_op__is_32bit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 36 \sr_op__is_signed$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 37 \sr_op__insn$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 38 \o$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 39 \o_ok$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 40 \cr_a$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 41 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 42 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 43 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" + wire width 65 \o$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $22 + end + process $group_0 + assign \o$21 65'00000000000000000000000000000000000000000000000000000000000000000 + assign \o$21 $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35" + wire width 64 \target + process $group_1 + assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \target \o$21 [63:0] + sync init + end + process $group_2 + assign \xer_ca$20 2'00 + assign \xer_ca$20 \xer_ca + sync init + end + process $group_3 + assign \xer_ca_ok 1'0 + assign \xer_ca_ok \sr_op__output_carry + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + wire width 1 \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + cell $eq $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \sr_op__insn_type + connect \B 7'0001010 + connect \Y $24 + end + process $group_4 + assign \is_cmp 1'0 + assign \is_cmp $24 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + wire width 1 \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + wire width 1 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64" + cell $eq $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \sr_op__insn_type + connect \B 7'0001100 + connect \Y $26 + end + process $group_5 + assign \is_cmpeqb 1'0 + assign \is_cmpeqb $26 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + wire width 1 \msb_test + process $group_6 + assign \msb_test 1'0 + assign \msb_test \target [63] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 1 \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $28 + end + process $group_7 + assign \is_nzero 1'0 + assign \is_nzero $28 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51" + wire width 1 \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $not $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $and $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $30 + connect \Y $32 + end + process $group_8 + assign \is_positive 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_positive \msb_test + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_positive $32 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52" + wire width 1 \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $not $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74" + cell $and $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $34 + connect \Y $36 + end + process $group_9 + assign \is_negative 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + switch { \is_cmp } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72" + case 1'1 + assign \is_negative $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75" + case + assign \is_negative \msb_test + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82" + cell $not $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $38 + end + process $group_10 + assign \cr0 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + switch { \is_cmpeqb } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79" + case 1'1 + assign \cr0 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + case + assign \cr0 { \is_negative \is_positive $38 1'0 } + end + sync init + end + process $group_11 + assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o$17 \o$21 [63:0] + sync init + end + process $group_12 + assign \o_ok$18 1'0 + assign \o_ok$18 \o_ok + sync init + end + process $group_13 + assign \cr_a$19 4'0000 + assign \cr_a$19 \cr0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 0 + parameter \Y_WIDTH 1 + connect \A { } + connect \Y $40 + end + process $group_14 + assign \cr_a_ok 1'0 + assign \cr_a_ok $40 + sync init + end + process $group_15 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_16 + assign \sr_op__insn_type$2 7'0000000 + assign \sr_op__fn_unit$3 11'00000000000 + assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__imm_ok$5 1'0 + assign \sr_op__rc__rc$6 1'0 + assign \sr_op__rc__rc_ok$7 1'0 + assign \sr_op__oe__oe$8 1'0 + assign \sr_op__oe__oe_ok$9 1'0 + assign { } 0'0 + assign \sr_op__input_carry$10 2'00 + assign \sr_op__output_carry$11 1'0 + assign \sr_op__input_cr$12 1'0 + assign \sr_op__output_cr$13 1'0 + assign \sr_op__is_32bit$14 1'0 + assign \sr_op__is_signed$15 1'0 + assign \sr_op__insn$16 32'00000000000000000000000000000000 + assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2" +module \pipe2$397 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \sr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 6 \sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \sr_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \sr_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \sr_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \sr_op__oe__oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 14 \sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 18 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 19 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 20 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 21 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 22 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 23 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 24 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 25 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 26 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 27 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 28 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 29 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 30 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 output 31 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \sr_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 32 \sr_op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 33 \sr_op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 34 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 35 \sr_op__rc__rc_ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__rc__rc_ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 36 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 37 \sr_op__oe__oe_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__oe_ok$9$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 39 \sr_op__input_carry$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 40 \sr_op__output_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__output_carry$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 41 \sr_op__input_cr$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__input_cr$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 42 \sr_op__output_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__output_cr$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 43 \sr_op__is_32bit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__is_32bit$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 output 44 \sr_op__is_signed$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__is_signed$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 45 \sr_op__insn$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 46 \o$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 47 \o_ok$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 48 \cr_a$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 49 \cr_a_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 50 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 51 \xer_ca_ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$22$next + cell \p$398 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$399 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute 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attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \output_sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_sr_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__oe__oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$23 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type$24 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \output_sr_op__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_sr_op__imm_data__imm$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__imm_data__imm_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__rc__rc$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__rc__rc_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__oe__oe$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__oe__oe_ok$31 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_sr_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__output_carry$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__input_cr$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__output_cr$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \output_sr_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_sr_op__insn$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_o_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \output_xer_ca_ok + cell \output$400 \output + connect \muxid \output_muxid + connect \sr_op__insn_type \output_sr_op__insn_type + connect \sr_op__fn_unit \output_sr_op__fn_unit + connect \sr_op__imm_data__imm \output_sr_op__imm_data__imm + connect \sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm_ok + connect \sr_op__rc__rc \output_sr_op__rc__rc + connect \sr_op__rc__rc_ok \output_sr_op__rc__rc_ok + connect \sr_op__oe__oe \output_sr_op__oe__oe + connect \sr_op__oe__oe_ok \output_sr_op__oe__oe_ok + connect \sr_op__input_carry \output_sr_op__input_carry + connect \sr_op__output_carry \output_sr_op__output_carry + connect \sr_op__input_cr \output_sr_op__input_cr + connect \sr_op__output_cr \output_sr_op__output_cr + connect \sr_op__is_32bit \output_sr_op__is_32bit + connect \sr_op__is_signed \output_sr_op__is_signed + connect \sr_op__insn \output_sr_op__insn + connect \o \output_o + connect \o_ok \output_o_ok + connect \cr_a \output_cr_a + connect \xer_ca \output_xer_ca + connect \muxid$1 \output_muxid$23 + connect \sr_op__insn_type$2 \output_sr_op__insn_type$24 + connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$25 + connect \sr_op__imm_data__imm$4 \output_sr_op__imm_data__imm$26 + connect \sr_op__imm_data__imm_ok$5 \output_sr_op__imm_data__imm_ok$27 + connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$28 + connect \sr_op__rc__rc_ok$7 \output_sr_op__rc__rc_ok$29 + connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$30 + connect \sr_op__oe__oe_ok$9 \output_sr_op__oe__oe_ok$31 + connect \sr_op__input_carry$10 \output_sr_op__input_carry$32 + connect \sr_op__output_carry$11 \output_sr_op__output_carry$33 + connect \sr_op__input_cr$12 \output_sr_op__input_cr$34 + connect \sr_op__output_cr$13 \output_sr_op__output_cr$35 + connect \sr_op__is_32bit$14 \output_sr_op__is_32bit$36 + connect \sr_op__is_signed$15 \output_sr_op__is_signed$37 + connect \sr_op__insn$16 \output_sr_op__insn$38 + connect \o$17 \output_o$39 + connect \o_ok$18 \output_o_ok$40 + connect \cr_a$19 \output_cr_a$41 + connect \cr_a_ok \output_cr_a_ok + connect \xer_ca$20 \output_xer_ca$42 + connect \xer_ca_ok \output_xer_ca_ok + end + process $group_0 + assign \output_muxid 2'00 + assign \output_muxid \muxid + sync init + end + process $group_1 + assign \output_sr_op__insn_type 7'0000000 + assign \output_sr_op__fn_unit 11'00000000000 + assign \output_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_sr_op__imm_data__imm_ok 1'0 + assign \output_sr_op__rc__rc 1'0 + assign \output_sr_op__rc__rc_ok 1'0 + assign \output_sr_op__oe__oe 1'0 + assign \output_sr_op__oe__oe_ok 1'0 + assign { } 0'0 + assign \output_sr_op__input_carry 2'00 + assign \output_sr_op__output_carry 1'0 + assign \output_sr_op__input_cr 1'0 + assign \output_sr_op__output_cr 1'0 + assign \output_sr_op__is_32bit 1'0 + assign \output_sr_op__is_signed 1'0 + assign \output_sr_op__insn 32'00000000000000000000000000000000 + assign { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry { } { \output_sr_op__oe__oe_ok \output_sr_op__oe__oe } { \output_sr_op__rc__rc_ok \output_sr_op__rc__rc } { \output_sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm } \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + sync init + end + process $group_17 + assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_o_ok 1'0 + assign { \output_o_ok \output_o } { \o_ok \o } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$43 + process $group_19 + assign \output_cr_a 4'0000 + assign \cr_a_ok$43 1'0 + assign { \cr_a_ok$43 \output_cr_a } { \cr_a_ok \cr_a } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$44 + process $group_21 + assign \output_xer_ca 2'00 + assign \xer_ca_ok$44 1'0 + assign { \xer_ca_ok$44 \output_xer_ca } { \xer_ca_ok \xer_ca } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$45 + process $group_23 + assign \p_valid_i$45 1'0 + assign \p_valid_i$45 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_24 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$45 + connect \B \p_ready_o + connect \Y $46 + end + process $group_25 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $46 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$48 + process $group_26 + assign \muxid$48 2'00 + assign \muxid$48 \output_muxid$23 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$49 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \sr_op__fn_unit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__imm$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__imm_data__imm_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__rc__rc$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__rc__rc_ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__oe$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__oe_ok$56 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__output_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__input_cr$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__output_cr$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__is_32bit$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__is_signed$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$63 + process $group_27 + assign \sr_op__insn_type$49 7'0000000 + assign \sr_op__fn_unit$50 11'00000000000 + assign \sr_op__imm_data__imm$51 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__imm_ok$52 1'0 + assign \sr_op__rc__rc$53 1'0 + assign \sr_op__rc__rc_ok$54 1'0 + assign \sr_op__oe__oe$55 1'0 + assign \sr_op__oe__oe_ok$56 1'0 + assign { } 0'0 + assign \sr_op__input_carry$57 2'00 + assign \sr_op__output_carry$58 1'0 + assign \sr_op__input_cr$59 1'0 + assign \sr_op__output_cr$60 1'0 + assign \sr_op__is_32bit$61 1'0 + assign \sr_op__is_signed$62 1'0 + assign \sr_op__insn$63 32'00000000000000000000000000000000 + assign { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 { } { \sr_op__oe__oe_ok$56 \sr_op__oe__oe$55 } { \sr_op__rc__rc_ok$54 \sr_op__rc__rc$53 } { \sr_op__imm_data__imm_ok$52 \sr_op__imm_data__imm$51 } \sr_op__fn_unit$50 \sr_op__insn_type$49 } { \output_sr_op__insn$38 \output_sr_op__is_signed$37 \output_sr_op__is_32bit$36 \output_sr_op__output_cr$35 \output_sr_op__input_cr$34 \output_sr_op__output_carry$33 \output_sr_op__input_carry$32 { } { \output_sr_op__oe__oe_ok$31 \output_sr_op__oe__oe$30 } { \output_sr_op__rc__rc_ok$29 \output_sr_op__rc__rc$28 } { \output_sr_op__imm_data__imm_ok$27 \output_sr_op__imm_data__imm$26 } \output_sr_op__fn_unit$25 \output_sr_op__insn_type$24 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok$65 + process $group_43 + assign \o$64 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$65 1'0 + assign { \o_ok$65 \o$64 } { \output_o_ok$40 \output_o$39 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_a_ok$67 + process $group_45 + assign \cr_a$66 4'0000 + assign \cr_a_ok$67 1'0 + assign { \cr_a_ok$67 \cr_a$66 } { \output_cr_a_ok \output_cr_a$41 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \xer_ca_ok$69 + process $group_47 + assign \xer_ca$68 2'00 + assign \xer_ca_ok$69 1'0 + assign { \xer_ca_ok$69 \xer_ca$68 } { \output_xer_ca_ok \output_xer_ca$42 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_49 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \coresync_clk + update \r_busy \r_busy$next + end + process $group_50 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$48 + end + sync init + update \muxid$1 2'00 + sync posedge \coresync_clk + update \muxid$1 \muxid$1$next + end + process $group_51 + assign \sr_op__insn_type$2$next \sr_op__insn_type$2 + assign \sr_op__fn_unit$3$next \sr_op__fn_unit$3 + assign \sr_op__imm_data__imm$4$next \sr_op__imm_data__imm$4 + assign \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm_ok$5 + assign \sr_op__rc__rc$6$next \sr_op__rc__rc$6 + assign \sr_op__rc__rc_ok$7$next \sr_op__rc__rc_ok$7 + assign \sr_op__oe__oe$8$next \sr_op__oe__oe$8 + assign \sr_op__oe__oe_ok$9$next \sr_op__oe__oe_ok$9 + assign { } { } + assign \sr_op__input_carry$10$next \sr_op__input_carry$10 + assign \sr_op__output_carry$11$next \sr_op__output_carry$11 + assign \sr_op__input_cr$12$next \sr_op__input_cr$12 + assign \sr_op__output_cr$13$next \sr_op__output_cr$13 + assign \sr_op__is_32bit$14$next \sr_op__is_32bit$14 + assign \sr_op__is_signed$15$next \sr_op__is_signed$15 + assign \sr_op__insn$16$next \sr_op__insn$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 { } { \sr_op__oe__oe_ok$56 \sr_op__oe__oe$55 } { \sr_op__rc__rc_ok$54 \sr_op__rc__rc$53 } { \sr_op__imm_data__imm_ok$52 \sr_op__imm_data__imm$51 } \sr_op__fn_unit$50 \sr_op__insn_type$49 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 { } { \sr_op__oe__oe_ok$56 \sr_op__oe__oe$55 } { \sr_op__rc__rc_ok$54 \sr_op__rc__rc$53 } { \sr_op__imm_data__imm_ok$52 \sr_op__imm_data__imm$51 } \sr_op__fn_unit$50 \sr_op__insn_type$49 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \sr_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__imm_ok$5$next 1'0 + assign \sr_op__rc__rc$6$next 1'0 + assign \sr_op__rc__rc_ok$7$next 1'0 + assign \sr_op__oe__oe$8$next 1'0 + assign \sr_op__oe__oe_ok$9$next 1'0 + end + sync init + update \sr_op__insn_type$2 7'0000000 + update \sr_op__fn_unit$3 11'00000000000 + update \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \sr_op__imm_data__imm_ok$5 1'0 + update \sr_op__rc__rc$6 1'0 + update \sr_op__rc__rc_ok$7 1'0 + update \sr_op__oe__oe$8 1'0 + update \sr_op__oe__oe_ok$9 1'0 + update { } 0'0 + update \sr_op__input_carry$10 2'00 + update \sr_op__output_carry$11 1'0 + update \sr_op__input_cr$12 1'0 + update \sr_op__output_cr$13 1'0 + update \sr_op__is_32bit$14 1'0 + update \sr_op__is_signed$15 1'0 + update \sr_op__insn$16 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \sr_op__insn_type$2 \sr_op__insn_type$2$next + update \sr_op__fn_unit$3 \sr_op__fn_unit$3$next + update \sr_op__imm_data__imm$4 \sr_op__imm_data__imm$4$next + update \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm_ok$5$next + update \sr_op__rc__rc$6 \sr_op__rc__rc$6$next + update \sr_op__rc__rc_ok$7 \sr_op__rc__rc_ok$7$next + update \sr_op__oe__oe$8 \sr_op__oe__oe$8$next + update \sr_op__oe__oe_ok$9 \sr_op__oe__oe_ok$9$next + update { } { } + update \sr_op__input_carry$10 \sr_op__input_carry$10$next + update \sr_op__output_carry$11 \sr_op__output_carry$11$next + update \sr_op__input_cr$12 \sr_op__input_cr$12$next + update \sr_op__output_cr$13 \sr_op__output_cr$13$next + update \sr_op__is_32bit$14 \sr_op__is_32bit$14$next + update \sr_op__is_signed$15 \sr_op__is_signed$15$next + update \sr_op__insn$16 \sr_op__insn$16$next + end + process $group_67 + assign \o$17$next \o$17 + assign \o_ok$18$next \o_ok$18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$18$next \o$17$next } { \o_ok$65 \o$64 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$18$next \o$17$next } { \o_ok$65 \o$64 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \o_ok$18$next 1'0 + end + sync init + update \o$17 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok$18 1'0 + sync posedge \coresync_clk + update \o$17 \o$17$next + update \o_ok$18 \o_ok$18$next + end + process $group_69 + assign \cr_a$19$next \cr_a$19 + assign \cr_a_ok$20$next \cr_a_ok$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$20$next \cr_a$19$next } { \cr_a_ok$67 \cr_a$66 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$20$next \cr_a$19$next } { \cr_a_ok$67 \cr_a$66 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cr_a_ok$20$next 1'0 + end + sync init + update \cr_a$19 4'0000 + update \cr_a_ok$20 1'0 + sync posedge \coresync_clk + update \cr_a$19 \cr_a$19$next + update \cr_a_ok$20 \cr_a_ok$20$next + end + process $group_71 + assign \xer_ca$21$next \xer_ca$21 + assign \xer_ca_ok$22$next \xer_ca_ok$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ca_ok$22$next \xer_ca$21$next } { \xer_ca_ok$69 \xer_ca$68 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ca_ok$22$next \xer_ca$21$next } { \xer_ca_ok$69 \xer_ca$68 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \xer_ca_ok$22$next 1'0 + end + sync init + update \xer_ca$21 2'00 + update \xer_ca_ok$22 1'0 + sync posedge \coresync_clk + update \xer_ca$21 \xer_ca$21$next + update \xer_ca_ok$22 \xer_ca_ok$22$next + end + process $group_73 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_74 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0" +module \alu_shift_rot0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \xer_ca_ok + attribute \src "simple/issuer.py:102" + wire width 1 input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 input 6 \n_ready_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \sr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 8 \sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \sr_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \sr_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \sr_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \sr_op__oe__oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 16 \sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 28 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 29 \xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 input 30 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 output 31 \p_ready_o + cell \p$390 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$391 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_sr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe1_sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__oe__oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe1_cr_a + attribute \src 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attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute 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attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe1_sr_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__imm$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__imm_data__imm_ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__oe__oe_ok$10 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe1_sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$18 + cell \pipe1$392 \pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \n_valid_o \pipe1_n_valid_o + connect \n_ready_i \pipe1_n_ready_i + connect \muxid \pipe1_muxid + connect \sr_op__insn_type \pipe1_sr_op__insn_type + connect \sr_op__fn_unit \pipe1_sr_op__fn_unit + connect \sr_op__imm_data__imm \pipe1_sr_op__imm_data__imm + connect \sr_op__imm_data__imm_ok \pipe1_sr_op__imm_data__imm_ok + connect \sr_op__rc__rc \pipe1_sr_op__rc__rc + connect \sr_op__rc__rc_ok \pipe1_sr_op__rc__rc_ok + connect \sr_op__oe__oe \pipe1_sr_op__oe__oe + connect \sr_op__oe__oe_ok \pipe1_sr_op__oe__oe_ok + connect \sr_op__input_carry \pipe1_sr_op__input_carry + connect \sr_op__output_carry \pipe1_sr_op__output_carry + connect \sr_op__input_cr \pipe1_sr_op__input_cr + connect \sr_op__output_cr \pipe1_sr_op__output_cr + connect \sr_op__is_32bit \pipe1_sr_op__is_32bit + connect \sr_op__is_signed \pipe1_sr_op__is_signed + connect \sr_op__insn \pipe1_sr_op__insn + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \xer_ca \pipe1_xer_ca + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \p_valid_i \pipe1_p_valid_i + connect \p_ready_o \pipe1_p_ready_o + connect \muxid$1 \pipe1_muxid$2 + connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 + connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 + connect \sr_op__imm_data__imm$4 \pipe1_sr_op__imm_data__imm$5 + connect \sr_op__imm_data__imm_ok$5 \pipe1_sr_op__imm_data__imm_ok$6 + connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 + connect \sr_op__rc__rc_ok$7 \pipe1_sr_op__rc__rc_ok$8 + connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 + connect \sr_op__oe__oe_ok$9 \pipe1_sr_op__oe__oe_ok$10 + connect \sr_op__input_carry$10 \pipe1_sr_op__input_carry$11 + connect \sr_op__output_carry$11 \pipe1_sr_op__output_carry$12 + connect \sr_op__input_cr$12 \pipe1_sr_op__input_cr$13 + connect \sr_op__output_cr$13 \pipe1_sr_op__output_cr$14 + connect \sr_op__is_32bit$14 \pipe1_sr_op__is_32bit$15 + connect \sr_op__is_signed$15 \pipe1_sr_op__is_signed$16 + connect \sr_op__insn$16 \pipe1_sr_op__insn$17 + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \rc \pipe1_rc + connect \xer_ca$17 \pipe1_xer_ca$18 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe2_sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__oe__oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type$20 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \pipe2_sr_op__fn_unit$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__imm$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__imm_data__imm_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__rc__rc$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__rc__rc_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__oe__oe$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__oe__oe_ok$27 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_sr_op__input_carry$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__output_carry$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__input_cr$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__output_cr$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__is_32bit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \pipe2_sr_op__is_signed$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_o_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_cr_a_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pipe2_xer_ca_ok$40 + cell \pipe2$397 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \p_valid_i \pipe2_p_valid_i + connect \p_ready_o \pipe2_p_ready_o + connect \muxid \pipe2_muxid + connect \sr_op__insn_type \pipe2_sr_op__insn_type + connect \sr_op__fn_unit \pipe2_sr_op__fn_unit + connect \sr_op__imm_data__imm \pipe2_sr_op__imm_data__imm + connect \sr_op__imm_data__imm_ok \pipe2_sr_op__imm_data__imm_ok + connect \sr_op__rc__rc \pipe2_sr_op__rc__rc + connect \sr_op__rc__rc_ok \pipe2_sr_op__rc__rc_ok + connect \sr_op__oe__oe \pipe2_sr_op__oe__oe + connect \sr_op__oe__oe_ok \pipe2_sr_op__oe__oe_ok + connect \sr_op__input_carry \pipe2_sr_op__input_carry + connect \sr_op__output_carry \pipe2_sr_op__output_carry + connect \sr_op__input_cr \pipe2_sr_op__input_cr + connect \sr_op__output_cr \pipe2_sr_op__output_cr + connect \sr_op__is_32bit \pipe2_sr_op__is_32bit + connect \sr_op__is_signed \pipe2_sr_op__is_signed + connect \sr_op__insn \pipe2_sr_op__insn + connect \o \pipe2_o + connect \o_ok \pipe2_o_ok + connect \cr_a \pipe2_cr_a + connect \cr_a_ok \pipe2_cr_a_ok + connect \xer_ca \pipe2_xer_ca + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \n_valid_o \pipe2_n_valid_o + connect \n_ready_i \pipe2_n_ready_i + connect \muxid$1 \pipe2_muxid$19 + connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$20 + connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$21 + connect \sr_op__imm_data__imm$4 \pipe2_sr_op__imm_data__imm$22 + connect \sr_op__imm_data__imm_ok$5 \pipe2_sr_op__imm_data__imm_ok$23 + connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$24 + connect \sr_op__rc__rc_ok$7 \pipe2_sr_op__rc__rc_ok$25 + connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$26 + connect \sr_op__oe__oe_ok$9 \pipe2_sr_op__oe__oe_ok$27 + connect \sr_op__input_carry$10 \pipe2_sr_op__input_carry$28 + connect \sr_op__output_carry$11 \pipe2_sr_op__output_carry$29 + connect \sr_op__input_cr$12 \pipe2_sr_op__input_cr$30 + connect \sr_op__output_cr$13 \pipe2_sr_op__output_cr$31 + connect \sr_op__is_32bit$14 \pipe2_sr_op__is_32bit$32 + connect \sr_op__is_signed$15 \pipe2_sr_op__is_signed$33 + connect \sr_op__insn$16 \pipe2_sr_op__insn$34 + connect \o$17 \pipe2_o$35 + connect \o_ok$18 \pipe2_o_ok$36 + connect \cr_a$19 \pipe2_cr_a$37 + connect \cr_a_ok$20 \pipe2_cr_a_ok$38 + connect \xer_ca$21 \pipe2_xer_ca$39 + connect \xer_ca_ok$22 \pipe2_xer_ca_ok$40 + end + process $group_0 + assign \pipe2_p_valid_i 1'0 + assign \pipe2_p_valid_i \pipe1_n_valid_o + sync init + end + process $group_1 + assign \pipe1_n_ready_i 1'0 + assign \pipe1_n_ready_i \pipe2_p_ready_o + sync init + end + process $group_2 + assign \pipe2_muxid 2'00 + assign \pipe2_muxid \pipe1_muxid + sync init + end + process $group_3 + assign \pipe2_sr_op__insn_type 7'0000000 + assign \pipe2_sr_op__fn_unit 11'00000000000 + assign \pipe2_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe2_sr_op__imm_data__imm_ok 1'0 + assign \pipe2_sr_op__rc__rc 1'0 + assign \pipe2_sr_op__rc__rc_ok 1'0 + assign \pipe2_sr_op__oe__oe 1'0 + assign \pipe2_sr_op__oe__oe_ok 1'0 + assign { } 0'0 + assign \pipe2_sr_op__input_carry 2'00 + assign \pipe2_sr_op__output_carry 1'0 + assign \pipe2_sr_op__input_cr 1'0 + assign \pipe2_sr_op__output_cr 1'0 + assign \pipe2_sr_op__is_32bit 1'0 + assign \pipe2_sr_op__is_signed 1'0 + assign \pipe2_sr_op__insn 32'00000000000000000000000000000000 + assign { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry { } { \pipe2_sr_op__oe__oe_ok \pipe2_sr_op__oe__oe } { \pipe2_sr_op__rc__rc_ok \pipe2_sr_op__rc__rc } { \pipe2_sr_op__imm_data__imm_ok \pipe2_sr_op__imm_data__imm } \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry { } { \pipe1_sr_op__oe__oe_ok \pipe1_sr_op__oe__oe } { \pipe1_sr_op__rc__rc_ok \pipe1_sr_op__rc__rc } { \pipe1_sr_op__imm_data__imm_ok \pipe1_sr_op__imm_data__imm } \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } + sync init + end + process $group_19 + assign \pipe2_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe2_o_ok 1'0 + assign { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + sync init + end + process $group_21 + assign \pipe2_cr_a 4'0000 + assign \pipe2_cr_a_ok 1'0 + assign { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + sync init + end + process $group_23 + assign \pipe2_xer_ca 2'00 + assign \pipe2_xer_ca_ok 1'0 + assign { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + sync init + end + process $group_25 + assign \pipe1_p_valid_i 1'0 + assign \pipe1_p_valid_i \p_valid_i + sync init + end + process $group_26 + assign \p_ready_o 1'0 + assign \p_ready_o \pipe1_p_ready_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + process $group_27 + assign \pipe1_muxid$2 2'00 + assign \pipe1_muxid$2 \muxid + sync init + end + process $group_28 + assign \pipe1_sr_op__insn_type$3 7'0000000 + assign \pipe1_sr_op__fn_unit$4 11'00000000000 + assign \pipe1_sr_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe1_sr_op__imm_data__imm_ok$6 1'0 + assign \pipe1_sr_op__rc__rc$7 1'0 + assign \pipe1_sr_op__rc__rc_ok$8 1'0 + assign \pipe1_sr_op__oe__oe$9 1'0 + assign \pipe1_sr_op__oe__oe_ok$10 1'0 + assign { } 0'0 + assign \pipe1_sr_op__input_carry$11 2'00 + assign \pipe1_sr_op__output_carry$12 1'0 + assign \pipe1_sr_op__input_cr$13 1'0 + assign \pipe1_sr_op__output_cr$14 1'0 + assign \pipe1_sr_op__is_32bit$15 1'0 + assign \pipe1_sr_op__is_signed$16 1'0 + assign \pipe1_sr_op__insn$17 32'00000000000000000000000000000000 + assign { \pipe1_sr_op__insn$17 \pipe1_sr_op__is_signed$16 \pipe1_sr_op__is_32bit$15 \pipe1_sr_op__output_cr$14 \pipe1_sr_op__input_cr$13 \pipe1_sr_op__output_carry$12 \pipe1_sr_op__input_carry$11 { } { \pipe1_sr_op__oe__oe_ok$10 \pipe1_sr_op__oe__oe$9 } { \pipe1_sr_op__rc__rc_ok$8 \pipe1_sr_op__rc__rc$7 } { \pipe1_sr_op__imm_data__imm_ok$6 \pipe1_sr_op__imm_data__imm$5 } \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type } + sync init + end + process $group_44 + assign \pipe1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe1_ra \ra + sync init + end + process $group_45 + assign \pipe1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe1_rb \rb + sync init + end + process $group_46 + assign \pipe1_rc 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe1_rc \rc + sync init + end + process $group_47 + assign \pipe1_xer_ca$18 2'00 + assign \pipe1_xer_ca$18 \xer_ca$1 + sync init + end + process $group_48 + assign \n_valid_o 1'0 + assign \n_valid_o \pipe2_n_valid_o + sync init + end + process $group_49 + assign \pipe2_n_ready_i 1'0 + assign \pipe2_n_ready_i \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$41 + process $group_50 + assign \muxid$41 2'00 + assign \muxid$41 \pipe2_muxid$19 + sync init + end + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$42 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \sr_op__fn_unit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__imm$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__imm_data__imm_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__rc__rc$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__rc__rc_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__oe__oe_ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__output_carry$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__input_cr$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__output_cr$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__is_32bit$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \sr_op__is_signed$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$56 + process $group_51 + assign \sr_op__insn_type$42 7'0000000 + assign \sr_op__fn_unit$43 11'00000000000 + assign \sr_op__imm_data__imm$44 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sr_op__imm_data__imm_ok$45 1'0 + assign \sr_op__rc__rc$46 1'0 + assign \sr_op__rc__rc_ok$47 1'0 + assign \sr_op__oe__oe$48 1'0 + assign \sr_op__oe__oe_ok$49 1'0 + assign { } 0'0 + assign \sr_op__input_carry$50 2'00 + assign \sr_op__output_carry$51 1'0 + assign \sr_op__input_cr$52 1'0 + assign \sr_op__output_cr$53 1'0 + assign \sr_op__is_32bit$54 1'0 + assign \sr_op__is_signed$55 1'0 + assign \sr_op__insn$56 32'00000000000000000000000000000000 + assign { \sr_op__insn$56 \sr_op__is_signed$55 \sr_op__is_32bit$54 \sr_op__output_cr$53 \sr_op__input_cr$52 \sr_op__output_carry$51 \sr_op__input_carry$50 { } { \sr_op__oe__oe_ok$49 \sr_op__oe__oe$48 } { \sr_op__rc__rc_ok$47 \sr_op__rc__rc$46 } { \sr_op__imm_data__imm_ok$45 \sr_op__imm_data__imm$44 } \sr_op__fn_unit$43 \sr_op__insn_type$42 } { \pipe2_sr_op__insn$34 \pipe2_sr_op__is_signed$33 \pipe2_sr_op__is_32bit$32 \pipe2_sr_op__output_cr$31 \pipe2_sr_op__input_cr$30 \pipe2_sr_op__output_carry$29 \pipe2_sr_op__input_carry$28 { } { \pipe2_sr_op__oe__oe_ok$27 \pipe2_sr_op__oe__oe$26 } { \pipe2_sr_op__rc__rc_ok$25 \pipe2_sr_op__rc__rc$24 } { \pipe2_sr_op__imm_data__imm_ok$23 \pipe2_sr_op__imm_data__imm$22 } \pipe2_sr_op__fn_unit$21 \pipe2_sr_op__insn_type$20 } + sync init + end + process $group_67 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'0 + assign { \o_ok \o } { \pipe2_o_ok$36 \pipe2_o$35 } + sync init + end + process $group_69 + assign \cr_a 4'0000 + assign \cr_a_ok 1'0 + assign { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$38 \pipe2_cr_a$37 } + sync init + end + process $group_71 + assign \xer_ca 2'00 + assign \xer_ca_ok 1'0 + assign { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$40 \pipe2_xer_ca$39 } + sync init + end + connect \muxid 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" +module \src_l$401 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $3 + connect \B \s_src + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 4'0000 + end + sync init + update \q_int 4'0000 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $9 + connect \B \s_src + connect \Y $11 + end + process $group_1 + assign \q_src 4'0000 + assign \q_src $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \Y $13 + end + process $group_2 + assign \qn_src 4'0000 + assign \qn_src $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_src 4'0000 + assign \qlq_src $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" +module \opc_l$402 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_opc + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_opc + connect \Y $11 + end + process $group_1 + assign \q_opc 1'0 + assign \q_opc $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $13 + end + process $group_2 + assign \qn_opc 1'0 + assign \qn_opc $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_opc 1'0 + assign \qlq_opc $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" +module \req_l$403 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $3 + connect \B \s_req + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 3'000 + end + sync init + update \q_int 3'000 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $9 + connect \B \s_req + connect \Y $11 + end + process $group_1 + assign \q_req 3'000 + assign \q_req $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $13 + end + process $group_2 + assign \qn_req 3'000 + assign \qn_req $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_req 3'000 + assign \qlq_req $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" +module \rst_l$404 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rst + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rst + connect \Y $11 + end + process $group_1 + assign \q_rst 1'0 + assign \q_rst $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $13 + end + process $group_2 + assign \qn_rst 1'0 + assign \qn_rst $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rst 1'0 + assign \qlq_rst $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" +module \rok_l$405 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rdok + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rdok + connect \Y $11 + end + process $group_1 + assign \q_rdok 1'0 + assign \q_rdok $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $13 + end + process $group_2 + assign \qn_rdok 1'0 + assign \qn_rdok $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rdok 1'0 + assign \qlq_rdok $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" +module \alui_l$406 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alui + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alui + connect \Y $11 + end + process $group_1 + assign \q_alui 1'0 + assign \q_alui $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $13 + end + process $group_2 + assign \qn_alui 1'0 + assign \qn_alui $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alui 1'0 + assign \qlq_alui $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" +module \alu_l$407 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alu + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alu + connect \Y $11 + end + process $group_1 + assign \q_alu 1'0 + assign \q_alu $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $13 + end + process $group_2 + assign \qn_alu 1'0 + assign \qn_alu $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alu 1'0 + assign \qlq_alu $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0" +module \shiftrot0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_shift_rot0__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 input 2 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_shift_rot0__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 4 \oper_i_alu_shift_rot0__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 5 \oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 6 \oper_i_alu_shift_rot0__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \oper_i_alu_shift_rot0__oe__oe_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 10 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 15 \oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \oper_i_alu_shift_rot0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 input 17 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 output 18 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 19 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 20 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 21 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 22 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 23 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 24 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 25 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 26 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 27 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 28 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 29 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 30 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 31 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 32 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 33 \dest3_o + attribute \src "simple/issuer.py:102" + wire width 1 input 34 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire width 1 \alu_shift_rot0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire width 1 \alu_shift_rot0_n_ready_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_shift_rot0_sr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_shift_rot0_sr_op__insn_type$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_shift_rot0_sr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 11 \alu_shift_rot0_sr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_shift_rot0_sr_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_shift_rot0_sr_op__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__oe__oe_ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_shift_rot0_sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_shift_rot0_sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \alu_shift_rot0_sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_shift_rot0_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_shift_rot0_sr_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_shift_rot0_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_shift_rot0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_shift_rot0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_shift_rot0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_shift_rot0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_shift_rot0_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_shift_rot0_xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire width 1 \alu_shift_rot0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire width 1 \alu_shift_rot0_p_ready_o + cell \alu_shift_rot0 \alu_shift_rot0 + connect \coresync_clk \coresync_clk + connect \o_ok \o_ok + connect \cr_a_ok \cr_a_ok + connect \xer_ca_ok \xer_ca_ok + connect \coresync_rst \coresync_rst + connect \n_valid_o \alu_shift_rot0_n_valid_o + connect \n_ready_i \alu_shift_rot0_n_ready_i + connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type + connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit + connect \sr_op__imm_data__imm \alu_shift_rot0_sr_op__imm_data__imm + connect \sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm_ok + connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc + connect \sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc_ok + connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe + connect \sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe_ok + connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry + connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry + connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr + connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr + connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit + connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed + connect \sr_op__insn \alu_shift_rot0_sr_op__insn + connect \o \alu_shift_rot0_o + connect \cr_a \alu_shift_rot0_cr_a + connect \xer_ca \alu_shift_rot0_xer_ca + connect \ra \alu_shift_rot0_ra + connect \rb \alu_shift_rot0_rb + connect \rc \alu_shift_rot0_rc + connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 + connect \p_valid_i \alu_shift_rot0_p_valid_i + connect \p_ready_o \alu_shift_rot0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \src_l_q_src + cell \src_l$401 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_src \src_l_s_src + connect \r_src \src_l_r_src + connect \q_src \src_l_q_src + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \opc_l_q_opc + cell \opc_l$402 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_opc \opc_l_s_opc + connect \r_opc \opc_l_r_opc + connect \q_opc \opc_l_q_opc + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req$next + cell \req_l$403 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \s_req \req_l_s_req + connect \r_req \req_l_r_req + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst$next + cell \rst_l$404 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_rst \rst_l_s_rst + connect \r_rst \rst_l_r_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok$next + cell \rok_l$405 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \s_rdok \rok_l_s_rdok + connect \r_rdok \rok_l_r_rdok + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alui_l_s_alui + cell \alui_l$406 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_s_alu + cell \alu_l$407 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire width 1 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $5 + connect \B \cu_rd__go_i + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A $7 + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $2 + connect \B $4 + connect \Y $10 + end + process $group_0 + assign \all_rd 1'0 + assign \all_rd $10 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \all_rd_dly$next + process $group_1 + assign \all_rd_dly$next \all_rd_dly + assign \all_rd_dly$next \all_rd + sync init + update \all_rd_dly 1'0 + sync posedge \coresync_clk + update \all_rd_dly \all_rd_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \all_rd_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B $12 + connect \Y $14 + end + process $group_2 + assign \all_rd_rise 1'0 + assign \all_rd_rise $14 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire width 1 \all_rd_pulse + process $group_3 + assign \all_rd_pulse 1'0 + assign \all_rd_pulse \all_rd_rise + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire width 1 \alu_done + process $group_4 + assign \alu_done 1'0 + assign \alu_done \alu_shift_rot0_n_valid_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \alu_done_dly$next + process $group_5 + assign \alu_done_dly$next \alu_done_dly + assign \alu_done_dly$next \alu_done + sync init + update \alu_done_dly 1'0 + sync posedge \coresync_clk + update \alu_done_dly \alu_done_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B $16 + connect \Y $18 + end + process $group_6 + assign \alu_done_rise 1'0 + assign \alu_done_rise $18 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire width 1 \alu_pulse + process $group_7 + assign \alu_pulse 1'0 + assign \alu_pulse \alu_done_rise + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 3 \alu_pulsem + process $group_8 + assign \alu_pulsem 3'000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 3 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + cell $and $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $20 + end + process $group_9 + assign \prev_wr_go$next \prev_wr_go + assign \prev_wr_go$next $20 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \prev_wr_go$next 3'000 + end + sync init + update \prev_wr_go 3'000 + sync posedge \coresync_clk + update \prev_wr_go \prev_wr_go$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire width 1 \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 3 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 3 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__rel_o + connect \B $24 + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_bool $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $26 + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $23 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + wire width 1 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B $22 + connect \Y $30 + end + process $group_10 + assign \cu_done_o 1'0 + assign \cu_done_o $30 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_bool $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $32 + connect \B $34 + connect \Y $36 + end + process $group_11 + assign \wr_any 1'0 + assign \wr_any $36 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire width 1 \req_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_n_ready_i + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B $38 + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 3 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $42 + connect \B 1'0 + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $40 + connect \B $44 + connect \Y $46 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $48 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $48 + connect \B \alu_shift_rot0_n_ready_i + connect \Y $50 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $50 + connect \B \alu_shift_rot0_n_valid_o + connect \Y $52 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $52 + connect \B \cu_busy_o + connect \Y $54 + end + process $group_12 + assign \req_done 1'0 + assign \req_done $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch { $54 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + case 1'1 + assign \req_done 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire width 1 \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire width 1 \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + wire width 1 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $56 + end + process $group_13 + assign \reset 1'0 + assign \reset $56 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire width 1 \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire width 1 $58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $58 + end + process $group_14 + assign \rst_r 1'0 + assign \rst_r $58 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 3 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 3 $60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $60 + end + process $group_15 + assign \reset_w 3'000 + assign \reset_w $60 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 4 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + wire width 4 $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $62 + end + process $group_16 + assign \reset_r 4'0000 + assign \reset_r $62 + sync init + end + process $group_17 + assign \rok_l_s_rdok$next \rok_l_s_rdok + assign \rok_l_s_rdok$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_s_rdok$next 1'0 + end + sync init + update \rok_l_s_rdok 1'0 + sync posedge \coresync_clk + update \rok_l_s_rdok \rok_l_s_rdok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + wire width 1 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $65 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_n_valid_o + connect \B \cu_busy_o + connect \Y $64 + end + process $group_18 + assign \rok_l_r_rdok$next \rok_l_r_rdok + assign \rok_l_r_rdok$next $64 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rok_l_r_rdok$next 1'1 + end + sync init + update \rok_l_r_rdok 1'1 + sync posedge \coresync_clk + update \rok_l_r_rdok \rok_l_r_rdok$next + end + process $group_19 + assign \rst_l_s_rst$next \rst_l_s_rst + assign \rst_l_s_rst$next \all_rd + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_s_rst$next 1'0 + end + sync init + update \rst_l_s_rst 1'0 + sync posedge \coresync_clk + update \rst_l_s_rst \rst_l_s_rst$next + end + process $group_20 + assign \rst_l_r_rst$next \rst_l_r_rst + assign \rst_l_r_rst$next \rst_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \rst_l_r_rst$next 1'1 + end + sync init + update \rst_l_r_rst 1'1 + sync posedge \coresync_clk + update \rst_l_r_rst \rst_l_r_rst$next + end + process $group_21 + assign \opc_l_s_opc$next \opc_l_s_opc + assign \opc_l_s_opc$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_s_opc$next 1'0 + end + sync init + update \opc_l_s_opc 1'0 + sync posedge \coresync_clk + update \opc_l_s_opc \opc_l_s_opc$next + end + process $group_22 + assign \opc_l_r_opc$next \opc_l_r_opc + assign \opc_l_r_opc$next \req_done + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_r_opc$next 1'1 + end + sync init + update \opc_l_r_opc 1'1 + sync posedge \coresync_clk + update \opc_l_r_opc \opc_l_r_opc$next + end + process $group_23 + assign \src_l_s_src$next \src_l_s_src + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_s_src$next 4'0000 + end + sync init + update \src_l_s_src 4'0000 + sync posedge \coresync_clk + update \src_l_s_src \src_l_s_src$next + end + process $group_24 + assign \src_l_r_src$next \src_l_r_src + assign \src_l_r_src$next \reset_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_r_src$next 4'1111 + end + sync init + update \src_l_r_src 4'1111 + sync posedge \coresync_clk + update \src_l_r_src \src_l_r_src$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + wire width 3 $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $66 + end + process $group_25 + assign \req_l_s_req$next \req_l_s_req + assign \req_l_s_req$next $66 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_s_req$next 3'000 + end + sync init + update \req_l_s_req 3'000 + sync posedge \coresync_clk + update \req_l_s_req \req_l_s_req$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + wire width 3 $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $68 + end + process $group_26 + assign \req_l_r_req$next \req_l_r_req + assign \req_l_r_req$next $68 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \req_l_r_req$next 3'111 + end + sync init + update \req_l_r_req 3'111 + sync posedge \coresync_clk + update \req_l_r_req \req_l_r_req$next + end + process $group_27 + assign \alu_shift_rot0_sr_op__insn_type$next \alu_shift_rot0_sr_op__insn_type + assign \alu_shift_rot0_sr_op__fn_unit$next \alu_shift_rot0_sr_op__fn_unit + assign \alu_shift_rot0_sr_op__imm_data__imm$next \alu_shift_rot0_sr_op__imm_data__imm + assign \alu_shift_rot0_sr_op__imm_data__imm_ok$next \alu_shift_rot0_sr_op__imm_data__imm_ok + assign \alu_shift_rot0_sr_op__rc__rc$next \alu_shift_rot0_sr_op__rc__rc + assign \alu_shift_rot0_sr_op__rc__rc_ok$next \alu_shift_rot0_sr_op__rc__rc_ok + assign \alu_shift_rot0_sr_op__oe__oe$next \alu_shift_rot0_sr_op__oe__oe + assign \alu_shift_rot0_sr_op__oe__oe_ok$next \alu_shift_rot0_sr_op__oe__oe_ok + assign { } { } + assign \alu_shift_rot0_sr_op__input_carry$next \alu_shift_rot0_sr_op__input_carry + assign \alu_shift_rot0_sr_op__output_carry$next \alu_shift_rot0_sr_op__output_carry + assign \alu_shift_rot0_sr_op__input_cr$next \alu_shift_rot0_sr_op__input_cr + assign \alu_shift_rot0_sr_op__output_cr$next \alu_shift_rot0_sr_op__output_cr + assign \alu_shift_rot0_sr_op__is_32bit$next \alu_shift_rot0_sr_op__is_32bit + assign \alu_shift_rot0_sr_op__is_signed$next \alu_shift_rot0_sr_op__is_signed + assign \alu_shift_rot0_sr_op__insn$next \alu_shift_rot0_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + case 1'1 + assign { \alu_shift_rot0_sr_op__insn$next \alu_shift_rot0_sr_op__is_signed$next \alu_shift_rot0_sr_op__is_32bit$next \alu_shift_rot0_sr_op__output_cr$next \alu_shift_rot0_sr_op__input_cr$next \alu_shift_rot0_sr_op__output_carry$next \alu_shift_rot0_sr_op__input_carry$next { } { \alu_shift_rot0_sr_op__oe__oe_ok$next \alu_shift_rot0_sr_op__oe__oe$next } { \alu_shift_rot0_sr_op__rc__rc_ok$next \alu_shift_rot0_sr_op__rc__rc$next } { \alu_shift_rot0_sr_op__imm_data__imm_ok$next \alu_shift_rot0_sr_op__imm_data__imm$next } \alu_shift_rot0_sr_op__fn_unit$next \alu_shift_rot0_sr_op__insn_type$next } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry { } { \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_shift_rot0_sr_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_shift_rot0_sr_op__imm_data__imm_ok$next 1'0 + assign \alu_shift_rot0_sr_op__rc__rc$next 1'0 + assign \alu_shift_rot0_sr_op__rc__rc_ok$next 1'0 + assign \alu_shift_rot0_sr_op__oe__oe$next 1'0 + assign \alu_shift_rot0_sr_op__oe__oe_ok$next 1'0 + end + sync init + update \alu_shift_rot0_sr_op__insn_type 7'0000000 + update \alu_shift_rot0_sr_op__fn_unit 11'00000000000 + update \alu_shift_rot0_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \alu_shift_rot0_sr_op__imm_data__imm_ok 1'0 + update \alu_shift_rot0_sr_op__rc__rc 1'0 + update \alu_shift_rot0_sr_op__rc__rc_ok 1'0 + update \alu_shift_rot0_sr_op__oe__oe 1'0 + update \alu_shift_rot0_sr_op__oe__oe_ok 1'0 + update { } 0'0 + update \alu_shift_rot0_sr_op__input_carry 2'00 + update \alu_shift_rot0_sr_op__output_carry 1'0 + update \alu_shift_rot0_sr_op__input_cr 1'0 + update \alu_shift_rot0_sr_op__output_cr 1'0 + update \alu_shift_rot0_sr_op__is_32bit 1'0 + update \alu_shift_rot0_sr_op__is_signed 1'0 + update \alu_shift_rot0_sr_op__insn 32'00000000000000000000000000000000 + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn_type \alu_shift_rot0_sr_op__insn_type$next + update \alu_shift_rot0_sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit$next + update \alu_shift_rot0_sr_op__imm_data__imm \alu_shift_rot0_sr_op__imm_data__imm$next + update \alu_shift_rot0_sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm_ok$next + update \alu_shift_rot0_sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc$next + update \alu_shift_rot0_sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc_ok$next + update \alu_shift_rot0_sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe$next + update \alu_shift_rot0_sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe_ok$next + update { } { } + update \alu_shift_rot0_sr_op__input_carry \alu_shift_rot0_sr_op__input_carry$next + update \alu_shift_rot0_sr_op__output_carry \alu_shift_rot0_sr_op__output_carry$next + update \alu_shift_rot0_sr_op__input_cr \alu_shift_rot0_sr_op__input_cr$next + update \alu_shift_rot0_sr_op__output_cr \alu_shift_rot0_sr_op__output_cr$next + update \alu_shift_rot0_sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit$next + update \alu_shift_rot0_sr_op__is_signed \alu_shift_rot0_sr_op__is_signed$next + update \alu_shift_rot0_sr_op__insn \alu_shift_rot0_sr_op__insn$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r0__o_ok$next + process $group_43 + assign \data_r0__o$next \data_r0__o + assign \data_r0__o_ok$next \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_shift_rot0_o } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r0__o_ok$next 1'0 + end + sync init + update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0__o_ok 1'0 + sync posedge \coresync_clk + update \data_r0__o \data_r0__o$next + update \data_r0__o_ok \data_r0__o_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r1__cr_a_ok$next + process $group_45 + assign \data_r1__cr_a$next \data_r1__cr_a + assign \data_r1__cr_a_ok$next \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } { \cr_a_ok \alu_shift_rot0_cr_a } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r1__cr_a_ok$next 1'0 + end + sync init + update \data_r1__cr_a 4'0000 + update \data_r1__cr_a_ok 1'0 + sync posedge \coresync_clk + update \data_r1__cr_a \data_r1__cr_a$next + update \data_r1__cr_a_ok \data_r1__cr_a_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 1 \data_r2__xer_ca_ok$next + process $group_47 + assign \data_r2__xer_ca$next \data_r2__xer_ca + assign \data_r2__xer_ca_ok$next \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch { \alu_pulse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + case 1'1 + assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } { \xer_ca_ok \alu_shift_rot0_xer_ca } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + case 1'1 + assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } 3'000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \data_r2__xer_ca_ok$next 1'0 + end + sync init + update \data_r2__xer_ca 2'00 + update \data_r2__xer_ca_ok 1'0 + sync posedge \coresync_clk + update \data_r2__xer_ca \data_r2__xer_ca$next + update \data_r2__xer_ca_ok \data_r2__xer_ca_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $70 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + wire width 1 $74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ca_ok + connect \B \cu_busy_o + connect \Y $74 + end + process $group_49 + assign \cu_wrmask_o 3'000 + assign \cu_wrmask_o { $74 $72 $70 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + wire width 1 $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $77 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_shift_rot0_sr_op__imm_data__imm_ok + connect \Y $76 + end + process $group_50 + assign \src_sel 1'0 + assign \src_sel $76 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + wire width 64 $78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $79 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_shift_rot0_sr_op__imm_data__imm + connect \S \alu_shift_rot0_sr_op__imm_data__imm_ok + connect \Y $78 + end + process $group_51 + assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm $78 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $80 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $81 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $80 + end + process $group_52 + assign \alu_shift_rot0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_shift_rot0_ra $80 + sync init + end + process $group_53 + assign \src_r0$next \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [0] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r0$next \src1_i + end + sync init + update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r0 \src_r0$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $82 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $83 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $82 + end + process $group_54 + assign \alu_shift_rot0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_shift_rot0_rb $82 + sync init + end + process $group_55 + assign \src_r1$next \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r1$next \src_or_imm + end + sync init + update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r1 \src_r1$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $84 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $85 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $84 + end + process $group_56 + assign \alu_shift_rot0_rc 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_shift_rot0_rc $84 + sync init + end + process $group_57 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r2$next \src3_i + end + sync init + update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r2 \src_r2$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $87 + parameter \WIDTH 2 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $86 + end + process $group_58 + assign \alu_shift_rot0_xer_ca$1 2'00 + assign \alu_shift_rot0_xer_ca$1 $86 + sync init + end + process $group_59 + assign \src_r3$next \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [3] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r3$next \src4_i + end + sync init + update \src_r3 2'00 + sync posedge \coresync_clk + update \src_r3 \src_r3$next + end + process $group_60 + assign \alu_shift_rot0_p_valid_i 1'0 + assign \alu_shift_rot0_p_valid_i \alui_l_q_alui + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire width 1 $88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $88 + end + process $group_61 + assign \alui_l_r_alui$next \alui_l_r_alui + assign \alui_l_r_alui$next $88 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alui_l_r_alui$next 1'1 + end + sync init + update \alui_l_r_alui 1'1 + sync posedge \coresync_clk + update \alui_l_r_alui \alui_l_r_alui$next + end + process $group_62 + assign \alui_l_s_alui 1'0 + assign \alui_l_s_alui \all_rd_pulse + sync init + end + process $group_63 + assign \alu_shift_rot0_n_ready_i 1'0 + assign \alu_shift_rot0_n_ready_i \alu_l_q_alu + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + wire width 1 $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $90 + end + process $group_64 + assign \alu_l_r_alu$next \alu_l_r_alu + assign \alu_l_r_alu$next $90 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \alu_l_r_alu$next 1'1 + end + sync init + update \alu_l_r_alu 1'1 + sync posedge \coresync_clk + update \alu_l_r_alu \alu_l_r_alu$next + end + process $group_65 + assign \alu_l_s_alu 1'0 + assign \alu_l_s_alu \all_rd_pulse + sync init + end + process $group_66 + assign \cu_busy_o 1'0 + assign \cu_busy_o \opc_l_q_opc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $92 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + wire width 1 $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_sr_op__imm_data__imm_ok + connect \Y $94 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $92 + connect \B { 1'1 1'1 $94 1'1 } + connect \Y $96 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rdmaskn_i + connect \Y $98 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + wire width 4 $100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $96 + connect \B $98 + connect \Y $100 + end + process $group_67 + assign \cu_rd__rel_o 4'0000 + assign \cu_rd__rel_o $100 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire width 1 \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $102 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $104 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + wire width 1 $106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $106 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 $108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B { $102 $104 $106 } + connect \Y $108 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + wire width 3 $110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $108 + connect \B \cu_wrmask_o + connect \Y $110 + end + process $group_68 + assign \cu_wr__rel_o 3'000 + assign \cu_wr__rel_o $110 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_busy_o + connect \Y $112 + end + process $group_69 + assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $112 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_busy_o + connect \Y $114 + end + process $group_70 + assign \dest2_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $114 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + wire width 1 $116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + cell $and $117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [2] + connect \B \cu_busy_o + connect \Y $116 + end + process $group_71 + assign \dest3_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch { $116 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + case 1'1 + assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] + end + sync init + end + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" +module \opc_l$408 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_opc + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_opc + connect \Y $11 + end + process $group_1 + assign \q_opc 1'0 + assign \q_opc $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $13 + end + process $group_2 + assign \qn_opc 1'0 + assign \qn_opc $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_opc 1'0 + assign \qlq_opc $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" +module \src_l$409 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $3 + connect \B \s_src + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 3'000 + end + sync init + update \q_int 3'000 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $9 + connect \B \s_src + connect \Y $11 + end + process $group_1 + assign \q_src 3'000 + assign \q_src $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $13 + end + process $group_2 + assign \qn_src 3'000 + assign \qn_src $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_src 3'000 + assign \qlq_src $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" +module \alu_l$410 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alu + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alu + connect \Y $11 + end + process $group_1 + assign \q_alu 1'0 + assign \q_alu $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $13 + end + process $group_2 + assign \qn_alu 1'0 + assign \qn_alu $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alu 1'0 + assign \qlq_alu $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l" +module \adr_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_adr + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_adr + connect \Y $11 + end + process $group_1 + assign \q_adr 1'0 + assign \q_adr $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \Y $13 + end + process $group_2 + assign \qn_adr 1'0 + assign \qn_adr $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_adr 1'0 + assign \qlq_adr $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l" +module \lod_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 output 4 \qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_lod + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \q_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_lod + connect \Y $11 + end + process $group_1 + assign \q_lod 1'0 + assign \q_lod $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \Y $13 + end + process $group_2 + assign \qn_lod 1'0 + assign \qn_lod $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_lod 1'0 + assign \qlq_lod $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l" +module \sto_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_sto + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_sto + connect \Y $11 + end + process $group_1 + assign \q_sto 1'0 + assign \q_sto $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \Y $13 + end + process $group_2 + assign \qn_sto 1'0 + assign \qn_sto $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_sto 1'0 + assign \qlq_sto $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l" +module \wri_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_wri + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_wri + connect \Y $11 + end + process $group_1 + assign \q_wri 1'0 + assign \q_wri $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \Y $13 + end + process $group_2 + assign \qn_wri 1'0 + assign \qn_wri $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_wri 1'0 + assign \qlq_wri $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l" +module \upd_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_upd + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_upd + connect \Y $11 + end + process $group_1 + assign \q_upd 1'0 + assign \q_upd $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \Y $13 + end + process $group_2 + assign \qn_upd 1'0 + assign \qn_upd $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_upd 1'0 + assign \qlq_upd $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" +module \rst_l$411 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rst + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rst + connect \Y $11 + end + process $group_1 + assign \q_rst 1'0 + assign \q_rst $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $13 + end + process $group_2 + assign \qn_rst 1'0 + assign \qn_rst $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rst 1'0 + assign \qlq_rst $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l" +module \lsd_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lsd + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_lsd + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lsd + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_lsd + connect \Y $11 + end + process $group_1 + assign \q_lsd 1'0 + assign \q_lsd $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lsd + connect \Y $13 + end + process $group_2 + assign \qn_lsd 1'0 + assign \qn_lsd $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lsd + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_lsd 1'0 + assign \qlq_lsd $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0" +module \ldst0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 output 1 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 input 2 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 output 3 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 input 4 \cu_st__go_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 6 \oper_i_ldst_ldst0__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 7 \oper_i_ldst_ldst0__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 8 \oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 9 \oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 10 \oper_i_ldst_ldst0__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 11 \oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 12 \oper_i_ldst_ldst0__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 13 \oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 14 \oper_i_ldst_ldst0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 15 \oper_i_ldst_ldst0__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 16 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 input 17 \oper_i_ldst_ldst0__sign_extend + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire width 1 output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 24 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 26 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 27 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 28 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 29 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 30 \ea + attribute \src "simple/issuer.py:102" + wire width 1 input 31 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire width 1 input 32 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire width 1 output 33 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire width 1 output 34 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 35 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 output 36 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 \ldst_port0_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 37 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \ldst_port0_addr_i_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire width 1 input 38 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire width 1 input 39 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 40 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 41 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 42 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 43 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \opc_l_q_opc + cell \opc_l$408 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_opc \opc_l_s_opc + connect \r_opc \opc_l_r_opc + connect \q_opc \opc_l_q_opc + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \src_l_q_src + cell \src_l$409 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_src \src_l_s_src + connect \r_src \src_l_r_src + connect \q_src \src_l_q_src + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alu_l_q_alu + cell \alu_l$410 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_alu \alu_l_s_alu + connect \r_alu \alu_l_r_alu + connect \q_alu \alu_l_q_alu + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \adr_l_s_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \adr_l_r_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \adr_l_r_adr$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \adr_l_q_adr + cell \adr_l \adr_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_adr \adr_l_s_adr + connect \r_adr \adr_l_r_adr + connect \q_adr \adr_l_q_adr + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \lod_l_s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \lod_l_r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \lod_l_qn_lod + cell \lod_l \lod_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_lod \lod_l_s_lod + connect \r_lod \lod_l_r_lod + connect \qn_lod \lod_l_qn_lod + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \sto_l_s_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \sto_l_r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \sto_l_r_sto$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \sto_l_q_sto + cell \sto_l \sto_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_sto \sto_l_s_sto + connect \r_sto \sto_l_r_sto + connect \q_sto \sto_l_q_sto + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \wri_l_s_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \wri_l_r_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \wri_l_r_wri$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \wri_l_q_wri + cell \wri_l \wri_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_wri \wri_l_s_wri + connect \r_wri \wri_l_r_wri + connect \q_wri \wri_l_q_wri + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \upd_l_s_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \upd_l_s_upd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \upd_l_r_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \upd_l_r_upd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \upd_l_q_upd + cell \upd_l \upd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_upd \upd_l_s_upd + connect \r_upd \upd_l_r_upd + connect \q_upd \upd_l_q_upd + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \rst_l_q_rst + cell \rst_l$411 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_rst \rst_l_s_rst + connect \r_rst \rst_l_r_rst + connect \q_rst \rst_l_q_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \lsd_l_s_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \lsd_l_r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \lsd_l_r_lsd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \lsd_l_q_lsd + cell \lsd_l \lsd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_lsd \lsd_l_s_lsd + connect \r_lsd \lsd_l_r_lsd + connect \q_lsd \lsd_l_q_lsd + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" + wire width 1 \reset_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire width 1 \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" + cell $or $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $1 + end + process $group_0 + assign \reset_i 1'0 + assign \reset_i $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286" + wire width 1 \reset_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire width 1 \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" + cell $or $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_done_o + connect \B \cu_go_die_i + connect \Y $3 + end + process $group_1 + assign \reset_o 1'0 + assign \reset_o $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" + wire width 1 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_go_die_i + connect \Y $5 + end + process $group_2 + assign \reset_w 1'0 + assign \reset_w $5 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" + wire width 1 \reset_u + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" + cell $or $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_go_die_i + connect \Y $7 + end + process $group_3 + assign \reset_u 1'0 + assign \reset_u $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" + wire width 1 \reset_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" + cell $or $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__go_i + connect \B \cu_go_die_i + connect \Y $9 + end + process $group_4 + assign \reset_s 1'0 + assign \reset_s $9 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $11 + end + process $group_5 + assign \reset_r 3'000 + assign \reset_r $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" + wire width 1 \reset_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" + cell $or $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_ad__go_i + connect \B \cu_go_die_i + connect \Y $13 + end + process $group_6 + assign \reset_a 1'0 + assign \reset_a $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" + wire width 1 \p_st_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" + wire width 1 \p_st_go$next + process $group_7 + assign \p_st_go$next \p_st_go + assign \p_st_go$next \cu_st__go_i + sync init + update \p_st_go 1'0 + sync posedge \coresync_clk + update \p_st_go \p_st_go$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" + wire width 1 \op_is_st + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \oper_r__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \oper_r__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" + cell $eq $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \oper_r__insn_type + connect \B 7'0100110 + connect \Y $15 + end + process $group_8 + assign \op_is_st 1'0 + assign \op_is_st $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:265" + wire width 1 \op_is_ld + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" + cell $eq $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \oper_r__insn_type + connect \B 7'0100101 + connect \Y $17 + end + process $group_9 + assign \op_is_ld 1'0 + assign \op_is_ld $17 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" + wire width 1 \load_mem_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:311" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:311" + cell $and $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_ld + connect \B \cu_ad__go_i + connect \Y $19 + end + process $group_10 + assign \load_mem_o 1'0 + assign \load_mem_o $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" + wire width 1 \stwd_mem_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" + cell $and $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_st + connect \B \cu_st__go_i + connect \Y $21 + end + process $group_11 + assign \stwd_mem_o 1'0 + assign \stwd_mem_o $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109" + wire width 1 \ld_o + process $group_12 + assign \ld_o 1'0 + assign \ld_o \op_is_ld + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" + wire width 1 \st_o + process $group_13 + assign \st_o 1'0 + assign \st_o \op_is_st + sync init + end + process $group_14 + assign \opc_l_s_opc$next \opc_l_s_opc + assign \opc_l_s_opc$next \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_s_opc$next 1'0 + end + sync init + update \opc_l_s_opc 1'0 + sync posedge \coresync_clk + update \opc_l_s_opc \opc_l_s_opc$next + end + process $group_15 + assign \opc_l_r_opc$next \opc_l_r_opc + assign \opc_l_r_opc$next \reset_o + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \opc_l_r_opc$next 1'1 + end + sync init + update \opc_l_r_opc 1'1 + sync posedge \coresync_clk + update \opc_l_r_opc \opc_l_r_opc$next + end + process $group_16 + assign \src_l_s_src$next \src_l_s_src + assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_s_src$next 3'000 + end + sync init + update \src_l_s_src 3'000 + sync posedge \coresync_clk + update \src_l_s_src \src_l_s_src$next + end + process $group_17 + assign \src_l_r_src$next \src_l_r_src + assign \src_l_r_src$next \reset_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src_l_r_src$next 3'111 + end + sync init + update \src_l_r_src 3'111 + sync posedge \coresync_clk + update \src_l_r_src \src_l_r_src$next + end + process $group_18 + assign \alu_l_s_alu 1'0 + assign \alu_l_s_alu \reset_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" + wire width 1 \alu_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" + wire width 1 \alu_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269" + wire width 1 \alu_valid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + cell $and $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_ok + connect \B $23 + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" + wire width 1 \rda_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + cell $not $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rda_any + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" + cell $and $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $25 + connect \B $27 + connect \Y $29 + end + process $group_19 + assign \alu_l_r_alu 1'1 + assign \alu_l_r_alu $29 + sync init + end + process $group_20 + assign \adr_l_s_adr 1'0 + assign \adr_l_s_adr \reset_i + sync init + end + process $group_21 + assign \adr_l_r_adr$next \adr_l_r_adr + assign \adr_l_r_adr$next \reset_a + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \adr_l_r_adr$next 1'1 + end + sync init + update \adr_l_r_adr 1'1 + sync posedge \coresync_clk + update \adr_l_r_adr \adr_l_r_adr$next + end + process $group_22 + assign \lod_l_s_lod 1'0 + assign \lod_l_s_lod \reset_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" + wire width 1 \ld_ok + process $group_23 + assign \lod_l_r_lod 1'1 + assign \lod_l_r_lod \ld_ok + sync init + end + process $group_24 + assign \wri_l_s_wri 1'0 + assign \wri_l_s_wri \cu_issue_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" + wire width 2 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" + wire width 1 \wr_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $not $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $32 + end + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \oper_r__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \oper_r__ldst_mode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire width 1 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $and $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $32 + connect \B $34 + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $or $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B $36 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $not $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $and $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $40 + connect \B $42 + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $or $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B $44 + connect \Y $46 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" + wire width 2 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" + cell $or $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reset_w + connect \B { $38 $46 } + connect \Y $48 + end + connect $31 $48 + process $group_25 + assign \wri_l_r_wri$next \wri_l_r_wri + assign \wri_l_r_wri$next $31 [0] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wri_l_r_wri$next 1'1 + end + sync init + update \wri_l_r_wri 1'1 + sync posedge \coresync_clk + update \wri_l_r_wri \wri_l_r_wri$next + end + process $group_26 + assign \upd_l_s_upd$next \upd_l_s_upd + assign \upd_l_s_upd$next \reset_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \upd_l_s_upd$next 1'0 + end + sync init + update \upd_l_s_upd 1'0 + sync posedge \coresync_clk + update \upd_l_s_upd \upd_l_s_upd$next + end + process $group_27 + assign \upd_l_r_upd$next \upd_l_r_upd + assign \upd_l_r_upd$next \reset_u + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \upd_l_r_upd$next 1'1 + end + sync init + update \upd_l_r_upd 1'1 + sync posedge \coresync_clk + update \upd_l_r_upd \upd_l_r_upd$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" + wire width 1 \addr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" + cell $and $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_ok + connect \B \op_is_st + connect \Y $50 + end + process $group_28 + assign \sto_l_s_sto 1'0 + assign \sto_l_s_sto $50 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" + wire width 1 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" + cell $or $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $52 + end + process $group_29 + assign \sto_l_r_sto$next \sto_l_r_sto + assign \sto_l_r_sto$next $52 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \sto_l_r_sto$next 1'1 + end + sync init + update \sto_l_r_sto 1'1 + sync posedge \coresync_clk + update \sto_l_r_sto \sto_l_r_sto$next + end + process $group_30 + assign \lsd_l_s_lsd 1'0 + assign \lsd_l_s_lsd \cu_issue_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" + wire width 1 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" + cell $or $55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $54 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" + wire width 1 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" + cell $or $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $54 + connect \B \ld_ok + connect \Y $56 + end + process $group_31 + assign \lsd_l_r_lsd$next \lsd_l_r_lsd + assign \lsd_l_r_lsd$next $56 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \lsd_l_r_lsd$next 1'1 + end + sync init + update \lsd_l_r_lsd 1'1 + sync posedge \coresync_clk + update \lsd_l_r_lsd \lsd_l_r_lsd$next + end + process $group_32 + assign \rst_l_s_rst 1'0 + assign \rst_l_s_rst \addr_ok + sync init + end + process $group_33 + assign \rst_l_r_rst 1'1 + assign \rst_l_r_rst \cu_issue_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \oper_r__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \oper_r__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \oper_r__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \oper_r__data_len$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__byte_reverse$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 1 \oper_r__sign_extend$next + process $group_34 + assign \oper_r__insn_type$next \oper_r__insn_type + assign \oper_r__imm_data__imm$next \oper_r__imm_data__imm + assign \oper_r__imm_data__imm_ok$next \oper_r__imm_data__imm_ok + assign \oper_r__zero_a$next \oper_r__zero_a + assign \oper_r__rc__rc$next \oper_r__rc__rc + assign \oper_r__rc__rc_ok$next \oper_r__rc__rc_ok + assign \oper_r__oe__oe$next \oper_r__oe__oe + assign \oper_r__oe__oe_ok$next \oper_r__oe__oe_ok + assign \oper_r__is_32bit$next \oper_r__is_32bit + assign \oper_r__is_signed$next \oper_r__is_signed + assign \oper_r__data_len$next \oper_r__data_len + assign \oper_r__byte_reverse$next \oper_r__byte_reverse + assign \oper_r__sign_extend$next \oper_r__sign_extend + assign \oper_r__ldst_mode$next \oper_r__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" + case 1'1 + assign { \oper_r__ldst_mode$next \oper_r__sign_extend$next \oper_r__byte_reverse$next \oper_r__data_len$next \oper_r__is_signed$next \oper_r__is_32bit$next { \oper_r__oe__oe_ok$next \oper_r__oe__oe$next } { \oper_r__rc__rc_ok$next \oper_r__rc__rc$next } \oper_r__zero_a$next { \oper_r__imm_data__imm_ok$next \oper_r__imm_data__imm$next } \oper_r__insn_type$next } { \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm } \oper_i_ldst_ldst0__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:380" + switch { \cu_done_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:380" + case 1'1 + assign { \oper_r__ldst_mode$next \oper_r__sign_extend$next \oper_r__byte_reverse$next \oper_r__data_len$next \oper_r__is_signed$next \oper_r__is_32bit$next { \oper_r__oe__oe_ok$next \oper_r__oe__oe$next } { \oper_r__rc__rc_ok$next \oper_r__rc__rc$next } \oper_r__zero_a$next { \oper_r__imm_data__imm_ok$next \oper_r__imm_data__imm$next } \oper_r__insn_type$next } 87'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \oper_r__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_r__imm_data__imm_ok$next 1'0 + assign \oper_r__rc__rc$next 1'0 + assign \oper_r__rc__rc_ok$next 1'0 + assign \oper_r__oe__oe$next 1'0 + assign \oper_r__oe__oe_ok$next 1'0 + end + sync init + update \oper_r__insn_type 7'0000000 + update \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \oper_r__imm_data__imm_ok 1'0 + update \oper_r__zero_a 1'0 + update \oper_r__rc__rc 1'0 + update \oper_r__rc__rc_ok 1'0 + update \oper_r__oe__oe 1'0 + update \oper_r__oe__oe_ok 1'0 + update \oper_r__is_32bit 1'0 + update \oper_r__is_signed 1'0 + update \oper_r__data_len 4'0000 + update \oper_r__byte_reverse 1'0 + update \oper_r__sign_extend 1'0 + update \oper_r__ldst_mode 2'00 + sync posedge \coresync_clk + update \oper_r__insn_type \oper_r__insn_type$next + update \oper_r__imm_data__imm \oper_r__imm_data__imm$next + update \oper_r__imm_data__imm_ok \oper_r__imm_data__imm_ok$next + update \oper_r__zero_a \oper_r__zero_a$next + update \oper_r__rc__rc \oper_r__rc__rc$next + update \oper_r__rc__rc_ok \oper_r__rc__rc_ok$next + update \oper_r__oe__oe \oper_r__oe__oe$next + update \oper_r__oe__oe_ok \oper_r__oe__oe_ok$next + update \oper_r__is_32bit \oper_r__is_32bit$next + update \oper_r__is_signed \oper_r__is_signed$next + update \oper_r__data_len \oper_r__data_len$next + update \oper_r__byte_reverse \oper_r__byte_reverse$next + update \oper_r__sign_extend \oper_r__sign_extend$next + update \oper_r__ldst_mode \oper_r__ldst_mode$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" + wire width 64 \ldd_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" + wire width 64 \ldd_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ldo_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ldo_r$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $59 + parameter \WIDTH 64 + connect \A \ldo_r + connect \B \ldd_o + connect \S \ld_ok + connect \Y $58 + end + process $group_48 + assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ldd_r $58 + sync init + end + process $group_49 + assign \ldo_r$next \ldo_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \ld_ok } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \ldo_r$next \ldd_o + end + sync init + update \ldo_r 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ldo_r \ldo_r$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r0$next + process $group_50 + assign \src_r0$next \src_r0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + switch { \cu_rd__go_i [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + case 1'1 + assign \src_r0$next \src1_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + case 1'1 + assign \src_r0$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r0 \src_r0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r1$next + process $group_51 + assign \src_r1$next \src_r1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + switch { \cu_rd__go_i [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + case 1'1 + assign \src_r1$next \src2_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + case 1'1 + assign \src_r1$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r1 \src_r1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" + wire width 64 \src_r2$next + process $group_52 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + switch { \cu_rd__go_i [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + case 1'1 + assign \src_r2$next \src3_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + switch { \cu_issue_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + case 1'1 + assign \src_r2$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \src_r2 \src_r2$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" + wire width 64 \addr_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279" + wire width 64 \alu_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ea_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ea_r$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $61 + parameter \WIDTH 64 + connect \A \ea_r + connect \B \alu_o + connect \S \alu_l_q_alu + connect \Y $60 + end + process $group_53 + assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \addr_r $60 + sync init + end + process $group_54 + assign \ea_r$next \ea_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \alu_l_q_alu } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \ea_r$next \alu_o + end + sync init + update \ea_r 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ea_r \ea_r$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:404" + wire width 64 \src1_or_z + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" + wire width 64 $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" + cell $mux $63 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \oper_r__zero_a + connect \Y $62 + end + process $group_55 + assign \src1_or_z 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_or_z $62 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:409" + wire width 64 \src2_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" + wire width 64 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" + cell $mux $65 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \oper_r__imm_data__imm + connect \S \oper_r__imm_data__imm_ok + connect \Y $64 + end + process $group_56 + assign \src2_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_or_imm $64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" + wire width 65 $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" + wire width 65 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" + cell $add $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \src1_or_z + connect \B \src2_or_imm + connect \Y $67 + end + connect $66 $67 + process $group_57 + assign \alu_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_o $66 [63:0] + sync init + end + process $group_58 + assign \alu_ok$next \alu_ok + assign \alu_ok$next \alu_valid + sync init + update \alu_ok 1'0 + sync posedge \coresync_clk + update \alu_ok \alu_ok$next + end + process $group_59 + assign \cu_busy_o 1'0 + assign \cu_busy_o \opc_l_q_opc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + wire width 3 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $and $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $69 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + wire width 2 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $not $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A { \oper_r__imm_data__imm_ok \oper_r__zero_a } + connect \Y $71 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + wire width 3 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $and $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A $69 + connect \B $71 + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + wire width 3 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $not $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $75 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + wire width 3 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $and $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $73 + connect \B $75 + connect \Y $77 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" + cell $and $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \src_l_q_src [2] + connect \B \cu_busy_o + connect \Y $79 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" + cell $and $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $79 + connect \B \op_is_st + connect \Y $81 + end + process $group_60 + assign \cu_rd__rel_o 3'000 + assign \cu_rd__rel_o $77 + assign \cu_rd__rel_o [2] $81 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430" + cell $or $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__go_i [0] + connect \B \cu_rd__go_i [1] + connect \Y $83 + end + process $group_61 + assign \rda_any 1'0 + assign \rda_any $83 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + wire width 1 $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + wire width 1 $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + cell $or $87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__rel_o [0] + connect \B \cu_rd__rel_o [1] + connect \Y $86 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + cell $not $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $86 + connect \Y $85 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + cell $and $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B $85 + connect \Y $89 + end + process $group_62 + assign \alu_valid 1'0 + assign \alu_valid $89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" + wire width 1 \rd_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" + cell $not $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__rel_o [2] + connect \Y $91 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" + wire width 1 $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" + cell $and $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \B $91 + connect \Y $93 + end + process $group_63 + assign \rd_done 1'0 + assign \rd_done $93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" + wire width 1 $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" + cell $and $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_valid + connect \B \adr_l_q_adr + connect \Y $95 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" + wire width 1 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" + cell $and $98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $95 + connect \B \cu_busy_o + connect \Y $97 + end + process $group_64 + assign \cu_ad__rel_o 1'0 + assign \cu_ad__rel_o $97 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + wire width 1 $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + cell $and $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sto_l_q_sto + connect \B \cu_busy_o + connect \Y $99 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + cell $and $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $99 + connect \B \rd_done + connect \Y $101 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" + cell $and $104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $101 + connect \B \op_is_st + connect \Y $103 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire width 1 \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" + cell $and $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $103 + connect \B \cu_shadown_i + connect \Y $105 + end + process $group_65 + assign \cu_st__rel_o 1'0 + assign \cu_st__rel_o $105 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + cell $and $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd_done + connect \B \wri_l_q_wri + connect \Y $107 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + cell $and $110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $107 + connect \B \cu_busy_o + connect \Y $109 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + cell $and $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $109 + connect \B \lod_l_qn_lod + connect \Y $111 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + cell $and $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $111 + connect \B \op_is_ld + connect \Y $113 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" + cell $and $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $113 + connect \B \cu_shadown_i + connect \Y $115 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + cell $and $118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \upd_l_q_upd + connect \B \cu_busy_o + connect \Y $117 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $119 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + cell $and $122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $117 + connect \B $119 + connect \Y $121 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + wire width 1 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + cell $and $124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $121 + connect \B \alu_valid + connect \Y $123 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + wire width 1 $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" + cell $and $126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $123 + connect \B \cu_shadown_i + connect \Y $125 + end + process $group_66 + assign \cu_wr__rel_o 2'00 + assign \cu_wr__rel_o [0] $115 + assign \cu_wr__rel_o [1] $125 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" + wire width 1 \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + wire width 1 $127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + cell $or $128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__go_i + connect \B \p_st_go + connect \Y $127 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + wire width 1 $129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + cell $or $130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $127 + connect \B \cu_wr__go_i [0] + connect \Y $129 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + wire width 1 $131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + cell $or $132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $129 + connect \B \cu_wr__go_i [1] + connect \Y $131 + end + process $group_67 + assign \wr_any 1'0 + assign \wr_any $131 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire width 1 $133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $and $134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rst_l_q_rst + connect \B \cu_busy_o + connect \Y $133 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire width 1 $135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $and $136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $133 + connect \B \cu_shadown_i + connect \Y $135 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire width 1 $137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire width 1 $138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $or $139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o + connect \B \cu_wr__rel_o [0] + connect \Y $138 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire width 1 $140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $or $141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $138 + connect \B \cu_wr__rel_o [1] + connect \Y $140 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $not $142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $140 + connect \Y $137 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + wire width 1 $143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $and $144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $135 + connect \B $137 + connect \Y $143 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + wire width 1 $145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $or $146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lod_l_qn_lod + connect \B \op_is_st + connect \Y $145 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + wire width 1 $147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $and $148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $143 + connect \B $145 + connect \Y $147 + end + process $group_68 + assign \wr_reset 1'0 + assign \wr_reset $147 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + wire width 1 $149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + cell $not $150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $149 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + wire width 1 $151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + cell $or $152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $149 + connect \B \op_is_ld + connect \Y $151 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + wire width 1 $153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + cell $and $154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B $151 + connect \Y $153 + end + process $group_69 + assign \cu_done_o 1'0 + assign \cu_done_o $153 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \dest1_o + process $group_70 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o \dest1_o + sync init + end + process $group_71 + assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:471" + switch { \cu_wr__go_i [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:471" + case 1'1 + assign \dest1_o \ldd_r + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \dest2_o + process $group_72 + assign \ea 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ea \dest2_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire width 1 $155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $155 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" + wire width 1 $157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" + cell $and $158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $155 + connect \B \cu_wr__go_i [1] + connect \Y $157 + end + process $group_73 + assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" + switch { $157 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" + case 1'1 + assign \dest2_o \addr_r + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 2 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" + wire width 3 $159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + wire width 1 $160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $160 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" + wire width 3 $162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" + cell $and $163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \B { $160 \op_is_ld } + connect \Y $162 + end + connect $159 $162 + process $group_74 + assign \cu_wrmask_o 2'00 + assign \cu_wrmask_o $159 [1:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:488" + wire width 1 $164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:488" + cell $and $165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_ld + connect \B \cu_busy_o + connect \Y $164 + end + process $group_75 + assign \ldst_port0_is_ld_i 1'0 + assign \ldst_port0_is_ld_i $164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" + wire width 1 $166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" + cell $and $167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op_is_st + connect \B \cu_busy_o + connect \Y $166 + end + process $group_76 + assign \ldst_port0_is_st_i 1'0 + assign \ldst_port0_is_st_i $166 + sync init + end + process $group_77 + assign \ldst_port0_data_len 4'0000 + assign \ldst_port0_data_len \oper_r__data_len + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" + wire width 96 $168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" + cell $pos $169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 96 + connect \A \addr_r + connect \Y $168 + end + process $group_78 + assign \ldst_port0_addr_i$next \ldst_port0_addr_i + assign \ldst_port0_addr_i$next $168 + sync init + update \ldst_port0_addr_i 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \ldst_port0_addr_i \ldst_port0_addr_i$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:493" + wire width 1 $170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:493" + cell $and $171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_ok + connect \B \lsd_l_q_lsd + connect \Y $170 + end + process $group_79 + assign \ldst_port0_addr_i_ok$next \ldst_port0_addr_i_ok + assign \ldst_port0_addr_i_ok$next $170 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ldst_port0_addr_i_ok$next 1'0 + end + sync init + update \ldst_port0_addr_i_ok 1'0 + sync posedge \coresync_clk + update \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:107" + wire width 1 \addr_exc_o + process $group_80 + assign \addr_exc_o 1'0 + assign \addr_exc_o \ldst_port0_addr_exc_o + sync init + end + process $group_81 + assign \addr_ok 1'0 + assign \addr_ok \ldst_port0_addr_ok_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" + wire width 64 \lddata_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 $172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A { \ldst_port0_ld_data_o [7:0] } + connect \Y $172 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 $174 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } + connect \Y $174 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 $176 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } + connect \Y $176 + end + process $group_82 + assign \lddata_r 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + switch { \oper_r__byte_reverse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" + switch \oper_r__data_len + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" + case 4'0001 + assign \lddata_r $172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" + case 4'0010 + assign \lddata_r $174 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" + case 4'0100 + assign \lddata_r $176 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" + case 4'1000 + assign \lddata_r { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:504" + case + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498" + wire width 64 \revnorev + process $group_83 + assign \revnorev 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + switch { \oper_r__byte_reverse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + case 1'1 + assign \revnorev \lddata_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:504" + case + assign \revnorev \ldst_port0_ld_data_o + end + sync init + end + process $group_84 + assign \ldd_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:508" + switch { \oper_r__sign_extend } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:508" + case 1'1 + assign \ldd_o { { \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] } \revnorev [31:0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + case + assign \ldd_o \revnorev + end + sync init + end + process $group_85 + assign \ld_ok 1'0 + assign \ld_ok \ldst_port0_ld_data_o_ok + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" + wire width 64 \stdata_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 $178 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A { \src_r2 [7:0] } + connect \Y $178 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 $180 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A { \src_r2 [7:0] \src_r2 [15:8] } + connect \Y $180 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + wire width 64 $182 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } + connect \Y $182 + end + process $group_86 + assign \stdata_r 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:518" + switch { \oper_r__byte_reverse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:518" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" + switch \oper_r__data_len + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" + case 4'0001 + assign \stdata_r $178 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" + case 4'0010 + assign \stdata_r $180 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" + case 4'0100 + assign \stdata_r $182 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" + case 4'1000 + assign \stdata_r { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + case + end + sync init + end + process $group_87 + assign \ldst_port0_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:518" + switch { \oper_r__byte_reverse } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:518" + case 1'1 + assign \ldst_port0_st_data_i \stdata_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + case + assign \ldst_port0_st_data_i \src_r2 + end + sync init + end + process $group_88 + assign \ldst_port0_st_data_i_ok 1'0 + assign \ldst_port0_st_data_i_ok \cu_st__go_i + sync init + end + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus" +module \fus + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 output 1 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 input 2 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 output 3 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 input 4 \cu_st__go_i + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute 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\src1_i$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 168 \cu_rd__rel_o$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 169 \cu_rd__go_i$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 170 \src1_i$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 171 \cu_rd__rel_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 172 \cu_rd__go_i$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 173 \src1_i$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 174 \cu_rd__rel_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 175 \cu_rd__go_i$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 176 \src1_i$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 177 \cu_rd__rel_o$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 178 \cu_rd__go_i$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 179 \src1_i$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 180 \cu_rd__rel_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 181 \cu_rd__go_i$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 182 \src1_i$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 183 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 184 \src2_i$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 185 \src2_i$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 186 \src2_i$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 187 \src2_i$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 188 \src2_i$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 189 \src2_i$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 190 \src2_i$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 191 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 192 \src3_i$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 input 193 \src3_i$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 input 194 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 input 195 \src3_i$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 1 input 196 \src3_i$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 197 \src4_i$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 198 \src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 199 \src4_i$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 200 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 input 201 \src3_i$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 202 \src4_i$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 203 \cu_rd__rel_o$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 204 \cu_rd__go_i$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 205 \src3_i$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 206 \src5_i$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 207 \src6_i$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 208 \src1_i$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 209 \src3_i$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 210 \src3_i$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 211 \src2_i$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 212 \src4_i$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 213 \src2_i$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 214 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 215 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 216 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 217 \o_ok$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 218 \cu_wr__rel_o$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 219 \cu_wr__go_i$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 220 \o_ok$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 221 \cu_wr__rel_o$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 222 \cu_wr__go_i$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 223 \o_ok$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 224 \cu_wr__rel_o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 225 \cu_wr__go_i$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 226 \o_ok$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 227 \cu_wr__rel_o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 228 \cu_wr__go_i$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 229 \o_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 230 \cu_wr__rel_o$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 231 \cu_wr__go_i$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 232 \o_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 233 \cu_wr__rel_o$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 234 \cu_wr__go_i$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 235 \o_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 236 \cu_wr__rel_o$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 237 \cu_wr__go_i$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 238 \cu_wr__rel_o$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 239 \cu_wr__go_i$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 240 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 241 \dest1_o$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 242 \dest1_o$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 243 \dest1_o$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 244 \dest1_o$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 245 \dest1_o$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 246 \dest1_o$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 247 \dest1_o$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 248 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 249 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 250 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 output 251 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 252 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 253 \cr_a_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 254 \cr_a_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 255 \cr_a_ok$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 256 \cr_a_ok$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 257 \cr_a_ok$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 258 \dest2_o$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 259 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 260 \dest2_o$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 261 \dest2_o$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 262 \dest2_o$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 263 \dest2_o$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 264 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 265 \xer_ca_ok$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 266 \xer_ca_ok$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 267 \xer_ca_ok$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 268 \dest3_o$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 269 \dest3_o$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 270 \dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 271 \dest3_o$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 272 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 273 \xer_ov_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 274 \xer_ov_ok$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 275 \xer_ov_ok$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 276 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 277 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 278 \dest3_o$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 279 \dest3_o$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 280 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 281 \xer_so_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 282 \xer_so_ok$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 283 \xer_so_ok$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 output 284 \dest5_o$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 output 285 \dest4_o$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 output 286 \dest4_o$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 1 output 287 \dest4_o$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 288 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 289 \cu_wr__rel_o$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 290 \cu_wr__go_i$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 291 \fast1_ok$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 292 \fast1_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 293 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 294 \fast2_ok$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 295 \dest1_o$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 296 \dest2_o$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 297 \dest3_o$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 298 \dest2_o$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 299 \dest3_o$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 300 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 301 \nia_ok$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 302 \dest3_o$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 303 \dest4_o$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 304 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 305 \dest5_o$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 306 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 307 \dest2_o$150 + attribute \src "simple/issuer.py:102" + wire width 1 input 308 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire width 1 input 309 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire width 1 output 310 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire width 1 output 311 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 312 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 output 313 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 314 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire width 1 input 315 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire width 1 input 316 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 317 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 318 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 319 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 320 \ldst_port0_st_data_i_ok + cell \alu0 \alu0 + connect \coresync_clk \coresync_clk + connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__imm \oper_i_alu_alu0__imm_data__imm + connect \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm_ok + connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc_ok + connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe_ok + connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a + connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn + connect \cu_issue_i \cu_issue_i + connect \cu_busy_o \cu_busy_o + connect \cu_rdmaskn_i \cu_rdmaskn_i + connect \cu_rd__rel_o \cu_rd__rel_o + connect \cu_rd__go_i \cu_rd__go_i + connect \src1_i \src1_i + connect \src2_i \src2_i + connect \src3_i \src3_i$60 + connect \src4_i \src4_i$63 + connect \o_ok \o_ok + connect \cu_wr__rel_o \cu_wr__rel_o + connect \cu_wr__go_i \cu_wr__go_i + connect \dest1_o \dest1_o + connect \cr_a_ok \cr_a_ok + connect \dest2_o \dest2_o$113 + connect \xer_ca_ok \xer_ca_ok + connect \dest3_o \dest3_o$121 + connect \xer_ov_ok \xer_ov_ok + connect \dest4_o \dest4_o + connect \xer_so_ok \xer_so_ok + connect \dest5_o \dest5_o$132 + connect \coresync_rst \coresync_rst + end + cell \cr0 \cr0 + connect \coresync_clk \coresync_clk + connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type + connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__read_cr_whole + connect \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__write_cr_whole + connect \cu_issue_i \cu_issue_i$1 + connect \cu_busy_o \cu_busy_o$2 + connect \cu_rdmaskn_i \cu_rdmaskn_i$3 + connect \cu_rd__rel_o \cu_rd__rel_o$28 + connect \cu_rd__go_i \cu_rd__go_i$29 + connect \src1_i \src1_i$30 + connect \src2_i \src2_i$52 + connect \src3_i \src3_i$65 + connect \src4_i \src4_i$66 + connect \src5_i \src5_i$70 + connect \src6_i \src6_i$71 + connect \o_ok \o_ok$78 + connect \cu_wr__rel_o \cu_wr__rel_o$79 + connect \cu_wr__go_i \cu_wr__go_i$80 + connect \dest1_o \dest1_o$101 + connect \full_cr_ok \full_cr_ok + connect \dest2_o \dest2_o + connect \cr_a_ok \cr_a_ok$108 + connect \dest3_o \dest3_o + connect \coresync_rst \coresync_rst + end + cell \branch0 \branch0 + connect \coresync_clk \coresync_clk + connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__imm_data__imm \oper_i_alu_branch0__imm_data__imm + connect \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm_ok + connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk + connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit + connect \cu_issue_i \cu_issue_i$4 + connect \cu_busy_o \cu_busy_o$5 + connect \cu_rdmaskn_i \cu_rdmaskn_i$6 + connect \cu_rd__rel_o \cu_rd__rel_o$67 + connect \cu_rd__go_i \cu_rd__go_i$68 + connect \src3_i \src3_i$69 + connect \src1_i \src1_i$72 + connect \src2_i \src2_i$75 + connect \fast1_ok \fast1_ok + connect \cu_wr__rel_o \cu_wr__rel_o$136 + connect \cu_wr__go_i \cu_wr__go_i$137 + connect \fast2_ok \fast2_ok + connect \dest1_o \dest1_o$141 + connect \dest2_o \dest2_o$144 + connect \nia_ok \nia_ok + connect \dest3_o \dest3_o$147 + connect \coresync_rst \coresync_rst + end + cell \trap0 \trap0 + connect \coresync_clk \coresync_clk + connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype + connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr + connect \cu_issue_i \cu_issue_i$7 + connect \cu_busy_o \cu_busy_o$8 + connect \cu_rdmaskn_i \cu_rdmaskn_i$9 + connect \cu_rd__rel_o \cu_rd__rel_o$31 + connect \cu_rd__go_i \cu_rd__go_i$32 + connect \src1_i \src1_i$33 + connect \src2_i \src2_i$53 + connect \src3_i \src3_i$73 + connect \src4_i \src4_i$76 + connect \o_ok \o_ok$81 + connect \cu_wr__rel_o \cu_wr__rel_o$82 + connect \cu_wr__go_i \cu_wr__go_i$83 + connect \dest1_o \dest1_o$102 + connect \fast1_ok \fast1_ok$138 + connect \fast2_ok \fast2_ok$140 + connect \dest2_o \dest2_o$142 + connect \dest3_o \dest3_o$145 + connect \nia_ok \nia_ok$146 + connect \dest4_o \dest4_o$148 + connect \msr_ok \msr_ok + connect \dest5_o \dest5_o$149 + connect \coresync_rst \coresync_rst + end + cell \logical0 \logical0 + connect \coresync_clk \coresync_clk + connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__imm \oper_i_alu_logical0__imm_data__imm + connect \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm_ok + connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc_ok + connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe_ok + connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a + connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn + connect \cu_issue_i \cu_issue_i$10 + connect \cu_busy_o \cu_busy_o$11 + connect \cu_rdmaskn_i \cu_rdmaskn_i$12 + connect \cu_rd__rel_o \cu_rd__rel_o$34 + connect \cu_rd__go_i \cu_rd__go_i$35 + connect \src1_i \src1_i$36 + connect \src2_i \src2_i$54 + connect \o_ok \o_ok$84 + connect \cu_wr__rel_o \cu_wr__rel_o$85 + connect \cu_wr__go_i \cu_wr__go_i$86 + connect \dest1_o \dest1_o$103 + connect \cr_a_ok \cr_a_ok$109 + connect \dest2_o \dest2_o$114 + connect \xer_ca_ok \xer_ca_ok$118 + connect \dest3_o \dest3_o$122 + connect \coresync_rst \coresync_rst + end + cell \spr0 \spr0 + connect \coresync_clk \coresync_clk + connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit + connect \cu_issue_i \cu_issue_i$13 + connect \cu_busy_o \cu_busy_o$14 + connect \cu_rdmaskn_i \cu_rdmaskn_i$15 + connect \cu_rd__rel_o \cu_rd__rel_o$37 + connect \cu_rd__go_i \cu_rd__go_i$38 + connect \src1_i \src1_i$39 + connect \src4_i \src4_i + connect \src6_i \src6_i + connect \src5_i \src5_i + connect \src3_i \src3_i$74 + connect \src2_i \src2_i$77 + connect \o_ok \o_ok$87 + connect \cu_wr__rel_o \cu_wr__rel_o$88 + connect \cu_wr__go_i \cu_wr__go_i$89 + connect \dest1_o \dest1_o$104 + connect \xer_ca_ok \xer_ca_ok$119 + connect \dest6_o \dest6_o + connect \xer_ov_ok \xer_ov_ok$124 + connect \dest5_o \dest5_o + connect \xer_so_ok \xer_so_ok$129 + connect \dest4_o \dest4_o$133 + connect \fast1_ok \fast1_ok$139 + connect \dest3_o \dest3_o$143 + connect \spr1_ok \spr1_ok + connect \dest2_o \dest2_o$150 + connect \coresync_rst \coresync_rst + end + cell \div0 \div0 + connect \coresync_clk \coresync_clk + connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__imm \oper_i_alu_div0__imm_data__imm + connect \oper_i_alu_div0__imm_data__imm_ok \oper_i_alu_div0__imm_data__imm_ok + connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__rc__rc_ok \oper_i_alu_div0__rc__rc_ok + connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__oe_ok \oper_i_alu_div0__oe__oe_ok + connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a + connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len + connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn + connect \cu_issue_i \cu_issue_i$16 + connect \cu_busy_o \cu_busy_o$17 + connect \cu_rdmaskn_i \cu_rdmaskn_i$18 + connect \cu_rd__rel_o \cu_rd__rel_o$40 + connect \cu_rd__go_i \cu_rd__go_i$41 + connect \src1_i \src1_i$42 + connect \src2_i \src2_i$55 + connect \src3_i \src3_i$61 + connect \o_ok \o_ok$90 + connect \cu_wr__rel_o \cu_wr__rel_o$91 + connect \cu_wr__go_i \cu_wr__go_i$92 + connect \dest1_o \dest1_o$105 + connect \cr_a_ok \cr_a_ok$110 + connect \dest2_o \dest2_o$115 + connect \xer_ov_ok \xer_ov_ok$125 + connect \dest3_o \dest3_o$127 + connect \xer_so_ok \xer_so_ok$130 + connect \dest4_o \dest4_o$134 + connect \coresync_rst \coresync_rst + end + cell \mul0 \mul0 + connect \coresync_clk \coresync_clk + connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__imm \oper_i_alu_mul0__imm_data__imm + connect \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm_ok + connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc_ok + connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe_ok + connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 + connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn + connect \cu_issue_i \cu_issue_i$19 + connect \cu_busy_o \cu_busy_o$20 + connect \cu_rdmaskn_i \cu_rdmaskn_i$21 + connect \cu_rd__rel_o \cu_rd__rel_o$43 + connect \cu_rd__go_i \cu_rd__go_i$44 + connect \src1_i \src1_i$45 + connect \src2_i \src2_i$56 + connect \src3_i \src3_i$62 + connect \o_ok \o_ok$93 + connect \cu_wr__rel_o \cu_wr__rel_o$94 + connect \cu_wr__go_i \cu_wr__go_i$95 + connect \dest1_o \dest1_o$106 + connect \cr_a_ok \cr_a_ok$111 + connect \dest2_o \dest2_o$116 + connect \xer_ov_ok \xer_ov_ok$126 + connect \dest3_o \dest3_o$128 + connect \xer_so_ok \xer_so_ok$131 + connect \dest4_o \dest4_o$135 + connect \coresync_rst \coresync_rst + end + cell \shiftrot0 \shiftrot0 + connect \coresync_clk \coresync_clk + connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__imm \oper_i_alu_shift_rot0__imm_data__imm + connect \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm_ok + connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc_ok + connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe_ok + connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn + connect \cu_issue_i \cu_issue_i$22 + connect \cu_busy_o \cu_busy_o$23 + connect \cu_rdmaskn_i \cu_rdmaskn_i$24 + connect \cu_rd__rel_o \cu_rd__rel_o$46 + connect \cu_rd__go_i \cu_rd__go_i$47 + connect \src1_i \src1_i$48 + connect \src2_i \src2_i$57 + connect \src3_i \src3_i + connect \src4_i \src4_i$64 + connect \o_ok \o_ok$96 + connect \cu_wr__rel_o \cu_wr__rel_o$97 + connect \cu_wr__go_i \cu_wr__go_i$98 + connect \dest1_o \dest1_o$107 + connect \cr_a_ok \cr_a_ok$112 + connect \dest2_o \dest2_o$117 + connect \xer_ca_ok \xer_ca_ok$120 + connect \dest3_o \dest3_o$123 + connect \coresync_rst \coresync_rst + end + cell \ldst0 \ldst0 + connect \coresync_clk \coresync_clk + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_st__go_i \cu_st__go_i + connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__imm_data__imm \oper_i_ldst_ldst0__imm_data__imm + connect \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm_ok + connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a + connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc_ok + connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe_ok + connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode + connect \cu_issue_i \cu_issue_i$25 + connect \cu_busy_o \cu_busy_o$26 + connect \cu_rdmaskn_i \cu_rdmaskn_i$27 + connect \cu_rd__rel_o \cu_rd__rel_o$49 + connect \cu_rd__go_i \cu_rd__go_i$50 + connect \src1_i \src1_i$51 + connect \src2_i \src2_i$58 + connect \src3_i \src3_i$59 + connect \cu_wr__rel_o \cu_wr__rel_o$99 + connect \cu_wr__go_i \cu_wr__go_i$100 + connect \o \o + connect \ea \ea + connect \coresync_rst \coresync_rst + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active" +module \st_active + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 2 \r_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_active + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_st_active + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_active + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_st_active + connect \Y $11 + end + process $group_1 + assign \q_st_active 1'0 + assign \q_st_active $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \Y $13 + end + process $group_2 + assign \qn_st_active 1'0 + assign \qn_st_active $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_st_active 1'0 + assign \qlq_st_active $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_done" +module \st_done + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_done + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_st_done + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_done + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_st_done + connect \Y $11 + end + process $group_1 + assign \q_st_done 1'0 + assign \q_st_done $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_done + connect \Y $13 + end + process $group_2 + assign \qn_st_done 1'0 + assign \qn_st_done $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_done + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_st_done 1'0 + assign \qlq_st_done $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active" +module \ld_active + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 2 \r_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_ld_active + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_ld_active + connect \Y $11 + end + process $group_1 + assign \q_ld_active 1'0 + assign \q_ld_active $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \Y $13 + end + process $group_2 + assign \qn_ld_active 1'0 + assign \qn_ld_active $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_ld_active 1'0 + assign \qlq_ld_active $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l" +module \reset_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_reset + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + process $group_1 + assign \q_reset 1'0 + assign \q_reset \q_int + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $7 + end + process $group_2 + assign \qn_reset 1'0 + assign \qn_reset $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $9 + end + process $group_3 + assign \qlq_reset 1'0 + assign \qlq_reset $9 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l" +module \adrok_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 output 4 \qn_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 5 \q_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_addr_acked + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_addr_acked + connect \Y $11 + end + process $group_1 + assign \q_addr_acked 1'0 + assign \q_addr_acked $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \Y $13 + end + process $group_2 + assign \qn_addr_acked 1'0 + assign \qn_addr_acked $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_addr_acked 1'0 + assign \qlq_addr_acked $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l" +module \busy_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_busy + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_busy + connect \Y $11 + end + process $group_1 + assign \q_busy 1'0 + assign \q_busy $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \Y $13 + end + process $group_2 + assign \qn_busy 1'0 + assign \qn_busy $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_busy 1'0 + assign \qlq_busy $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l" +module \cyc_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_cyc + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_cyc + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + process $group_1 + assign \q_cyc 1'0 + assign \q_cyc \q_int + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \Y $7 + end + process $group_2 + assign \qn_cyc 1'0 + assign \qn_cyc $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \B \q_int + connect \Y $9 + end + process $group_3 + assign \qlq_cyc 1'0 + assign \qlq_cyc $9 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp" +module \lenexp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" + wire width 4 input 0 \len_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" + wire width 4 input 1 \addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" + wire width 64 output 2 \lexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" + wire width 176 output 3 \rexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" + wire width 17 \binlen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 20 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sshl $3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 20 + connect \A 5'00001 + connect \B \len_i + connect \Y $2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sub $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 21 + connect \A $2 + connect \B 1'1 + connect \Y $4 + end + connect $1 $4 + process $group_0 + assign \binlen 17'00000000000000000 + assign \binlen $1 [16:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 64 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 32 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $sshl $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 17 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 32 + connect \A \binlen + connect \B \addr_i + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A $7 + connect \Y $6 + end + process $group_1 + assign \lexp_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \lexp_o $6 + sync init + end + process $group_2 + assign \rexp_o 176'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \rexp_o { { \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] } { \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] } { \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] } { \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] } { \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] } { \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] } { \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] } { \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] } { \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] } { \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] } { \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] } { \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] } { \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] } { \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] } { \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] } { \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] } { \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] } { \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] } { \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] } { \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] } { \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] } { \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] } { \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] } { \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] } { \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] } { \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] } { \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] } { \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] } { \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] } { \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] } { \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] } { \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] } { \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] } { \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] } { \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] } { \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] } { \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] } { \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] } { \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] } { \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] } { \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] } { \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] } { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] } { \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] } { \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] } { \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] } { \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] } { \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] } { \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] } { \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] } { \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] } { \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] } { \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] } { \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] } { \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] } { \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] } { \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] } { \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] } { \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] } { \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] } { \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] } { \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] } { \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] } { \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } } [175:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l" +module \valid_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 3 \q_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 4 \r_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_valid + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_valid + connect \Y $11 + end + process $group_1 + assign \q_valid 1'0 + assign \q_valid $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \Y $13 + end + process $group_2 + assign \qn_valid 1'0 + assign \qn_valid $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_valid 1'0 + assign \qlq_valid $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem" +module \pimem + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire width 1 input 2 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire width 1 input 3 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire width 1 output 4 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 48 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + wire width 8 output 8 \x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + wire width 48 output 9 \x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire width 1 output 10 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + wire width 64 input 11 \m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 12 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 13 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 14 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 15 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + wire width 64 output 16 \x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + wire width 1 input 17 \x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire width 1 input 18 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + wire width 1 output 19 \x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + wire width 1 output 20 \x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire width 1 output 21 \m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire width 1 output 22 \x_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \st_active_r_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \st_active_s_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \st_active_q_st_active + cell \st_active \st_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_st_active \st_active_r_st_active + connect \s_st_active \st_active_s_st_active + connect \q_st_active \st_active_q_st_active + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \st_done_s_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \st_done_s_st_done$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \st_done_r_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \st_done_q_st_done + cell \st_done \st_done + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_st_done \st_done_s_st_done + connect \r_st_done \st_done_r_st_done + connect \q_st_done \st_done_q_st_done + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \ld_active_r_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \ld_active_s_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \ld_active_q_ld_active + cell \ld_active \ld_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_ld_active \ld_active_r_ld_active + connect \s_ld_active \ld_active_s_ld_active + connect \q_ld_active \ld_active_q_ld_active + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \reset_l_q_reset + cell \reset_l \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_reset \reset_l_s_reset + connect \r_reset \reset_l_r_reset + connect \q_reset \reset_l_q_reset + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \adrok_l_s_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \adrok_l_s_addr_acked$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \adrok_l_r_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \adrok_l_qn_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \adrok_l_q_addr_acked + cell \adrok_l \adrok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_addr_acked \adrok_l_s_addr_acked + connect \r_addr_acked \adrok_l_r_addr_acked + connect \qn_addr_acked \adrok_l_qn_addr_acked + connect \q_addr_acked \adrok_l_q_addr_acked + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \busy_l_s_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \busy_l_r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \busy_l_q_busy + cell \busy_l \busy_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_busy \busy_l_s_busy + connect \r_busy \busy_l_r_busy + connect \q_busy \busy_l_q_busy + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \cyc_l_s_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \cyc_l_r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \cyc_l_q_cyc + cell \cyc_l \cyc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_cyc \cyc_l_s_cyc + connect \r_cyc \cyc_l_r_cyc + connect \q_cyc \cyc_l_q_cyc + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" + wire width 4 \lenexp_len_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" + wire width 4 \lenexp_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" + wire width 64 \lenexp_lexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" + wire width 176 \lenexp_rexp_o + cell \lenexp \lenexp + connect \len_i \lenexp_len_i + connect \addr_i \lenexp_addr_i + connect \lexp_o \lenexp_lexp_o + connect \rexp_o \lenexp_rexp_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \valid_l_s_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \valid_l_q_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \valid_l_r_valid + cell \valid_l \valid_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_valid \valid_l_s_valid + connect \q_valid \valid_l_q_valid + connect \r_valid \valid_l_r_valid + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $1 + end + process $group_0 + assign \st_done_s_st_done$next \st_done_s_st_done + assign \st_done_s_st_done$next 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + case 1'1 + assign \st_done_s_st_done$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \st_done_s_st_done$next 1'0 + end + sync init + update \st_done_s_st_done 1'0 + sync posedge \coresync_clk + update \st_done_s_st_done \st_done_s_st_done$next + end + process $group_1 + assign \st_done_r_st_done 1'1 + assign \st_done_r_st_done 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + switch { \reset_l_q_reset } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + case 1'1 + assign \st_done_r_st_done 1'1 + end + sync init + end + process $group_2 + assign \st_active_r_st_active 1'1 + assign \st_active_r_st_active 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + switch { \reset_l_q_reset } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + case 1'1 + assign \st_active_r_st_active 1'1 + end + sync init + end + process $group_3 + assign \ld_active_r_ld_active 1'1 + assign \ld_active_r_ld_active 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + switch { \reset_l_q_reset } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + case 1'1 + assign \ld_active_r_ld_active 1'1 + end + sync init + end + process $group_4 + assign \cyc_l_s_cyc 1'0 + assign \cyc_l_s_cyc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" + switch { \reset_l_s_reset } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" + case 1'1 + assign \cyc_l_s_cyc 1'1 + end + sync init + end + process $group_5 + assign \cyc_l_r_cyc 1'1 + assign \cyc_l_r_cyc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:285" + switch { \cyc_l_q_cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:285" + case 1'1 + assign \cyc_l_r_cyc 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" + cell $or $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196" + wire width 1 \busy_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196" + wire width 1 \busy_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $5 + end + process $group_6 + assign \busy_l_s_busy 1'0 + assign \busy_l_s_busy 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" + case 1'1 + assign \busy_l_s_busy $5 + end + sync init + end + process $group_7 + assign \busy_l_r_busy 1'1 + assign \busy_l_r_busy 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:277" + switch { \ldst_port0_addr_exc_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:277" + case 1'1 + assign \busy_l_r_busy 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:285" + switch { \cyc_l_q_cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:285" + case 1'1 + assign \busy_l_r_busy 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $7 + end + process $group_8 + assign \adrok_l_s_addr_acked$next \adrok_l_s_addr_acked + assign \adrok_l_s_addr_acked$next 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + switch { \ld_active_q_ld_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + case 1'1 + assign \adrok_l_s_addr_acked$next 1'1 + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch { \st_active_q_st_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch { \ldst_port0_addr_i_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:230" + switch { \adrok_l_qn_addr_acked } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:230" + case 1'1 + assign \adrok_l_s_addr_acked$next 1'1 + end + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \adrok_l_s_addr_acked$next 1'0 + end + sync init + update \adrok_l_s_addr_acked 1'0 + sync posedge \coresync_clk + update \adrok_l_s_addr_acked \adrok_l_s_addr_acked$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" + wire width 1 \reset_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" + wire width 1 \reset_delay$next + process $group_9 + assign \adrok_l_r_addr_acked 1'1 + assign \adrok_l_r_addr_acked 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:265" + switch { \reset_delay } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:265" + case 1'1 + assign \adrok_l_r_addr_acked 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + switch { \reset_l_q_reset } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + case 1'1 + assign \adrok_l_r_addr_acked 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:189" + wire width 1 \lds + process $group_10 + assign \lds 1'0 + assign \lds \ldst_port0_is_ld_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190" + wire width 1 \sts + process $group_11 + assign \sts 1'0 + assign \sts \ldst_port0_is_st_i + sync init + end + process $group_12 + assign \busy_delay$next \busy_delay + assign \busy_delay$next \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \busy_delay$next 1'0 + end + sync init + update \busy_delay 1'0 + sync posedge \coresync_clk + update \busy_delay \busy_delay$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:197" + wire width 1 \busy_edge + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:199" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:199" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:199" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:199" + cell $and $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \B $9 + connect \Y $11 + end + process $group_13 + assign \busy_edge 1'0 + assign \busy_edge $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \lds_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \lds_dly$next + process $group_14 + assign \lds_dly$next \lds_dly + assign \lds_dly$next \lds + sync init + update \lds_dly 1'0 + sync posedge \coresync_clk + update \lds_dly \lds_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \lds_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds_dly + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds + connect \B $13 + connect \Y $15 + end + process $group_15 + assign \lds_rise 1'0 + assign \lds_rise $15 + sync init + end + process $group_16 + assign \ld_active_s_ld_active 1'0 + assign \ld_active_s_ld_active \lds_rise + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \sts_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \sts_dly$next + process $group_17 + assign \sts_dly$next \sts_dly + assign \sts_dly$next \sts + sync init + update \sts_dly 1'0 + sync posedge \coresync_clk + update \sts_dly \sts_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \sts_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts_dly + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts + connect \B $17 + connect \Y $19 + end + process $group_18 + assign \sts_rise 1'0 + assign \sts_rise $19 + sync init + end + process $group_19 + assign \st_active_s_st_active 1'0 + assign \st_active_s_st_active \sts_rise + sync init + end + process $group_20 + assign \lenexp_len_i 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + switch { \ld_active_q_ld_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + case 1'1 + assign \lenexp_len_i \ldst_port0_data_len + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch { \st_active_q_st_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + case 1'1 + assign \lenexp_len_i \ldst_port0_data_len + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 4 $21 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \ldst_port0_addr_i [2:0] + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + wire width 4 $23 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \ldst_port0_addr_i [2:0] + connect \Y $23 + end + process $group_21 + assign \lenexp_addr_i 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + switch { \ld_active_q_ld_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + case 1'1 + assign \lenexp_addr_i $21 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch { \st_active_q_st_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + case 1'1 + assign \lenexp_addr_i $23 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $and $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $25 + end + process $group_22 + assign \valid_l_s_valid 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + switch { \ld_active_q_ld_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + case 1'1 + assign \valid_l_s_valid 1'1 + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch { \st_active_q_st_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch { \ldst_port0_addr_i_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + case 1'1 + assign \valid_l_s_valid 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $and $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $27 + end + process $group_23 + assign \x_mask_i 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + switch { \ld_active_q_ld_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + switch { $27 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + case 1'1 + assign \x_mask_i \lenexp_lexp_o [7:0] + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch { \st_active_q_st_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch { \ldst_port0_addr_i_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + case 1'1 + assign \x_mask_i \lenexp_lexp_o [7:0] + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $and $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $29 + end + process $group_24 + assign \x_addr_i 48'000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + switch { \ld_active_q_ld_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + switch { $29 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + case 1'1 + assign \x_addr_i \ldst_port0_addr_i + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch { \st_active_q_st_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch { \ldst_port0_addr_i_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + case 1'1 + assign \x_addr_i \ldst_port0_addr_i + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $and $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $31 + end + process $group_25 + assign \ldst_port0_addr_ok_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + switch { \ld_active_q_ld_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + switch { $31 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + case 1'1 + assign \ldst_port0_addr_ok_o 1'1 + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch { \st_active_q_st_active } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch { \ldst_port0_addr_i_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:230" + switch { \adrok_l_qn_addr_acked } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:230" + case 1'1 + assign \ldst_port0_addr_ok_o 1'1 + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + cell $and $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" + wire width 1 \lsui_busy + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + wire width 1 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $or $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \B \lsui_busy + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $not $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $38 + connect \Y $37 + end + process $group_26 + assign \reset_l_s_reset 1'0 + assign \reset_l_s_reset 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + switch { $33 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + case 1'1 + assign \reset_l_s_reset $35 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch { \st_done_q_st_done } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + case 1'1 + assign \reset_l_s_reset $37 + end + sync init + end + process $group_27 + assign \reset_l_r_reset 1'1 + assign \reset_l_r_reset 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + switch { \reset_l_q_reset } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" + case 1'1 + assign \reset_l_r_reset 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:238" + wire width 64 \lddata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:241" + wire width 176 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + wire width 176 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + cell $and $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 176 + parameter \Y_WIDTH 176 + connect \A \m_ld_data_o + connect \B \lenexp_rexp_o + connect \Y $42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:241" + wire width 8 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:241" + cell $mul $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:241" + wire width 176 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:241" + cell $sshr $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 176 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 176 + connect \A $42 + connect \B $44 + connect \Y $46 + end + connect $41 $46 + process $group_28 + assign \lddata 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \lddata $41 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + wire width 1 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + cell $and $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $48 + end + process $group_29 + assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + switch { $48 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + case 1'1 + assign \ldst_port0_ld_data_o \lddata + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + cell $and $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $50 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + wire width 1 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $52 + end + process $group_30 + assign \ldst_port0_ld_data_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + switch { $50 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" + case 1'1 + assign \ldst_port0_ld_data_o_ok $52 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253" + wire width 64 \stdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + wire width 1 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + cell $and $55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $54 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:254" + wire width 319 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:254" + wire width 8 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:254" + cell $mul $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $57 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:254" + wire width 319 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:254" + cell $sshl $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 319 + connect \A \ldst_port0_st_data_i + connect \B $57 + connect \Y $59 + end + connect $56 $59 + process $group_31 + assign \stdata 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + switch { $54 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + case 1'1 + assign \stdata $56 [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + cell $and $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $61 + end + process $group_32 + assign \x_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + switch { $61 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" + case 1'1 + assign \x_st_data_i \stdata + end + sync init + end + process $group_33 + assign \reset_delay$next \reset_delay + assign \reset_delay$next \reset_l_q_reset + sync init + update \reset_delay 1'0 + sync posedge \coresync_clk + update \reset_delay \reset_delay$next + end + process $group_34 + assign \ldst_port0_busy_o 1'0 + assign \ldst_port0_busy_o \busy_l_q_busy + sync init + end + process $group_35 + assign \x_ld_i 1'0 + assign \x_ld_i \ldst_port0_is_ld_i + sync init + end + process $group_36 + assign \x_st_i 1'0 + assign \x_st_i \ldst_port0_is_st_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + wire width 2 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $63 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $and $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $63 + connect \B \valid_l_q_valid + connect \Y $65 + end + process $group_37 + assign \lsui_busy 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" + attribute \nmigen.decoding "IDLE/0" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch { $65 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + case 1'1 + assign \lsui_busy 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:91" + attribute \nmigen.decoding "BUSY/1" + case 2'01 + assign \lsui_busy 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97" + attribute \nmigen.decoding "WAITDEASSERT/2" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $67 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $and $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $67 + connect \B \valid_l_q_valid + connect \Y $69 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + cell $not $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $71 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_st_i + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $75 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $and $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $73 + connect \B $75 + connect \Y $77 + end + process $group_38 + assign \fsm_state$next \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" + attribute \nmigen.decoding "IDLE/0" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch { $69 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + case 1'1 + assign \fsm_state$next 2'01 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:91" + attribute \nmigen.decoding "BUSY/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + switch { $71 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + case 1'1 + assign \fsm_state$next 2'10 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97" + attribute \nmigen.decoding "WAITDEASSERT/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + switch { $77 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + case 1'1 + assign \fsm_state$next 2'00 + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \fsm_state$next 2'00 + end + sync init + update \fsm_state 2'00 + sync posedge \coresync_clk + update \fsm_state \fsm_state$next + end + process $group_39 + assign \m_valid_i 1'0 + assign \m_valid_i \valid_l_q_valid + sync init + end + process $group_40 + assign \x_valid_i 1'0 + assign \x_valid_i \valid_l_q_valid + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:107" + wire width 1 \lsui_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" + cell $not $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $79 + end + process $group_41 + assign \lsui_active 1'0 + assign \lsui_active $79 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \lsui_active_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \lsui_active_dly$next + process $group_42 + assign \lsui_active_dly$next \lsui_active_dly + assign \lsui_active_dly$next \lsui_active + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \lsui_active_dly$next 1'0 + end + sync init + update \lsui_active_dly 1'0 + sync posedge \coresync_clk + update \lsui_active_dly \lsui_active_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \lsui_active_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active_dly + connect \Y $81 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active + connect \B $81 + connect \Y $83 + end + process $group_43 + assign \lsui_active_rise 1'0 + assign \lsui_active_rise $83 + sync init + end + process $group_44 + assign \valid_l_r_valid 1'1 + assign \valid_l_r_valid \lsui_active_rise + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l" +module \idx_l + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 4 \r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_idx_l + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_idx_l + connect \Y $11 + end + process $group_1 + assign \q_idx_l 1'0 + assign \q_idx_l $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \Y $13 + end + process $group_2 + assign \qn_idx_l 1'0 + assign \qn_idx_l $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_idx_l 1'0 + assign \qlq_idx_l $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" +module \reset_l$413 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_reset + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \coresync_clk + update \q_int \q_int$next + end + process $group_1 + assign \q_reset 1'0 + assign \q_reset \q_int + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $7 + end + process $group_2 + assign \qn_reset 1'0 + assign \qn_reset $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $9 + end + process $group_3 + assign \qlq_reset 1'0 + assign \qlq_reset $9 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.l0.pick" +module \pick + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 1 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 2 \n + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.l0" +module \l0$412 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire width 1 output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire width 1 input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire width 1 input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire width 1 output 8 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire width 1 output 9 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 10 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 11 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 12 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 13 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire width 1 output 14 \ldst_port0_is_ld_i$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire width 1 output 15 \ldst_port0_is_st_i$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire width 1 input 16 \ldst_port0_busy_o$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 17 \ldst_port0_data_len$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 48 output 18 \ldst_port0_addr_i$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 19 \ldst_port0_addr_i_ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire width 1 input 20 \ldst_port0_addr_ok_o$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 21 \ldst_port0_ld_data_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 22 \ldst_port0_ld_data_o_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 23 \ldst_port0_st_data_i_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \ldst_port0_st_data_i$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire width 1 input 25 \ldst_port0_addr_exc_o$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \idx_l_s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \idx_l_r_idx_l + cell \idx_l \idx_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_idx_l \idx_l_q_idx_l + connect \s_idx_l \idx_l_s_idx_l + connect \r_idx_l \idx_l_r_idx_l + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \reset_l_q_reset + cell \reset_l$413 \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \s_reset \reset_l_s_reset + connect \r_reset \reset_l_r_reset + connect \q_reset \reset_l_q_reset + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 1 \pick_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pick_o + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pick_n + cell \pick \pick + connect \i \pick_i + connect \o \pick_o + connect \n \pick_n + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + cell $or $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $13 + end + process $group_0 + assign \pick_i 1'0 + assign \pick_i { $13 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \idx_l$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \idx_l$16$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $18 + parameter \WIDTH 1 + connect \A \idx_l$16 + connect \B \pick_o + connect \S \idx_l_q_idx_l + connect \Y $17 + end + connect $15 $17 + process $group_1 + assign { } 0'0 + assign { } {} + sync init + end + process $group_2 + assign \idx_l$16$next \idx_l$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \idx_l$16$next \pick_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \idx_l$16$next 1'0 + end + sync init + update \idx_l$16 1'0 + sync posedge \coresync_clk + update \idx_l$16 \idx_l$16$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + cell $not $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pick_n + connect \Y $19 + end + process $group_3 + assign \idx_l_s_idx_l 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + switch { $19 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + case 1'1 + assign \idx_l_s_idx_l 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o$3 + connect \Y $21 + end + process $group_4 + assign \reset_l_s_reset 1'0 + assign \reset_l_s_reset 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + switch { $21 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + case 1'1 + assign \reset_l_s_reset 1'1 + end + end + sync init + end + process $group_5 + assign \reset_l_r_reset 1'1 + assign \reset_l_r_reset 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch { \reset_l_q_reset } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + case 1'1 + assign \reset_l_r_reset 1'1 + end + sync init + end + process $group_6 + assign \ldst_port0_is_ld_i$1 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118" + switch { } + case 0' + assign \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i + end + end + sync init + end + process $group_7 + assign \ldst_port0_is_st_i$2 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" + switch { } + case 0' + assign \ldst_port0_is_st_i$2 \ldst_port0_is_st_i + end + end + sync init + end + process $group_8 + assign \ldst_port0_data_len$4 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" + switch { } + case 0' + assign \ldst_port0_data_len$4 \ldst_port0_data_len + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire width 1 \ldst_port0_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire width 1 \ldst_port0_go_die_i$23 + process $group_9 + assign \ldst_port0_go_die_i 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:121" + switch { } + case 0' + assign \ldst_port0_go_die_i \ldst_port0_go_die_i$23 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122" + wire width 96 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122" + wire width 96 $25 + connect $25 \ldst_port0_addr_i + process $group_10 + assign \ldst_port0_addr_i$5 48'000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122" + switch { } + case 0' + assign \ldst_port0_addr_i$5 $25 [47:0] + end + end + sync init + end + process $group_11 + assign \ldst_port0_addr_i_ok$6 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + switch { } + case 0' + assign \ldst_port0_addr_i_ok$6 \ldst_port0_addr_i_ok + end + end + sync init + end + process $group_12 + assign \ldst_port0_st_data_i$11 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ldst_port0_st_data_i_ok$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:124" + switch { } + case 0' + assign { \ldst_port0_st_data_i_ok$10 \ldst_port0_st_data_i$11 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + end + end + sync init + end + process $group_14 + assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ldst_port0_ld_data_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:125" + switch { } + case 0' + assign { \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o } { \ldst_port0_ld_data_o_ok$9 \ldst_port0_ld_data_o$8 } + end + end + sync init + end + process $group_16 + assign \ldst_port0_busy_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + switch { } + case 0' + assign \ldst_port0_busy_o \ldst_port0_busy_o$3 + end + end + sync init + end + process $group_17 + assign \ldst_port0_addr_ok_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:127" + switch { } + case 0' + assign \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$7 + end + end + sync init + end + process $group_18 + assign \ldst_port0_addr_exc_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch { \idx_l_q_idx_l } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + switch { } + case 0' + assign \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$12 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire width 1 \reset_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire width 1 \reset_delay$next + process $group_19 + assign \reset_delay$next \reset_delay + assign \reset_delay$next \reset_l_q_reset + sync init + update \reset_delay 1'0 + sync posedge \coresync_clk + update \reset_delay \reset_delay$next + end + process $group_20 + assign \idx_l_r_idx_l 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch { \reset_l_q_reset } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + case 1'1 + assign \idx_l_r_idx_l 1'1 + end + sync init + end + connect \ldst_port0_go_die_i$23 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem" +module \lsmem + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + wire width 8 input 2 \x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + wire width 48 input 3 \x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + wire width 64 output 4 \m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + wire width 64 \m_ld_data_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + wire width 64 input 5 \x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + wire width 1 output 6 \x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + wire width 1 input 7 \x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + wire width 1 input 8 \x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire width 1 input 9 \m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire width 1 input 10 \x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 11 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 \dbus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 input 12 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 input 13 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 14 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 \dbus__stb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 15 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 \dbus__sel$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 16 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 17 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 \dbus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 18 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 \dbus__we$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 19 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 \dbus__dat_w$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B \x_valid_i + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:49" + wire width 1 \x_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B $5 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B $11 + connect \Y $13 + end + process $group_0 + assign \dbus__cyc$next \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { $7 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + case 1'1 + assign \dbus__cyc$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + case 2'1- + assign \dbus__cyc$next 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dbus__cyc$next 1'0 + end + sync init + update \dbus__cyc 1'0 + sync posedge \coresync_clk + update \dbus__cyc \dbus__cyc$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $15 + connect \B \x_valid_i + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $19 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $17 + connect \B $19 + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $23 + connect \B $25 + connect \Y $27 + end + process $group_1 + assign \dbus__stb$next \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { $21 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch { $27 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + case 1'1 + assign \dbus__stb$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + case 2'1- + assign \dbus__stb$next 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dbus__stb$next 1'0 + end + sync init + update \dbus__stb 1'0 + sync posedge \coresync_clk + update \dbus__stb \dbus__stb$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $29 + connect \B \x_valid_i + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $31 + connect \B $33 + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $37 + connect \B $39 + connect \Y $41 + end + process $group_2 + assign \dbus__sel$next \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { $35 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch { $41 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + case 1'1 + assign \dbus__sel$next 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + case 2'1- + assign \dbus__sel$next \x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + case + assign \dbus__sel$next 8'00000000 + assign \dbus__sel$next 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dbus__sel$next 8'00000000 + end + sync init + update \dbus__sel 8'00000000 + sync posedge \coresync_clk + update \dbus__sel \dbus__sel$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $43 + connect \B \x_valid_i + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $45 + connect \B $47 + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $53 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $51 + connect \B $53 + connect \Y $55 + end + process $group_3 + assign \m_ld_data_o$next \m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { $49 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch { $55 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + case 1'1 + assign \m_ld_data_o$next \dbus__dat_r + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + case 2'1- + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \m_ld_data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \m_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \m_ld_data_o \m_ld_data_o$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $57 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $57 + connect \B \x_valid_i + connect \Y $59 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $61 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $59 + connect \B $61 + connect \Y $63 + end + process $group_4 + assign \dbus__adr$next \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { $63 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + case 2'1- + assign \dbus__adr$next \x_addr_i [47:3] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + case + assign \dbus__adr$next 45'000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dbus__adr$next 45'000000000000000000000000000000000000000000000 + end + sync init + update \dbus__adr 45'000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \dbus__adr \dbus__adr$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $65 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $65 + connect \B \x_valid_i + connect \Y $67 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $69 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $67 + connect \B $69 + connect \Y $71 + end + process $group_5 + assign \dbus__we$next \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { $71 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + case 2'1- + assign \dbus__we$next \x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + case + assign \dbus__we$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dbus__we$next 1'0 + end + sync init + update \dbus__we 1'0 + sync posedge \coresync_clk + update \dbus__we \dbus__we$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $73 + connect \B \x_valid_i + connect \Y $75 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $77 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $75 + connect \B $77 + connect \Y $79 + end + process $group_6 + assign \dbus__dat_w$next \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { $79 \dbus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + case 2'1- + assign \dbus__dat_w$next \x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + case + assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \dbus__dat_w 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \dbus__dat_w \dbus__dat_w$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" + wire width 1 \m_load_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" + wire width 1 \m_load_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + cell $and $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $81 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" + wire width 1 \m_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + cell $not $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $83 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:133" + wire width 1 $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:133" + cell $not $86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__we + connect \Y $85 + end + process $group_7 + assign \m_load_err_o$next \m_load_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + switch { $83 $81 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + case 2'-1 + assign \m_load_err_o$next $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + case 2'1- + assign \m_load_err_o$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \m_load_err_o$next 1'0 + end + sync init + update \m_load_err_o 1'0 + sync posedge \coresync_clk + update \m_load_err_o \m_load_err_o$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:68" + wire width 1 \m_store_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:68" + wire width 1 \m_store_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + cell $and $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $87 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + cell $not $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $89 + end + process $group_8 + assign \m_store_err_o$next \m_store_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + switch { $89 $87 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + case 2'-1 + assign \m_store_err_o$next \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + case 2'1- + assign \m_store_err_o$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \m_store_err_o$next 1'0 + end + sync init + update \m_store_err_o 1'0 + sync posedge \coresync_clk + update \m_store_err_o \m_store_err_o$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:70" + wire width 45 \m_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:70" + wire width 45 \m_badaddr_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + cell $and $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $91 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + wire width 1 $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + cell $not $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $93 + end + process $group_9 + assign \m_badaddr_o$next \m_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + switch { $93 $91 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + case 2'-1 + assign \m_badaddr_o$next \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + case 2'1- + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \m_badaddr_o$next 45'000000000000000000000000000000000000000000000 + end + sync init + update \m_badaddr_o 45'000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \m_badaddr_o \m_badaddr_o$next + end + process $group_10 + assign \x_busy_o 1'0 + assign \x_busy_o \dbus__cyc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:60" + wire width 1 \m_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" + wire width 1 $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" + cell $or $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_load_err_o + connect \B \m_store_err_o + connect \Y $95 + end + process $group_11 + assign \m_busy_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" + switch { $95 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" + case 1'1 + assign \m_busy_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:147" + case + assign \m_busy_o \dbus__cyc + end + sync init + end + connect \x_stall_i 1'0 + connect \m_stall_i 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.l0" +module \l0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire width 1 output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire width 1 input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire width 1 input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire width 1 output 8 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire width 1 output 9 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 10 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 11 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 12 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 13 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 14 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 input 15 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 input 16 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 17 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 18 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 19 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 20 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 21 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 22 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire width 1 \pimem_ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire width 1 \pimem_ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire width 1 \pimem_ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 \pimem_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 48 \pimem_ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pimem_ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + wire width 8 \pimem_x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + wire width 48 \pimem_x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire width 1 \pimem_ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + wire width 64 \pimem_m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pimem_ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pimem_ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \pimem_ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pimem_ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + wire width 64 \pimem_x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + wire width 1 \pimem_x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire width 1 \pimem_ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + wire width 1 \pimem_x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + wire width 1 \pimem_x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire width 1 \pimem_m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire width 1 \pimem_x_valid_i + cell \pimem \pimem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i + connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \pimem_ldst_port0_data_len + connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok + connect \x_mask_i \pimem_x_mask_i + connect \x_addr_i \pimem_x_addr_i + connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o + connect \m_ld_data_o \pimem_m_ld_data_o + connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_busy_o \pimem_x_busy_o + connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o + connect \x_ld_i \pimem_x_ld_i + connect \x_st_i \pimem_x_st_i + connect \m_valid_i \pimem_m_valid_i + connect \x_valid_i \pimem_x_valid_i + end + cell \l0$412 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i + connect \ldst_port0_busy_o$3 \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len$4 \pimem_ldst_port0_data_len + connect \ldst_port0_addr_i$5 \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok$6 \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o$7 \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_ld_data_o$8 \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok$9 \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i_ok$10 \pimem_ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i$11 \pimem_ldst_port0_st_data_i + connect \ldst_port0_addr_exc_o$12 \pimem_ldst_port0_addr_exc_o + end + cell \lsmem \lsmem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \x_mask_i \pimem_x_mask_i + connect \x_addr_i \pimem_x_addr_i + connect \m_ld_data_o \pimem_m_ld_data_o + connect \x_st_data_i \pimem_x_st_data_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_st_i \pimem_x_st_i + connect \m_valid_i \pimem_m_valid_i + connect \x_valid_i \pimem_x_valid_i + connect \dbus__cyc \dbus__cyc + connect \dbus__ack \dbus__ack + connect \dbus__err \dbus__err + connect \dbus__stb \dbus__stb + connect \dbus__sel \dbus__sel + connect \dbus__dat_r \dbus__dat_r + connect \dbus__adr \dbus__adr + connect \dbus__we \dbus__we + connect \dbus__dat_w \dbus__dat_w + end + connect \pimem_ldst_port0_addr_exc_o 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.int" +module \int + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 1 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \dmi__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 4 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 5 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 7 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 8 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 9 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 10 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 11 \src3__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 12 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 13 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 14 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \dest1__wen + attribute \src "simple/issuer.py:102" + wire width 1 input 16 \coresync_rst + memory width 64 size 32 \memory + cell $meminit $1 + parameter \MEMID "\\memory" + parameter \ABITS 6 + parameter \WIDTH 64 + parameter \WORDS 32 + parameter \PRIORITY 0 + connect \ADDR 6'000000 + connect \DATA 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 5 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 64 \memory_r_data + cell $memrd \rp_src1 + parameter \MEMID "\\memory" + parameter \ABITS 5 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \TRANSPARENT 1 + connect \CLK \coresync_clk + connect \EN 1'1 + connect \ADDR \memory_r_addr + connect \DATA \memory_r_data + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 5 \memory_r_addr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 64 \memory_r_data$3 + cell $memrd \rp_src2 + parameter \MEMID "\\memory" + parameter \ABITS 5 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \TRANSPARENT 1 + connect \CLK \coresync_clk + connect \EN 1'1 + connect \ADDR \memory_r_addr$2 + connect \DATA \memory_r_data$3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 5 \memory_r_addr$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 64 \memory_r_data$5 + cell $memrd \rp_src3 + parameter \MEMID "\\memory" + parameter \ABITS 5 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \TRANSPARENT 1 + connect \CLK \coresync_clk + connect \EN 1'1 + connect \ADDR \memory_r_addr$4 + connect \DATA \memory_r_data$5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 5 \memory_r_addr$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 64 \memory_r_data$7 + cell $memrd \rp_dmi + parameter \MEMID "\\memory" + parameter \ABITS 5 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \TRANSPARENT 1 + connect \CLK \coresync_clk + connect \EN 1'1 + connect \ADDR \memory_r_addr$6 + connect \DATA \memory_r_data$7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + wire width 1 \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + wire width 5 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + wire width 64 \memory_w_data + cell $memwr \wp_dest1 + parameter \MEMID "\\memory" + parameter \ABITS 5 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \PRIORITY 0 + connect \CLK \coresync_clk + connect \EN { { \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en } } + connect \ADDR \memory_w_addr + connect \DATA \memory_w_data + end + process $group_0 + assign \memory_r_addr 5'00000 + assign \memory_r_addr \src1__addr + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$next + process $group_1 + assign \ren_delay$next \ren_delay + assign \ren_delay$next \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$next 1'0 + end + sync init + update \ren_delay 1'0 + sync posedge \coresync_clk + update \ren_delay \ren_delay$next + end + process $group_2 + assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + switch { \ren_delay } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + case 1'1 + assign \src1__data_o \memory_r_data + end + sync init + end + process $group_3 + assign \memory_r_addr$2 5'00000 + assign \memory_r_addr$2 \src2__addr + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$8$next + process $group_4 + assign \ren_delay$8$next \ren_delay$8 + assign \ren_delay$8$next \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$8$next 1'0 + end + sync init + update \ren_delay$8 1'0 + sync posedge \coresync_clk + update \ren_delay$8 \ren_delay$8$next + end + process $group_5 + assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + switch { \ren_delay$8 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + case 1'1 + assign \src2__data_o \memory_r_data$3 + end + sync init + end + process $group_6 + assign \memory_r_addr$4 5'00000 + assign \memory_r_addr$4 \src3__addr + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$9$next + process $group_7 + assign \ren_delay$9$next \ren_delay$9 + assign \ren_delay$9$next \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$9$next 1'0 + end + sync init + update \ren_delay$9 1'0 + sync posedge \coresync_clk + update \ren_delay$9 \ren_delay$9$next + end + process $group_8 + assign \src3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + switch { \ren_delay$9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + case 1'1 + assign \src3__data_o \memory_r_data$5 + end + sync init + end + process $group_9 + assign \memory_r_addr$6 5'00000 + assign \memory_r_addr$6 \dmi__addr + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$10$next + process $group_10 + assign \ren_delay$10$next \ren_delay$10 + assign \ren_delay$10$next \dmi__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$10$next 1'0 + end + sync init + update \ren_delay$10 1'0 + sync posedge \coresync_clk + update \ren_delay$10 \ren_delay$10$next + end + process $group_11 + assign \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + switch { \ren_delay$10 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + case 1'1 + assign \dmi__data_o \memory_r_data$7 + end + sync init + end + process $group_12 + assign \memory_w_addr 5'00000 + assign \memory_w_addr \dest1__addr + sync init + end + process $group_13 + assign \memory_w_en 1'0 + assign \memory_w_en \dest1__wen + sync init + end + process $group_14 + assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \memory_w_data \dest1__data_i + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0" +module \reg_0 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 13 \r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 14 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg$next + process $group_0 + assign \src10__data_o$next \src10__data_o + assign \src10__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src10__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src10__data_o$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src10__data_o$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src10__data_o$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src10__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src10__data_o$next 4'0000 + end + sync init + update \src10__data_o 4'0000 + sync posedge \coresync_clk + update \src10__data_o \src10__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src10__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src20__data_o$next \src20__data_o + assign \src20__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src20__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src20__data_o$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src20__data_o$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src20__data_o$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src20__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src20__data_o$next 4'0000 + end + sync init + update \src20__data_o 4'0000 + sync posedge \coresync_clk + update \src20__data_o \src20__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src20__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src30__data_o$next \src30__data_o + assign \src30__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src30__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src30__data_o$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src30__data_o$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src30__data_o$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src30__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src30__data_o$next 4'0000 + end + sync init + update \src30__data_o 4'0000 + sync posedge \coresync_clk + update \src30__data_o \src30__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src30__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r0__data_o$next \r0__data_o + assign \r0__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r0__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r0__data_o$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r0__data_o$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r0__data_o$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r0__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r0__data_o$next 4'0000 + end + sync init + update \r0__data_o 4'0000 + sync posedge \coresync_clk + update \r0__data_o \r0__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r0__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 4'0000 + end + sync init + update \reg 4'0000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" +module \reg_1 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 13 \r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 14 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg$next + process $group_0 + assign \src11__data_o$next \src11__data_o + assign \src11__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src11__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src11__data_o$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src11__data_o$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src11__data_o$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src11__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src11__data_o$next 4'0000 + end + sync init + update \src11__data_o 4'0000 + sync posedge \coresync_clk + update \src11__data_o \src11__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src11__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src21__data_o$next \src21__data_o + assign \src21__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src21__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src21__data_o$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src21__data_o$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src21__data_o$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src21__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src21__data_o$next 4'0000 + end + sync init + update \src21__data_o 4'0000 + sync posedge \coresync_clk + update \src21__data_o \src21__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src21__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src31__data_o$next \src31__data_o + assign \src31__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src31__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src31__data_o$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src31__data_o$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src31__data_o$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src31__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src31__data_o$next 4'0000 + end + sync init + update \src31__data_o 4'0000 + sync posedge \coresync_clk + update \src31__data_o \src31__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src31__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r1__data_o$next \r1__data_o + assign \r1__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r1__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r1__data_o$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r1__data_o$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r1__data_o$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r1__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r1__data_o$next 4'0000 + end + sync init + update \r1__data_o 4'0000 + sync posedge \coresync_clk + update \r1__data_o \r1__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r1__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 4'0000 + end + sync init + update \reg 4'0000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" +module \reg_2 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 13 \r2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 14 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg$next + process $group_0 + assign \src12__data_o$next \src12__data_o + assign \src12__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src12__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src12__data_o$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src12__data_o$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src12__data_o$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src12__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src12__data_o$next 4'0000 + end + sync init + update \src12__data_o 4'0000 + sync posedge \coresync_clk + update \src12__data_o \src12__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src12__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src22__data_o$next \src22__data_o + assign \src22__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src22__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src22__data_o$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src22__data_o$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src22__data_o$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src22__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src22__data_o$next 4'0000 + end + sync init + update \src22__data_o 4'0000 + sync posedge \coresync_clk + update \src22__data_o \src22__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src22__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src32__data_o$next \src32__data_o + assign \src32__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src32__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src32__data_o$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src32__data_o$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src32__data_o$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src32__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src32__data_o$next 4'0000 + end + sync init + update \src32__data_o 4'0000 + sync posedge \coresync_clk + update \src32__data_o \src32__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src32__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r2__data_o$next \r2__data_o + assign \r2__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r2__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r2__data_o$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r2__data_o$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r2__data_o$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r2__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r2__data_o$next 4'0000 + end + sync init + update \r2__data_o 4'0000 + sync posedge \coresync_clk + update \r2__data_o \r2__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r2__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 4'0000 + end + sync init + update \reg 4'0000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" +module \reg_3 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src13__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src13__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src13__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src33__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src33__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src33__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest23__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest23__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 13 \r3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 14 \w3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \w3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg$next + process $group_0 + assign \src13__data_o$next \src13__data_o + assign \src13__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src13__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src13__data_o$next \dest13__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src13__data_o$next \dest23__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src13__data_o$next \w3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src13__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src13__data_o$next 4'0000 + end + sync init + update \src13__data_o 4'0000 + sync posedge \coresync_clk + update \src13__data_o \src13__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src13__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src23__data_o$next \src23__data_o + assign \src23__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src23__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src23__data_o$next \dest13__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src23__data_o$next \dest23__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src23__data_o$next \w3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src23__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src23__data_o$next 4'0000 + end + sync init + update \src23__data_o 4'0000 + sync posedge \coresync_clk + update \src23__data_o \src23__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src23__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src33__data_o$next \src33__data_o + assign \src33__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src33__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src33__data_o$next \dest13__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src33__data_o$next \dest23__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src33__data_o$next \w3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src33__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src33__data_o$next 4'0000 + end + sync init + update \src33__data_o 4'0000 + sync posedge \coresync_clk + update \src33__data_o \src33__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src33__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r3__data_o$next \r3__data_o + assign \r3__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r3__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r3__data_o$next \dest13__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r3__data_o$next \dest23__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r3__data_o$next \w3__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r3__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r3__data_o$next 4'0000 + end + sync init + update \r3__data_o 4'0000 + sync posedge \coresync_clk + update \r3__data_o \r3__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r3__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest13__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest13__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest23__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest23__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w3__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w3__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 4'0000 + end + sync init + update \reg 4'0000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" +module \reg_4 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src14__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src14__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src14__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src34__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src34__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src34__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest14__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest14__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest24__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest24__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r4__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 13 \r4__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 14 \w4__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \w4__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg$next + process $group_0 + assign \src14__data_o$next \src14__data_o + assign \src14__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src14__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src14__data_o$next \dest14__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src14__data_o$next \dest24__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src14__data_o$next \w4__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src14__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src14__data_o$next 4'0000 + end + sync init + update \src14__data_o 4'0000 + sync posedge \coresync_clk + update \src14__data_o \src14__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src14__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src24__data_o$next \src24__data_o + assign \src24__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src24__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src24__data_o$next \dest14__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src24__data_o$next \dest24__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src24__data_o$next \w4__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src24__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src24__data_o$next 4'0000 + end + sync init + update \src24__data_o 4'0000 + sync posedge \coresync_clk + update \src24__data_o \src24__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src24__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src34__data_o$next \src34__data_o + assign \src34__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src34__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src34__data_o$next \dest14__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src34__data_o$next \dest24__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src34__data_o$next \w4__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src34__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src34__data_o$next 4'0000 + end + sync init + update \src34__data_o 4'0000 + sync posedge \coresync_clk + update \src34__data_o \src34__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src34__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r4__data_o$next \r4__data_o + assign \r4__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r4__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r4__data_o$next \dest14__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r4__data_o$next \dest24__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r4__data_o$next \w4__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r4__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r4__data_o$next 4'0000 + end + sync init + update \r4__data_o 4'0000 + sync posedge \coresync_clk + update \r4__data_o \r4__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r4__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest14__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest14__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest24__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest24__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w4__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w4__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 4'0000 + end + sync init + update \reg 4'0000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" +module \reg_5 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src15__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src15__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src15__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src35__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src35__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src35__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest15__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest15__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest25__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r5__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 13 \r5__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 14 \w5__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \w5__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg$next + process $group_0 + assign \src15__data_o$next \src15__data_o + assign \src15__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src15__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src15__data_o$next \dest15__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src15__data_o$next \dest25__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src15__data_o$next \w5__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src15__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src15__data_o$next 4'0000 + end + sync init + update \src15__data_o 4'0000 + sync posedge \coresync_clk + update \src15__data_o \src15__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src15__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src25__data_o$next \src25__data_o + assign \src25__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src25__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src25__data_o$next \dest15__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src25__data_o$next \dest25__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src25__data_o$next \w5__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src25__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src25__data_o$next 4'0000 + end + sync init + update \src25__data_o 4'0000 + sync posedge \coresync_clk + update \src25__data_o \src25__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src25__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src35__data_o$next \src35__data_o + assign \src35__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src35__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src35__data_o$next \dest15__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src35__data_o$next \dest25__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src35__data_o$next \w5__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src35__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src35__data_o$next 4'0000 + end + sync init + update \src35__data_o 4'0000 + sync posedge \coresync_clk + update \src35__data_o \src35__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src35__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r5__data_o$next \r5__data_o + assign \r5__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r5__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r5__data_o$next \dest15__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r5__data_o$next \dest25__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r5__data_o$next \w5__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r5__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r5__data_o$next 4'0000 + end + sync init + update \r5__data_o 4'0000 + sync posedge \coresync_clk + update \r5__data_o \r5__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r5__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest15__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest15__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest25__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest25__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w5__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w5__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 4'0000 + end + sync init + update \reg 4'0000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" +module \reg_6 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src16__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src16__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src16__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src36__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src36__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src36__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest26__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r6__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 13 \r6__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 14 \w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \w6__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg$next + process $group_0 + assign \src16__data_o$next \src16__data_o + assign \src16__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src16__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src16__data_o$next \dest16__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src16__data_o$next \dest26__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src16__data_o$next \w6__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src16__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src16__data_o$next 4'0000 + end + sync init + update \src16__data_o 4'0000 + sync posedge \coresync_clk + update \src16__data_o \src16__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src16__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src26__data_o$next \src26__data_o + assign \src26__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src26__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src26__data_o$next \dest16__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src26__data_o$next \dest26__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src26__data_o$next \w6__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src26__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src26__data_o$next 4'0000 + end + sync init + update \src26__data_o 4'0000 + sync posedge \coresync_clk + update \src26__data_o \src26__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src26__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src36__data_o$next \src36__data_o + assign \src36__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src36__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src36__data_o$next \dest16__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src36__data_o$next \dest26__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src36__data_o$next \w6__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src36__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src36__data_o$next 4'0000 + end + sync init + update \src36__data_o 4'0000 + sync posedge \coresync_clk + update \src36__data_o \src36__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src36__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r6__data_o$next \r6__data_o + assign \r6__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r6__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r6__data_o$next \dest16__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r6__data_o$next \dest26__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r6__data_o$next \w6__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r6__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r6__data_o$next 4'0000 + end + sync init + update \r6__data_o 4'0000 + sync posedge \coresync_clk + update \r6__data_o \r6__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r6__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest16__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest16__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest26__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest26__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w6__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w6__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 4'0000 + end + sync init + update \reg 4'0000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" +module \reg_7 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src17__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src17__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src17__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src37__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src37__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src37__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest27__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r7__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 13 \r7__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 14 \w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \w7__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 4 \reg$next + process $group_0 + assign \src17__data_o$next \src17__data_o + assign \src17__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src17__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src17__data_o$next \dest17__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src17__data_o$next \dest27__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src17__data_o$next \w7__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src17__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src17__data_o$next 4'0000 + end + sync init + update \src17__data_o 4'0000 + sync posedge \coresync_clk + update \src17__data_o \src17__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src17__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src27__data_o$next \src27__data_o + assign \src27__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src27__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src27__data_o$next \dest17__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src27__data_o$next \dest27__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src27__data_o$next \w7__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src27__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src27__data_o$next 4'0000 + end + sync init + update \src27__data_o 4'0000 + sync posedge \coresync_clk + update \src27__data_o \src27__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src27__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src37__data_o$next \src37__data_o + assign \src37__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src37__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src37__data_o$next \dest17__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src37__data_o$next \dest27__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src37__data_o$next \w7__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src37__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src37__data_o$next 4'0000 + end + sync init + update \src37__data_o 4'0000 + sync posedge \coresync_clk + update \src37__data_o \src37__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src37__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r7__data_o$next \r7__data_o + assign \r7__data_o$next 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r7__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r7__data_o$next \dest17__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r7__data_o$next \dest27__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r7__data_o$next \w7__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r7__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r7__data_o$next 4'0000 + end + sync init + update \r7__data_o 4'0000 + sync posedge \coresync_clk + update \r7__data_o \r7__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r7__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest17__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest17__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest27__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest27__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w7__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w7__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 4'0000 + end + sync init + update \reg 4'0000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.cr" +module \cr + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 output 1 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 2 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 4 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 6 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 8 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 input 9 \full_wr__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 10 \full_wr__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 12 \wen + attribute \src "simple/issuer.py:102" + wire width 1 input 13 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_0_w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_w0__wen + cell \reg_0 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src10__ren \reg_0_src10__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src20__ren \reg_0_src20__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src30__ren \reg_0_src30__ren + connect \src30__data_o \reg_0_src30__data_o + connect \dest10__wen \reg_0_dest10__wen + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_1_w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_w1__wen + cell \reg_1 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src11__ren \reg_1_src11__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src21__ren \reg_1_src21__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src31__ren \reg_1_src31__ren + connect \src31__data_o \reg_1_src31__data_o + connect \dest11__wen \reg_1_dest11__wen + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_r2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_2_w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_w2__wen + cell \reg_2 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src12__ren \reg_2_src12__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src22__ren \reg_2_src22__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src32__ren \reg_2_src32__ren + connect \src32__data_o \reg_2_src32__data_o + connect \dest12__wen \reg_2_dest12__wen + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_src13__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_src13__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_src23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_src23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_src33__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_src33__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_dest13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_dest13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_dest23__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_dest23__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_r3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_r3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_3_w3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_3_w3__wen + cell \reg_3 \reg_3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src13__ren \reg_3_src13__ren + connect \src13__data_o \reg_3_src13__data_o + connect \src23__ren \reg_3_src23__ren + connect \src23__data_o \reg_3_src23__data_o + connect \src33__ren \reg_3_src33__ren + connect \src33__data_o \reg_3_src33__data_o + connect \dest13__wen \reg_3_dest13__wen + connect \dest13__data_i \reg_3_dest13__data_i + connect \dest23__wen \reg_3_dest23__wen + connect \dest23__data_i \reg_3_dest23__data_i + connect \r3__data_o \reg_3_r3__data_o + connect \r3__ren \reg_3_r3__ren + connect \w3__data_i \reg_3_w3__data_i + connect \w3__wen \reg_3_w3__wen + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_4_src14__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_src14__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_4_src24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_src24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_4_src34__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_src34__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_4_dest14__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_dest14__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_4_dest24__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_dest24__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_r4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_4_r4__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_4_w4__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_4_w4__wen + cell \reg_4 \reg_4 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src14__ren \reg_4_src14__ren + connect \src14__data_o \reg_4_src14__data_o + connect \src24__ren \reg_4_src24__ren + connect \src24__data_o \reg_4_src24__data_o + connect \src34__ren \reg_4_src34__ren + connect \src34__data_o \reg_4_src34__data_o + connect \dest14__wen \reg_4_dest14__wen + connect \dest14__data_i \reg_4_dest14__data_i + connect \dest24__wen \reg_4_dest24__wen + connect \dest24__data_i \reg_4_dest24__data_i + connect \r4__data_o \reg_4_r4__data_o + connect \r4__ren \reg_4_r4__ren + connect \w4__data_i \reg_4_w4__data_i + connect \w4__wen \reg_4_w4__wen + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_5_src15__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_src15__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_5_src25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_src25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_5_src35__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_src35__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_5_dest15__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_dest15__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_5_dest25__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_r5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_5_r5__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_5_w5__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_5_w5__wen + cell \reg_5 \reg_5 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src15__ren \reg_5_src15__ren + connect \src15__data_o \reg_5_src15__data_o + connect \src25__ren \reg_5_src25__ren + connect \src25__data_o \reg_5_src25__data_o + connect \src35__ren \reg_5_src35__ren + connect \src35__data_o \reg_5_src35__data_o + connect \dest15__wen \reg_5_dest15__wen + connect \dest15__data_i \reg_5_dest15__data_i + connect \dest25__wen \reg_5_dest25__wen + connect \dest25__data_i \reg_5_dest25__data_i + connect \r5__data_o \reg_5_r5__data_o + connect \r5__ren \reg_5_r5__ren + connect \w5__data_i \reg_5_w5__data_i + connect \w5__wen \reg_5_w5__wen + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_6_src16__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_src16__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_6_src26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_src26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_6_src36__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_src36__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_6_dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_6_dest26__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_r6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_6_r6__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_6_w6__wen + cell \reg_6 \reg_6 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src16__ren \reg_6_src16__ren + connect \src16__data_o \reg_6_src16__data_o + connect \src26__ren \reg_6_src26__ren + connect \src26__data_o \reg_6_src26__data_o + connect \src36__ren \reg_6_src36__ren + connect \src36__data_o \reg_6_src36__data_o + connect \dest16__wen \reg_6_dest16__wen + connect \dest16__data_i \reg_6_dest16__data_i + connect \dest26__wen \reg_6_dest26__wen + connect \dest26__data_i \reg_6_dest26__data_i + connect \r6__data_o \reg_6_r6__data_o + connect \r6__ren \reg_6_r6__ren + connect \w6__data_i \reg_6_w6__data_i + connect \w6__wen \reg_6_w6__wen + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_7_src17__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_src17__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_7_src27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_src27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_7_src37__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_src37__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_7_dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_7_dest27__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_r7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_7_r7__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_7_w7__wen + cell \reg_7 \reg_7 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src17__ren \reg_7_src17__ren + connect \src17__data_o \reg_7_src17__data_o + connect \src27__ren \reg_7_src27__ren + connect \src27__data_o \reg_7_src27__data_o + connect \src37__ren \reg_7_src37__ren + connect \src37__data_o \reg_7_src37__data_o + connect \dest17__wen \reg_7_dest17__wen + connect \dest17__data_i \reg_7_dest17__data_i + connect \dest27__wen \reg_7_dest27__wen + connect \dest27__data_i \reg_7_dest27__data_i + connect \r7__data_o \reg_7_r7__data_o + connect \r7__ren \reg_7_r7__ren + connect \w7__data_i \reg_7_w7__data_i + connect \w7__wen \reg_7_w7__wen + end + process $group_0 + assign \reg_0_src10__ren 1'0 + assign \reg_1_src11__ren 1'0 + assign \reg_2_src12__ren 1'0 + assign \reg_3_src13__ren 1'0 + assign \reg_4_src14__ren 1'0 + assign \reg_5_src15__ren 1'0 + assign \reg_6_src16__ren 1'0 + assign \reg_7_src17__ren 1'0 + assign { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 8 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 8 \ren_delay$next + process $group_8 + assign \ren_delay$next \ren_delay + assign \ren_delay$next \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$next 8'00000000 + end + sync init + update \ren_delay 8'00000000 + sync posedge \coresync_clk + update \ren_delay \ren_delay$next + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src10__data_o + connect \B \reg_1_src11__data_o + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src12__data_o + connect \B \reg_3_src13__data_o + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $3 + connect \B $5 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src14__data_o + connect \B \reg_5_src15__data_o + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src16__data_o + connect \B \reg_7_src17__data_o + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $9 + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $7 + connect \B $13 + connect \Y $15 + end + process $group_9 + assign \src1__data_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + case 1'1 + assign \src1__data_o $15 + end + sync init + end + process $group_10 + assign \reg_0_src20__ren 1'0 + assign \reg_1_src21__ren 1'0 + assign \reg_2_src22__ren 1'0 + assign \reg_3_src23__ren 1'0 + assign \reg_4_src24__ren 1'0 + assign \reg_5_src25__ren 1'0 + assign \reg_6_src26__ren 1'0 + assign \reg_7_src27__ren 1'0 + assign { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 8 \ren_delay$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 8 \ren_delay$17$next + process $group_18 + assign \ren_delay$17$next \ren_delay$17 + assign \ren_delay$17$next \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$17$next 8'00000000 + end + sync init + update \ren_delay$17 8'00000000 + sync posedge \coresync_clk + update \ren_delay$17 \ren_delay$17$next + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$17 + connect \Y $18 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src20__data_o + connect \B \reg_1_src21__data_o + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src22__data_o + connect \B \reg_3_src23__data_o + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $20 + connect \B $22 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src24__data_o + connect \B \reg_5_src25__data_o + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src26__data_o + connect \B \reg_7_src27__data_o + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $26 + connect \B $28 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $24 + connect \B $30 + connect \Y $32 + end + process $group_19 + assign \src2__data_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + switch { $18 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + case 1'1 + assign \src2__data_o $32 + end + sync init + end + process $group_20 + assign \reg_0_src30__ren 1'0 + assign \reg_1_src31__ren 1'0 + assign \reg_2_src32__ren 1'0 + assign \reg_3_src33__ren 1'0 + assign \reg_4_src34__ren 1'0 + assign \reg_5_src35__ren 1'0 + assign \reg_6_src36__ren 1'0 + assign \reg_7_src37__ren 1'0 + assign { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 8 \ren_delay$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 8 \ren_delay$34$next + process $group_28 + assign \ren_delay$34$next \ren_delay$34 + assign \ren_delay$34$next \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$34$next 8'00000000 + end + sync init + update \ren_delay$34 8'00000000 + sync posedge \coresync_clk + update \ren_delay$34 \ren_delay$34$next + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$34 + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src30__data_o + connect \B \reg_1_src31__data_o + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src32__data_o + connect \B \reg_3_src33__data_o + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $37 + connect \B $39 + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src34__data_o + connect \B \reg_5_src35__data_o + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src36__data_o + connect \B \reg_7_src37__data_o + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $43 + connect \B $45 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $41 + connect \B $47 + connect \Y $49 + end + process $group_29 + assign \src3__data_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + switch { $35 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + case 1'1 + assign \src3__data_o $49 + end + sync init + end + process $group_30 + assign \reg_0_dest10__wen 1'0 + assign \reg_1_dest11__wen 1'0 + assign \reg_2_dest12__wen 1'0 + assign \reg_3_dest13__wen 1'0 + assign \reg_4_dest14__wen 1'0 + assign \reg_5_dest15__wen 1'0 + assign \reg_6_dest16__wen 1'0 + assign \reg_7_dest17__wen 1'0 + assign { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen + sync init + end + process $group_38 + assign \reg_0_dest10__data_i 4'0000 + assign \reg_0_dest10__data_i \data_i + sync init + end + process $group_39 + assign \reg_1_dest11__data_i 4'0000 + assign \reg_1_dest11__data_i \data_i + sync init + end + process $group_40 + assign \reg_2_dest12__data_i 4'0000 + assign \reg_2_dest12__data_i \data_i + sync init + end + process $group_41 + assign \reg_3_dest13__data_i 4'0000 + assign \reg_3_dest13__data_i \data_i + sync init + end + process $group_42 + assign \reg_4_dest14__data_i 4'0000 + assign \reg_4_dest14__data_i \data_i + sync init + end + process $group_43 + assign \reg_5_dest15__data_i 4'0000 + assign \reg_5_dest15__data_i \data_i + sync init + end + process $group_44 + assign \reg_6_dest16__data_i 4'0000 + assign \reg_6_dest16__data_i \data_i + sync init + end + process $group_45 + assign \reg_7_dest17__data_i 4'0000 + assign \reg_7_dest17__data_i \data_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \wen$51 + process $group_46 + assign \reg_0_dest20__wen 1'0 + assign \reg_1_dest21__wen 1'0 + assign \reg_2_dest22__wen 1'0 + assign \reg_3_dest23__wen 1'0 + assign \reg_4_dest24__wen 1'0 + assign \reg_5_dest25__wen 1'0 + assign \reg_6_dest26__wen 1'0 + assign \reg_7_dest27__wen 1'0 + assign { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen$51 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \data_i$52 + process $group_54 + assign \reg_0_dest20__data_i 4'0000 + assign \reg_0_dest20__data_i \data_i$52 + sync init + end + process $group_55 + assign \reg_1_dest21__data_i 4'0000 + assign \reg_1_dest21__data_i \data_i$52 + sync init + end + process $group_56 + assign \reg_2_dest22__data_i 4'0000 + assign \reg_2_dest22__data_i \data_i$52 + sync init + end + process $group_57 + assign \reg_3_dest23__data_i 4'0000 + assign \reg_3_dest23__data_i \data_i$52 + sync init + end + process $group_58 + assign \reg_4_dest24__data_i 4'0000 + assign \reg_4_dest24__data_i \data_i$52 + sync init + end + process $group_59 + assign \reg_5_dest25__data_i 4'0000 + assign \reg_5_dest25__data_i \data_i$52 + sync init + end + process $group_60 + assign \reg_6_dest26__data_i 4'0000 + assign \reg_6_dest26__data_i \data_i$52 + sync init + end + process $group_61 + assign \reg_7_dest27__data_i 4'0000 + assign \reg_7_dest27__data_i \data_i$52 + sync init + end + process $group_62 + assign \full_rd__data_o 32'00000000000000000000000000000000 + assign \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + sync init + end + process $group_63 + assign \reg_0_r0__ren 1'0 + assign \reg_1_r1__ren 1'0 + assign \reg_2_r2__ren 1'0 + assign \reg_3_r3__ren 1'0 + assign \reg_4_r4__ren 1'0 + assign \reg_5_r5__ren 1'0 + assign \reg_6_r6__ren 1'0 + assign \reg_7_r7__ren 1'0 + assign { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + sync init + end + process $group_71 + assign \reg_0_w0__data_i 4'0000 + assign \reg_1_w1__data_i 4'0000 + assign \reg_2_w2__data_i 4'0000 + assign \reg_3_w3__data_i 4'0000 + assign \reg_4_w4__data_i 4'0000 + assign \reg_5_w5__data_i 4'0000 + assign \reg_6_w6__data_i 4'0000 + assign \reg_7_w7__data_i 4'0000 + assign { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i + sync init + end + process $group_79 + assign \reg_0_w0__wen 1'0 + assign \reg_1_w1__wen 1'0 + assign \reg_2_w2__wen 1'0 + assign \reg_3_w3__wen 1'0 + assign \reg_4_w4__wen 1'0 + assign \reg_5_w5__wen 1'0 + assign \reg_6_w6__wen 1'0 + assign \reg_7_w7__wen 1'0 + assign { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen + sync init + end + connect \wen$51 8'00000000 + connect \data_i$52 4'0000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" +module \reg_0$414 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 12 \dest30__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest30__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 17 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 2 \reg$next + process $group_0 + assign \src10__data_o$next \src10__data_o + assign \src10__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src10__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src10__data_o$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src10__data_o$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest30__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src10__data_o$next \dest30__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src10__data_o$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src10__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src10__data_o$next 2'00 + end + sync init + update \src10__data_o 2'00 + sync posedge \coresync_clk + update \src10__data_o \src10__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src10__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest30__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src20__data_o$next \src20__data_o + assign \src20__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src20__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src20__data_o$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src20__data_o$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest30__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src20__data_o$next \dest30__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src20__data_o$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src20__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src20__data_o$next 2'00 + end + sync init + update \src20__data_o 2'00 + sync posedge \coresync_clk + update \src20__data_o \src20__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src20__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest30__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src30__data_o$next \src30__data_o + assign \src30__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src30__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src30__data_o$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src30__data_o$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest30__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src30__data_o$next \dest30__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src30__data_o$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src30__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src30__data_o$next 2'00 + end + sync init + update \src30__data_o 2'00 + sync posedge \coresync_clk + update \src30__data_o \src30__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src30__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest30__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r0__data_o$next \r0__data_o + assign \r0__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r0__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r0__data_o$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r0__data_o$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest30__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r0__data_o$next \dest30__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r0__data_o$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r0__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r0__data_o$next 2'00 + end + sync init + update \r0__data_o 2'00 + sync posedge \coresync_clk + update \r0__data_o \r0__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r0__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest30__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest20__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest20__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest30__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest30__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w0__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 2'00 + end + sync init + update \reg 2'00 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" +module \reg_1$415 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 12 \dest31__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest31__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 2 \reg$next + process $group_0 + assign \src11__data_o$next \src11__data_o + assign \src11__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src11__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src11__data_o$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src11__data_o$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest31__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src11__data_o$next \dest31__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src11__data_o$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src11__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src11__data_o$next 2'00 + end + sync init + update \src11__data_o 2'00 + sync posedge \coresync_clk + update \src11__data_o \src11__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src11__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest31__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src21__data_o$next \src21__data_o + assign \src21__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src21__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src21__data_o$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src21__data_o$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest31__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src21__data_o$next \dest31__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src21__data_o$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src21__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src21__data_o$next 2'00 + end + sync init + update \src21__data_o 2'00 + sync posedge \coresync_clk + update \src21__data_o \src21__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src21__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest31__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src31__data_o$next \src31__data_o + assign \src31__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src31__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src31__data_o$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src31__data_o$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest31__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src31__data_o$next \dest31__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src31__data_o$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src31__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src31__data_o$next 2'00 + end + sync init + update \src31__data_o 2'00 + sync posedge \coresync_clk + update \src31__data_o \src31__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src31__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest31__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r1__data_o$next \r1__data_o + assign \r1__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r1__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r1__data_o$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r1__data_o$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest31__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r1__data_o$next \dest31__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r1__data_o$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r1__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r1__data_o$next 2'00 + end + sync init + update \r1__data_o 2'00 + sync posedge \coresync_clk + update \r1__data_o \r1__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r1__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest31__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest21__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest21__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest31__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest31__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w1__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 2'00 + end + sync init + update \reg 2'00 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" +module \reg_2$416 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 12 \dest32__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 15 \r2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 2 \reg$next + process $group_0 + assign \src12__data_o$next \src12__data_o + assign \src12__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src12__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src12__data_o$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src12__data_o$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest32__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src12__data_o$next \dest32__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src12__data_o$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src12__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src12__data_o$next 2'00 + end + sync init + update \src12__data_o 2'00 + sync posedge \coresync_clk + update \src12__data_o \src12__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src12__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest32__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \src22__data_o$next \src22__data_o + assign \src22__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src22__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src22__data_o$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src22__data_o$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest32__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src22__data_o$next \dest32__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src22__data_o$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src22__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src22__data_o$next 2'00 + end + sync init + update \src22__data_o 2'00 + sync posedge \coresync_clk + update \src22__data_o \src22__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src22__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest32__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $6 + end + process $group_4 + assign \src32__data_o$next \src32__data_o + assign \src32__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src32__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src32__data_o$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src32__data_o$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest32__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src32__data_o$next \dest32__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \src32__data_o$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \src32__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \src32__data_o$next 2'00 + end + sync init + update \src32__data_o 2'00 + sync posedge \coresync_clk + update \src32__data_o \src32__data_o$next + end + process $group_5 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \src32__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest32__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$7 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $9 + end + process $group_6 + assign \r2__data_o$next \r2__data_o + assign \r2__data_o$next 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r2__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r2__data_o$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r2__data_o$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest32__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r2__data_o$next \dest32__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \r2__data_o$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \r2__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \r2__data_o$next 2'00 + end + sync init + update \r2__data_o 2'00 + sync posedge \coresync_clk + update \r2__data_o \r2__data_o$next + end + process $group_7 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \r2__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$10 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \dest32__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$10 1'1 + end + end + sync init + end + process $group_8 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest12__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest12__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest22__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest22__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \dest32__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \dest32__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \w2__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \w2__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 2'00 + end + sync init + update \reg 2'00 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.xer" +module \xer + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 1 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 2 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 4 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 6 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 7 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 8 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \data_i$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 10 \wen$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \data_i$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 12 \wen$4 + attribute \src "simple/issuer.py:102" + wire width 1 input 13 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_dest30__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_dest30__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_0_w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_w0__wen + cell \reg_0$414 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src10__ren \reg_0_src10__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src20__ren \reg_0_src20__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src30__ren \reg_0_src30__ren + connect \src30__data_o \reg_0_src30__data_o + connect \dest10__wen \reg_0_dest10__wen + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest30__wen \reg_0_dest30__wen + connect \dest30__data_i \reg_0_dest30__data_i + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_dest31__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_dest31__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_w1__wen + cell \reg_1$415 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src11__ren \reg_1_src11__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src21__ren \reg_1_src21__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src31__ren \reg_1_src31__ren + connect \src31__data_o \reg_1_src31__data_o + connect \dest11__wen \reg_1_dest11__wen + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest31__wen \reg_1_dest31__wen + connect \dest31__data_i \reg_1_dest31__data_i + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_dest32__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_r2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_2_w2__wen + cell \reg_2$416 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \src12__ren \reg_2_src12__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src22__ren \reg_2_src22__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src32__ren \reg_2_src32__ren + connect \src32__data_o \reg_2_src32__data_o + connect \dest12__wen \reg_2_dest12__wen + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest32__wen \reg_2_dest32__wen + connect \dest32__data_i \reg_2_dest32__data_i + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + process $group_0 + assign \reg_0_src10__ren 1'0 + assign \reg_1_src11__ren 1'0 + assign \reg_2_src12__ren 1'0 + assign { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 3 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 3 \ren_delay$next + process $group_3 + assign \ren_delay$next \ren_delay + assign \ren_delay$next \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$next 3'000 + end + sync init + update \ren_delay 3'000 + sync posedge \coresync_clk + update \ren_delay \ren_delay$next + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src11__data_o + connect \B \reg_2_src12__data_o + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src10__data_o + connect \B $7 + connect \Y $9 + end + process $group_4 + assign \src1__data_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + case 1'1 + assign \src1__data_o $9 + end + sync init + end + process $group_5 + assign \reg_0_src20__ren 1'0 + assign \reg_1_src21__ren 1'0 + assign \reg_2_src22__ren 1'0 + assign { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 3 \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 3 \ren_delay$11$next + process $group_8 + assign \ren_delay$11$next \ren_delay$11 + assign \ren_delay$11$next \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$11$next 3'000 + end + sync init + update \ren_delay$11 3'000 + sync posedge \coresync_clk + update \ren_delay$11 \ren_delay$11$next + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$11 + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src21__data_o + connect \B \reg_2_src22__data_o + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src20__data_o + connect \B $14 + connect \Y $16 + end + process $group_9 + assign \src2__data_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + switch { $12 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + case 1'1 + assign \src2__data_o $16 + end + sync init + end + process $group_10 + assign \reg_0_src30__ren 1'0 + assign \reg_1_src31__ren 1'0 + assign \reg_2_src32__ren 1'0 + assign { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 3 \ren_delay$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 3 \ren_delay$18$next + process $group_13 + assign \ren_delay$18$next \ren_delay$18 + assign \ren_delay$18$next \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$18$next 3'000 + end + sync init + update \ren_delay$18 3'000 + sync posedge \coresync_clk + update \ren_delay$18 \ren_delay$18$next + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$18 + connect \Y $19 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src31__data_o + connect \B \reg_2_src32__data_o + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src30__data_o + connect \B $21 + connect \Y $23 + end + process $group_14 + assign \src3__data_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + switch { $19 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + case 1'1 + assign \src3__data_o $23 + end + sync init + end + process $group_15 + assign \reg_0_dest10__wen 1'0 + assign \reg_1_dest11__wen 1'0 + assign \reg_2_dest12__wen 1'0 + assign { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 + sync init + end + process $group_18 + assign \reg_0_dest10__data_i 2'00 + assign \reg_0_dest10__data_i \data_i$3 + sync init + end + process $group_19 + assign \reg_1_dest11__data_i 2'00 + assign \reg_1_dest11__data_i \data_i$3 + sync init + end + process $group_20 + assign \reg_2_dest12__data_i 2'00 + assign \reg_2_dest12__data_i \data_i$3 + sync init + end + process $group_21 + assign \reg_0_dest20__wen 1'0 + assign \reg_1_dest21__wen 1'0 + assign \reg_2_dest22__wen 1'0 + assign { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen + sync init + end + process $group_24 + assign \reg_0_dest20__data_i 2'00 + assign \reg_0_dest20__data_i \data_i + sync init + end + process $group_25 + assign \reg_1_dest21__data_i 2'00 + assign \reg_1_dest21__data_i \data_i + sync init + end + process $group_26 + assign \reg_2_dest22__data_i 2'00 + assign \reg_2_dest22__data_i \data_i + sync init + end + process $group_27 + assign \reg_0_dest30__wen 1'0 + assign \reg_1_dest31__wen 1'0 + assign \reg_2_dest32__wen 1'0 + assign { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 + sync init + end + process $group_30 + assign \reg_0_dest30__data_i 2'00 + assign \reg_0_dest30__data_i \data_i$1 + sync init + end + process $group_31 + assign \reg_1_dest31__data_i 2'00 + assign \reg_1_dest31__data_i \data_i$1 + sync init + end + process $group_32 + assign \reg_2_dest32__data_i 2'00 + assign \reg_2_dest32__data_i \data_i$1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 \full_rd__data_o + process $group_33 + assign \full_rd__data_o 6'000000 + assign \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \full_rd__ren + process $group_34 + assign \reg_0_r0__ren 1'0 + assign \reg_1_r1__ren 1'0 + assign \reg_2_r2__ren 1'0 + assign { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 \full_wr__data_i + process $group_37 + assign \reg_0_w0__data_i 2'00 + assign \reg_1_w1__data_i 2'00 + assign \reg_2_w2__data_i 2'00 + assign { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \full_wr__wen + process $group_40 + assign \reg_0_w0__wen 1'0 + assign \reg_1_w1__wen 1'0 + assign \reg_2_w2__wen 1'0 + assign { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen + sync init + end + connect \full_rd__ren 3'000 + connect \full_wr__data_i 6'000000 + connect \full_wr__wen 3'000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fast" +module \fast + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 1 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 2 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 3 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 4 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 5 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 8 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 9 \dest1__wen + attribute \src "simple/issuer.py:102" + wire width 1 input 10 \coresync_rst + memory width 64 size 5 \memory + cell $meminit $1 + parameter \MEMID "\\memory" + parameter \ABITS 3 + parameter \WIDTH 64 + parameter \WORDS 5 + parameter \PRIORITY 0 + connect \ADDR 3'000 + connect \DATA 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 3 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 64 \memory_r_data + cell $memrd \rp_src1 + parameter \MEMID "\\memory" + parameter \ABITS 3 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \TRANSPARENT 1 + connect \CLK \coresync_clk + connect \EN 1'1 + connect \ADDR \memory_r_addr + connect \DATA \memory_r_data + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 3 \memory_r_addr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 64 \memory_r_data$3 + cell $memrd \rp_src2 + parameter \MEMID "\\memory" + parameter \ABITS 3 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \TRANSPARENT 1 + connect \CLK \coresync_clk + connect \EN 1'1 + connect \ADDR \memory_r_addr$2 + connect \DATA \memory_r_data$3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + wire width 1 \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + wire width 3 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + wire width 64 \memory_w_data + cell $memwr \wp_dest1 + parameter \MEMID "\\memory" + parameter \ABITS 3 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \PRIORITY 0 + connect \CLK \coresync_clk + connect \EN { { \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en } } + connect \ADDR \memory_w_addr + connect \DATA \memory_w_data + end + process $group_0 + assign \memory_r_addr 3'000 + assign \memory_r_addr \src1__addr + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$next + process $group_1 + assign \ren_delay$next \ren_delay + assign \ren_delay$next \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$next 1'0 + end + sync init + update \ren_delay 1'0 + sync posedge \coresync_clk + update \ren_delay \ren_delay$next + end + process $group_2 + assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + switch { \ren_delay } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + case 1'1 + assign \src1__data_o \memory_r_data + end + sync init + end + process $group_3 + assign \memory_r_addr$2 3'000 + assign \memory_r_addr$2 \src2__addr + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$4$next + process $group_4 + assign \ren_delay$4$next \ren_delay$4 + assign \ren_delay$4$next \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$4$next 1'0 + end + sync init + update \ren_delay$4 1'0 + sync posedge \coresync_clk + update \ren_delay$4 \ren_delay$4$next + end + process $group_5 + assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + switch { \ren_delay$4 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + case 1'1 + assign \src2__data_o \memory_r_data$3 + end + sync init + end + process $group_6 + assign \memory_w_addr 3'000 + assign \memory_w_addr \dest1__addr + sync init + end + process $group_7 + assign \memory_w_en 1'0 + assign \memory_w_en \dest1__wen + sync init + end + process $group_8 + assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \memory_w_data \dest1__data_i + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.state.reg_0" +module \reg_0$417 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \cia0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \nia0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \d_wr10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 64 \reg$next + process $group_0 + assign \cia0__data_o$next \cia0__data_o + assign \cia0__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \cia0__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \nia0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \cia0__data_o$next \nia0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \msr0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \cia0__data_o$next \msr0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \d_wr10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \cia0__data_o$next \d_wr10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \cia0__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cia0__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \cia0__data_o \cia0__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \cia0__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \nia0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \msr0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \d_wr10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \msr0__data_o$next \msr0__data_o + assign \msr0__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \msr0__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \nia0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \msr0__data_o$next \nia0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \msr0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \msr0__data_o$next \msr0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \d_wr10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \msr0__data_o$next \d_wr10__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \msr0__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \msr0__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \msr0__data_o \msr0__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \msr0__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \nia0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \msr0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \d_wr10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + process $group_4 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \nia0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \nia0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \msr0__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \msr0__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \d_wr10__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \d_wr10__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.state.reg_1" +module \reg_1$418 + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "simple/issuer.py:102" + wire width 1 input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 2 \cia1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \nia1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 8 \msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 10 \d_wr11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:58" + wire width 64 \reg$next + process $group_0 + assign \cia1__data_o$next \cia1__data_o + assign \cia1__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \cia1__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \nia1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \cia1__data_o$next \nia1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \msr1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \cia1__data_o$next \msr1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \d_wr11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \cia1__data_o$next \d_wr11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \cia1__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \cia1__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \cia1__data_o \cia1__data_o$next + end + process $group_1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \cia1__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \nia1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \msr1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \d_wr11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect 1'1 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:70" + wire width 1 \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $3 + end + process $group_2 + assign \msr1__data_o$next \msr1__data_o + assign \msr1__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \msr1__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \nia1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \msr1__data_o$next \nia1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \msr1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \msr1__data_o$next \msr1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \d_wr11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \msr1__data_o$next \d_wr11__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76" + case 1'1 + assign \msr1__data_o$next \reg + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \msr1__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \msr1__data_o \msr1__data_o$next + end + process $group_3 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + switch { \msr1__ren } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:68" + case 1'1 + assign \wr_detect$4 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \nia1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \msr1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + switch { \d_wr11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:73" + case 1'1 + assign \wr_detect$4 1'1 + end + end + sync init + end + process $group_4 + assign \reg$next \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \nia1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \nia1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \msr1__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \msr1__data_i + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + switch { \d_wr11__wen } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:83" + case 1'1 + assign \reg$next \d_wr11__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \coresync_clk + update \reg \reg$next + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.state" +module \state + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 1 \cia__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 2 \cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 3 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 4 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 5 \msr__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 6 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 7 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 8 \data_i$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \data_i$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 10 \wen$3 + attribute \src "simple/issuer.py:102" + wire width 1 input 11 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_cia0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_nia0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_0_d_wr10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_d_wr10__data_i + cell \reg_0$417 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cia0__ren \reg_0_cia0__ren + connect \cia0__data_o \reg_0_cia0__data_o + connect \msr0__ren \reg_0_msr0__ren + connect \msr0__data_o \reg_0_msr0__data_o + connect \nia0__wen \reg_0_nia0__wen + connect \nia0__data_i \reg_0_nia0__data_i + connect \msr0__wen \reg_0_msr0__wen + connect \msr0__data_i \reg_0_msr0__data_i + connect \d_wr10__wen \reg_0_d_wr10__wen + connect \d_wr10__data_i \reg_0_d_wr10__data_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_cia1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_nia1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \reg_1_d_wr11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_d_wr11__data_i + cell \reg_1$418 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cia1__ren \reg_1_cia1__ren + connect \cia1__data_o \reg_1_cia1__data_o + connect \msr1__ren \reg_1_msr1__ren + connect \msr1__data_o \reg_1_msr1__data_o + connect \nia1__wen \reg_1_nia1__wen + connect \nia1__data_i \reg_1_nia1__data_i + connect \msr1__wen \reg_1_msr1__wen + connect \msr1__data_i \reg_1_msr1__data_i + connect \d_wr11__wen \reg_1_d_wr11__wen + connect \d_wr11__data_i \reg_1_d_wr11__data_i + end + process $group_0 + assign \reg_0_cia0__ren 1'0 + assign \reg_1_cia1__ren 1'0 + assign { \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 2 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 2 \ren_delay$next + process $group_2 + assign \ren_delay$next \ren_delay + assign \ren_delay$next \cia__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$next 2'00 + end + sync init + update \ren_delay 2'00 + sync posedge \coresync_clk + update \ren_delay \ren_delay$next + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 $6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_cia0__data_o + connect \B \reg_1_cia1__data_o + connect \Y $6 + end + process $group_3 + assign \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + switch { $4 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + case 1'1 + assign \cia__data_o $6 + end + sync init + end + process $group_4 + assign \reg_0_msr0__ren 1'0 + assign \reg_1_msr1__ren 1'0 + assign { \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 2 \ren_delay$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:169" + wire width 2 \ren_delay$8$next + process $group_6 + assign \ren_delay$8$next \ren_delay$8 + assign \ren_delay$8$next \msr__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$8$next 2'00 + end + sync init + update \ren_delay$8 2'00 + sync posedge \coresync_clk + update \ren_delay$8 \ren_delay$8$next + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_bool $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \ren_delay$8 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_msr0__data_o + connect \B \reg_1_msr1__data_o + connect \Y $11 + end + process $group_7 + assign \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:171" + case 1'1 + assign \msr__data_o $11 + end + sync init + end + process $group_8 + assign \reg_0_nia0__wen 1'0 + assign \reg_1_nia1__wen 1'0 + assign { \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen + sync init + end + process $group_10 + assign \reg_0_nia0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_0_nia0__data_i \data_i$1 + sync init + end + process $group_11 + assign \reg_1_nia1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_1_nia1__data_i \data_i$1 + sync init + end + process $group_12 + assign \reg_0_msr0__wen 1'0 + assign \reg_1_msr1__wen 1'0 + assign { \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 + sync init + end + process $group_14 + assign \reg_0_msr0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_0_msr0__data_i \data_i$2 + sync init + end + process $group_15 + assign \reg_1_msr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_1_msr1__data_i \data_i$2 + sync init + end + process $group_16 + assign \reg_0_d_wr10__wen 1'0 + assign \reg_1_d_wr11__wen 1'0 + assign { \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen + sync init + end + process $group_18 + assign \reg_0_d_wr10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_0_d_wr10__data_i \data_i + sync init + end + process $group_19 + assign \reg_1_d_wr11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \reg_1_d_wr11__data_i \data_i + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.spr" +module \spr + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 1 \spr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 input 2 \spr1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 3 \spr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 4 \spr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 input 5 \spr1__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 6 \spr1__wen + attribute \src "simple/issuer.py:102" + wire width 1 input 7 \coresync_rst + memory width 64 size 110 \memory + cell $meminit $2 + parameter \MEMID "\\memory" + parameter \ABITS 7 + parameter \WIDTH 64 + parameter \WORDS 110 + parameter \PRIORITY 0 + connect \ADDR 7'0000000 + connect \DATA 7040'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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+ end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 7 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:209" + wire width 64 \memory_r_data + cell $memrd \rp_spr1 + parameter \MEMID "\\memory" + parameter \ABITS 7 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \TRANSPARENT 1 + connect \CLK \coresync_clk + connect \EN 1'1 + connect \ADDR \memory_r_addr + connect \DATA \memory_r_data + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + wire width 1 \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + wire width 7 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:217" + wire width 64 \memory_w_data + cell $memwr \wp_spr1 + parameter \MEMID "\\memory" + parameter \ABITS 7 + parameter \WIDTH 64 + parameter \CLK_ENABLE 1 + parameter \CLK_POLARITY 1 + parameter \PRIORITY 0 + connect \CLK \coresync_clk + connect \EN { { \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en } } + connect \ADDR \memory_w_addr + connect \DATA \memory_w_data + end + process $group_0 + assign \memory_r_addr 7'0000000 + assign \memory_r_addr \spr1__addr + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:242" + wire width 1 \ren_delay$next + process $group_1 + assign \ren_delay$next \ren_delay + assign \ren_delay$next \spr1__ren + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \ren_delay$next 1'0 + end + sync init + update \ren_delay 1'0 + sync posedge \coresync_clk + update \ren_delay \ren_delay$next + end + process $group_2 + assign \spr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + switch { \ren_delay } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:244" + case 1'1 + assign \spr1__data_o \memory_r_data + end + sync init + end + process $group_3 + assign \memory_w_addr 7'0000000 + assign \memory_w_addr \spr1__addr$1 + sync init + end + process $group_4 + assign \memory_w_en 1'0 + assign \memory_w_en \spr1__wen + sync init + end + process $group_5 + assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \memory_w_data \spr1__data_i + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra" +module \rdpick_INT_ra + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 9 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 9 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 9 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 9 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 9 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 9'000000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] } + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $32 + connect \Y $31 + end + process $group_9 + assign \t8 1'0 + assign \t8 $31 + sync init + end + process $group_10 + assign \o 9'000000000 + assign \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $35 + end + process $group_11 + assign \en_o 1'0 + assign \en_o $35 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rb" +module \rdpick_INT_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 8 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 8'00000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + process $group_9 + assign \o 8'00000000 + assign \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $31 + end + process $group_10 + assign \en_o 1'0 + assign \en_o $31 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rc" +module \rdpick_INT_rc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 2 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 2'00 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + process $group_3 + assign \o 2'00 + assign \o { \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $7 + end + process $group_4 + assign \en_o 1'0 + assign \en_o $7 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so" +module \rdpick_XER_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 4 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 4'0000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + process $group_5 + assign \o 4'0000 + assign \o { \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $15 + end + process $group_6 + assign \en_o 1'0 + assign \en_o $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca" +module \rdpick_XER_xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 3 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 3'000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + process $group_4 + assign \o 3'000 + assign \o { \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $11 + end + process $group_5 + assign \en_o 1'0 + assign \en_o $11 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ov" +module \rdpick_XER_xer_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 1'0 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i + sync init + end + process $group_2 + assign \o 1'0 + assign \o { \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $3 + end + process $group_3 + assign \en_o 1'0 + assign \en_o $3 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr" +module \rdpick_CR_full_cr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 1'0 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i + sync init + end + process $group_2 + assign \o 1'0 + assign \o { \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $3 + end + process $group_3 + assign \en_o 1'0 + assign \en_o $3 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_a" +module \rdpick_CR_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 2 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 2'00 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + process $group_3 + assign \o 2'00 + assign \o { \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $7 + end + process $group_4 + assign \en_o 1'0 + assign \en_o $7 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_b" +module \rdpick_CR_cr_b + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 1'0 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i + sync init + end + process $group_2 + assign \o 1'0 + assign \o { \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $3 + end + process $group_3 + assign \en_o 1'0 + assign \en_o $3 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c" +module \rdpick_CR_cr_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 1'0 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i + sync init + end + process $group_2 + assign \o 1'0 + assign \o { \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $3 + end + process $group_3 + assign \en_o 1'0 + assign \en_o $3 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1" +module \rdpick_FAST_fast1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 3 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 3'000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + process $group_4 + assign \o 3'000 + assign \o { \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $11 + end + process $group_5 + assign \en_o 1'0 + assign \en_o $11 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2" +module \rdpick_FAST_fast2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 2 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 2'00 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + process $group_3 + assign \o 2'00 + assign \o { \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $7 + end + process $group_4 + assign \en_o 1'0 + assign \en_o $7 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1" +module \rdpick_SPR_spr1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 1'0 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i + sync init + end + process $group_2 + assign \o 1'0 + assign \o { \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $3 + end + process $group_3 + assign \en_o 1'0 + assign \en_o $3 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o" +module \wrpick_INT_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 10 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 10 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 10 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 10 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 10 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 10'0000000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end + process $group_7 + assign \t6 1'0 + assign \t6 $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] } + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $28 + connect \Y $27 + end + process $group_8 + assign \t7 1'0 + assign \t7 $27 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] } + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $32 + connect \Y $31 + end + process $group_9 + assign \t8 1'0 + assign \t8 $31 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A { \i [8:0] [8] \i [8:0] [7] \i [8:0] [6] \i [8:0] [5] \i [8:0] [4] \i [8:0] [3] \i [8:0] [2] \i [8:0] [1] \i [8:0] [0] \ni [9] } + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $36 + connect \Y $35 + end + process $group_10 + assign \t9 1'0 + assign \t9 $35 + sync init + end + process $group_11 + assign \o 10'0000000000 + assign \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $39 + end + process $group_12 + assign \en_o 1'0 + assign \en_o $39 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr" +module \wrpick_CR_full_cr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 1'0 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i + sync init + end + process $group_2 + assign \o 1'0 + assign \o { \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $3 + end + process $group_3 + assign \en_o 1'0 + assign \en_o $3 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a" +module \wrpick_CR_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 6 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 6 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 6'000000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] } + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $20 + connect \Y $19 + end + process $group_6 + assign \t5 1'0 + assign \t5 $19 + sync init + end + process $group_7 + assign \o 6'000000 + assign \o { \t5 \t4 \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $23 + end + process $group_8 + assign \en_o 1'0 + assign \en_o $23 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca" +module \wrpick_XER_xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 4 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 4'0000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + process $group_5 + assign \o 4'0000 + assign \o { \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $15 + end + process $group_6 + assign \en_o 1'0 + assign \en_o $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov" +module \wrpick_XER_xer_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 4 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 4'0000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + process $group_5 + assign \o 4'0000 + assign \o { \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $15 + end + process $group_6 + assign \en_o 1'0 + assign \en_o $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so" +module \wrpick_XER_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 4 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 4'0000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + process $group_5 + assign \o 4'0000 + assign \o { \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $15 + end + process $group_6 + assign \en_o 1'0 + assign \en_o $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast1" +module \wrpick_FAST_fast1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 5 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 5 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 5 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 5 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 5'00000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + process $group_6 + assign \o 5'00000 + assign \o { \t4 \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $19 + end + process $group_7 + assign \en_o 1'0 + assign \en_o $19 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_nia" +module \wrpick_STATE_nia + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 2 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 2'00 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + process $group_3 + assign \o 2'00 + assign \o { \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $7 + end + process $group_4 + assign \en_o 1'0 + assign \en_o $7 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_msr" +module \wrpick_STATE_msr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 1'0 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i + sync init + end + process $group_2 + assign \o 1'0 + assign \o { \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $3 + end + process $group_3 + assign \en_o 1'0 + assign \en_o $3 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_SPR_spr1" +module \wrpick_SPR_spr1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 1'0 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i + sync init + end + process $group_2 + assign \o 1'0 + assign \o { \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $3 + end + process $group_3 + assign \en_o 1'0 + assign \en_o $3 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core" +module \core + attribute \src "simple/issuer.py:102" + wire width 1 input 0 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88" + wire width 1 input 1 \core_reset_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:84" + wire width 1 output 2 \corebusy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 output 3 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 input 4 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 output 5 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 input 6 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 7 \cia__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 8 \cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 10 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \msr__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + wire width 1 output 12 \core_terminate_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" + wire width 1 \core_terminate_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 input 13 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 input 14 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 input 15 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 16 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 input 17 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 18 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 input 19 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 20 \reg3_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 input 21 \spro + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute 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attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute 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attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 input 22 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 23 \spr1_ok + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest3_o$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest2_o$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest3_o$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_nia_ok$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest3_o$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest4_o$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest5_o$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 \fus_dest2_o$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire width 1 \fus_ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire width 1 \fus_ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire width 1 \fus_ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 \fus_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 \fus_ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire width 1 \fus_ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire width 1 \fus_ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fus_ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fus_ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fus_ldst_port0_st_data_i_ok + cell \fus \fus + connect \coresync_clk \coresync_clk + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_st__go_i \cu_st__go_i + connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__imm \fus_oper_i_alu_alu0__imm_data__imm + connect \oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm_ok + connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc_ok + connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe_ok + connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a + connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn + connect \cu_issue_i \fus_cu_issue_i + connect \cu_busy_o \fus_cu_busy_o + connect \cu_rdmaskn_i \fus_cu_rdmaskn_i + connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type + connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__read_cr_whole \fus_oper_i_alu_cr0__read_cr_whole + connect \oper_i_alu_cr0__write_cr_whole \fus_oper_i_alu_cr0__write_cr_whole + connect \cu_issue_i$1 \fus_cu_issue_i$3 + connect \cu_busy_o$2 \fus_cu_busy_o$4 + connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$5 + connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__imm_data__imm \fus_oper_i_alu_branch0__imm_data__imm + connect \oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm_ok + connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk + connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit + connect \cu_issue_i$4 \fus_cu_issue_i$6 + connect \cu_busy_o$5 \fus_cu_busy_o$7 + connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$8 + connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype + connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr + connect \cu_issue_i$7 \fus_cu_issue_i$9 + connect \cu_busy_o$8 \fus_cu_busy_o$10 + connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$11 + connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__imm \fus_oper_i_alu_logical0__imm_data__imm + connect \oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm_ok + connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc_ok + connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe_ok + connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a + connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn + connect \cu_issue_i$10 \fus_cu_issue_i$12 + connect \cu_busy_o$11 \fus_cu_busy_o$13 + connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$14 + connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit + connect \cu_issue_i$13 \fus_cu_issue_i$15 + connect \cu_busy_o$14 \fus_cu_busy_o$16 + connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$17 + connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__imm \fus_oper_i_alu_div0__imm_data__imm + connect \oper_i_alu_div0__imm_data__imm_ok \fus_oper_i_alu_div0__imm_data__imm_ok + connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__rc__rc_ok \fus_oper_i_alu_div0__rc__rc_ok + connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__oe_ok \fus_oper_i_alu_div0__oe__oe_ok + connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a + connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry @@ -142771,9 +226337,6 @@ module \core connect \oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc_ok connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe connect \oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe_ok - connect \oper_i_alu_mul0__invert_a \fus_oper_i_alu_mul0__invert_a - connect \oper_i_alu_mul0__zero_a \fus_oper_i_alu_mul0__zero_a - connect \oper_i_alu_mul0__invert_out \fus_oper_i_alu_mul0__invert_out connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed @@ -142818,41 +226381,41 @@ module \core connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$29 connect \cu_rd__rel_o \fus_cu_rd__rel_o connect \cu_rd__go_i \fus_cu_rd__go_i - connect \src2_i \fus_src2_i + connect \src1_i \fus_src1_i connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$30 connect \cu_rd__go_i$29 \fus_cu_rd__go_i$31 - connect \src2_i$30 \fus_src2_i$32 + connect \src1_i$30 \fus_src1_i$32 connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$33 connect \cu_rd__go_i$32 \fus_cu_rd__go_i$34 - connect \src2_i$33 \fus_src2_i$35 + connect \src1_i$33 \fus_src1_i$35 connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$36 connect \cu_rd__go_i$35 \fus_cu_rd__go_i$37 - connect \src2_i$36 \fus_src2_i$38 + connect \src1_i$36 \fus_src1_i$38 connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$39 connect \cu_rd__go_i$38 \fus_cu_rd__go_i$40 - connect \src2_i$39 \fus_src2_i$41 + connect \src1_i$39 \fus_src1_i$41 connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$42 connect \cu_rd__go_i$41 \fus_cu_rd__go_i$43 - connect \src2_i$42 \fus_src2_i$44 + connect \src1_i$42 \fus_src1_i$44 connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$45 connect \cu_rd__go_i$44 \fus_cu_rd__go_i$46 - connect \src2_i$45 \fus_src2_i$47 + connect \src1_i$45 \fus_src1_i$47 connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$48 connect \cu_rd__go_i$47 \fus_cu_rd__go_i$49 - connect \src2_i$48 \fus_src2_i$50 - connect \src3_i \fus_src3_i - connect \src3_i$49 \fus_src3_i$51 - connect \src1_i \fus_src1_i - connect \src1_i$50 \fus_src1_i$52 + connect \src1_i$48 \fus_src1_i$50 + connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$51 + connect \cu_rd__go_i$50 \fus_cu_rd__go_i$52 connect \src1_i$51 \fus_src1_i$53 - connect \src1_i$52 \fus_src1_i$54 - connect \cu_rd__rel_o$53 \fus_cu_rd__rel_o$55 - connect \cu_rd__go_i$54 \fus_cu_rd__go_i$56 - connect \src1_i$55 \fus_src1_i$57 - connect \src1_i$56 \fus_src1_i$58 - connect \src1_i$57 \fus_src1_i$59 - connect \src1_i$58 \fus_src1_i$60 - connect \src1_i$59 \fus_src1_i$61 + connect \src2_i \fus_src2_i + connect \src2_i$52 \fus_src2_i$54 + connect \src2_i$53 \fus_src2_i$55 + connect \src2_i$54 \fus_src2_i$56 + connect \src2_i$55 \fus_src2_i$57 + connect \src2_i$56 \fus_src2_i$58 + connect \src2_i$57 \fus_src2_i$59 + connect \src2_i$58 \fus_src2_i$60 + connect \src3_i \fus_src3_i + connect \src3_i$59 \fus_src3_i$61 connect \src3_i$60 \fus_src3_i$62 connect \src4_i \fus_src4_i connect \src3_i$61 \fus_src3_i$63 @@ -142969,6 +226532,23 @@ module \core connect \spr1_ok \fus_spr1_ok connect \dest2_o$150 \fus_dest2_o$152 connect \coresync_rst \coresync_rst + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + end + cell \l0 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i connect \ldst_port0_data_len \fus_ldst_port0_data_len @@ -142980,17258 +226560,63922 @@ module \core connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \dbus__cyc \dbus__cyc + connect \dbus__ack \dbus__ack + connect \dbus__err \dbus__err + connect \dbus__stb \dbus__stb + connect \dbus__sel \dbus__sel + connect \dbus__dat_r \dbus__dat_r + connect \dbus__adr \dbus__adr + connect \dbus__we \dbus__we + connect \dbus__dat_w \dbus__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \int_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \int_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_src3__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \int_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \int_dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \int_dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \int_dest1__wen + cell \int \int + connect \coresync_clk \coresync_clk + connect \dmi__addr \dmi__addr + connect \dmi__ren \dmi__ren + connect \dmi__data_o \dmi__data_o + connect \src1__data_o \int_src1__data_o + connect \src1__addr \int_src1__addr + connect \src1__ren \int_src1__ren + connect \src2__data_o \int_src2__data_o + connect \src2__addr \int_src2__addr + connect \src2__ren \int_src2__ren + connect \src3__data_o \int_src3__data_o + connect \src3__addr \int_src3__addr + connect \src3__ren \int_src3__ren + connect \dest1__data_i \int_dest1__data_i + connect \dest1__addr \int_dest1__addr + connect \dest1__wen \int_dest1__wen + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \cr_full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \cr_full_wr__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_full_wr__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_wen + cell \cr \cr + connect \coresync_clk \coresync_clk + connect \full_rd__data_o \cr_full_rd__data_o + connect \full_rd__ren \cr_full_rd__ren + connect \src1__data_o \cr_src1__data_o + connect \src1__ren \cr_src1__ren + connect \src2__data_o \cr_src2__data_o + connect \src2__ren \cr_src2__ren + connect \src3__data_o \cr_src3__data_o + connect \src3__ren \cr_src3__ren + connect \full_wr__data_i \cr_full_wr__data_i + connect \full_wr__wen \cr_full_wr__wen + connect \data_i \cr_data_i + connect \wen \cr_wen + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_data_i$153 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_wen$154 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_data_i$155 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_wen$156 + cell \xer \xer + connect \coresync_clk \coresync_clk + connect \src1__data_o \xer_src1__data_o + connect \src1__ren \xer_src1__ren + connect \src2__data_o \xer_src2__data_o + connect \src2__ren \xer_src2__ren + connect \src3__data_o \xer_src3__data_o + connect \src3__ren \xer_src3__ren + connect \data_i \xer_data_i + connect \wen \xer_wen + connect \data_i$1 \xer_data_i$153 + connect \wen$2 \xer_wen$154 + connect \data_i$3 \xer_data_i$155 + connect \wen$4 \xer_wen$156 + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \fast_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \fast_src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \fast_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \fast_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \fast_src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \fast_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \fast_dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \fast_dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \fast_dest1__wen + cell \fast \fast + connect \coresync_clk \coresync_clk + connect \src1__data_o \fast_src1__data_o + connect \src1__addr \fast_src1__addr + connect \src1__ren \fast_src1__ren + connect \src2__data_o \fast_src2__data_o + connect \src2__addr \fast_src2__addr + connect \src2__ren \fast_src2__ren + connect \dest1__data_i \fast_dest1__data_i + connect \dest1__addr \fast_dest1__addr + connect \dest1__wen \fast_dest1__wen + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \state_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \state_data_i$157 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \state_wen + cell \state \state + connect \coresync_clk \coresync_clk + connect \cia__ren \cia__ren + connect \cia__data_o \cia__data_o + connect \wen \wen + connect \data_i \data_i + connect \msr__ren \msr__ren + connect \msr__data_o \msr__data_o + connect \state_nia_wen \state_nia_wen + connect \data_i$1 \state_data_i + connect \data_i$2 \state_data_i$157 + connect \wen$3 \state_wen + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \spr_spr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 \spr_spr1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \spr_spr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \spr_spr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 \spr_spr1__addr$158 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \spr_spr1__wen + cell \spr \spr + connect \coresync_clk \coresync_clk + connect \spr1__data_o \spr_spr1__data_o + connect \spr1__addr \spr_spr1__addr + connect \spr1__ren \spr_spr1__ren + connect \spr1__data_i \spr_spr1__data_i + connect \spr1__addr$1 \spr_spr1__addr$158 + connect \spr1__wen \spr_spr1__wen + connect \coresync_rst \coresync_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 9 \rdpick_INT_ra_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 9 \rdpick_INT_ra_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_INT_ra_en_o + cell \rdpick_INT_ra \rdpick_INT_ra + connect \i \rdpick_INT_ra_i + connect \o \rdpick_INT_ra_o + connect \en_o \rdpick_INT_ra_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 8 \rdpick_INT_rb_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 8 \rdpick_INT_rb_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_INT_rb_en_o + cell \rdpick_INT_rb \rdpick_INT_rb + connect \i \rdpick_INT_rb_i + connect \o \rdpick_INT_rb_o + connect \en_o \rdpick_INT_rb_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 \rdpick_INT_rc_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 2 \rdpick_INT_rc_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_INT_rc_en_o + cell \rdpick_INT_rc \rdpick_INT_rc + connect \i \rdpick_INT_rc_i + connect \o \rdpick_INT_rc_o + connect \en_o \rdpick_INT_rc_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 4 \rdpick_XER_xer_so_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 4 \rdpick_XER_xer_so_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_XER_xer_so_en_o + cell \rdpick_XER_xer_so \rdpick_XER_xer_so + connect \i \rdpick_XER_xer_so_i + connect \o \rdpick_XER_xer_so_o + connect \en_o \rdpick_XER_xer_so_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 3 \rdpick_XER_xer_ca_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 3 \rdpick_XER_xer_ca_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_XER_xer_ca_en_o + cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca + connect \i \rdpick_XER_xer_ca_i + connect \o \rdpick_XER_xer_ca_o + connect \en_o \rdpick_XER_xer_ca_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \rdpick_XER_xer_ov_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \rdpick_XER_xer_ov_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_XER_xer_ov_en_o + cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov + connect \i \rdpick_XER_xer_ov_i + connect \o \rdpick_XER_xer_ov_o + connect \en_o \rdpick_XER_xer_ov_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \rdpick_CR_full_cr_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \rdpick_CR_full_cr_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_CR_full_cr_en_o + cell \rdpick_CR_full_cr \rdpick_CR_full_cr + connect \i \rdpick_CR_full_cr_i + connect \o \rdpick_CR_full_cr_o + connect \en_o \rdpick_CR_full_cr_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 \rdpick_CR_cr_a_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 2 \rdpick_CR_cr_a_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_CR_cr_a_en_o + cell \rdpick_CR_cr_a \rdpick_CR_cr_a + connect \i \rdpick_CR_cr_a_i + connect \o \rdpick_CR_cr_a_o + connect \en_o \rdpick_CR_cr_a_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \rdpick_CR_cr_b_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \rdpick_CR_cr_b_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_CR_cr_b_en_o + cell \rdpick_CR_cr_b \rdpick_CR_cr_b + connect \i \rdpick_CR_cr_b_i + connect \o \rdpick_CR_cr_b_o + connect \en_o \rdpick_CR_cr_b_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \rdpick_CR_cr_c_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \rdpick_CR_cr_c_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_CR_cr_c_en_o + cell \rdpick_CR_cr_c \rdpick_CR_cr_c + connect \i \rdpick_CR_cr_c_i + connect \o \rdpick_CR_cr_c_o + connect \en_o \rdpick_CR_cr_c_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 3 \rdpick_FAST_fast1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 3 \rdpick_FAST_fast1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_FAST_fast1_en_o + cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 + connect \i \rdpick_FAST_fast1_i + connect \o \rdpick_FAST_fast1_o + connect \en_o \rdpick_FAST_fast1_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 \rdpick_FAST_fast2_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 2 \rdpick_FAST_fast2_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_FAST_fast2_en_o + cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 + connect \i \rdpick_FAST_fast2_i + connect \o \rdpick_FAST_fast2_o + connect \en_o \rdpick_FAST_fast2_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \rdpick_SPR_spr1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \rdpick_SPR_spr1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_SPR_spr1_en_o + cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 + connect \i \rdpick_SPR_spr1_i + connect \o \rdpick_SPR_spr1_o + connect \en_o \rdpick_SPR_spr1_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 10 \wrpick_INT_o_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 10 \wrpick_INT_o_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_INT_o_en_o + cell \wrpick_INT_o \wrpick_INT_o + connect \i \wrpick_INT_o_i + connect \o \wrpick_INT_o_o + connect \en_o \wrpick_INT_o_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \wrpick_CR_full_cr_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \wrpick_CR_full_cr_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_CR_full_cr_en_o + cell \wrpick_CR_full_cr \wrpick_CR_full_cr + connect \i \wrpick_CR_full_cr_i + connect \o \wrpick_CR_full_cr_o + connect \en_o \wrpick_CR_full_cr_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 6 \wrpick_CR_cr_a_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 6 \wrpick_CR_cr_a_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_CR_cr_a_en_o + cell \wrpick_CR_cr_a \wrpick_CR_cr_a + connect \i \wrpick_CR_cr_a_i + connect \o \wrpick_CR_cr_a_o + connect \en_o \wrpick_CR_cr_a_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 4 \wrpick_XER_xer_ca_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 4 \wrpick_XER_xer_ca_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_XER_xer_ca_en_o + cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca + connect \i \wrpick_XER_xer_ca_i + connect \o \wrpick_XER_xer_ca_o + connect \en_o \wrpick_XER_xer_ca_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 4 \wrpick_XER_xer_ov_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 4 \wrpick_XER_xer_ov_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_XER_xer_ov_en_o + cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov + connect \i \wrpick_XER_xer_ov_i + connect \o \wrpick_XER_xer_ov_o + connect \en_o \wrpick_XER_xer_ov_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 4 \wrpick_XER_xer_so_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 4 \wrpick_XER_xer_so_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_XER_xer_so_en_o + cell \wrpick_XER_xer_so \wrpick_XER_xer_so + connect \i \wrpick_XER_xer_so_i + connect \o \wrpick_XER_xer_so_o + connect \en_o \wrpick_XER_xer_so_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 5 \wrpick_FAST_fast1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 5 \wrpick_FAST_fast1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_FAST_fast1_en_o + cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 + connect \i \wrpick_FAST_fast1_i + connect \o \wrpick_FAST_fast1_o + connect \en_o \wrpick_FAST_fast1_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 \wrpick_STATE_nia_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 2 \wrpick_STATE_nia_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_STATE_nia_en_o + cell \wrpick_STATE_nia \wrpick_STATE_nia + connect \i \wrpick_STATE_nia_i + connect \o \wrpick_STATE_nia_o + connect \en_o \wrpick_STATE_nia_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \wrpick_STATE_msr_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \wrpick_STATE_msr_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_STATE_msr_en_o + cell \wrpick_STATE_msr \wrpick_STATE_msr + connect \i \wrpick_STATE_msr_i + connect \o \wrpick_STATE_msr_o + connect \en_o \wrpick_STATE_msr_en_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \wrpick_SPR_spr1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \wrpick_SPR_spr1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_SPR_spr1_en_o + cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 + connect \i \wrpick_SPR_spr1_i + connect \o \wrpick_SPR_spr1_o + connect \en_o \wrpick_SPR_spr1_en_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + wire width 1 \en_alu0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 1 $159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 11 $160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $and $161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 2'10 + connect \Y $160 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $reduce_bool $162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $160 + connect \Y $159 + end + process $group_0 + assign \en_alu0 1'0 + assign \en_alu0 $159 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:127" + wire width 10 \fu_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + wire width 1 \en_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + wire width 1 \en_branch0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + wire width 1 \en_trap0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + wire width 1 \en_logical0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + wire width 1 \en_spr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + wire width 1 \en_div0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + wire width 1 \en_mul0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + wire width 1 \en_shiftrot0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:137" + wire width 1 \en_ldst0 + process $group_1 + assign \fu_enable 10'0000000000 + assign \fu_enable [0] \en_alu0 + assign \fu_enable [1] \en_cr0 + assign \fu_enable [2] \en_branch0 + assign \fu_enable [3] \en_trap0 + assign \fu_enable [4] \en_logical0 + assign \fu_enable [5] \en_spr0 + assign \fu_enable [6] \en_div0 + assign \fu_enable [7] \en_mul0 + assign \fu_enable [8] \en_shiftrot0 + assign \fu_enable [9] \en_ldst0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 1 $163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 11 $164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $and $165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 7'1000000 + connect \Y $164 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $reduce_bool $166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $164 + connect \Y $163 + end + process $group_2 + assign \en_cr0 1'0 + assign \en_cr0 $163 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 1 $167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 11 $168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $and $169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 6'100000 + connect \Y $168 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $reduce_bool $170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $168 + connect \Y $167 + end + process $group_3 + assign \en_branch0 1'0 + assign \en_branch0 $167 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 1 $171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 11 $172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $and $173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 8'10000000 + connect \Y $172 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $reduce_bool $174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $172 + connect \Y $171 + end + process $group_4 + assign \en_trap0 1'0 + assign \en_trap0 $171 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 1 $175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 11 $176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $and $177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 5'10000 + connect \Y $176 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $reduce_bool $178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $176 + connect \Y $175 + end + process $group_5 + assign \en_logical0 1'0 + assign \en_logical0 $175 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 1 $179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 11 $180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $and $181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 11 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 11'10000000000 + connect \Y $180 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $reduce_bool $182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $180 + connect \Y $179 + end + process $group_6 + assign \en_spr0 1'0 + assign \en_spr0 $179 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 1 $183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 11 $184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $and $185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 10'1000000000 + connect \Y $184 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $reduce_bool $186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $184 + connect \Y $183 + end + process $group_7 + assign \en_div0 1'0 + assign \en_div0 $183 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 1 $187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 11 $188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $and $189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 9 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 9'100000000 + connect \Y $188 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $reduce_bool $190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $188 + connect \Y $187 + end + process $group_8 + assign \en_mul0 1'0 + assign \en_mul0 $187 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 1 $191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 11 $192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $and $193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 4'1000 + connect \Y $192 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $reduce_bool $194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $192 + connect \Y $191 + end + process $group_9 + assign \en_shiftrot0 1'0 + assign \en_shiftrot0 $191 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 1 $195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + wire width 11 $196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $and $197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 3'100 + connect \Y $196 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138" + cell $reduce_bool $198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $196 + connect \Y $195 + end + process $group_10 + assign \en_ldst0 1'0 + assign \en_ldst0 $195 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:142" + wire width 2 \counter + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:142" + wire width 2 \counter$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" + wire width 1 $199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" + cell $ne $200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \counter + connect \B 1'0 + connect \Y $199 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144" + wire width 3 $201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144" + wire width 3 $202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144" + cell $sub $203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \counter + connect \B 1'1 + connect \Y $202 + end + connect $201 $202 + process $group_11 + assign \counter$next \counter + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" + switch { $199 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" + case 1'1 + assign \counter$next $201 [1:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + assign \counter$next 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \counter$next 2'00 + end + sync init + update \counter 2'00 + sync posedge \coresync_clk + update \counter \counter$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" + wire width 1 $204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" + cell $ne $205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \counter + connect \B 1'0 + connect \Y $204 + end + process $group_12 + assign \corebusy_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" + switch { $204 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143" + case 1'1 + assign \corebusy_o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + assign \corebusy_o 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \corebusy_o \fus_cu_busy_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \corebusy_o \fus_cu_busy_o$4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \corebusy_o \fus_cu_busy_o$7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \corebusy_o \fus_cu_busy_o$10 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \corebusy_o \fus_cu_busy_o$13 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \corebusy_o \fus_cu_busy_o$16 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \corebusy_o \fus_cu_busy_o$19 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \corebusy_o \fus_cu_busy_o$22 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \corebusy_o \fus_cu_busy_o$25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \corebusy_o \fus_cu_busy_o$28 + end + end + end + sync init + end + process $group_13 + assign \core_terminate_o$next \core_terminate_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + assign \core_terminate_o$next 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \core_terminate_o$next 1'0 + end + sync init + update \core_terminate_o 1'0 + sync posedge \coresync_clk + update \core_terminate_o \core_terminate_o$next + end + process $group_14 + assign \fus_oper_i_alu_alu0__insn_type 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__insn_type \insn_type + end + end + end + sync init + end + process $group_15 + assign \fus_oper_i_alu_alu0__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__fn_unit \fn_unit + end + end + end + sync init + end + process $group_16 + assign \fus_oper_i_alu_alu0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_alu0__imm_data__imm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm } { \imm_ok \imm } + end + end + end + sync init + end + process $group_18 + assign \fus_oper_i_alu_alu0__rc__rc 1'0 + assign \fus_oper_i_alu_alu0__rc__rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc } { \rc_ok \rc } + end + end + end + sync init + end + process $group_20 + assign \fus_oper_i_alu_alu0__oe__oe 1'0 + assign \fus_oper_i_alu_alu0__oe__oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe } { \oe_ok \oe } + end + end + end + sync init + end + process $group_22 + assign \fus_oper_i_alu_alu0__invert_in 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__invert_in \invert_in + end + end + end + sync init + end + process $group_23 + assign \fus_oper_i_alu_alu0__zero_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__zero_a \zero_a + end + end + end + sync init + end + process $group_24 + assign \fus_oper_i_alu_alu0__invert_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__invert_out \invert_out + end + end + end + sync init + end + process $group_25 + assign \fus_oper_i_alu_alu0__write_cr0 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__write_cr0 \write_cr0 + end + end + end + sync init + end + process $group_26 + assign \fus_oper_i_alu_alu0__input_carry 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__input_carry \input_carry + end + end + end + sync init + end + process $group_27 + assign \fus_oper_i_alu_alu0__output_carry 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__output_carry \output_carry + end + end + end + sync init + end + process $group_28 + assign \fus_oper_i_alu_alu0__is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__is_32bit \is_32bit + end + end + end + sync init + end + process $group_29 + assign \fus_oper_i_alu_alu0__is_signed 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__is_signed \is_signed + end + end + end + sync init + end + process $group_30 + assign \fus_oper_i_alu_alu0__data_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__data_len \data_len + end + end + end + sync init + end + process $group_31 + assign \fus_oper_i_alu_alu0__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_alu0__insn \insn + end + end + end + sync init + end + process $group_32 + assign \fus_cu_issue_i 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_issue_i \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + wire width 4 $206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $and $208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $207 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $or $210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $207 + connect \B \xer_in + connect \Y $209 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire width 1 $211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $eq $212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \input_carry + connect \B 2'10 + connect \Y $211 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire width 1 $213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $or $214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $211 + connect \B \xer_in + connect \Y $213 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + cell $not $215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { $213 $209 \reg2_ok \reg1_ok } + connect \Y $206 + end + process $group_33 + assign \fus_cu_rdmaskn_i 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_rdmaskn_i $206 + end + end + end + sync init + end + process $group_34 + assign \fus_oper_i_alu_cr0__insn_type 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_cr0__insn_type \insn_type + end + end + end + sync init + end + process $group_35 + assign \fus_oper_i_alu_cr0__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_cr0__fn_unit \fn_unit + end + end + end + sync init + end + process $group_36 + assign \fus_oper_i_alu_cr0__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_cr0__insn \insn + end + end + end + sync init + end + process $group_37 + assign \fus_oper_i_alu_cr0__read_cr_whole 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_cr0__read_cr_whole \read_cr_whole + end + end + end + sync init + end + process $group_38 + assign \fus_oper_i_alu_cr0__write_cr_whole 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_cr0__write_cr_whole \write_cr_whole + end + end + end + sync init + end + process $group_39 + assign \fus_cu_issue_i$3 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_issue_i$3 \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + wire width 6 $216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + cell $not $217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { \cr_in2_ok$2 \cr_in2_ok \cr_in1_ok \read_cr_whole \reg2_ok \reg1_ok } + connect \Y $216 + end + process $group_40 + assign \fus_cu_rdmaskn_i$5 6'000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_rdmaskn_i$5 $216 + end + end + end + sync init + end + process $group_41 + assign \fus_oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_branch0__cia \cia + end + end + end + sync init + end + process $group_42 + assign \fus_oper_i_alu_branch0__insn_type 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_branch0__insn_type \insn_type + end + end + end + sync init + end + process $group_43 + assign \fus_oper_i_alu_branch0__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_branch0__fn_unit \fn_unit + end + end + end + sync init + end + process $group_44 + assign \fus_oper_i_alu_branch0__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_branch0__insn \insn + end + end + end + sync init + end + process $group_45 + assign \fus_oper_i_alu_branch0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_branch0__imm_data__imm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm } { \imm_ok \imm } + end + end + end + sync init + end + process $group_47 + assign \fus_oper_i_alu_branch0__lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_branch0__lk \lk + end + end + end + sync init + end + process $group_48 + assign \fus_oper_i_alu_branch0__is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_branch0__is_32bit \is_32bit + end + end + end + sync init + end + process $group_49 + assign \fus_cu_issue_i$6 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_issue_i$6 \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + wire width 3 $218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + cell $not $219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \cr_in1_ok \fast2_ok \fast1_ok } + connect \Y $218 + end + process $group_50 + assign \fus_cu_rdmaskn_i$8 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_rdmaskn_i$8 $218 + end + end + end + sync init + end + process $group_51 + assign \fus_oper_i_alu_trap0__insn_type 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_trap0__insn_type \insn_type + end + end + end + sync init + end + process $group_52 + assign \fus_oper_i_alu_trap0__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_trap0__fn_unit \fn_unit + end + end + end + sync init + end + process $group_53 + assign \fus_oper_i_alu_trap0__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_trap0__insn \insn + end + end + end + sync init + end + process $group_54 + assign \fus_oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_trap0__msr \msr + end + end + end + sync init + end + process $group_55 + assign \fus_oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_trap0__cia \cia + end + end + end + sync init + end + process $group_56 + assign \fus_oper_i_alu_trap0__is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_trap0__is_32bit \is_32bit + end + end + end + sync init + end + process $group_57 + assign \fus_oper_i_alu_trap0__traptype 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_trap0__traptype \traptype + end + end + end + sync init + end + process $group_58 + assign \fus_oper_i_alu_trap0__trapaddr 13'0000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_trap0__trapaddr \trapaddr + end + end + end + sync init + end + process $group_59 + assign \fus_cu_issue_i$9 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_issue_i$9 \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + wire width 4 $220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + cell $not $221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { \fast2_ok \fast1_ok \reg2_ok \reg1_ok } + connect \Y $220 + end + process $group_60 + assign \fus_cu_rdmaskn_i$11 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_rdmaskn_i$11 $220 + end + end + end + sync init + end + process $group_61 + assign \fus_oper_i_alu_logical0__insn_type 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__insn_type \insn_type + end + end + end + sync init + end + process $group_62 + assign \fus_oper_i_alu_logical0__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__fn_unit \fn_unit + end + end + end + sync init + end + process $group_63 + assign \fus_oper_i_alu_logical0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_logical0__imm_data__imm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm } { \imm_ok \imm } + end + end + end + sync init + end + process $group_65 + assign \fus_oper_i_alu_logical0__rc__rc 1'0 + assign \fus_oper_i_alu_logical0__rc__rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc } { \rc_ok \rc } + end + end + end + sync init + end + process $group_67 + assign \fus_oper_i_alu_logical0__oe__oe 1'0 + assign \fus_oper_i_alu_logical0__oe__oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe } { \oe_ok \oe } + end + end + end + sync init + end + process $group_69 + assign \fus_oper_i_alu_logical0__invert_in 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__invert_in \invert_in + end + end + end + sync init + end + process $group_70 + assign \fus_oper_i_alu_logical0__zero_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__zero_a \zero_a + end + end + end + sync init + end + process $group_71 + assign \fus_oper_i_alu_logical0__input_carry 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__input_carry \input_carry + end + end + end + sync init + end + process $group_72 + assign \fus_oper_i_alu_logical0__invert_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__invert_out \invert_out + end + end + end + sync init + end + process $group_73 + assign \fus_oper_i_alu_logical0__write_cr0 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__write_cr0 \write_cr0 + end + end + end + sync init + end + process $group_74 + assign \fus_oper_i_alu_logical0__output_carry 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__output_carry \output_carry + end + end + end + sync init + end + process $group_75 + assign \fus_oper_i_alu_logical0__is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__is_32bit \is_32bit + end + end + end + sync init + end + process $group_76 + assign \fus_oper_i_alu_logical0__is_signed 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__is_signed \is_signed + end + end + end + sync init + end + process $group_77 + assign \fus_oper_i_alu_logical0__data_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__data_len \data_len + end + end + end + sync init + end + process $group_78 + assign \fus_oper_i_alu_logical0__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_logical0__insn \insn + end + end + end + sync init + end + process $group_79 + assign \fus_cu_issue_i$12 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_issue_i$12 \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + wire width 2 $222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + cell $not $223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A { \reg2_ok \reg1_ok } + connect \Y $222 + end + process $group_80 + assign \fus_cu_rdmaskn_i$14 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_rdmaskn_i$14 $222 + end + end + end + sync init + end + process $group_81 + assign \fus_oper_i_alu_spr0__insn_type 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_spr0__insn_type \insn_type + end + end + end + sync init + end + process $group_82 + assign \fus_oper_i_alu_spr0__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_spr0__fn_unit \fn_unit + end + end + end + sync init + end + process $group_83 + assign \fus_oper_i_alu_spr0__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_spr0__insn \insn + end + end + end + sync init + end + process $group_84 + assign \fus_oper_i_alu_spr0__is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_spr0__is_32bit \is_32bit + end + end + end + sync init + end + process $group_85 + assign \fus_cu_issue_i$15 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_issue_i$15 \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + wire width 6 $224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $and $226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $225 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $or $228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $225 + connect \B \xer_in + connect \Y $227 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $229 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $229 + connect \B \xer_in + connect \Y $231 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire width 1 $233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $eq $234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \input_carry + connect \B 2'10 + connect \Y $233 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire width 1 $235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $or $236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $233 + connect \B \xer_in + connect \Y $235 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + cell $not $237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { $235 $231 $227 \fast1_ok \spr1_ok \reg1_ok } + connect \Y $224 + end + process $group_86 + assign \fus_cu_rdmaskn_i$17 6'000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_rdmaskn_i$17 $224 + end + end + end + sync init + end + process $group_87 + assign \fus_oper_i_alu_div0__insn_type 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__insn_type \insn_type + end + end + end + sync init + end + process $group_88 + assign \fus_oper_i_alu_div0__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__fn_unit \fn_unit + end + end + end + sync init + end + process $group_89 + assign \fus_oper_i_alu_div0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_div0__imm_data__imm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_div0__imm_data__imm_ok \fus_oper_i_alu_div0__imm_data__imm } { \imm_ok \imm } + end + end + end + sync init + end + process $group_91 + assign \fus_oper_i_alu_div0__rc__rc 1'0 + assign \fus_oper_i_alu_div0__rc__rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_div0__rc__rc_ok \fus_oper_i_alu_div0__rc__rc } { \rc_ok \rc } + end + end + end + sync init + end + process $group_93 + assign \fus_oper_i_alu_div0__oe__oe 1'0 + assign \fus_oper_i_alu_div0__oe__oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_div0__oe__oe_ok \fus_oper_i_alu_div0__oe__oe } { \oe_ok \oe } + end + end + end + sync init + end + process $group_95 + assign \fus_oper_i_alu_div0__invert_in 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__invert_in \invert_in + end + end + end + sync init + end + process $group_96 + assign \fus_oper_i_alu_div0__zero_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__zero_a \zero_a + end + end + end + sync init + end + process $group_97 + assign \fus_oper_i_alu_div0__input_carry 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__input_carry \input_carry + end + end + end + sync init + end + process $group_98 + assign \fus_oper_i_alu_div0__invert_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__invert_out \invert_out + end + end + end + sync init + end + process $group_99 + assign \fus_oper_i_alu_div0__write_cr0 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__write_cr0 \write_cr0 + end + end + end + sync init + end + process $group_100 + assign \fus_oper_i_alu_div0__output_carry 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__output_carry \output_carry + end + end + end + sync init + end + process $group_101 + assign \fus_oper_i_alu_div0__is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__is_32bit \is_32bit + end + end + end + sync init + end + process $group_102 + assign \fus_oper_i_alu_div0__is_signed 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__is_signed \is_signed + end + end + end + sync init + end + process $group_103 + assign \fus_oper_i_alu_div0__data_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__data_len \data_len + end + end + end + sync init + end + process $group_104 + assign \fus_oper_i_alu_div0__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_div0__insn \insn + end + end + end + sync init + end + process $group_105 + assign \fus_cu_issue_i$18 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_issue_i$18 \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + wire width 3 $238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $239 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $and $240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $239 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $or $242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $239 + connect \B \xer_in + connect \Y $241 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + cell $not $243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { $241 \reg2_ok \reg1_ok } + connect \Y $238 + end + process $group_106 + assign \fus_cu_rdmaskn_i$20 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [6] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_rdmaskn_i$20 $238 + end + end + end + sync init + end + process $group_107 + assign \fus_oper_i_alu_mul0__insn_type 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_mul0__insn_type \insn_type + end + end + end + sync init + end + process $group_108 + assign \fus_oper_i_alu_mul0__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_mul0__fn_unit \fn_unit + end + end + end + sync init + end + process $group_109 + assign \fus_oper_i_alu_mul0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_mul0__imm_data__imm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm } { \imm_ok \imm } + end + end + end + sync init + end + process $group_111 + assign \fus_oper_i_alu_mul0__rc__rc 1'0 + assign \fus_oper_i_alu_mul0__rc__rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc } { \rc_ok \rc } + end + end + end + sync init + end + process $group_113 + assign \fus_oper_i_alu_mul0__oe__oe 1'0 + assign \fus_oper_i_alu_mul0__oe__oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe } { \oe_ok \oe } + end + end + end + sync init + end + process $group_115 + assign \fus_oper_i_alu_mul0__write_cr0 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_mul0__write_cr0 \write_cr0 + end + end + end + sync init + end + process $group_116 + assign \fus_oper_i_alu_mul0__is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_mul0__is_32bit \is_32bit + end + end + end + sync init + end + process $group_117 + assign \fus_oper_i_alu_mul0__is_signed 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_mul0__is_signed \is_signed + end + end + end + sync init + end + process $group_118 + assign \fus_oper_i_alu_mul0__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_mul0__insn \insn + end + end + end + sync init + end + process $group_119 + assign \fus_cu_issue_i$21 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_issue_i$21 \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + wire width 3 $244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $and $246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $245 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $or $248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $245 + connect \B \xer_in + connect \Y $247 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + cell $not $249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { $247 \reg2_ok \reg1_ok } + connect \Y $244 + end + process $group_120 + assign \fus_cu_rdmaskn_i$23 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [7] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_rdmaskn_i$23 $244 + end + end + end + sync init + end + process $group_121 + assign \fus_oper_i_alu_shift_rot0__insn_type 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_shift_rot0__insn_type \insn_type + end + end + end + sync init + end + process $group_122 + assign \fus_oper_i_alu_shift_rot0__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_shift_rot0__fn_unit \fn_unit + end + end + end + sync init + end + process $group_123 + assign \fus_oper_i_alu_shift_rot0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_alu_shift_rot0__imm_data__imm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm } { \imm_ok \imm } + end + end + end + sync init + end + process $group_125 + assign \fus_oper_i_alu_shift_rot0__rc__rc 1'0 + assign \fus_oper_i_alu_shift_rot0__rc__rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc } { \rc_ok \rc } + end + end + end + sync init + end + process $group_127 + assign \fus_oper_i_alu_shift_rot0__oe__oe 1'0 + assign \fus_oper_i_alu_shift_rot0__oe__oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe } { \oe_ok \oe } + end + end + end + sync init + end + process $group_129 + assign { } 0'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { } {} + end + end + end + sync init + end + process $group_130 + assign \fus_oper_i_alu_shift_rot0__input_carry 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_shift_rot0__input_carry \input_carry + end + end + end + sync init + end + process $group_131 + assign \fus_oper_i_alu_shift_rot0__output_carry 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_shift_rot0__output_carry \output_carry + end + end + end + sync init + end + process $group_132 + assign \fus_oper_i_alu_shift_rot0__input_cr 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_shift_rot0__input_cr \input_cr + end + end + end + sync init + end + process $group_133 + assign \fus_oper_i_alu_shift_rot0__output_cr 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_shift_rot0__output_cr \output_cr + end + end + end + sync init + end + process $group_134 + assign \fus_oper_i_alu_shift_rot0__is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_shift_rot0__is_32bit \is_32bit + end + end + end + sync init + end + process $group_135 + assign \fus_oper_i_alu_shift_rot0__is_signed 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_shift_rot0__is_signed \is_signed + end + end + end + sync init + end + process $group_136 + assign \fus_oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_alu_shift_rot0__insn \insn + end + end + end + sync init + end + process $group_137 + assign \fus_cu_issue_i$24 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_issue_i$24 \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + wire width 4 $250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire width 1 $251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $eq $252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \input_carry + connect \B 2'10 + connect \Y $251 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire width 1 $253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $or $254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $251 + connect \B \xer_in + connect \Y $253 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + cell $not $255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { $253 \reg3_ok \reg2_ok \reg1_ok } + connect \Y $250 + end + process $group_138 + assign \fus_cu_rdmaskn_i$26 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [8] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_rdmaskn_i$26 $250 + end + end + end + sync init + end + process $group_139 + assign \fus_oper_i_ldst_ldst0__insn_type 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_ldst_ldst0__insn_type \insn_type + end + end + end + sync init + end + process $group_140 + assign \fus_oper_i_ldst_ldst0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i_ldst_ldst0__imm_data__imm_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm } { \imm_ok \imm } + end + end + end + sync init + end + process $group_142 + assign \fus_oper_i_ldst_ldst0__zero_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_ldst_ldst0__zero_a \zero_a + end + end + end + sync init + end + process $group_143 + assign \fus_oper_i_ldst_ldst0__rc__rc 1'0 + assign \fus_oper_i_ldst_ldst0__rc__rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc } { \rc_ok \rc } + end + end + end + sync init + end + process $group_145 + assign \fus_oper_i_ldst_ldst0__oe__oe 1'0 + assign \fus_oper_i_ldst_ldst0__oe__oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign { \fus_oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe } { \oe_ok \oe } + end + end + end + sync init + end + process $group_147 + assign \fus_oper_i_ldst_ldst0__is_32bit 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_ldst_ldst0__is_32bit \is_32bit + end + end + end + sync init + end + process $group_148 + assign \fus_oper_i_ldst_ldst0__is_signed 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_ldst_ldst0__is_signed \is_signed + end + end + end + sync init + end + process $group_149 + assign \fus_oper_i_ldst_ldst0__data_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_ldst_ldst0__data_len \data_len + end + end + end + sync init + end + process $group_150 + assign \fus_oper_i_ldst_ldst0__byte_reverse 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_ldst_ldst0__byte_reverse \byte_reverse + end + end + end + sync init + end + process $group_151 + assign \fus_oper_i_ldst_ldst0__sign_extend 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_ldst_ldst0__sign_extend \sign_extend + end + end + end + sync init + end + process $group_152 + assign \fus_oper_i_ldst_ldst0__ldst_mode 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_oper_i_ldst_ldst0__ldst_mode \ldst_mode + end + end + end + sync init + end + process $group_153 + assign \fus_cu_issue_i$27 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_issue_i$27 \issue_i + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + wire width 3 $256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:169" + cell $not $257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { \reg3_ok \reg2_ok \reg1_ok } + connect \Y $256 + end + process $group_154 + assign \fus_cu_rdmaskn_i$29 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + switch { \ivalid_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148" + switch \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" + attribute \nmigen.decoding "OP_ATTN/5" + case 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" + attribute \nmigen.decoding "OP_NOP/1" + case 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \fu_enable [9] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \fus_cu_rdmaskn_i$29 $256 + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_INT_ra_0 + process $group_155 + assign \rdflag_INT_ra_0 1'0 + assign \rdflag_INT_ra_0 \reg1_ok + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o [0] + connect \B \fu_enable [0] + connect \Y $258 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $258 + connect \B \rdflag_INT_ra_0 + connect \Y $260 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_alu0_0 + connect \Y $262 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $260 + connect \B $262 + connect \Y $264 + end + process $group_156 + assign \pick_INT_ra_alu0_0 1'0 + assign \pick_INT_ra_alu0_0 $264 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_ra_ldst0_8 + process $group_157 + assign \rdpick_INT_ra_i 9'000000000 + assign \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 + assign \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 + assign \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 + assign \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3 + assign \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4 + assign \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5 + assign \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6 + assign \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7 + assign \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_so_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_ca_alu0_0$next + process $group_158 + assign \fus_cu_rd__go_i 4'0000 + assign \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 + assign \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 + assign \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 + assign \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [0] + connect \B \rdpick_INT_ra_en_o + connect \Y $266 + end + process $group_159 + assign \rp_INT_ra_alu0_0 1'0 + assign \rp_INT_ra_alu0_0 $266 + sync init + end + process $group_160 + assign \dp_INT_ra_alu0_0$next \dp_INT_ra_alu0_0 + assign \dp_INT_ra_alu0_0$next \rp_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_ra_alu0_0$next 1'0 + end + sync init + update \dp_INT_ra_alu0_0 1'0 + sync posedge \coresync_clk + update \dp_INT_ra_alu0_0 \dp_INT_ra_alu0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $269 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg1 + connect \S \rp_INT_ra_alu0_0 + connect \Y $268 + end + process $group_161 + assign \addr_en_INT_ra_alu0_0 5'00000 + assign \addr_en_INT_ra_alu0_0 $268 + sync init + end + process $group_162 + assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_ra_alu0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src1_i \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$30 [0] + connect \B \fu_enable [1] + connect \Y $270 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $270 + connect \B \rdflag_INT_ra_0 + connect \Y $272 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_cr0_1 + connect \Y $274 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $272 + connect \B $274 + connect \Y $276 + end + process $group_163 + assign \pick_INT_ra_cr0_1 1'0 + assign \pick_INT_ra_cr0_1 $276 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_CR_full_cr_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_CR_cr_a_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_CR_cr_b_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_CR_cr_c_cr0_0$next + process $group_164 + assign \fus_cu_rd__go_i$31 6'000000 + assign \fus_cu_rd__go_i$31 [0] \dp_INT_ra_cr0_1 + assign \fus_cu_rd__go_i$31 [1] \dp_INT_rb_cr0_1 + assign \fus_cu_rd__go_i$31 [2] \dp_CR_full_cr_cr0_0 + assign \fus_cu_rd__go_i$31 [3] \dp_CR_cr_a_cr0_0 + assign \fus_cu_rd__go_i$31 [4] \dp_CR_cr_b_cr0_0 + assign \fus_cu_rd__go_i$31 [5] \dp_CR_cr_c_cr0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [1] + connect \B \rdpick_INT_ra_en_o + connect \Y $278 + end + process $group_165 + assign \rp_INT_ra_cr0_1 1'0 + assign \rp_INT_ra_cr0_1 $278 + sync init + end + process $group_166 + assign \dp_INT_ra_cr0_1$next \dp_INT_ra_cr0_1 + assign \dp_INT_ra_cr0_1$next \rp_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_ra_cr0_1$next 1'0 + end + sync init + update \dp_INT_ra_cr0_1 1'0 + sync posedge \coresync_clk + update \dp_INT_ra_cr0_1 \dp_INT_ra_cr0_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $281 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg1 + connect \S \rp_INT_ra_cr0_1 + connect \Y $280 + end + process $group_167 + assign \addr_en_INT_ra_cr0_1 5'00000 + assign \addr_en_INT_ra_cr0_1 $280 + sync init + end + process $group_168 + assign \fus_src1_i$32 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_ra_cr0_1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src1_i$32 \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$33 [0] + connect \B \fu_enable [3] + connect \Y $282 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $282 + connect \B \rdflag_INT_ra_0 + connect \Y $284 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_trap0_2 + connect \Y $286 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $284 + connect \B $286 + connect \Y $288 + end + process $group_169 + assign \pick_INT_ra_trap0_2 1'0 + assign \pick_INT_ra_trap0_2 $288 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_FAST_fast1_trap0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_FAST_fast2_trap0_1$next + process $group_170 + assign \fus_cu_rd__go_i$34 4'0000 + assign \fus_cu_rd__go_i$34 [0] \dp_INT_ra_trap0_2 + assign \fus_cu_rd__go_i$34 [1] \dp_INT_rb_trap0_2 + assign \fus_cu_rd__go_i$34 [2] \dp_FAST_fast1_trap0_1 + assign \fus_cu_rd__go_i$34 [3] \dp_FAST_fast2_trap0_1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [2] + connect \B \rdpick_INT_ra_en_o + connect \Y $290 + end + process $group_171 + assign \rp_INT_ra_trap0_2 1'0 + assign \rp_INT_ra_trap0_2 $290 + sync init + end + process $group_172 + assign \dp_INT_ra_trap0_2$next \dp_INT_ra_trap0_2 + assign \dp_INT_ra_trap0_2$next \rp_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_ra_trap0_2$next 1'0 + end + sync init + update \dp_INT_ra_trap0_2 1'0 + sync posedge \coresync_clk + update \dp_INT_ra_trap0_2 \dp_INT_ra_trap0_2$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $292 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $293 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg1 + connect \S \rp_INT_ra_trap0_2 + connect \Y $292 + end + process $group_173 + assign \addr_en_INT_ra_trap0_2 5'00000 + assign \addr_en_INT_ra_trap0_2 $292 + sync init + end + process $group_174 + assign \fus_src1_i$35 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_ra_trap0_2 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src1_i$35 \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$36 [0] + connect \B \fu_enable [4] + connect \Y $294 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $294 + connect \B \rdflag_INT_ra_0 + connect \Y $296 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_logical0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_logical0_3 + connect \Y $298 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $296 + connect \B $298 + connect \Y $300 + end + process $group_175 + assign \pick_INT_ra_logical0_3 1'0 + assign \pick_INT_ra_logical0_3 $300 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_logical0_3$next + process $group_176 + assign \fus_cu_rd__go_i$37 2'00 + assign \fus_cu_rd__go_i$37 [0] \dp_INT_ra_logical0_3 + assign \fus_cu_rd__go_i$37 [1] \dp_INT_rb_logical0_3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [3] + connect \B \rdpick_INT_ra_en_o + connect \Y $302 + end + process $group_177 + assign \rp_INT_ra_logical0_3 1'0 + assign \rp_INT_ra_logical0_3 $302 + sync init + end + process $group_178 + assign \dp_INT_ra_logical0_3$next \dp_INT_ra_logical0_3 + assign \dp_INT_ra_logical0_3$next \rp_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_ra_logical0_3$next 1'0 + end + sync init + update \dp_INT_ra_logical0_3 1'0 + sync posedge \coresync_clk + update \dp_INT_ra_logical0_3 \dp_INT_ra_logical0_3$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $305 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg1 + connect \S \rp_INT_ra_logical0_3 + connect \Y $304 + end + process $group_179 + assign \addr_en_INT_ra_logical0_3 5'00000 + assign \addr_en_INT_ra_logical0_3 $304 + sync init + end + process $group_180 + assign \fus_src1_i$38 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_ra_logical0_3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src1_i$38 \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$39 [0] + connect \B \fu_enable [5] + connect \Y $306 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $306 + connect \B \rdflag_INT_ra_0 + connect \Y $308 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_spr0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_spr0_4 + connect \Y $310 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $308 + connect \B $310 + connect \Y $312 + end + process $group_181 + assign \pick_INT_ra_spr0_4 1'0 + assign \pick_INT_ra_spr0_4 $312 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_so_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_so_spr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_ca_spr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_ov_spr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_FAST_fast1_spr0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_SPR_spr1_spr0_0$next + process $group_182 + assign \fus_cu_rd__go_i$40 6'000000 + assign \fus_cu_rd__go_i$40 [0] \dp_INT_ra_spr0_4 + assign \fus_cu_rd__go_i$40 [3] \dp_XER_xer_so_spr0_1 + assign \fus_cu_rd__go_i$40 [5] \dp_XER_xer_ca_spr0_1 + assign \fus_cu_rd__go_i$40 [4] \dp_XER_xer_ov_spr0_0 + assign \fus_cu_rd__go_i$40 [2] \dp_FAST_fast1_spr0_2 + assign \fus_cu_rd__go_i$40 [1] \dp_SPR_spr1_spr0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [4] + connect \B \rdpick_INT_ra_en_o + connect \Y $314 + end + process $group_183 + assign \rp_INT_ra_spr0_4 1'0 + assign \rp_INT_ra_spr0_4 $314 + sync init + end + process $group_184 + assign \dp_INT_ra_spr0_4$next \dp_INT_ra_spr0_4 + assign \dp_INT_ra_spr0_4$next \rp_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_ra_spr0_4$next 1'0 + end + sync init + update \dp_INT_ra_spr0_4 1'0 + sync posedge \coresync_clk + update \dp_INT_ra_spr0_4 \dp_INT_ra_spr0_4$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $317 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg1 + connect \S \rp_INT_ra_spr0_4 + connect \Y $316 + end + process $group_185 + assign \addr_en_INT_ra_spr0_4 5'00000 + assign \addr_en_INT_ra_spr0_4 $316 + sync init + end + process $group_186 + assign \fus_src1_i$41 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_ra_spr0_4 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src1_i$41 \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$42 [0] + connect \B \fu_enable [6] + connect \Y $318 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $318 + connect \B \rdflag_INT_ra_0 + connect \Y $320 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_div0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_div0_5 + connect \Y $322 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $320 + connect \B $322 + connect \Y $324 + end + process $group_187 + assign \pick_INT_ra_div0_5 1'0 + assign \pick_INT_ra_div0_5 $324 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_div0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_so_div0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_so_div0_2$next + process $group_188 + assign \fus_cu_rd__go_i$43 3'000 + assign \fus_cu_rd__go_i$43 [0] \dp_INT_ra_div0_5 + assign \fus_cu_rd__go_i$43 [1] \dp_INT_rb_div0_4 + assign \fus_cu_rd__go_i$43 [2] \dp_XER_xer_so_div0_2 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [5] + connect \B \rdpick_INT_ra_en_o + connect \Y $326 + end + process $group_189 + assign \rp_INT_ra_div0_5 1'0 + assign \rp_INT_ra_div0_5 $326 + sync init + end + process $group_190 + assign \dp_INT_ra_div0_5$next \dp_INT_ra_div0_5 + assign \dp_INT_ra_div0_5$next \rp_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_ra_div0_5$next 1'0 + end + sync init + update \dp_INT_ra_div0_5 1'0 + sync posedge \coresync_clk + update \dp_INT_ra_div0_5 \dp_INT_ra_div0_5$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $329 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg1 + connect \S \rp_INT_ra_div0_5 + connect \Y $328 + end + process $group_191 + assign \addr_en_INT_ra_div0_5 5'00000 + assign \addr_en_INT_ra_div0_5 $328 + sync init + end + process $group_192 + assign \fus_src1_i$44 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_ra_div0_5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src1_i$44 \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$45 [0] + connect \B \fu_enable [7] + connect \Y $330 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $330 + connect \B \rdflag_INT_ra_0 + connect \Y $332 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_mul0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_mul0_6 + connect \Y $334 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $332 + connect \B $334 + connect \Y $336 + end + process $group_193 + assign \pick_INT_ra_mul0_6 1'0 + assign \pick_INT_ra_mul0_6 $336 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_mul0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_so_mul0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_so_mul0_3$next + process $group_194 + assign \fus_cu_rd__go_i$46 3'000 + assign \fus_cu_rd__go_i$46 [0] \dp_INT_ra_mul0_6 + assign \fus_cu_rd__go_i$46 [1] \dp_INT_rb_mul0_5 + assign \fus_cu_rd__go_i$46 [2] \dp_XER_xer_so_mul0_3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [6] + connect \B \rdpick_INT_ra_en_o + connect \Y $338 + end + process $group_195 + assign \rp_INT_ra_mul0_6 1'0 + assign \rp_INT_ra_mul0_6 $338 + sync init + end + process $group_196 + assign \dp_INT_ra_mul0_6$next \dp_INT_ra_mul0_6 + assign \dp_INT_ra_mul0_6$next \rp_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_ra_mul0_6$next 1'0 + end + sync init + update \dp_INT_ra_mul0_6 1'0 + sync posedge \coresync_clk + update \dp_INT_ra_mul0_6 \dp_INT_ra_mul0_6$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $340 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $341 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg1 + connect \S \rp_INT_ra_mul0_6 + connect \Y $340 + end + process $group_197 + assign \addr_en_INT_ra_mul0_6 5'00000 + assign \addr_en_INT_ra_mul0_6 $340 + sync init + end + process $group_198 + assign \fus_src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_ra_mul0_6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src1_i$47 \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$48 [0] + connect \B \fu_enable [8] + connect \Y $342 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $344 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $342 + connect \B \rdflag_INT_ra_0 + connect \Y $344 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $346 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_shiftrot0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_shiftrot0_7 + connect \Y $346 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $348 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $344 + connect \B $346 + connect \Y $348 + end + process $group_199 + assign \pick_INT_ra_shiftrot0_7 1'0 + assign \pick_INT_ra_shiftrot0_7 $348 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_shiftrot0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rc_shiftrot0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_XER_xer_ca_shiftrot0_2$next + process $group_200 + assign \fus_cu_rd__go_i$49 4'0000 + assign \fus_cu_rd__go_i$49 [0] \dp_INT_ra_shiftrot0_7 + assign \fus_cu_rd__go_i$49 [1] \dp_INT_rb_shiftrot0_6 + assign \fus_cu_rd__go_i$49 [2] \dp_INT_rc_shiftrot0_0 + assign \fus_cu_rd__go_i$49 [3] \dp_XER_xer_ca_shiftrot0_2 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [7] + connect \B \rdpick_INT_ra_en_o + connect \Y $350 + end + process $group_201 + assign \rp_INT_ra_shiftrot0_7 1'0 + assign \rp_INT_ra_shiftrot0_7 $350 + sync init + end + process $group_202 + assign \dp_INT_ra_shiftrot0_7$next \dp_INT_ra_shiftrot0_7 + assign \dp_INT_ra_shiftrot0_7$next \rp_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_ra_shiftrot0_7$next 1'0 + end + sync init + update \dp_INT_ra_shiftrot0_7 1'0 + sync posedge \coresync_clk + update \dp_INT_ra_shiftrot0_7 \dp_INT_ra_shiftrot0_7$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $353 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg1 + connect \S \rp_INT_ra_shiftrot0_7 + connect \Y $352 + end + process $group_203 + assign \addr_en_INT_ra_shiftrot0_7 5'00000 + assign \addr_en_INT_ra_shiftrot0_7 $352 + sync init + end + process $group_204 + assign \fus_src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_ra_shiftrot0_7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src1_i$50 \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $354 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$51 [0] + connect \B \fu_enable [9] + connect \Y $354 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $356 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $354 + connect \B \rdflag_INT_ra_0 + connect \Y $356 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_ra_ldst0_8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_ra_ldst0_8 + connect \Y $358 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $360 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $356 + connect \B $358 + connect \Y $360 + end + process $group_205 + assign \pick_INT_ra_ldst0_8 1'0 + assign \pick_INT_ra_ldst0_8 $360 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rb_ldst0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_INT_rc_ldst0_1$next + process $group_206 + assign \fus_cu_rd__go_i$52 3'000 + assign \fus_cu_rd__go_i$52 [0] \dp_INT_ra_ldst0_8 + assign \fus_cu_rd__go_i$52 [1] \dp_INT_rb_ldst0_7 + assign \fus_cu_rd__go_i$52 [2] \dp_INT_rc_ldst0_1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $362 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_ra_o [8] + connect \B \rdpick_INT_ra_en_o + connect \Y $362 + end + process $group_207 + assign \rp_INT_ra_ldst0_8 1'0 + assign \rp_INT_ra_ldst0_8 $362 + sync init + end + process $group_208 + assign \dp_INT_ra_ldst0_8$next \dp_INT_ra_ldst0_8 + assign \dp_INT_ra_ldst0_8$next \rp_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_ra_ldst0_8$next 1'0 + end + sync init + update \dp_INT_ra_ldst0_8 1'0 + sync posedge \coresync_clk + update \dp_INT_ra_ldst0_8 \dp_INT_ra_ldst0_8$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $364 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $365 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg1 + connect \S \rp_INT_ra_ldst0_8 + connect \Y $364 + end + process $group_209 + assign \addr_en_INT_ra_ldst0_8 5'00000 + assign \addr_en_INT_ra_ldst0_8 $364 + sync init + end + process $group_210 + assign \fus_src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_ra_ldst0_8 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src1_i$53 \int_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $366 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_ra_alu0_0 + connect \B \addr_en_INT_ra_cr0_1 + connect \Y $366 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $368 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_ra_trap0_2 + connect \B \addr_en_INT_ra_logical0_3 + connect \Y $368 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $370 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $366 + connect \B $368 + connect \Y $370 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $372 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_ra_spr0_4 + connect \B \addr_en_INT_ra_div0_5 + connect \Y $372 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $374 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_ra_shiftrot0_7 + connect \B \addr_en_INT_ra_ldst0_8 + connect \Y $374 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $376 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_ra_mul0_6 + connect \B $374 + connect \Y $376 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $378 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $372 + connect \B $376 + connect \Y $378 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $380 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $370 + connect \B $378 + connect \Y $380 + end + process $group_211 + assign \int_src1__addr 5'00000 + assign \int_src1__addr $380 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 $382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + cell $reduce_bool $383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } + connect \Y $382 + end + process $group_212 + assign \int_src1__ren 1'0 + assign \int_src1__ren $382 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_INT_rb_0 + process $group_213 + assign \rdflag_INT_rb_0 1'0 + assign \rdflag_INT_rb_0 \reg2_ok + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o [1] + connect \B \fu_enable [0] + connect \Y $384 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $384 + connect \B \rdflag_INT_rb_0 + connect \Y $386 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_alu0_0 + connect \Y $388 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $386 + connect \B $388 + connect \Y $390 + end + process $group_214 + assign \pick_INT_rb_alu0_0 1'0 + assign \pick_INT_rb_alu0_0 $390 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_rb_ldst0_7 + process $group_215 + assign \rdpick_INT_rb_i 8'00000000 + assign \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 + assign \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 + assign \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 + assign \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3 + assign \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4 + assign \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 + assign \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 + assign \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [0] + connect \B \rdpick_INT_rb_en_o + connect \Y $392 + end + process $group_216 + assign \rp_INT_rb_alu0_0 1'0 + assign \rp_INT_rb_alu0_0 $392 + sync init + end + process $group_217 + assign \dp_INT_rb_alu0_0$next \dp_INT_rb_alu0_0 + assign \dp_INT_rb_alu0_0$next \rp_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_rb_alu0_0$next 1'0 + end + sync init + update \dp_INT_rb_alu0_0 1'0 + sync posedge \coresync_clk + update \dp_INT_rb_alu0_0 \dp_INT_rb_alu0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $395 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg2 + connect \S \rp_INT_rb_alu0_0 + connect \Y $394 + end + process $group_218 + assign \addr_en_INT_rb_alu0_0 5'00000 + assign \addr_en_INT_rb_alu0_0 $394 + sync init + end + process $group_219 + assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_rb_alu0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src2_i \int_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$30 [1] + connect \B \fu_enable [1] + connect \Y $396 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $396 + connect \B \rdflag_INT_rb_0 + connect \Y $398 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_cr0_1 + connect \Y $400 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $398 + connect \B $400 + connect \Y $402 + end + process $group_220 + assign \pick_INT_rb_cr0_1 1'0 + assign \pick_INT_rb_cr0_1 $402 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $404 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [1] + connect \B \rdpick_INT_rb_en_o + connect \Y $404 + end + process $group_221 + assign \rp_INT_rb_cr0_1 1'0 + assign \rp_INT_rb_cr0_1 $404 + sync init + end + process $group_222 + assign \dp_INT_rb_cr0_1$next \dp_INT_rb_cr0_1 + assign \dp_INT_rb_cr0_1$next \rp_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_rb_cr0_1$next 1'0 + end + sync init + update \dp_INT_rb_cr0_1 1'0 + sync posedge \coresync_clk + update \dp_INT_rb_cr0_1 \dp_INT_rb_cr0_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $407 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg2 + connect \S \rp_INT_rb_cr0_1 + connect \Y $406 + end + process $group_223 + assign \addr_en_INT_rb_cr0_1 5'00000 + assign \addr_en_INT_rb_cr0_1 $406 + sync init + end + process $group_224 + assign \fus_src2_i$54 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_rb_cr0_1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src2_i$54 \int_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$33 [1] + connect \B \fu_enable [3] + connect \Y $408 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $408 + connect \B \rdflag_INT_rb_0 + connect \Y $410 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_trap0_2 + connect \Y $412 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $410 + connect \B $412 + connect \Y $414 + end + process $group_225 + assign \pick_INT_rb_trap0_2 1'0 + assign \pick_INT_rb_trap0_2 $414 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [2] + connect \B \rdpick_INT_rb_en_o + connect \Y $416 + end + process $group_226 + assign \rp_INT_rb_trap0_2 1'0 + assign \rp_INT_rb_trap0_2 $416 + sync init + end + process $group_227 + assign \dp_INT_rb_trap0_2$next \dp_INT_rb_trap0_2 + assign \dp_INT_rb_trap0_2$next \rp_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_rb_trap0_2$next 1'0 + end + sync init + update \dp_INT_rb_trap0_2 1'0 + sync posedge \coresync_clk + update \dp_INT_rb_trap0_2 \dp_INT_rb_trap0_2$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $419 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg2 + connect \S \rp_INT_rb_trap0_2 + connect \Y $418 + end + process $group_228 + assign \addr_en_INT_rb_trap0_2 5'00000 + assign \addr_en_INT_rb_trap0_2 $418 + sync init + end + process $group_229 + assign \fus_src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_rb_trap0_2 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src2_i$55 \int_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$36 [1] + connect \B \fu_enable [4] + connect \Y $420 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $420 + connect \B \rdflag_INT_rb_0 + connect \Y $422 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_logical0_3 + connect \Y $424 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $422 + connect \B $424 + connect \Y $426 + end + process $group_230 + assign \pick_INT_rb_logical0_3 1'0 + assign \pick_INT_rb_logical0_3 $426 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [3] + connect \B \rdpick_INT_rb_en_o + connect \Y $428 + end + process $group_231 + assign \rp_INT_rb_logical0_3 1'0 + assign \rp_INT_rb_logical0_3 $428 + sync init + end + process $group_232 + assign \dp_INT_rb_logical0_3$next \dp_INT_rb_logical0_3 + assign \dp_INT_rb_logical0_3$next \rp_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_rb_logical0_3$next 1'0 + end + sync init + update \dp_INT_rb_logical0_3 1'0 + sync posedge \coresync_clk + update \dp_INT_rb_logical0_3 \dp_INT_rb_logical0_3$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $430 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $431 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg2 + connect \S \rp_INT_rb_logical0_3 + connect \Y $430 + end + process $group_233 + assign \addr_en_INT_rb_logical0_3 5'00000 + assign \addr_en_INT_rb_logical0_3 $430 + sync init + end + process $group_234 + assign \fus_src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_rb_logical0_3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src2_i$56 \int_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$42 [1] + connect \B \fu_enable [6] + connect \Y $432 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $432 + connect \B \rdflag_INT_rb_0 + connect \Y $434 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_div0_4 + connect \Y $436 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $434 + connect \B $436 + connect \Y $438 + end + process $group_235 + assign \pick_INT_rb_div0_4 1'0 + assign \pick_INT_rb_div0_4 $438 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [4] + connect \B \rdpick_INT_rb_en_o + connect \Y $440 + end + process $group_236 + assign \rp_INT_rb_div0_4 1'0 + assign \rp_INT_rb_div0_4 $440 + sync init + end + process $group_237 + assign \dp_INT_rb_div0_4$next \dp_INT_rb_div0_4 + assign \dp_INT_rb_div0_4$next \rp_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_rb_div0_4$next 1'0 + end + sync init + update \dp_INT_rb_div0_4 1'0 + sync posedge \coresync_clk + update \dp_INT_rb_div0_4 \dp_INT_rb_div0_4$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $443 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg2 + connect \S \rp_INT_rb_div0_4 + connect \Y $442 + end + process $group_238 + assign \addr_en_INT_rb_div0_4 5'00000 + assign \addr_en_INT_rb_div0_4 $442 + sync init + end + process $group_239 + assign \fus_src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_rb_div0_4 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src2_i$57 \int_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$45 [1] + connect \B \fu_enable [7] + connect \Y $444 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $446 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $444 + connect \B \rdflag_INT_rb_0 + connect \Y $446 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_mul0_5 + connect \Y $448 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $446 + connect \B $448 + connect \Y $450 + end + process $group_240 + assign \pick_INT_rb_mul0_5 1'0 + assign \pick_INT_rb_mul0_5 $450 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [5] + connect \B \rdpick_INT_rb_en_o + connect \Y $452 + end + process $group_241 + assign \rp_INT_rb_mul0_5 1'0 + assign \rp_INT_rb_mul0_5 $452 + sync init + end + process $group_242 + assign \dp_INT_rb_mul0_5$next \dp_INT_rb_mul0_5 + assign \dp_INT_rb_mul0_5$next \rp_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_rb_mul0_5$next 1'0 + end + sync init + update \dp_INT_rb_mul0_5 1'0 + sync posedge \coresync_clk + update \dp_INT_rb_mul0_5 \dp_INT_rb_mul0_5$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $455 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg2 + connect \S \rp_INT_rb_mul0_5 + connect \Y $454 + end + process $group_243 + assign \addr_en_INT_rb_mul0_5 5'00000 + assign \addr_en_INT_rb_mul0_5 $454 + sync init + end + process $group_244 + assign \fus_src2_i$58 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_rb_mul0_5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src2_i$58 \int_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$48 [1] + connect \B \fu_enable [8] + connect \Y $456 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $456 + connect \B \rdflag_INT_rb_0 + connect \Y $458 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_shiftrot0_6 + connect \Y $460 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $458 + connect \B $460 + connect \Y $462 + end + process $group_245 + assign \pick_INT_rb_shiftrot0_6 1'0 + assign \pick_INT_rb_shiftrot0_6 $462 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [6] + connect \B \rdpick_INT_rb_en_o + connect \Y $464 + end + process $group_246 + assign \rp_INT_rb_shiftrot0_6 1'0 + assign \rp_INT_rb_shiftrot0_6 $464 + sync init + end + process $group_247 + assign \dp_INT_rb_shiftrot0_6$next \dp_INT_rb_shiftrot0_6 + assign \dp_INT_rb_shiftrot0_6$next \rp_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_rb_shiftrot0_6$next 1'0 + end + sync init + update \dp_INT_rb_shiftrot0_6 1'0 + sync posedge \coresync_clk + update \dp_INT_rb_shiftrot0_6 \dp_INT_rb_shiftrot0_6$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $467 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg2 + connect \S \rp_INT_rb_shiftrot0_6 + connect \Y $466 + end + process $group_248 + assign \addr_en_INT_rb_shiftrot0_6 5'00000 + assign \addr_en_INT_rb_shiftrot0_6 $466 + sync init + end + process $group_249 + assign \fus_src2_i$59 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_rb_shiftrot0_6 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src2_i$59 \int_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$51 [1] + connect \B \fu_enable [9] + connect \Y $468 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $468 + connect \B \rdflag_INT_rb_0 + connect \Y $470 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rb_ldst0_7 + connect \Y $472 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $470 + connect \B $472 + connect \Y $474 + end + process $group_250 + assign \pick_INT_rb_ldst0_7 1'0 + assign \pick_INT_rb_ldst0_7 $474 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rb_o [7] + connect \B \rdpick_INT_rb_en_o + connect \Y $476 + end + process $group_251 + assign \rp_INT_rb_ldst0_7 1'0 + assign \rp_INT_rb_ldst0_7 $476 + sync init + end + process $group_252 + assign \dp_INT_rb_ldst0_7$next \dp_INT_rb_ldst0_7 + assign \dp_INT_rb_ldst0_7$next \rp_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_rb_ldst0_7$next 1'0 + end + sync init + update \dp_INT_rb_ldst0_7 1'0 + sync posedge \coresync_clk + update \dp_INT_rb_ldst0_7 \dp_INT_rb_ldst0_7$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $479 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg2 + connect \S \rp_INT_rb_ldst0_7 + connect \Y $478 + end + process $group_253 + assign \addr_en_INT_rb_ldst0_7 5'00000 + assign \addr_en_INT_rb_ldst0_7 $478 + sync init + end + process $group_254 + assign \fus_src2_i$60 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_rb_ldst0_7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src2_i$60 \int_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $480 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_rb_alu0_0 + connect \B \addr_en_INT_rb_cr0_1 + connect \Y $480 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $482 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_rb_trap0_2 + connect \B \addr_en_INT_rb_logical0_3 + connect \Y $482 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $484 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $480 + connect \B $482 + connect \Y $484 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $486 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_rb_div0_4 + connect \B \addr_en_INT_rb_mul0_5 + connect \Y $486 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $488 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_rb_shiftrot0_6 + connect \B \addr_en_INT_rb_ldst0_7 + connect \Y $488 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $490 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $486 + connect \B $488 + connect \Y $490 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $492 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $484 + connect \B $490 + connect \Y $492 + end + process $group_255 + assign \int_src2__addr 5'00000 + assign \int_src2__addr $492 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 $494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + cell $reduce_bool $495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } + connect \Y $494 + end + process $group_256 + assign \int_src2__ren 1'0 + assign \int_src2__ren $494 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_INT_rc_0 + process $group_257 + assign \rdflag_INT_rc_0 1'0 + assign \rdflag_INT_rc_0 \reg3_ok + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$48 [2] + connect \B \fu_enable [8] + connect \Y $496 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $496 + connect \B \rdflag_INT_rc_0 + connect \Y $498 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rc_shiftrot0_0 + connect \Y $500 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $498 + connect \B $500 + connect \Y $502 + end + process $group_258 + assign \pick_INT_rc_shiftrot0_0 1'0 + assign \pick_INT_rc_shiftrot0_0 $502 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_INT_rc_ldst0_1 + process $group_259 + assign \rdpick_INT_rc_i 2'00 + assign \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 + assign \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rc_o [0] + connect \B \rdpick_INT_rc_en_o + connect \Y $504 + end + process $group_260 + assign \rp_INT_rc_shiftrot0_0 1'0 + assign \rp_INT_rc_shiftrot0_0 $504 + sync init + end + process $group_261 + assign \dp_INT_rc_shiftrot0_0$next \dp_INT_rc_shiftrot0_0 + assign \dp_INT_rc_shiftrot0_0$next \rp_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_rc_shiftrot0_0$next 1'0 + end + sync init + update \dp_INT_rc_shiftrot0_0 1'0 + sync posedge \coresync_clk + update \dp_INT_rc_shiftrot0_0 \dp_INT_rc_shiftrot0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $507 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg3 + connect \S \rp_INT_rc_shiftrot0_0 + connect \Y $506 + end + process $group_262 + assign \addr_en_INT_rc_shiftrot0_0 5'00000 + assign \addr_en_INT_rc_shiftrot0_0 $506 + sync init + end + process $group_263 + assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_rc_shiftrot0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src3_i \int_src3__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$51 [2] + connect \B \fu_enable [9] + connect \Y $508 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $510 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $508 + connect \B \rdflag_INT_rc_0 + connect \Y $510 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_INT_rc_ldst0_1 + connect \Y $512 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $510 + connect \B $512 + connect \Y $514 + end + process $group_264 + assign \pick_INT_rc_ldst0_1 1'0 + assign \pick_INT_rc_ldst0_1 $514 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_INT_rc_o [1] + connect \B \rdpick_INT_rc_en_o + connect \Y $516 + end + process $group_265 + assign \rp_INT_rc_ldst0_1 1'0 + assign \rp_INT_rc_ldst0_1 $516 + sync init + end + process $group_266 + assign \dp_INT_rc_ldst0_1$next \dp_INT_rc_ldst0_1 + assign \dp_INT_rc_ldst0_1$next \rp_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_INT_rc_ldst0_1$next 1'0 + end + sync init + update \dp_INT_rc_ldst0_1 1'0 + sync posedge \coresync_clk + update \dp_INT_rc_ldst0_1 \dp_INT_rc_ldst0_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 5 \addr_en_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 5 $518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $519 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \reg3 + connect \S \rp_INT_rc_ldst0_1 + connect \Y $518 + end + process $group_267 + assign \addr_en_INT_rc_ldst0_1 5'00000 + assign \addr_en_INT_rc_ldst0_1 $518 + sync init + end + process $group_268 + assign \fus_src3_i$61 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_INT_rc_ldst0_1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src3_i$61 \int_src3__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $520 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en_INT_rc_shiftrot0_0 + connect \B \addr_en_INT_rc_ldst0_1 + connect \Y $520 + end + process $group_269 + assign \int_src3__addr 5'00000 + assign \int_src3__addr $520 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 $522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + cell $reduce_bool $523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } + connect \Y $522 + end + process $group_270 + assign \int_src3__ren 1'0 + assign \int_src3__ren $522 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_XER_xer_so_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $and $525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $524 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + wire width 1 $526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" + cell $or $527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $524 + connect \B \xer_in + connect \Y $526 + end + process $group_271 + assign \rdflag_XER_xer_so_0 1'0 + assign \rdflag_XER_xer_so_0 $526 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o [2] + connect \B \fu_enable [0] + connect \Y $528 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $528 + connect \B \rdflag_XER_xer_so_0 + connect \Y $530 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_alu0_0 + connect \Y $532 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $530 + connect \B $532 + connect \Y $534 + end + process $group_272 + assign \pick_XER_xer_so_alu0_0 1'0 + assign \pick_XER_xer_so_alu0_0 $534 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_XER_xer_so_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_XER_xer_so_div0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_XER_xer_so_mul0_3 + process $group_273 + assign \rdpick_XER_xer_so_i 4'0000 + assign \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 + assign \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_spr0_1 + assign \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_div0_2 + assign \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_mul0_3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [0] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $536 + end + process $group_274 + assign \rp_XER_xer_so_alu0_0 1'0 + assign \rp_XER_xer_so_alu0_0 $536 + sync init + end + process $group_275 + assign \dp_XER_xer_so_alu0_0$next \dp_XER_xer_so_alu0_0 + assign \dp_XER_xer_so_alu0_0$next \rp_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_XER_xer_so_alu0_0$next 1'0 + end + sync init + update \dp_XER_xer_so_alu0_0 1'0 + sync posedge \coresync_clk + update \dp_XER_xer_so_alu0_0 \dp_XER_xer_so_alu0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \addr_en_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 1 $538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $539 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_alu0_0 + connect \Y $538 + end + process $group_276 + assign \addr_en_XER_xer_so_alu0_0 1'0 + assign \addr_en_XER_xer_so_alu0_0 $538 + sync init + end + process $group_277 + assign \fus_src3_i$62 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_XER_xer_so_alu0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src3_i$62 \xer_src1__data_o [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$39 [3] + connect \B \fu_enable [5] + connect \Y $540 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $540 + connect \B \rdflag_XER_xer_so_0 + connect \Y $542 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_spr0_1 + connect \Y $544 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $542 + connect \B $544 + connect \Y $546 + end + process $group_278 + assign \pick_XER_xer_so_spr0_1 1'0 + assign \pick_XER_xer_so_spr0_1 $546 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_XER_xer_so_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [1] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $548 + end + process $group_279 + assign \rp_XER_xer_so_spr0_1 1'0 + assign \rp_XER_xer_so_spr0_1 $548 + sync init + end + process $group_280 + assign \dp_XER_xer_so_spr0_1$next \dp_XER_xer_so_spr0_1 + assign \dp_XER_xer_so_spr0_1$next \rp_XER_xer_so_spr0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_XER_xer_so_spr0_1$next 1'0 + end + sync init + update \dp_XER_xer_so_spr0_1 1'0 + sync posedge \coresync_clk + update \dp_XER_xer_so_spr0_1 \dp_XER_xer_so_spr0_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \addr_en_XER_xer_so_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 1 $550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $551 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_spr0_1 + connect \Y $550 + end + process $group_281 + assign \addr_en_XER_xer_so_spr0_1 1'0 + assign \addr_en_XER_xer_so_spr0_1 $550 + sync init + end + process $group_282 + assign \fus_src4_i 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_XER_xer_so_spr0_1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src4_i \xer_src1__data_o [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$42 [2] + connect \B \fu_enable [6] + connect \Y $552 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $552 + connect \B \rdflag_XER_xer_so_0 + connect \Y $554 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_div0_2 + connect \Y $556 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $554 + connect \B $556 + connect \Y $558 + end + process $group_283 + assign \pick_XER_xer_so_div0_2 1'0 + assign \pick_XER_xer_so_div0_2 $558 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_XER_xer_so_div0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [2] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $560 + end + process $group_284 + assign \rp_XER_xer_so_div0_2 1'0 + assign \rp_XER_xer_so_div0_2 $560 + sync init + end + process $group_285 + assign \dp_XER_xer_so_div0_2$next \dp_XER_xer_so_div0_2 + assign \dp_XER_xer_so_div0_2$next \rp_XER_xer_so_div0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_XER_xer_so_div0_2$next 1'0 + end + sync init + update \dp_XER_xer_so_div0_2 1'0 + sync posedge \coresync_clk + update \dp_XER_xer_so_div0_2 \dp_XER_xer_so_div0_2$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \addr_en_XER_xer_so_div0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 1 $562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $563 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_div0_2 + connect \Y $562 + end + process $group_286 + assign \addr_en_XER_xer_so_div0_2 1'0 + assign \addr_en_XER_xer_so_div0_2 $562 + sync init + end + process $group_287 + assign \fus_src3_i$63 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_XER_xer_so_div0_2 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src3_i$63 \xer_src1__data_o [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$45 [2] + connect \B \fu_enable [7] + connect \Y $564 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $564 + connect \B \rdflag_XER_xer_so_0 + connect \Y $566 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_so_mul0_3 + connect \Y $568 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $570 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $566 + connect \B $568 + connect \Y $570 + end + process $group_288 + assign \pick_XER_xer_so_mul0_3 1'0 + assign \pick_XER_xer_so_mul0_3 $570 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_XER_xer_so_mul0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $572 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_so_o [3] + connect \B \rdpick_XER_xer_so_en_o + connect \Y $572 + end + process $group_289 + assign \rp_XER_xer_so_mul0_3 1'0 + assign \rp_XER_xer_so_mul0_3 $572 + sync init + end + process $group_290 + assign \dp_XER_xer_so_mul0_3$next \dp_XER_xer_so_mul0_3 + assign \dp_XER_xer_so_mul0_3$next \rp_XER_xer_so_mul0_3 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_XER_xer_so_mul0_3$next 1'0 + end + sync init + update \dp_XER_xer_so_mul0_3 1'0 + sync posedge \coresync_clk + update \dp_XER_xer_so_mul0_3 \dp_XER_xer_so_mul0_3$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 1 \addr_en_XER_xer_so_mul0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 1 $574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $575 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_mul0_3 + connect \Y $574 + end + process $group_291 + assign \addr_en_XER_xer_so_mul0_3 1'0 + assign \addr_en_XER_xer_so_mul0_3 $574 + sync init + end + process $group_292 + assign \fus_src3_i$64 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_XER_xer_so_mul0_3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src3_i$64 \xer_src1__data_o [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $576 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $577 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en_XER_xer_so_alu0_0 + connect \B \addr_en_XER_xer_so_spr0_1 + connect \Y $577 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $579 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en_XER_xer_so_div0_2 + connect \B \addr_en_XER_xer_so_mul0_3 + connect \Y $579 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $581 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $577 + connect \B $579 + connect \Y $581 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A $581 + connect \Y $576 + end + process $group_293 + assign \xer_src1__ren 3'000 + assign \xer_src1__ren $576 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_XER_xer_ca_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire width 1 $584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $eq $585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \input_carry + connect \B 2'10 + connect \Y $584 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + wire width 1 $586 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" + cell $or $587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $584 + connect \B \xer_in + connect \Y $586 + end + process $group_294 + assign \rdflag_XER_xer_ca_0 1'0 + assign \rdflag_XER_xer_ca_0 $586 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $588 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o [3] + connect \B \fu_enable [0] + connect \Y $588 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $588 + connect \B \rdflag_XER_xer_ca_0 + connect \Y $590 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_ca_alu0_0 + connect \Y $592 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $590 + connect \B $592 + connect \Y $594 + end + process $group_295 + assign \pick_XER_xer_ca_alu0_0 1'0 + assign \pick_XER_xer_ca_alu0_0 $594 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_XER_xer_ca_shiftrot0_2 + process $group_296 + assign \rdpick_XER_xer_ca_i 3'000 + assign \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 + assign \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 + assign \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $596 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_ca_o [0] + connect \B \rdpick_XER_xer_ca_en_o + connect \Y $596 + end + process $group_297 + assign \rp_XER_xer_ca_alu0_0 1'0 + assign \rp_XER_xer_ca_alu0_0 $596 + sync init + end + process $group_298 + assign \dp_XER_xer_ca_alu0_0$next \dp_XER_xer_ca_alu0_0 + assign \dp_XER_xer_ca_alu0_0$next \rp_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_XER_xer_ca_alu0_0$next 1'0 + end + sync init + update \dp_XER_xer_ca_alu0_0 1'0 + sync posedge \coresync_clk + update \dp_XER_xer_ca_alu0_0 \dp_XER_xer_ca_alu0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 2 \addr_en_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 2 $598 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $599 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_alu0_0 + connect \Y $598 + end + process $group_299 + assign \addr_en_XER_xer_ca_alu0_0 2'00 + assign \addr_en_XER_xer_ca_alu0_0 $598 + sync init + end + process $group_300 + assign \fus_src4_i$65 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_XER_xer_ca_alu0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src4_i$65 \xer_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $600 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$39 [5] + connect \B \fu_enable [5] + connect \Y $600 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $600 + connect \B \rdflag_XER_xer_ca_0 + connect \Y $602 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_ca_spr0_1 + connect \Y $604 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $606 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $602 + connect \B $604 + connect \Y $606 + end + process $group_301 + assign \pick_XER_xer_ca_spr0_1 1'0 + assign \pick_XER_xer_ca_spr0_1 $606 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $608 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_ca_o [1] + connect \B \rdpick_XER_xer_ca_en_o + connect \Y $608 + end + process $group_302 + assign \rp_XER_xer_ca_spr0_1 1'0 + assign \rp_XER_xer_ca_spr0_1 $608 + sync init + end + process $group_303 + assign \dp_XER_xer_ca_spr0_1$next \dp_XER_xer_ca_spr0_1 + assign \dp_XER_xer_ca_spr0_1$next \rp_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_XER_xer_ca_spr0_1$next 1'0 + end + sync init + update \dp_XER_xer_ca_spr0_1 1'0 + sync posedge \coresync_clk + update \dp_XER_xer_ca_spr0_1 \dp_XER_xer_ca_spr0_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 2 \addr_en_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 2 $610 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $611 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_spr0_1 + connect \Y $610 + end + process $group_304 + assign \addr_en_XER_xer_ca_spr0_1 2'00 + assign \addr_en_XER_xer_ca_spr0_1 $610 + sync init + end + process $group_305 + assign \fus_src6_i 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_XER_xer_ca_spr0_1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src6_i \xer_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $612 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$48 [3] + connect \B \fu_enable [8] + connect \Y $612 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $614 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $612 + connect \B \rdflag_XER_xer_ca_0 + connect \Y $614 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_ca_shiftrot0_2 + connect \Y $616 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $618 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $614 + connect \B $616 + connect \Y $618 + end + process $group_306 + assign \pick_XER_xer_ca_shiftrot0_2 1'0 + assign \pick_XER_xer_ca_shiftrot0_2 $618 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_ca_o [2] + connect \B \rdpick_XER_xer_ca_en_o + connect \Y $620 + end + process $group_307 + assign \rp_XER_xer_ca_shiftrot0_2 1'0 + assign \rp_XER_xer_ca_shiftrot0_2 $620 + sync init + end + process $group_308 + assign \dp_XER_xer_ca_shiftrot0_2$next \dp_XER_xer_ca_shiftrot0_2 + assign \dp_XER_xer_ca_shiftrot0_2$next \rp_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_XER_xer_ca_shiftrot0_2$next 1'0 + end + sync init + update \dp_XER_xer_ca_shiftrot0_2 1'0 + sync posedge \coresync_clk + update \dp_XER_xer_ca_shiftrot0_2 \dp_XER_xer_ca_shiftrot0_2$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 2 $622 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $623 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_shiftrot0_2 + connect \Y $622 + end + process $group_309 + assign \addr_en_XER_xer_ca_shiftrot0_2 2'00 + assign \addr_en_XER_xer_ca_shiftrot0_2 $622 + sync init + end + process $group_310 + assign \fus_src4_i$66 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_XER_xer_ca_shiftrot0_2 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src4_i$66 \xer_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $624 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $625 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \addr_en_XER_xer_ca_spr0_1 + connect \B \addr_en_XER_xer_ca_shiftrot0_2 + connect \Y $625 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 $627 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \addr_en_XER_xer_ca_alu0_0 + connect \B $625 + connect \Y $627 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A $627 + connect \Y $624 + end + process $group_311 + assign \xer_src2__ren 3'000 + assign \xer_src2__ren $624 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_XER_xer_ov_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $630 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $and $631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $630 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + wire width 1 $632 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" + cell $or $633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $630 + connect \B \xer_in + connect \Y $632 + end + process $group_312 + assign \rdflag_XER_xer_ov_0 1'0 + assign \rdflag_XER_xer_ov_0 $632 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$39 [4] + connect \B \fu_enable [5] + connect \Y $634 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $636 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $634 + connect \B \rdflag_XER_xer_ov_0 + connect \Y $636 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_XER_xer_ov_spr0_0 + connect \Y $638 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $636 + connect \B $638 + connect \Y $640 + end + process $group_313 + assign \pick_XER_xer_ov_spr0_0 1'0 + assign \pick_XER_xer_ov_spr0_0 $640 + sync init + end + process $group_314 + assign \rdpick_XER_xer_ov_i 1'0 + assign \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_XER_xer_ov_o + connect \B \rdpick_XER_xer_ov_en_o + connect \Y $642 + end + process $group_315 + assign \rp_XER_xer_ov_spr0_0 1'0 + assign \rp_XER_xer_ov_spr0_0 $642 + sync init + end + process $group_316 + assign \dp_XER_xer_ov_spr0_0$next \dp_XER_xer_ov_spr0_0 + assign \dp_XER_xer_ov_spr0_0$next \rp_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_XER_xer_ov_spr0_0$next 1'0 + end + sync init + update \dp_XER_xer_ov_spr0_0 1'0 + sync posedge \coresync_clk + update \dp_XER_xer_ov_spr0_0 \dp_XER_xer_ov_spr0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 3 \addr_en_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 3 $644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $645 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \rp_XER_xer_ov_spr0_0 + connect \Y $644 + end + process $group_317 + assign \addr_en_XER_xer_ov_spr0_0 3'000 + assign \addr_en_XER_xer_ov_spr0_0 $644 + sync init + end + process $group_318 + assign \fus_src5_i 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_XER_xer_ov_spr0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src5_i \xer_src3__data_o + end + sync init + end + process $group_319 + assign \xer_src3__ren 3'000 + assign \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_CR_full_cr_0 + process $group_320 + assign \rdflag_CR_full_cr_0 1'0 + assign \rdflag_CR_full_cr_0 \read_cr_whole + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $646 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$30 [2] + connect \B \fu_enable [1] + connect \Y $646 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $648 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $646 + connect \B \rdflag_CR_full_cr_0 + connect \Y $648 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_CR_full_cr_cr0_0 + connect \Y $650 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $648 + connect \B $650 + connect \Y $652 + end + process $group_321 + assign \pick_CR_full_cr_cr0_0 1'0 + assign \pick_CR_full_cr_cr0_0 $652 + sync init + end + process $group_322 + assign \rdpick_CR_full_cr_i 1'0 + assign \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_full_cr_o + connect \B \rdpick_CR_full_cr_en_o + connect \Y $654 + end + process $group_323 + assign \rp_CR_full_cr_cr0_0 1'0 + assign \rp_CR_full_cr_cr0_0 $654 + sync init + end + process $group_324 + assign \dp_CR_full_cr_cr0_0$next \dp_CR_full_cr_cr0_0 + assign \dp_CR_full_cr_cr0_0$next \rp_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_CR_full_cr_cr0_0$next 1'0 + end + sync init + update \dp_CR_full_cr_cr0_0 1'0 + sync posedge \coresync_clk + update \dp_CR_full_cr_cr0_0 \dp_CR_full_cr_cr0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 8 \addr_en_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 8 $656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $657 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B 8'11111111 + connect \S \rp_CR_full_cr_cr0_0 + connect \Y $656 + end + process $group_325 + assign \addr_en_CR_full_cr_cr0_0 8'00000000 + assign \addr_en_CR_full_cr_cr0_0 $656 + sync init + end + process $group_326 + assign \fus_src3_i$67 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_CR_full_cr_cr0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src3_i$67 \cr_full_rd__data_o + end + sync init + end + process $group_327 + assign \cr_full_rd__ren 8'00000000 + assign \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_CR_cr_a_0 + process $group_328 + assign \rdflag_CR_cr_a_0 1'0 + assign \rdflag_CR_cr_a_0 \cr_in1_ok + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $658 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$30 [3] + connect \B \fu_enable [1] + connect \Y $658 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $660 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $658 + connect \B \rdflag_CR_cr_a_0 + connect \Y $660 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_CR_cr_a_cr0_0 + connect \Y $662 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $660 + connect \B $662 + connect \Y $664 + end + process $group_329 + assign \pick_CR_cr_a_cr0_0 1'0 + assign \pick_CR_cr_a_cr0_0 $664 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_CR_cr_a_branch0_1 + process $group_330 + assign \rdpick_CR_cr_a_i 2'00 + assign \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 + assign \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_a_o [0] + connect \B \rdpick_CR_cr_a_en_o + connect \Y $666 + end + process $group_331 + assign \rp_CR_cr_a_cr0_0 1'0 + assign \rp_CR_cr_a_cr0_0 $666 + sync init + end + process $group_332 + assign \dp_CR_cr_a_cr0_0$next \dp_CR_cr_a_cr0_0 + assign \dp_CR_cr_a_cr0_0$next \rp_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_CR_cr_a_cr0_0$next 1'0 + end + sync init + update \dp_CR_cr_a_cr0_0 1'0 + sync posedge \coresync_clk + update \dp_CR_cr_a_cr0_0 \dp_CR_cr_a_cr0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 16 \addr_en_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + wire width 4 $668 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + cell $sub $669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \cr_in1 + connect \Y $668 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + wire width 16 $670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + cell $sshl $671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $668 + connect \Y $670 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 16 $672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $673 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $670 + connect \S \rp_CR_cr_a_cr0_0 + connect \Y $672 + end + process $group_333 + assign \addr_en_CR_cr_a_cr0_0 16'0000000000000000 + assign \addr_en_CR_cr_a_cr0_0 $672 + sync init + end + process $group_334 + assign \fus_src4_i$68 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_CR_cr_a_cr0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src4_i$68 \cr_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$69 [2] + connect \B \fu_enable [2] + connect \Y $674 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $676 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $674 + connect \B \rdflag_CR_cr_a_0 + connect \Y $676 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_CR_cr_a_branch0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_CR_cr_a_branch0_1 + connect \Y $678 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $676 + connect \B $678 + connect \Y $680 + end + process $group_335 + assign \pick_CR_cr_a_branch0_1 1'0 + assign \pick_CR_cr_a_branch0_1 $680 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_FAST_fast1_branch0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" + wire width 1 \dp_FAST_fast2_branch0_0$next + process $group_336 + assign \fus_cu_rd__go_i$70 3'000 + assign \fus_cu_rd__go_i$70 [2] \dp_CR_cr_a_branch0_1 + assign \fus_cu_rd__go_i$70 [0] \dp_FAST_fast1_branch0_0 + assign \fus_cu_rd__go_i$70 [1] \dp_FAST_fast2_branch0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_a_o [1] + connect \B \rdpick_CR_cr_a_en_o + connect \Y $682 + end + process $group_337 + assign \rp_CR_cr_a_branch0_1 1'0 + assign \rp_CR_cr_a_branch0_1 $682 + sync init + end + process $group_338 + assign \dp_CR_cr_a_branch0_1$next \dp_CR_cr_a_branch0_1 + assign \dp_CR_cr_a_branch0_1$next \rp_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_CR_cr_a_branch0_1$next 1'0 + end + sync init + update \dp_CR_cr_a_branch0_1 1'0 + sync posedge \coresync_clk + update \dp_CR_cr_a_branch0_1 \dp_CR_cr_a_branch0_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 16 \addr_en_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + wire width 4 $684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + cell $sub $685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \cr_in1 + connect \Y $684 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + wire width 16 $686 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" + cell $sshl $687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $684 + connect \Y $686 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 16 $688 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $689 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $686 + connect \S \rp_CR_cr_a_branch0_1 + connect \Y $688 + end + process $group_339 + assign \addr_en_CR_cr_a_branch0_1 16'0000000000000000 + assign \addr_en_CR_cr_a_branch0_1 $688 + sync init + end + process $group_340 + assign \fus_src3_i$71 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_CR_cr_a_branch0_1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src3_i$71 \cr_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 $690 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 $691 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \addr_en_CR_cr_a_cr0_0 + connect \B \addr_en_CR_cr_a_branch0_1 + connect \Y $691 + end + connect $690 $691 + process $group_341 + assign \cr_src1__ren 8'00000000 + assign \cr_src1__ren $690 [7:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_CR_cr_b_0 + process $group_342 + assign \rdflag_CR_cr_b_0 1'0 + assign \rdflag_CR_cr_b_0 \cr_in2_ok + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$30 [4] + connect \B \fu_enable [1] + connect \Y $693 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $693 + connect \B \rdflag_CR_cr_b_0 + connect \Y $695 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_CR_cr_b_cr0_0 + connect \Y $697 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $695 + connect \B $697 + connect \Y $699 + end + process $group_343 + assign \pick_CR_cr_b_cr0_0 1'0 + assign \pick_CR_cr_b_cr0_0 $699 + sync init + end + process $group_344 + assign \rdpick_CR_cr_b_i 1'0 + assign \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $701 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_b_o + connect \B \rdpick_CR_cr_b_en_o + connect \Y $701 + end + process $group_345 + assign \rp_CR_cr_b_cr0_0 1'0 + assign \rp_CR_cr_b_cr0_0 $701 + sync init + end + process $group_346 + assign \dp_CR_cr_b_cr0_0$next \dp_CR_cr_b_cr0_0 + assign \dp_CR_cr_b_cr0_0$next \rp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_CR_cr_b_cr0_0$next 1'0 + end + sync init + update \dp_CR_cr_b_cr0_0 1'0 + sync posedge \coresync_clk + update \dp_CR_cr_b_cr0_0 \dp_CR_cr_b_cr0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 16 \addr_en_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" + wire width 4 $703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" + cell $sub $704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \cr_in2 + connect \Y $703 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" + wire width 16 $705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" + cell $sshl $706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $703 + connect \Y $705 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 16 $707 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $708 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $705 + connect \S \rp_CR_cr_b_cr0_0 + connect \Y $707 + end + process $group_347 + assign \addr_en_CR_cr_b_cr0_0 16'0000000000000000 + assign \addr_en_CR_cr_b_cr0_0 $707 + sync init + end + process $group_348 + assign \fus_src5_i$72 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_CR_cr_b_cr0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src5_i$72 \cr_src2__data_o + end + sync init + end + process $group_349 + assign \cr_src2__ren 8'00000000 + assign \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_CR_cr_c_0 + process $group_350 + assign \rdflag_CR_cr_c_0 1'0 + assign \rdflag_CR_cr_c_0 \cr_in2_ok$2 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$30 [5] + connect \B \fu_enable [1] + connect \Y $709 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $709 + connect \B \rdflag_CR_cr_c_0 + connect \Y $711 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_CR_cr_c_cr0_0 + connect \Y $713 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $715 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $711 + connect \B $713 + connect \Y $715 + end + process $group_351 + assign \pick_CR_cr_c_cr0_0 1'0 + assign \pick_CR_cr_c_cr0_0 $715 + sync init + end + process $group_352 + assign \rdpick_CR_cr_c_i 1'0 + assign \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $717 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_CR_cr_c_o + connect \B \rdpick_CR_cr_c_en_o + connect \Y $717 + end + process $group_353 + assign \rp_CR_cr_c_cr0_0 1'0 + assign \rp_CR_cr_c_cr0_0 $717 + sync init + end + process $group_354 + assign \dp_CR_cr_c_cr0_0$next \dp_CR_cr_c_cr0_0 + assign \dp_CR_cr_c_cr0_0$next \rp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_CR_cr_c_cr0_0$next 1'0 + end + sync init + update \dp_CR_cr_c_cr0_0 1'0 + sync posedge \coresync_clk + update \dp_CR_cr_c_cr0_0 \dp_CR_cr_c_cr0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 16 \addr_en_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" + wire width 4 $719 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" + cell $sub $720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \cr_in2$1 + connect \Y $719 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" + wire width 16 $721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" + cell $sshl $722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $719 + connect \Y $721 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 16 $723 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $724 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $721 + connect \S \rp_CR_cr_c_cr0_0 + connect \Y $723 + end + process $group_355 + assign \addr_en_CR_cr_c_cr0_0 16'0000000000000000 + assign \addr_en_CR_cr_c_cr0_0 $723 + sync init + end + process $group_356 + assign \fus_src6_i$73 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_CR_cr_c_cr0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src6_i$73 \cr_src3__data_o + end + sync init + end + process $group_357 + assign \cr_src3__ren 8'00000000 + assign \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_FAST_fast1_0 + process $group_358 + assign \rdflag_FAST_fast1_0 1'0 + assign \rdflag_FAST_fast1_0 \fast1_ok + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $725 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$69 [0] + connect \B \fu_enable [2] + connect \Y $725 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $725 + connect \B \rdflag_FAST_fast1_0 + connect \Y $727 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $729 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_FAST_fast1_branch0_0 + connect \Y $729 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $727 + connect \B $729 + connect \Y $731 + end + process $group_359 + assign \pick_FAST_fast1_branch0_0 1'0 + assign \pick_FAST_fast1_branch0_0 $731 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_FAST_fast1_spr0_2 + process $group_360 + assign \rdpick_FAST_fast1_i 3'000 + assign \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 + assign \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 + assign \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $733 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast1_o [0] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $733 + end + process $group_361 + assign \rp_FAST_fast1_branch0_0 1'0 + assign \rp_FAST_fast1_branch0_0 $733 + sync init + end + process $group_362 + assign \dp_FAST_fast1_branch0_0$next \dp_FAST_fast1_branch0_0 + assign \dp_FAST_fast1_branch0_0$next \rp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_FAST_fast1_branch0_0$next 1'0 + end + sync init + update \dp_FAST_fast1_branch0_0 1'0 + sync posedge \coresync_clk + update \dp_FAST_fast1_branch0_0 \dp_FAST_fast1_branch0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 3 \addr_en_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 3 $735 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $736 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \fast1 + connect \S \rp_FAST_fast1_branch0_0 + connect \Y $735 + end + process $group_363 + assign \addr_en_FAST_fast1_branch0_0 3'000 + assign \addr_en_FAST_fast1_branch0_0 $735 + sync init + end + process $group_364 + assign \fus_src1_i$74 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_FAST_fast1_branch0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src1_i$74 \fast_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $737 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$33 [2] + connect \B \fu_enable [3] + connect \Y $737 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $739 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $737 + connect \B \rdflag_FAST_fast1_0 + connect \Y $739 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $741 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_FAST_fast1_trap0_1 + connect \Y $741 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $743 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $739 + connect \B $741 + connect \Y $743 + end + process $group_365 + assign \pick_FAST_fast1_trap0_1 1'0 + assign \pick_FAST_fast1_trap0_1 $743 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast1_o [1] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $745 + end + process $group_366 + assign \rp_FAST_fast1_trap0_1 1'0 + assign \rp_FAST_fast1_trap0_1 $745 + sync init + end + process $group_367 + assign \dp_FAST_fast1_trap0_1$next \dp_FAST_fast1_trap0_1 + assign \dp_FAST_fast1_trap0_1$next \rp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_FAST_fast1_trap0_1$next 1'0 + end + sync init + update \dp_FAST_fast1_trap0_1 1'0 + sync posedge \coresync_clk + update \dp_FAST_fast1_trap0_1 \dp_FAST_fast1_trap0_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 3 \addr_en_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 3 $747 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $748 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \fast1 + connect \S \rp_FAST_fast1_trap0_1 + connect \Y $747 + end + process $group_368 + assign \addr_en_FAST_fast1_trap0_1 3'000 + assign \addr_en_FAST_fast1_trap0_1 $747 + sync init + end + process $group_369 + assign \fus_src3_i$75 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_FAST_fast1_trap0_1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src3_i$75 \fast_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $749 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$39 [2] + connect \B \fu_enable [5] + connect \Y $749 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $751 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $749 + connect \B \rdflag_FAST_fast1_0 + connect \Y $751 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_FAST_fast1_spr0_2 + connect \Y $753 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $751 + connect \B $753 + connect \Y $755 + end + process $group_370 + assign \pick_FAST_fast1_spr0_2 1'0 + assign \pick_FAST_fast1_spr0_2 $755 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $757 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast1_o [2] + connect \B \rdpick_FAST_fast1_en_o + connect \Y $757 + end + process $group_371 + assign \rp_FAST_fast1_spr0_2 1'0 + assign \rp_FAST_fast1_spr0_2 $757 + sync init + end + process $group_372 + assign \dp_FAST_fast1_spr0_2$next \dp_FAST_fast1_spr0_2 + assign \dp_FAST_fast1_spr0_2$next \rp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_FAST_fast1_spr0_2$next 1'0 + end + sync init + update \dp_FAST_fast1_spr0_2 1'0 + sync posedge \coresync_clk + update \dp_FAST_fast1_spr0_2 \dp_FAST_fast1_spr0_2$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 3 \addr_en_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 3 $759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $760 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \fast1 + connect \S \rp_FAST_fast1_spr0_2 + connect \Y $759 + end + process $group_373 + assign \addr_en_FAST_fast1_spr0_2 3'000 + assign \addr_en_FAST_fast1_spr0_2 $759 + sync init + end + process $group_374 + assign \fus_src3_i$76 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_FAST_fast1_spr0_2 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src3_i$76 \fast_src1__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 $761 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en_FAST_fast1_trap0_1 + connect \B \addr_en_FAST_fast1_spr0_2 + connect \Y $761 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $763 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en_FAST_fast1_branch0_0 + connect \B $761 + connect \Y $763 + end + process $group_375 + assign \fast_src1__addr 3'000 + assign \fast_src1__addr $763 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 $765 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + cell $reduce_bool $766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } + connect \Y $765 + end + process $group_376 + assign \fast_src1__ren 1'0 + assign \fast_src1__ren $765 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_FAST_fast2_0 + process $group_377 + assign \rdflag_FAST_fast2_0 1'0 + assign \rdflag_FAST_fast2_0 \fast2_ok + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $767 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$69 [1] + connect \B \fu_enable [2] + connect \Y $767 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $769 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $767 + connect \B \rdflag_FAST_fast2_0 + connect \Y $769 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_FAST_fast2_branch0_0 + connect \Y $771 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $769 + connect \B $771 + connect \Y $773 + end + process $group_378 + assign \pick_FAST_fast2_branch0_0 1'0 + assign \pick_FAST_fast2_branch0_0 $773 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_FAST_fast2_trap0_1 + process $group_379 + assign \rdpick_FAST_fast2_i 2'00 + assign \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 + assign \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $775 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast2_o [0] + connect \B \rdpick_FAST_fast2_en_o + connect \Y $775 + end + process $group_380 + assign \rp_FAST_fast2_branch0_0 1'0 + assign \rp_FAST_fast2_branch0_0 $775 + sync init + end + process $group_381 + assign \dp_FAST_fast2_branch0_0$next \dp_FAST_fast2_branch0_0 + assign \dp_FAST_fast2_branch0_0$next \rp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_FAST_fast2_branch0_0$next 1'0 + end + sync init + update \dp_FAST_fast2_branch0_0 1'0 + sync posedge \coresync_clk + update \dp_FAST_fast2_branch0_0 \dp_FAST_fast2_branch0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 3 \addr_en_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 3 $777 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $778 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \fast2 + connect \S \rp_FAST_fast2_branch0_0 + connect \Y $777 + end + process $group_382 + assign \addr_en_FAST_fast2_branch0_0 3'000 + assign \addr_en_FAST_fast2_branch0_0 $777 + sync init + end + process $group_383 + assign \fus_src2_i$77 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_FAST_fast2_branch0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src2_i$77 \fast_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$33 [3] + connect \B \fu_enable [3] + connect \Y $779 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $781 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $779 + connect \B \rdflag_FAST_fast2_0 + connect \Y $781 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_FAST_fast2_trap0_1 + connect \Y $783 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $785 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $781 + connect \B $783 + connect \Y $785 + end + process $group_384 + assign \pick_FAST_fast2_trap0_1 1'0 + assign \pick_FAST_fast2_trap0_1 $785 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_FAST_fast2_o [1] + connect \B \rdpick_FAST_fast2_en_o + connect \Y $787 + end + process $group_385 + assign \rp_FAST_fast2_trap0_1 1'0 + assign \rp_FAST_fast2_trap0_1 $787 + sync init + end + process $group_386 + assign \dp_FAST_fast2_trap0_1$next \dp_FAST_fast2_trap0_1 + assign \dp_FAST_fast2_trap0_1$next \rp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_FAST_fast2_trap0_1$next 1'0 + end + sync init + update \dp_FAST_fast2_trap0_1 1'0 + sync posedge \coresync_clk + update \dp_FAST_fast2_trap0_1 \dp_FAST_fast2_trap0_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 3 \addr_en_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 3 $789 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $790 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \fast2 + connect \S \rp_FAST_fast2_trap0_1 + connect \Y $789 + end + process $group_387 + assign \addr_en_FAST_fast2_trap0_1 3'000 + assign \addr_en_FAST_fast2_trap0_1 $789 + sync init + end + process $group_388 + assign \fus_src4_i$78 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_FAST_fast2_trap0_1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src4_i$78 \fast_src2__data_o + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 $791 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en_FAST_fast2_branch0_0 + connect \B \addr_en_FAST_fast2_trap0_1 + connect \Y $791 + end + process $group_389 + assign \fast_src2__addr 3'000 + assign \fast_src2__addr $791 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 $793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + cell $reduce_bool $794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } + connect \Y $793 + end + process $group_390 + assign \fast_src2__ren 1'0 + assign \fast_src2__ren $793 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:201" + wire width 1 \rdflag_SPR_spr1_0 + process $group_391 + assign \rdflag_SPR_spr1_0 1'0 + assign \rdflag_SPR_spr1_0 \spr1_ok + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + wire width 1 \pick_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $795 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_rd__rel_o$39 [1] + connect \B \fu_enable [5] + connect \Y $795 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + wire width 1 $797 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" + cell $and $798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $795 + connect \B \rdflag_SPR_spr1_0 + connect \Y $797 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $799 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $not $800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dp_SPR_spr1_spr0_0 + connect \Y $799 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + wire width 1 $801 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:231" + cell $and $802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $797 + connect \B $799 + connect \Y $801 + end + process $group_392 + assign \pick_SPR_spr1_spr0_0 1'0 + assign \pick_SPR_spr1_spr0_0 $801 + sync init + end + process $group_393 + assign \rdpick_SPR_spr1_i 1'0 + assign \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + wire width 1 \rp_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 $803 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + cell $and $804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rdpick_SPR_spr1_o + connect \B \rdpick_SPR_spr1_en_o + connect \Y $803 + end + process $group_394 + assign \rp_SPR_spr1_spr0_0 1'0 + assign \rp_SPR_spr1_spr0_0 $803 + sync init + end + process $group_395 + assign \dp_SPR_spr1_spr0_0$next \dp_SPR_spr1_spr0_0 + assign \dp_SPR_spr1_spr0_0$next \rp_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \dp_SPR_spr1_spr0_0$next 1'0 + end + sync init + update \dp_SPR_spr1_spr0_0 1'0 + sync posedge \coresync_clk + update \dp_SPR_spr1_spr0_0 \dp_SPR_spr1_spr0_0$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + wire width 10 \addr_en_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + wire width 10 $805 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:238" + cell $mux $806 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \spr1 + connect \S \rp_SPR_spr1_spr0_0 + connect \Y $805 + end + process $group_396 + assign \addr_en_SPR_spr1_spr0_0 10'0000000000 + assign \addr_en_SPR_spr1_spr0_0 $805 + sync init + end + process $group_397 + assign \fus_src2_i$79 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + switch { \dp_SPR_spr1_spr0_0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:249" + case 1'1 + assign \fus_src2_i$79 \spr_spr1__data_o + end + sync init + end + process $group_398 + assign \spr_spr1__addr 7'0000000 + assign \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + wire width 1 $807 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" + cell $reduce_bool $808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A { \rp_SPR_spr1_spr0_0 } + connect \Y $807 + end + process $group_399 + assign \spr_spr1__ren 1'0 + assign \spr_spr1__ren $807 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_alu0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok + connect \B \fus_cu_busy_o + connect \Y $809 + end + process $group_400 + assign \wrflag_alu0_o_0 1'0 + assign \wrflag_alu0_o_0 $809 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [0] + connect \B \fu_enable [0] + connect \Y $811 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$81 [0] + connect \B \fu_enable [1] + connect \Y $813 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$84 [0] + connect \B \fu_enable [3] + connect \Y $815 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$87 [0] + connect \B \fu_enable [4] + connect \Y $817 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $819 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$90 [0] + connect \B \fu_enable [5] + connect \Y $819 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $821 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$93 [0] + connect \B \fu_enable [6] + connect \Y $821 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$96 [0] + connect \B \fu_enable [7] + connect \Y $823 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $825 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$99 [0] + connect \B \fu_enable [8] + connect \Y $825 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$101 [0] + connect \B \fu_enable [9] + connect \Y $827 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$101 [1] + connect \B \fu_enable [9] + connect \Y $829 + end + process $group_401 + assign \wrpick_INT_o_i 10'0000000000 + assign \wrpick_INT_o_i [0] $811 + assign \wrpick_INT_o_i [1] $813 + assign \wrpick_INT_o_i [2] $815 + assign \wrpick_INT_o_i [3] $817 + assign \wrpick_INT_o_i [4] $819 + assign \wrpick_INT_o_i [5] $821 + assign \wrpick_INT_o_i [6] $823 + assign \wrpick_INT_o_i [7] $825 + assign \wrpick_INT_o_i [8] $827 + assign \wrpick_INT_o_i [9] $829 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $831 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [0] + connect \B \wrpick_INT_o_en_o + connect \Y $831 + end + process $group_402 + assign \wr_pick 1'0 + assign \wr_pick $831 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$next + process $group_403 + assign \wr_pick_dly$next \wr_pick_dly + assign \wr_pick_dly$next \wr_pick + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$next 1'0 + end + sync init + update \wr_pick_dly 1'0 + sync posedge \coresync_clk + update \wr_pick_dly \wr_pick_dly$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $833 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly + connect \Y $833 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $835 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick + connect \B $833 + connect \Y $835 + end + process $group_404 + assign \wr_pick_rise 1'0 + assign \wr_pick_rise $835 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$837 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$838 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$839 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$840 + process $group_405 + assign \fus_cu_wr__go_i 5'00000 + assign \fus_cu_wr__go_i [0] \wr_pick_rise + assign \fus_cu_wr__go_i [1] \wr_pick_rise$837 + assign \fus_cu_wr__go_i [2] \wr_pick_rise$838 + assign \fus_cu_wr__go_i [3] \wr_pick_rise$839 + assign \fus_cu_wr__go_i [4] \wr_pick_rise$840 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick + connect \B \wrpick_INT_o_en_o + connect \Y $841 + end + process $group_406 + assign \wp 1'0 + assign \wp $841 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 5 \addr_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 5 $843 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $844 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \rego + connect \S \wp + connect \Y $843 + end + process $group_407 + assign \addr_en 5'00000 + assign \addr_en $843 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_cr0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $845 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$80 + connect \B \fus_cu_busy_o$4 + connect \Y $845 + end + process $group_408 + assign \wrflag_cr0_o_0 1'0 + assign \wrflag_cr0_o_0 $845 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$847 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [1] + connect \B \wrpick_INT_o_en_o + connect \Y $848 + end + process $group_409 + assign \wr_pick$847 1'0 + assign \wr_pick$847 $848 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$850 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$850$next + process $group_410 + assign \wr_pick_dly$850$next \wr_pick_dly$850 + assign \wr_pick_dly$850$next \wr_pick$847 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$850$next 1'0 + end + sync init + update \wr_pick_dly$850 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$850 \wr_pick_dly$850$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$851 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $852 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$850 + connect \Y $852 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $854 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$847 + connect \B $852 + connect \Y $854 + end + process $group_411 + assign \wr_pick_rise$851 1'0 + assign \wr_pick_rise$851 $854 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$856 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$857 + process $group_412 + assign \fus_cu_wr__go_i$82 3'000 + assign \fus_cu_wr__go_i$82 [0] \wr_pick_rise$851 + assign \fus_cu_wr__go_i$82 [1] \wr_pick_rise$856 + assign \fus_cu_wr__go_i$82 [2] \wr_pick_rise$857 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $859 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$847 + connect \B \wrpick_INT_o_en_o + connect \Y $859 + end + process $group_413 + assign \wp$858 1'0 + assign \wp$858 $859 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 5 \addr_en$861 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 5 $862 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $863 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \rego + connect \S \wp$858 + connect \Y $862 + end + process $group_414 + assign \addr_en$861 5'00000 + assign \addr_en$861 $862 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_trap0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $864 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$83 + connect \B \fus_cu_busy_o$10 + connect \Y $864 + end + process $group_415 + assign \wrflag_trap0_o_0 1'0 + assign \wrflag_trap0_o_0 $864 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $867 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [2] + connect \B \wrpick_INT_o_en_o + connect \Y $867 + end + process $group_416 + assign \wr_pick$866 1'0 + assign \wr_pick$866 $867 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$869 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$869$next + process $group_417 + assign \wr_pick_dly$869$next \wr_pick_dly$869 + assign \wr_pick_dly$869$next \wr_pick$866 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$869$next 1'0 + end + sync init + update \wr_pick_dly$869 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$869 \wr_pick_dly$869$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$870 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $871 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$869 + connect \Y $871 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $873 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$866 + connect \B $871 + connect \Y $873 + end + process $group_418 + assign \wr_pick_rise$870 1'0 + assign \wr_pick_rise$870 $873 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$875 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$876 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$877 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$878 + process $group_419 + assign \fus_cu_wr__go_i$85 5'00000 + assign \fus_cu_wr__go_i$85 [0] \wr_pick_rise$870 + assign \fus_cu_wr__go_i$85 [1] \wr_pick_rise$875 + assign \fus_cu_wr__go_i$85 [2] \wr_pick_rise$876 + assign \fus_cu_wr__go_i$85 [3] \wr_pick_rise$877 + assign \fus_cu_wr__go_i$85 [4] \wr_pick_rise$878 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$879 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $880 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$866 + connect \B \wrpick_INT_o_en_o + connect \Y $880 + end + process $group_420 + assign \wp$879 1'0 + assign \wp$879 $880 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 5 \addr_en$882 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 5 $883 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $884 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \rego + connect \S \wp$879 + connect \Y $883 + end + process $group_421 + assign \addr_en$882 5'00000 + assign \addr_en$882 $883 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_logical0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $885 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$86 + connect \B \fus_cu_busy_o$13 + connect \Y $885 + end + process $group_422 + assign \wrflag_logical0_o_0 1'0 + assign \wrflag_logical0_o_0 $885 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$887 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $888 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [3] + connect \B \wrpick_INT_o_en_o + connect \Y $888 + end + process $group_423 + assign \wr_pick$887 1'0 + assign \wr_pick$887 $888 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$890 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$890$next + process $group_424 + assign \wr_pick_dly$890$next \wr_pick_dly$890 + assign \wr_pick_dly$890$next \wr_pick$887 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$890$next 1'0 + end + sync init + update \wr_pick_dly$890 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$890 \wr_pick_dly$890$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$891 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $892 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$890 + connect \Y $892 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $894 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$887 + connect \B $892 + connect \Y $894 + end + process $group_425 + assign \wr_pick_rise$891 1'0 + assign \wr_pick_rise$891 $894 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$896 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$897 + process $group_426 + assign \fus_cu_wr__go_i$88 3'000 + assign \fus_cu_wr__go_i$88 [0] \wr_pick_rise$891 + assign \fus_cu_wr__go_i$88 [1] \wr_pick_rise$896 + assign \fus_cu_wr__go_i$88 [2] \wr_pick_rise$897 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $899 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$887 + connect \B \wrpick_INT_o_en_o + connect \Y $899 + end + process $group_427 + assign \wp$898 1'0 + assign \wp$898 $899 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 5 \addr_en$901 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 5 $902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $903 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \rego + connect \S \wp$898 + connect \Y $902 + end + process $group_428 + assign \addr_en$901 5'00000 + assign \addr_en$901 $902 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_spr0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $904 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$89 + connect \B \fus_cu_busy_o$16 + connect \Y $904 + end + process $group_429 + assign \wrflag_spr0_o_0 1'0 + assign \wrflag_spr0_o_0 $904 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$906 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $907 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [4] + connect \B \wrpick_INT_o_en_o + connect \Y $907 + end + process $group_430 + assign \wr_pick$906 1'0 + assign \wr_pick$906 $907 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$909 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$909$next + process $group_431 + assign \wr_pick_dly$909$next \wr_pick_dly$909 + assign \wr_pick_dly$909$next \wr_pick$906 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$909$next 1'0 + end + sync init + update \wr_pick_dly$909 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$909 \wr_pick_dly$909$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$910 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $911 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$909 + connect \Y $911 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $913 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$906 + connect \B $911 + connect \Y $913 + end + process $group_432 + assign \wr_pick_rise$910 1'0 + assign \wr_pick_rise$910 $913 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$915 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$916 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$917 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$918 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$919 + process $group_433 + assign \fus_cu_wr__go_i$91 6'000000 + assign \fus_cu_wr__go_i$91 [0] \wr_pick_rise$910 + assign \fus_cu_wr__go_i$91 [5] \wr_pick_rise$915 + assign \fus_cu_wr__go_i$91 [4] \wr_pick_rise$916 + assign \fus_cu_wr__go_i$91 [3] \wr_pick_rise$917 + assign \fus_cu_wr__go_i$91 [2] \wr_pick_rise$918 + assign \fus_cu_wr__go_i$91 [1] \wr_pick_rise$919 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $921 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$906 + connect \B \wrpick_INT_o_en_o + connect \Y $921 + end + process $group_434 + assign \wp$920 1'0 + assign \wp$920 $921 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 5 \addr_en$923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 5 $924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $925 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \rego + connect \S \wp$920 + connect \Y $924 + end + process $group_435 + assign \addr_en$923 5'00000 + assign \addr_en$923 $924 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_div0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $926 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$92 + connect \B \fus_cu_busy_o$19 + connect \Y $926 + end + process $group_436 + assign \wrflag_div0_o_0 1'0 + assign \wrflag_div0_o_0 $926 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $929 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [5] + connect \B \wrpick_INT_o_en_o + connect \Y $929 + end + process $group_437 + assign \wr_pick$928 1'0 + assign \wr_pick$928 $929 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$931 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$931$next + process $group_438 + assign \wr_pick_dly$931$next \wr_pick_dly$931 + assign \wr_pick_dly$931$next \wr_pick$928 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$931$next 1'0 + end + sync init + update \wr_pick_dly$931 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$931 \wr_pick_dly$931$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$932 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $933 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$931 + connect \Y $933 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $935 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$928 + connect \B $933 + connect \Y $935 + end + process $group_439 + assign \wr_pick_rise$932 1'0 + assign \wr_pick_rise$932 $935 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$937 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$938 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$939 + process $group_440 + assign \fus_cu_wr__go_i$94 4'0000 + assign \fus_cu_wr__go_i$94 [0] \wr_pick_rise$932 + assign \fus_cu_wr__go_i$94 [1] \wr_pick_rise$937 + assign \fus_cu_wr__go_i$94 [2] \wr_pick_rise$938 + assign \fus_cu_wr__go_i$94 [3] \wr_pick_rise$939 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$928 + connect \B \wrpick_INT_o_en_o + connect \Y $941 + end + process $group_441 + assign \wp$940 1'0 + assign \wp$940 $941 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 5 \addr_en$943 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 5 $944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $945 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \rego + connect \S \wp$940 + connect \Y $944 + end + process $group_442 + assign \addr_en$943 5'00000 + assign \addr_en$943 $944 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_mul0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$95 + connect \B \fus_cu_busy_o$22 + connect \Y $946 + end + process $group_443 + assign \wrflag_mul0_o_0 1'0 + assign \wrflag_mul0_o_0 $946 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $949 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [6] + connect \B \wrpick_INT_o_en_o + connect \Y $949 + end + process $group_444 + assign \wr_pick$948 1'0 + assign \wr_pick$948 $949 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$951 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$951$next + process $group_445 + assign \wr_pick_dly$951$next \wr_pick_dly$951 + assign \wr_pick_dly$951$next \wr_pick$948 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$951$next 1'0 + end + sync init + update \wr_pick_dly$951 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$951 \wr_pick_dly$951$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$952 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $953 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$951 + connect \Y $953 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $955 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$948 + connect \B $953 + connect \Y $955 + end + process $group_446 + assign \wr_pick_rise$952 1'0 + assign \wr_pick_rise$952 $955 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$957 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$958 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$959 + process $group_447 + assign \fus_cu_wr__go_i$97 4'0000 + assign \fus_cu_wr__go_i$97 [0] \wr_pick_rise$952 + assign \fus_cu_wr__go_i$97 [1] \wr_pick_rise$957 + assign \fus_cu_wr__go_i$97 [2] \wr_pick_rise$958 + assign \fus_cu_wr__go_i$97 [3] \wr_pick_rise$959 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$960 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $961 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$948 + connect \B \wrpick_INT_o_en_o + connect \Y $961 + end + process $group_448 + assign \wp$960 1'0 + assign \wp$960 $961 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 5 \addr_en$963 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 5 $964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $965 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \rego + connect \S \wp$960 + connect \Y $964 + end + process $group_449 + assign \addr_en$963 5'00000 + assign \addr_en$963 $964 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_shiftrot0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_o_ok$98 + connect \B \fus_cu_busy_o$25 + connect \Y $966 + end + process $group_450 + assign \wrflag_shiftrot0_o_0 1'0 + assign \wrflag_shiftrot0_o_0 $966 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$968 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $969 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [7] + connect \B \wrpick_INT_o_en_o + connect \Y $969 + end + process $group_451 + assign \wr_pick$968 1'0 + assign \wr_pick$968 $969 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$971 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$971$next + process $group_452 + assign \wr_pick_dly$971$next \wr_pick_dly$971 + assign \wr_pick_dly$971$next \wr_pick$968 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$971$next 1'0 + end + sync init + update \wr_pick_dly$971 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$971 \wr_pick_dly$971$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$972 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $973 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$971 + connect \Y $973 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $975 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$968 + connect \B $973 + connect \Y $975 + end + process $group_453 + assign \wr_pick_rise$972 1'0 + assign \wr_pick_rise$972 $975 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$977 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$978 + process $group_454 + assign \fus_cu_wr__go_i$100 3'000 + assign \fus_cu_wr__go_i$100 [0] \wr_pick_rise$972 + assign \fus_cu_wr__go_i$100 [1] \wr_pick_rise$977 + assign \fus_cu_wr__go_i$100 [2] \wr_pick_rise$978 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $980 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$968 + connect \B \wrpick_INT_o_en_o + connect \Y $980 + end + process $group_455 + assign \wp$979 1'0 + assign \wp$979 $980 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 5 \addr_en$982 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 5 $983 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $984 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \rego + connect \S \wp$979 + connect \Y $983 + end + process $group_456 + assign \addr_en$982 5'00000 + assign \addr_en$982 $983 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_ldst0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $985 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \fus_cu_busy_o$28 + connect \Y $985 + end + process $group_457 + assign \wrflag_ldst0_o_0 1'0 + assign \wrflag_ldst0_o_0 $985 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [8] + connect \B \wrpick_INT_o_en_o + connect \Y $988 + end + process $group_458 + assign \wr_pick$987 1'0 + assign \wr_pick$987 $988 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$990 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$990$next + process $group_459 + assign \wr_pick_dly$990$next \wr_pick_dly$990 + assign \wr_pick_dly$990$next \wr_pick$987 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$990$next 1'0 + end + sync init + update \wr_pick_dly$990 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$990 \wr_pick_dly$990$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$991 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $992 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$990 + connect \Y $992 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $994 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$987 + connect \B $992 + connect \Y $994 + end + process $group_460 + assign \wr_pick_rise$991 1'0 + assign \wr_pick_rise$991 $994 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$996 + process $group_461 + assign \fus_cu_wr__go_i$102 2'00 + assign \fus_cu_wr__go_i$102 [0] \wr_pick_rise$991 + assign \fus_cu_wr__go_i$102 [1] \wr_pick_rise$996 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$997 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$987 + connect \B \wrpick_INT_o_en_o + connect \Y $998 + end + process $group_462 + assign \wp$997 1'0 + assign \wp$997 $998 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 5 \addr_en$1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 5 $1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1002 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \rego + connect \S \wp$997 + connect \Y $1001 + end + process $group_463 + assign \addr_en$1000 5'00000 + assign \addr_en$1000 $1001 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_ldst0_o_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1003 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ea_ok + connect \B \fus_cu_busy_o$28 + connect \Y $1003 + end + process $group_464 + assign \wrflag_ldst0_o_1 1'0 + assign \wrflag_ldst0_o_1 $1003 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [9] + connect \B \wrpick_INT_o_en_o + connect \Y $1006 + end + process $group_465 + assign \wr_pick$1005 1'0 + assign \wr_pick$1005 $1006 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1008 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1008$next + process $group_466 + assign \wr_pick_dly$1008$next \wr_pick_dly$1008 + assign \wr_pick_dly$1008$next \wr_pick$1005 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1008$next 1'0 + end + sync init + update \wr_pick_dly$1008 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1008 \wr_pick_dly$1008$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1009 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1008 + connect \Y $1009 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1011 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1005 + connect \B $1009 + connect \Y $1011 + end + process $group_467 + assign \wr_pick_rise$996 1'0 + assign \wr_pick_rise$996 $1011 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1013 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1005 + connect \B \wrpick_INT_o_en_o + connect \Y $1014 + end + process $group_468 + assign \wp$1013 1'0 + assign \wp$1013 $1014 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 5 \addr_en$1016 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 5 $1017 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1018 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \ea + connect \S \wp$1013 + connect \Y $1017 + end + process $group_469 + assign \addr_en$1016 5'00000 + assign \addr_en$1016 $1017 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 65 $1019 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 $1020 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest1_o + connect \B \fus_dest1_o$103 + connect \Y $1020 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 $1022 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest1_o$105 + connect \B \fus_dest1_o$106 + connect \Y $1022 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 $1024 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest1_o$104 + connect \B $1022 + connect \Y $1024 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 $1026 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $1020 + connect \B $1024 + connect \Y $1026 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 $1028 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest1_o$107 + connect \B \fus_dest1_o$108 + connect \Y $1028 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 65 $1030 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A { \o_ok \fus_o } + connect \B { \ea_ok \fus_ea } + connect \Y $1030 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 65 $1032 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A \fus_dest1_o$109 + connect \B $1030 + connect \Y $1032 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 65 $1034 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $1028 + connect \B $1032 + connect \Y $1034 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 65 $1036 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $1026 + connect \B $1034 + connect \Y $1036 + end + connect $1019 $1036 + process $group_470 + assign \int_dest1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \int_dest1__data_i $1019 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $1038 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en + connect \B \addr_en$861 + connect \Y $1038 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $1040 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en$901 + connect \B \addr_en$923 + connect \Y $1040 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $1042 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en$882 + connect \B $1040 + connect \Y $1042 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $1044 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $1038 + connect \B $1042 + connect \Y $1044 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $1046 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en$943 + connect \B \addr_en$963 + connect \Y $1046 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 5 $1048 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en$1000 + connect \B \addr_en$1016 + connect \Y $1048 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $1050 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \addr_en$982 + connect \B $1048 + connect \Y $1050 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $1052 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $1046 + connect \B $1050 + connect \Y $1052 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 5 $1054 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $1044 + connect \B $1052 + connect \Y $1054 + end + process $group_471 + assign \int_dest1__addr 5'00000 + assign \int_dest1__addr $1054 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1056 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp + connect \B \wp$858 + connect \Y $1056 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1058 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$898 + connect \B \wp$920 + connect \Y $1058 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $1060 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$879 + connect \B $1058 + connect \Y $1060 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $1062 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1056 + connect \B $1060 + connect \Y $1062 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1064 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$940 + connect \B \wp$960 + connect \Y $1064 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1066 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$997 + connect \B \wp$1013 + connect \Y $1066 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $1068 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$979 + connect \B $1066 + connect \Y $1068 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $1070 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1064 + connect \B $1068 + connect \Y $1070 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $1072 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1062 + connect \B $1070 + connect \Y $1072 + end + process $group_472 + assign \int_dest1__wen 1'0 + assign \int_dest1__wen $1072 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_cr0_full_cr_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1074 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_full_cr_ok + connect \B \fus_cu_busy_o$4 + connect \Y $1074 + end + process $group_473 + assign \wrflag_cr0_full_cr_1 1'0 + assign \wrflag_cr0_full_cr_1 $1074 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$81 [1] + connect \B \fu_enable [1] + connect \Y $1076 + end + process $group_474 + assign \wrpick_CR_full_cr_i 1'0 + assign \wrpick_CR_full_cr_i $1076 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1079 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_full_cr_o + connect \B \wrpick_CR_full_cr_en_o + connect \Y $1079 + end + process $group_475 + assign \wr_pick$1078 1'0 + assign \wr_pick$1078 $1079 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1081 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1081$next + process $group_476 + assign \wr_pick_dly$1081$next \wr_pick_dly$1081 + assign \wr_pick_dly$1081$next \wr_pick$1078 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1081$next 1'0 + end + sync init + update \wr_pick_dly$1081 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1081 \wr_pick_dly$1081$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1082 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1081 + connect \Y $1082 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1084 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1078 + connect \B $1082 + connect \Y $1084 + end + process $group_477 + assign \wr_pick_rise$856 1'0 + assign \wr_pick_rise$856 $1084 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1087 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1078 + connect \B \wrpick_CR_full_cr_en_o + connect \Y $1087 + end + process $group_478 + assign \wp$1086 1'0 + assign \wp$1086 $1087 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 8 \addr_en$1089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 8 $1090 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1091 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B 8'11111111 + connect \S \wp$1086 + connect \Y $1090 + end + process $group_479 + assign \addr_en$1089 8'00000000 + assign \addr_en$1089 $1090 + sync init + end + process $group_480 + assign \cr_full_wr__data_i 32'00000000000000000000000000000000 + assign \cr_full_wr__data_i \fus_dest2_o + sync init + end + process $group_481 + assign \cr_full_wr__wen 8'00000000 + assign \cr_full_wr__wen \addr_en$1089 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_alu0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1092 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok + connect \B \fus_cu_busy_o + connect \Y $1092 + end + process $group_482 + assign \wrflag_alu0_cr_a_1 1'0 + assign \wrflag_alu0_cr_a_1 $1092 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1094 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [1] + connect \B \fu_enable [0] + connect \Y $1094 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$81 [2] + connect \B \fu_enable [1] + connect \Y $1096 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1098 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$87 [1] + connect \B \fu_enable [4] + connect \Y $1098 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$93 [1] + connect \B \fu_enable [6] + connect \Y $1100 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$96 [1] + connect \B \fu_enable [7] + connect \Y $1102 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$99 [1] + connect \B \fu_enable [8] + connect \Y $1104 + end + process $group_483 + assign \wrpick_CR_cr_a_i 6'000000 + assign \wrpick_CR_cr_a_i [0] $1094 + assign \wrpick_CR_cr_a_i [1] $1096 + assign \wrpick_CR_cr_a_i [2] $1098 + assign \wrpick_CR_cr_a_i [3] $1100 + assign \wrpick_CR_cr_a_i [4] $1102 + assign \wrpick_CR_cr_a_i [5] $1104 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [0] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1107 + end + process $group_484 + assign \wr_pick$1106 1'0 + assign \wr_pick$1106 $1107 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1109$next + process $group_485 + assign \wr_pick_dly$1109$next \wr_pick_dly$1109 + assign \wr_pick_dly$1109$next \wr_pick$1106 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1109$next 1'0 + end + sync init + update \wr_pick_dly$1109 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1109 \wr_pick_dly$1109$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1110 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1109 + connect \Y $1110 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1112 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1106 + connect \B $1110 + connect \Y $1112 + end + process $group_486 + assign \wr_pick_rise$837 1'0 + assign \wr_pick_rise$837 $1112 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1106 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1115 + end + process $group_487 + assign \wp$1114 1'0 + assign \wp$1114 $1115 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 16 \addr_en$1117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 4 $1118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sub $1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \cr_out + connect \Y $1118 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 16 $1120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sshl $1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1118 + connect \Y $1120 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 16 $1122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1123 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1120 + connect \S \wp$1114 + connect \Y $1122 + end + process $group_488 + assign \addr_en$1117 16'0000000000000000 + assign \addr_en$1117 $1122 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_cr0_cr_a_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$110 + connect \B \fus_cu_busy_o$4 + connect \Y $1124 + end + process $group_489 + assign \wrflag_cr0_cr_a_2 1'0 + assign \wrflag_cr0_cr_a_2 $1124 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [1] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1127 + end + process $group_490 + assign \wr_pick$1126 1'0 + assign \wr_pick$1126 $1127 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1129$next + process $group_491 + assign \wr_pick_dly$1129$next \wr_pick_dly$1129 + assign \wr_pick_dly$1129$next \wr_pick$1126 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1129$next 1'0 + end + sync init + update \wr_pick_dly$1129 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1129 \wr_pick_dly$1129$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1129 + connect \Y $1130 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1132 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1126 + connect \B $1130 + connect \Y $1132 + end + process $group_492 + assign \wr_pick_rise$857 1'0 + assign \wr_pick_rise$857 $1132 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1126 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1135 + end + process $group_493 + assign \wp$1134 1'0 + assign \wp$1134 $1135 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 16 \addr_en$1137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 4 $1138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sub $1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \cr_out + connect \Y $1138 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 16 $1140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sshl $1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1138 + connect \Y $1140 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 16 $1142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1143 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1140 + connect \S \wp$1134 + connect \Y $1142 + end + process $group_494 + assign \addr_en$1137 16'0000000000000000 + assign \addr_en$1137 $1142 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_logical0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$111 + connect \B \fus_cu_busy_o$13 + connect \Y $1144 + end + process $group_495 + assign \wrflag_logical0_cr_a_1 1'0 + assign \wrflag_logical0_cr_a_1 $1144 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [2] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1147 + end + process $group_496 + assign \wr_pick$1146 1'0 + assign \wr_pick$1146 $1147 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1149 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1149$next + process $group_497 + assign \wr_pick_dly$1149$next \wr_pick_dly$1149 + assign \wr_pick_dly$1149$next \wr_pick$1146 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1149$next 1'0 + end + sync init + update \wr_pick_dly$1149 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1149 \wr_pick_dly$1149$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1150 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1149 + connect \Y $1150 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1152 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1146 + connect \B $1150 + connect \Y $1152 + end + process $group_498 + assign \wr_pick_rise$896 1'0 + assign \wr_pick_rise$896 $1152 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1146 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1155 + end + process $group_499 + assign \wp$1154 1'0 + assign \wp$1154 $1155 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 16 \addr_en$1157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 4 $1158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sub $1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \cr_out + connect \Y $1158 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 16 $1160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sshl $1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1158 + connect \Y $1160 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 16 $1162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1163 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1160 + connect \S \wp$1154 + connect \Y $1162 + end + process $group_500 + assign \addr_en$1157 16'0000000000000000 + assign \addr_en$1157 $1162 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_div0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$112 + connect \B \fus_cu_busy_o$19 + connect \Y $1164 + end + process $group_501 + assign \wrflag_div0_cr_a_1 1'0 + assign \wrflag_div0_cr_a_1 $1164 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [3] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1167 + end + process $group_502 + assign \wr_pick$1166 1'0 + assign \wr_pick$1166 $1167 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1169 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1169$next + process $group_503 + assign \wr_pick_dly$1169$next \wr_pick_dly$1169 + assign \wr_pick_dly$1169$next \wr_pick$1166 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1169$next 1'0 + end + sync init + update \wr_pick_dly$1169 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1169 \wr_pick_dly$1169$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1170 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1169 + connect \Y $1170 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1172 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1166 + connect \B $1170 + connect \Y $1172 + end + process $group_504 + assign \wr_pick_rise$937 1'0 + assign \wr_pick_rise$937 $1172 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1166 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1175 + end + process $group_505 + assign \wp$1174 1'0 + assign \wp$1174 $1175 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 16 \addr_en$1177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 4 $1178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sub $1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \cr_out + connect \Y $1178 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 16 $1180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sshl $1181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1178 + connect \Y $1180 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 16 $1182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1183 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1180 + connect \S \wp$1174 + connect \Y $1182 + end + process $group_506 + assign \addr_en$1177 16'0000000000000000 + assign \addr_en$1177 $1182 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_mul0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$113 + connect \B \fus_cu_busy_o$22 + connect \Y $1184 + end + process $group_507 + assign \wrflag_mul0_cr_a_1 1'0 + assign \wrflag_mul0_cr_a_1 $1184 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [4] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1187 + end + process $group_508 + assign \wr_pick$1186 1'0 + assign \wr_pick$1186 $1187 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1189 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1189$next + process $group_509 + assign \wr_pick_dly$1189$next \wr_pick_dly$1189 + assign \wr_pick_dly$1189$next \wr_pick$1186 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1189$next 1'0 + end + sync init + update \wr_pick_dly$1189 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1189 \wr_pick_dly$1189$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1190 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1189 + connect \Y $1190 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1192 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1186 + connect \B $1190 + connect \Y $1192 + end + process $group_510 + assign \wr_pick_rise$957 1'0 + assign \wr_pick_rise$957 $1192 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1186 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1195 + end + process $group_511 + assign \wp$1194 1'0 + assign \wp$1194 $1195 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 16 \addr_en$1197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 4 $1198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sub $1199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \cr_out + connect \Y $1198 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 16 $1200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sshl $1201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1198 + connect \Y $1200 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 16 $1202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1203 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1200 + connect \S \wp$1194 + connect \Y $1202 + end + process $group_512 + assign \addr_en$1197 16'0000000000000000 + assign \addr_en$1197 $1202 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_shiftrot0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cr_a_ok$114 + connect \B \fus_cu_busy_o$25 + connect \Y $1204 + end + process $group_513 + assign \wrflag_shiftrot0_cr_a_1 1'0 + assign \wrflag_shiftrot0_cr_a_1 $1204 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [5] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1207 + end + process $group_514 + assign \wr_pick$1206 1'0 + assign \wr_pick$1206 $1207 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1209 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1209$next + process $group_515 + assign \wr_pick_dly$1209$next \wr_pick_dly$1209 + assign \wr_pick_dly$1209$next \wr_pick$1206 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1209$next 1'0 + end + sync init + update \wr_pick_dly$1209 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1209 \wr_pick_dly$1209$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1210 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1209 + connect \Y $1210 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1212 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1206 + connect \B $1210 + connect \Y $1212 + end + process $group_516 + assign \wr_pick_rise$977 1'0 + assign \wr_pick_rise$977 $1212 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1206 + connect \B \wrpick_CR_cr_a_en_o + connect \Y $1215 + end + process $group_517 + assign \wp$1214 1'0 + assign \wp$1214 $1215 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 16 \addr_en$1217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 4 $1218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sub $1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A 3'111 + connect \B \cr_out + connect \Y $1218 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + wire width 16 $1220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:136" + cell $sshl $1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A 1'1 + connect \B $1218 + connect \Y $1220 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 16 $1222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1223 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B $1220 + connect \S \wp$1214 + connect \Y $1222 + end + process $group_518 + assign \addr_en$1217 16'0000000000000000 + assign \addr_en$1217 $1222 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $1224 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \fus_dest3_o + connect \B \fus_dest2_o$116 + connect \Y $1224 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $1226 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \fus_dest2_o$115 + connect \B $1224 + connect \Y $1226 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 4 $1228 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \fus_dest2_o$118 + connect \B \fus_dest2_o$119 + connect \Y $1228 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $1230 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \fus_dest2_o$117 + connect \B $1228 + connect \Y $1230 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 4 $1232 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $1226 + connect \B $1230 + connect \Y $1232 + end + process $group_519 + assign \cr_data_i 4'0000 + assign \cr_data_i $1232 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 $1234 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 $1235 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \addr_en$1137 + connect \B \addr_en$1157 + connect \Y $1235 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 $1237 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \addr_en$1117 + connect \B $1235 + connect \Y $1237 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 16 $1239 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \addr_en$1197 + connect \B \addr_en$1217 + connect \Y $1239 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 $1241 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A \addr_en$1177 + connect \B $1239 + connect \Y $1241 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 16 $1243 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 16 + connect \A $1237 + connect \B $1241 + connect \Y $1243 + end + connect $1234 $1243 + process $group_520 + assign \cr_wen 8'00000000 + assign \cr_wen $1234 [7:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_alu0_xer_ca_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ca_ok + connect \B \fus_cu_busy_o + connect \Y $1245 + end + process $group_521 + assign \wrflag_alu0_xer_ca_2 1'0 + assign \wrflag_alu0_xer_ca_2 $1245 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [2] + connect \B \fu_enable [0] + connect \Y $1247 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$87 [2] + connect \B \fu_enable [4] + connect \Y $1249 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$90 [5] + connect \B \fu_enable [5] + connect \Y $1251 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$99 [2] + connect \B \fu_enable [8] + connect \Y $1253 + end + process $group_522 + assign \wrpick_XER_xer_ca_i 4'0000 + assign \wrpick_XER_xer_ca_i [0] $1247 + assign \wrpick_XER_xer_ca_i [1] $1249 + assign \wrpick_XER_xer_ca_i [2] $1251 + assign \wrpick_XER_xer_ca_i [3] $1253 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [0] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1256 + end + process $group_523 + assign \wr_pick$1255 1'0 + assign \wr_pick$1255 $1256 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1258 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1258$next + process $group_524 + assign \wr_pick_dly$1258$next \wr_pick_dly$1258 + assign \wr_pick_dly$1258$next \wr_pick$1255 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1258$next 1'0 + end + sync init + update \wr_pick_dly$1258 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1258 \wr_pick_dly$1258$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1259 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1258 + connect \Y $1259 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1261 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1255 + connect \B $1259 + connect \Y $1261 + end + process $group_525 + assign \wr_pick_rise$838 1'0 + assign \wr_pick_rise$838 $1261 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1255 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1264 + end + process $group_526 + assign \wp$1263 1'0 + assign \wp$1263 $1264 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 2 \addr_en$1266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 2 $1267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1268 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1263 + connect \Y $1267 + end + process $group_527 + assign \addr_en$1266 2'00 + assign \addr_en$1266 $1267 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_logical0_xer_ca_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ca_ok$120 + connect \B \fus_cu_busy_o$13 + connect \Y $1269 + end + process $group_528 + assign \wrflag_logical0_xer_ca_2 1'0 + assign \wrflag_logical0_xer_ca_2 $1269 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [1] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1272 + end + process $group_529 + assign \wr_pick$1271 1'0 + assign \wr_pick$1271 $1272 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1274 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1274$next + process $group_530 + assign \wr_pick_dly$1274$next \wr_pick_dly$1274 + assign \wr_pick_dly$1274$next \wr_pick$1271 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1274$next 1'0 + end + sync init + update \wr_pick_dly$1274 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1274 \wr_pick_dly$1274$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1275 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1274 + connect \Y $1275 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1277 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1271 + connect \B $1275 + connect \Y $1277 + end + process $group_531 + assign \wr_pick_rise$897 1'0 + assign \wr_pick_rise$897 $1277 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1271 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1280 + end + process $group_532 + assign \wp$1279 1'0 + assign \wp$1279 $1280 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 2 \addr_en$1282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 2 $1283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1284 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1279 + connect \Y $1283 + end + process $group_533 + assign \addr_en$1282 2'00 + assign \addr_en$1282 $1283 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_spr0_xer_ca_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ca_ok$121 + connect \B \fus_cu_busy_o$16 + connect \Y $1285 + end + process $group_534 + assign \wrflag_spr0_xer_ca_5 1'0 + assign \wrflag_spr0_xer_ca_5 $1285 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [2] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1288 + end + process $group_535 + assign \wr_pick$1287 1'0 + assign \wr_pick$1287 $1288 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1290 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1290$next + process $group_536 + assign \wr_pick_dly$1290$next \wr_pick_dly$1290 + assign \wr_pick_dly$1290$next \wr_pick$1287 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1290$next 1'0 + end + sync init + update \wr_pick_dly$1290 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1290 \wr_pick_dly$1290$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1291 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1290 + connect \Y $1291 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1293 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1287 + connect \B $1291 + connect \Y $1293 + end + process $group_537 + assign \wr_pick_rise$915 1'0 + assign \wr_pick_rise$915 $1293 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1287 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1296 + end + process $group_538 + assign \wp$1295 1'0 + assign \wp$1295 $1296 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 2 \addr_en$1298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 2 $1299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1300 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1295 + connect \Y $1299 + end + process $group_539 + assign \addr_en$1298 2'00 + assign \addr_en$1298 $1299 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_shiftrot0_xer_ca_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1301 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ca_ok$122 + connect \B \fus_cu_busy_o$25 + connect \Y $1301 + end + process $group_540 + assign \wrflag_shiftrot0_xer_ca_2 1'0 + assign \wrflag_shiftrot0_xer_ca_2 $1301 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [3] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1304 + end + process $group_541 + assign \wr_pick$1303 1'0 + assign \wr_pick$1303 $1304 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1306 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1306$next + process $group_542 + assign \wr_pick_dly$1306$next \wr_pick_dly$1306 + assign \wr_pick_dly$1306$next \wr_pick$1303 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1306$next 1'0 + end + sync init + update \wr_pick_dly$1306 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1306 \wr_pick_dly$1306$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1307 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1306 + connect \Y $1307 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1309 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1303 + connect \B $1307 + connect \Y $1309 + end + process $group_543 + assign \wr_pick_rise$978 1'0 + assign \wr_pick_rise$978 $1309 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1303 + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $1312 + end + process $group_544 + assign \wp$1311 1'0 + assign \wp$1311 $1312 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 2 \addr_en$1314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 2 $1315 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1316 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1311 + connect \Y $1315 + end + process $group_545 + assign \addr_en$1314 2'00 + assign \addr_en$1314 $1315 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $1317 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_dest3_o$123 + connect \B \fus_dest3_o$124 + connect \Y $1317 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $1319 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_dest6_o + connect \B \fus_dest3_o$125 + connect \Y $1319 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 $1321 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $1317 + connect \B $1319 + connect \Y $1321 + end + process $group_546 + assign \xer_data_i 2'00 + assign \xer_data_i $1321 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $1323 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $1324 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \addr_en$1266 + connect \B \addr_en$1282 + connect \Y $1324 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $1326 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \addr_en$1298 + connect \B \addr_en$1314 + connect \Y $1326 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 $1328 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $1324 + connect \B $1326 + connect \Y $1328 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A $1328 + connect \Y $1323 + end + process $group_547 + assign \xer_wen 3'000 + assign \xer_wen $1323 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_alu0_xer_ov_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok + connect \B \fus_cu_busy_o + connect \Y $1331 + end + process $group_548 + assign \wrflag_alu0_xer_ov_3 1'0 + assign \wrflag_alu0_xer_ov_3 $1331 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [3] + connect \B \fu_enable [0] + connect \Y $1333 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$90 [4] + connect \B \fu_enable [5] + connect \Y $1335 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$93 [2] + connect \B \fu_enable [6] + connect \Y $1337 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1339 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$96 [2] + connect \B \fu_enable [7] + connect \Y $1339 + end + process $group_549 + assign \wrpick_XER_xer_ov_i 4'0000 + assign \wrpick_XER_xer_ov_i [0] $1333 + assign \wrpick_XER_xer_ov_i [1] $1335 + assign \wrpick_XER_xer_ov_i [2] $1337 + assign \wrpick_XER_xer_ov_i [3] $1339 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [0] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1342 + end + process $group_550 + assign \wr_pick$1341 1'0 + assign \wr_pick$1341 $1342 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1344 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1344$next + process $group_551 + assign \wr_pick_dly$1344$next \wr_pick_dly$1344 + assign \wr_pick_dly$1344$next \wr_pick$1341 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1344$next 1'0 + end + sync init + update \wr_pick_dly$1344 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1344 \wr_pick_dly$1344$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1345 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1344 + connect \Y $1345 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1347 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1341 + connect \B $1345 + connect \Y $1347 + end + process $group_552 + assign \wr_pick_rise$839 1'0 + assign \wr_pick_rise$839 $1347 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1341 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1350 + end + process $group_553 + assign \wp$1349 1'0 + assign \wp$1349 $1350 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 3 \addr_en$1352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 3 $1353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1354 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1349 + connect \Y $1353 + end + process $group_554 + assign \addr_en$1352 3'000 + assign \addr_en$1352 $1353 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_spr0_xer_ov_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok$126 + connect \B \fus_cu_busy_o$16 + connect \Y $1355 + end + process $group_555 + assign \wrflag_spr0_xer_ov_4 1'0 + assign \wrflag_spr0_xer_ov_4 $1355 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1357 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [1] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1358 + end + process $group_556 + assign \wr_pick$1357 1'0 + assign \wr_pick$1357 $1358 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1360 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1360$next + process $group_557 + assign \wr_pick_dly$1360$next \wr_pick_dly$1360 + assign \wr_pick_dly$1360$next \wr_pick$1357 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1360$next 1'0 + end + sync init + update \wr_pick_dly$1360 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1360 \wr_pick_dly$1360$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1361 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1360 + connect \Y $1361 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1363 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1357 + connect \B $1361 + connect \Y $1363 + end + process $group_558 + assign \wr_pick_rise$916 1'0 + assign \wr_pick_rise$916 $1363 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1357 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1366 + end + process $group_559 + assign \wp$1365 1'0 + assign \wp$1365 $1366 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 3 \addr_en$1368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 3 $1369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1370 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1365 + connect \Y $1369 + end + process $group_560 + assign \addr_en$1368 3'000 + assign \addr_en$1368 $1369 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_div0_xer_ov_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok$127 + connect \B \fus_cu_busy_o$19 + connect \Y $1371 + end + process $group_561 + assign \wrflag_div0_xer_ov_2 1'0 + assign \wrflag_div0_xer_ov_2 $1371 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1374 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [2] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1374 + end + process $group_562 + assign \wr_pick$1373 1'0 + assign \wr_pick$1373 $1374 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1376 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1376$next + process $group_563 + assign \wr_pick_dly$1376$next \wr_pick_dly$1376 + assign \wr_pick_dly$1376$next \wr_pick$1373 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1376$next 1'0 + end + sync init + update \wr_pick_dly$1376 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1376 \wr_pick_dly$1376$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1377 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1376 + connect \Y $1377 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1379 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1373 + connect \B $1377 + connect \Y $1379 + end + process $group_564 + assign \wr_pick_rise$938 1'0 + assign \wr_pick_rise$938 $1379 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1373 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1382 + end + process $group_565 + assign \wp$1381 1'0 + assign \wp$1381 $1382 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 3 \addr_en$1384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 3 $1385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1386 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1381 + connect \Y $1385 + end + process $group_566 + assign \addr_en$1384 3'000 + assign \addr_en$1384 $1385 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_mul0_xer_ov_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_ov_ok$128 + connect \B \fus_cu_busy_o$22 + connect \Y $1387 + end + process $group_567 + assign \wrflag_mul0_xer_ov_2 1'0 + assign \wrflag_mul0_xer_ov_2 $1387 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [3] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1390 + end + process $group_568 + assign \wr_pick$1389 1'0 + assign \wr_pick$1389 $1390 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1392 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1392$next + process $group_569 + assign \wr_pick_dly$1392$next \wr_pick_dly$1392 + assign \wr_pick_dly$1392$next \wr_pick$1389 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1392$next 1'0 + end + sync init + update \wr_pick_dly$1392 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1392 \wr_pick_dly$1392$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1393 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1392 + connect \Y $1393 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1395 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1389 + connect \B $1393 + connect \Y $1395 + end + process $group_570 + assign \wr_pick_rise$958 1'0 + assign \wr_pick_rise$958 $1395 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1389 + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $1398 + end + process $group_571 + assign \wp$1397 1'0 + assign \wp$1397 $1398 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 3 \addr_en$1400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 3 $1401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1402 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1397 + connect \Y $1401 + end + process $group_572 + assign \addr_en$1400 3'000 + assign \addr_en$1400 $1401 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $1403 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_dest4_o + connect \B \fus_dest5_o + connect \Y $1403 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $1405 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_dest3_o$129 + connect \B \fus_dest3_o$130 + connect \Y $1405 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 $1407 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $1403 + connect \B $1405 + connect \Y $1407 + end + process $group_573 + assign \xer_data_i$153 2'00 + assign \xer_data_i$153 $1407 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 $1409 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en$1352 + connect \B \addr_en$1368 + connect \Y $1409 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 $1411 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en$1384 + connect \B \addr_en$1400 + connect \Y $1411 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $1413 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $1409 + connect \B $1411 + connect \Y $1413 + end + process $group_574 + assign \xer_wen$154 3'000 + assign \xer_wen$154 $1413 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_alu0_xer_so_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_so_ok + connect \B \fus_cu_busy_o + connect \Y $1415 + end + process $group_575 + assign \wrflag_alu0_xer_so_4 1'0 + assign \wrflag_alu0_xer_so_4 $1415 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o [4] + connect \B \fu_enable [0] + connect \Y $1417 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$90 [3] + connect \B \fu_enable [5] + connect \Y $1419 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$93 [3] + connect \B \fu_enable [6] + connect \Y $1421 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$96 [3] + connect \B \fu_enable [7] + connect \Y $1423 + end + process $group_576 + assign \wrpick_XER_xer_so_i 4'0000 + assign \wrpick_XER_xer_so_i [0] $1417 + assign \wrpick_XER_xer_so_i [1] $1419 + assign \wrpick_XER_xer_so_i [2] $1421 + assign \wrpick_XER_xer_so_i [3] $1423 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [0] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1426 + end + process $group_577 + assign \wr_pick$1425 1'0 + assign \wr_pick$1425 $1426 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1428 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1428$next + process $group_578 + assign \wr_pick_dly$1428$next \wr_pick_dly$1428 + assign \wr_pick_dly$1428$next \wr_pick$1425 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1428$next 1'0 + end + sync init + update \wr_pick_dly$1428 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1428 \wr_pick_dly$1428$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1429 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1428 + connect \Y $1429 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1431 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1425 + connect \B $1429 + connect \Y $1431 + end + process $group_579 + assign \wr_pick_rise$840 1'0 + assign \wr_pick_rise$840 $1431 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1425 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1434 + end + process $group_580 + assign \wp$1433 1'0 + assign \wp$1433 $1434 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 1 \addr_en$1436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 1 $1437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1438 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1433 + connect \Y $1437 + end + process $group_581 + assign \addr_en$1436 1'0 + assign \addr_en$1436 $1437 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_spr0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1439 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_so_ok$131 + connect \B \fus_cu_busy_o$16 + connect \Y $1439 + end + process $group_582 + assign \wrflag_spr0_xer_so_3 1'0 + assign \wrflag_spr0_xer_so_3 $1439 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1441 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [1] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1442 + end + process $group_583 + assign \wr_pick$1441 1'0 + assign \wr_pick$1441 $1442 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1444 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1444$next + process $group_584 + assign \wr_pick_dly$1444$next \wr_pick_dly$1444 + assign \wr_pick_dly$1444$next \wr_pick$1441 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1444$next 1'0 + end + sync init + update \wr_pick_dly$1444 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1444 \wr_pick_dly$1444$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1445 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1444 + connect \Y $1445 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1447 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1441 + connect \B $1445 + connect \Y $1447 + end + process $group_585 + assign \wr_pick_rise$917 1'0 + assign \wr_pick_rise$917 $1447 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1441 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1450 + end + process $group_586 + assign \wp$1449 1'0 + assign \wp$1449 $1450 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 1 \addr_en$1452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 1 $1453 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1454 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1449 + connect \Y $1453 + end + process $group_587 + assign \addr_en$1452 1'0 + assign \addr_en$1452 $1453 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_div0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1455 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_so_ok$132 + connect \B \fus_cu_busy_o$19 + connect \Y $1455 + end + process $group_588 + assign \wrflag_div0_xer_so_3 1'0 + assign \wrflag_div0_xer_so_3 $1455 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [2] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1458 + end + process $group_589 + assign \wr_pick$1457 1'0 + assign \wr_pick$1457 $1458 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1460 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1460$next + process $group_590 + assign \wr_pick_dly$1460$next \wr_pick_dly$1460 + assign \wr_pick_dly$1460$next \wr_pick$1457 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1460$next 1'0 + end + sync init + update \wr_pick_dly$1460 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1460 \wr_pick_dly$1460$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1461 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1460 + connect \Y $1461 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1463 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1457 + connect \B $1461 + connect \Y $1463 + end + process $group_591 + assign \wr_pick_rise$939 1'0 + assign \wr_pick_rise$939 $1463 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1457 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1466 + end + process $group_592 + assign \wp$1465 1'0 + assign \wp$1465 $1466 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 1 \addr_en$1468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 1 $1469 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1470 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1465 + connect \Y $1469 + end + process $group_593 + assign \addr_en$1468 1'0 + assign \addr_en$1468 $1469 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_mul0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1471 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_xer_so_ok$133 + connect \B \fus_cu_busy_o$22 + connect \Y $1471 + end + process $group_594 + assign \wrflag_mul0_xer_so_3 1'0 + assign \wrflag_mul0_xer_so_3 $1471 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1473 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [3] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1474 + end + process $group_595 + assign \wr_pick$1473 1'0 + assign \wr_pick$1473 $1474 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1476 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1476$next + process $group_596 + assign \wr_pick_dly$1476$next \wr_pick_dly$1476 + assign \wr_pick_dly$1476$next \wr_pick$1473 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1476$next 1'0 + end + sync init + update \wr_pick_dly$1476 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1476 \wr_pick_dly$1476$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1477 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1476 + connect \Y $1477 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1479 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1473 + connect \B $1477 + connect \Y $1479 + end + process $group_597 + assign \wr_pick_rise$959 1'0 + assign \wr_pick_rise$959 $1479 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1481 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1482 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1473 + connect \B \wrpick_XER_xer_so_en_o + connect \Y $1482 + end + process $group_598 + assign \wp$1481 1'0 + assign \wp$1481 $1482 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 1 \addr_en$1484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 1 $1485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1486 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1481 + connect \Y $1485 + end + process $group_599 + assign \addr_en$1484 1'0 + assign \addr_en$1484 $1485 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 2 $1487 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1488 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_dest5_o$134 + connect \B \fus_dest4_o$135 + connect \Y $1488 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1490 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_dest4_o$136 + connect \B \fus_dest4_o$137 + connect \Y $1490 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $1492 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1488 + connect \B $1490 + connect \Y $1492 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $1494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A $1492 + connect \Y $1487 + end + process $group_600 + assign \xer_data_i$155 2'00 + assign \xer_data_i$155 $1487 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $1495 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1496 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en$1436 + connect \B \addr_en$1452 + connect \Y $1496 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1498 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en$1468 + connect \B \addr_en$1484 + connect \Y $1498 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $1500 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1496 + connect \B $1498 + connect \Y $1500 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $pos $1502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A $1500 + connect \Y $1495 + end + process $group_601 + assign \xer_wen$156 3'000 + assign \xer_wen$156 $1495 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_branch0_fast1_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_fast1_ok + connect \B \fus_cu_busy_o$7 + connect \Y $1503 + end + process $group_602 + assign \wrflag_branch0_fast1_0 1'0 + assign \wrflag_branch0_fast1_0 $1503 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$138 [0] + connect \B \fu_enable [2] + connect \Y $1505 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$84 [1] + connect \B \fu_enable [3] + connect \Y $1507 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$90 [2] + connect \B \fu_enable [5] + connect \Y $1509 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$138 [1] + connect \B \fu_enable [2] + connect \Y $1511 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$84 [2] + connect \B \fu_enable [3] + connect \Y $1513 + end + process $group_603 + assign \wrpick_FAST_fast1_i 5'00000 + assign \wrpick_FAST_fast1_i [0] $1505 + assign \wrpick_FAST_fast1_i [1] $1507 + assign \wrpick_FAST_fast1_i [2] $1509 + assign \wrpick_FAST_fast1_i [3] $1511 + assign \wrpick_FAST_fast1_i [4] $1513 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [0] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1516 + end + process $group_604 + assign \wr_pick$1515 1'0 + assign \wr_pick$1515 $1516 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1518 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1518$next + process $group_605 + assign \wr_pick_dly$1518$next \wr_pick_dly$1518 + assign \wr_pick_dly$1518$next \wr_pick$1515 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1518$next 1'0 + end + sync init + update \wr_pick_dly$1518 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1518 \wr_pick_dly$1518$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$1519 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1520 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1518 + connect \Y $1520 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1522 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1515 + connect \B $1520 + connect \Y $1522 + end + process $group_606 + assign \wr_pick_rise$1519 1'0 + assign \wr_pick_rise$1519 $1522 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$1524 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire width 1 \wr_pick_rise$1525 + process $group_607 + assign \fus_cu_wr__go_i$139 3'000 + assign \fus_cu_wr__go_i$139 [0] \wr_pick_rise$1519 + assign \fus_cu_wr__go_i$139 [1] \wr_pick_rise$1524 + assign \fus_cu_wr__go_i$139 [2] \wr_pick_rise$1525 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1515 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1527 + end + process $group_608 + assign \wp$1526 1'0 + assign \wp$1526 $1527 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 3 \addr_en$1529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 3 $1530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1531 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \fasto1 + connect \S \wp$1526 + connect \Y $1530 + end + process $group_609 + assign \addr_en$1529 3'000 + assign \addr_en$1529 $1530 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_trap0_fast1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_fast1_ok$140 + connect \B \fus_cu_busy_o$10 + connect \Y $1532 + end + process $group_610 + assign \wrflag_trap0_fast1_1 1'0 + assign \wrflag_trap0_fast1_1 $1532 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [1] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1535 + end + process $group_611 + assign \wr_pick$1534 1'0 + assign \wr_pick$1534 $1535 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1537 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1537$next + process $group_612 + assign \wr_pick_dly$1537$next \wr_pick_dly$1537 + assign \wr_pick_dly$1537$next \wr_pick$1534 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1537$next 1'0 + end + sync init + update \wr_pick_dly$1537 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1537 \wr_pick_dly$1537$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1538 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1537 + connect \Y $1538 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1540 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1534 + connect \B $1538 + connect \Y $1540 + end + process $group_613 + assign \wr_pick_rise$875 1'0 + assign \wr_pick_rise$875 $1540 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1534 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1543 + end + process $group_614 + assign \wp$1542 1'0 + assign \wp$1542 $1543 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 3 \addr_en$1545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 3 $1546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1547 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \fasto1 + connect \S \wp$1542 + connect \Y $1546 + end + process $group_615 + assign \addr_en$1545 3'000 + assign \addr_en$1545 $1546 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_spr0_fast1_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1548 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_fast1_ok$141 + connect \B \fus_cu_busy_o$16 + connect \Y $1548 + end + process $group_616 + assign \wrflag_spr0_fast1_2 1'0 + assign \wrflag_spr0_fast1_2 $1548 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [2] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1551 + end + process $group_617 + assign \wr_pick$1550 1'0 + assign \wr_pick$1550 $1551 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1553 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1553$next + process $group_618 + assign \wr_pick_dly$1553$next \wr_pick_dly$1553 + assign \wr_pick_dly$1553$next \wr_pick$1550 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1553$next 1'0 + end + sync init + update \wr_pick_dly$1553 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1553 \wr_pick_dly$1553$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1554 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1553 + connect \Y $1554 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1556 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1550 + connect \B $1554 + connect \Y $1556 + end + process $group_619 + assign \wr_pick_rise$918 1'0 + assign \wr_pick_rise$918 $1556 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1550 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1559 + end + process $group_620 + assign \wp$1558 1'0 + assign \wp$1558 $1559 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 3 \addr_en$1561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 3 $1562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1563 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \fasto1 + connect \S \wp$1558 + connect \Y $1562 + end + process $group_621 + assign \addr_en$1561 3'000 + assign \addr_en$1561 $1562 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_branch0_fast1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_fast2_ok + connect \B \fus_cu_busy_o$7 + connect \Y $1564 + end + process $group_622 + assign \wrflag_branch0_fast1_1 1'0 + assign \wrflag_branch0_fast1_1 $1564 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [3] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1567 + end + process $group_623 + assign \wr_pick$1566 1'0 + assign \wr_pick$1566 $1567 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1569 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1569$next + process $group_624 + assign \wr_pick_dly$1569$next \wr_pick_dly$1569 + assign \wr_pick_dly$1569$next \wr_pick$1566 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1569$next 1'0 + end + sync init + update \wr_pick_dly$1569 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1569 \wr_pick_dly$1569$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1570 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1569 + connect \Y $1570 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1572 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1566 + connect \B $1570 + connect \Y $1572 + end + process $group_625 + assign \wr_pick_rise$1524 1'0 + assign \wr_pick_rise$1524 $1572 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1566 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1575 + end + process $group_626 + assign \wp$1574 1'0 + assign \wp$1574 $1575 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 3 \addr_en$1577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 3 $1578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1579 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \fasto2 + connect \S \wp$1574 + connect \Y $1578 + end + process $group_627 + assign \addr_en$1577 3'000 + assign \addr_en$1577 $1578 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_trap0_fast1_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1580 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_fast2_ok$142 + connect \B \fus_cu_busy_o$10 + connect \Y $1580 + end + process $group_628 + assign \wrflag_trap0_fast1_2 1'0 + assign \wrflag_trap0_fast1_2 $1580 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [4] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1583 + end + process $group_629 + assign \wr_pick$1582 1'0 + assign \wr_pick$1582 $1583 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1585 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1585$next + process $group_630 + assign \wr_pick_dly$1585$next \wr_pick_dly$1585 + assign \wr_pick_dly$1585$next \wr_pick$1582 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1585$next 1'0 + end + sync init + update \wr_pick_dly$1585 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1585 \wr_pick_dly$1585$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1586 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1585 + connect \Y $1586 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1588 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1582 + connect \B $1586 + connect \Y $1588 + end + process $group_631 + assign \wr_pick_rise$876 1'0 + assign \wr_pick_rise$876 $1588 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1582 + connect \B \wrpick_FAST_fast1_en_o + connect \Y $1591 + end + process $group_632 + assign \wp$1590 1'0 + assign \wp$1590 $1591 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 3 \addr_en$1593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 3 $1594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1595 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \fasto2 + connect \S \wp$1590 + connect \Y $1594 + end + process $group_633 + assign \addr_en$1593 3'000 + assign \addr_en$1593 $1594 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 $1596 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest1_o$143 + connect \B \fus_dest2_o$144 + connect \Y $1596 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 $1598 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest2_o$146 + connect \B \fus_dest3_o$147 + connect \Y $1598 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 $1600 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest3_o$145 + connect \B $1598 + connect \Y $1600 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 $1602 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $1596 + connect \B $1600 + connect \Y $1602 + end + process $group_634 + assign \fast_dest1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast_dest1__data_i $1602 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 $1604 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en$1529 + connect \B \addr_en$1545 + connect \Y $1604 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 3 $1606 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en$1577 + connect \B \addr_en$1593 + connect \Y $1606 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $1608 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \addr_en$1561 + connect \B $1606 + connect \Y $1608 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 3 $1610 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $1604 + connect \B $1608 + connect \Y $1610 + end + process $group_635 + assign \fast_dest1__addr 3'000 + assign \fast_dest1__addr $1610 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1612 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$1526 + connect \B \wp$1542 + connect \Y $1612 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1614 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$1574 + connect \B \wp$1590 + connect \Y $1614 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $1616 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wp$1558 + connect \B $1614 + connect \Y $1616 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 1 $1618 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1612 + connect \B $1616 + connect \Y $1618 + end + process $group_636 + assign \fast_dest1__wen 1'0 + assign \fast_dest1__wen $1618 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_branch0_nia_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_nia_ok + connect \B \fus_cu_busy_o$7 + connect \Y $1620 + end + process $group_637 + assign \wrflag_branch0_nia_2 1'0 + assign \wrflag_branch0_nia_2 $1620 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1622 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$138 [2] + connect \B \fu_enable [2] + connect \Y $1622 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$84 [3] + connect \B \fu_enable [3] + connect \Y $1624 + end + process $group_638 + assign \wrpick_STATE_nia_i 2'00 + assign \wrpick_STATE_nia_i [0] $1622 + assign \wrpick_STATE_nia_i [1] $1624 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1626 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_STATE_nia_o [0] + connect \B \wrpick_STATE_nia_en_o + connect \Y $1627 + end + process $group_639 + assign \wr_pick$1626 1'0 + assign \wr_pick$1626 $1627 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1629 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1629$next + process $group_640 + assign \wr_pick_dly$1629$next \wr_pick_dly$1629 + assign \wr_pick_dly$1629$next \wr_pick$1626 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1629$next 1'0 + end + sync init + update \wr_pick_dly$1629 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1629 \wr_pick_dly$1629$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1630 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1629 + connect \Y $1630 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1632 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1626 + connect \B $1630 + connect \Y $1632 + end + process $group_641 + assign \wr_pick_rise$1525 1'0 + assign \wr_pick_rise$1525 $1632 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1634 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1626 + connect \B \wrpick_STATE_nia_en_o + connect \Y $1635 + end + process $group_642 + assign \wp$1634 1'0 + assign \wp$1634 $1635 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 1 \addr_en$1637 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 1 $1638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1639 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1634 + connect \Y $1638 + end + process $group_643 + assign \addr_en$1637 1'0 + assign \addr_en$1637 $1638 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_trap0_nia_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_nia_ok$148 + connect \B \fus_cu_busy_o$10 + connect \Y $1640 + end + process $group_644 + assign \wrflag_trap0_nia_3 1'0 + assign \wrflag_trap0_nia_3 $1640 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1643 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_STATE_nia_o [1] + connect \B \wrpick_STATE_nia_en_o + connect \Y $1643 + end + process $group_645 + assign \wr_pick$1642 1'0 + assign \wr_pick$1642 $1643 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1645 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1645$next + process $group_646 + assign \wr_pick_dly$1645$next \wr_pick_dly$1645 + assign \wr_pick_dly$1645$next \wr_pick$1642 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1645$next 1'0 + end + sync init + update \wr_pick_dly$1645 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1645 \wr_pick_dly$1645$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1646 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1645 + connect \Y $1646 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1648 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1642 + connect \B $1646 + connect \Y $1648 + end + process $group_647 + assign \wr_pick_rise$877 1'0 + assign \wr_pick_rise$877 $1648 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1650 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1651 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1642 + connect \B \wrpick_STATE_nia_en_o + connect \Y $1651 + end + process $group_648 + assign \wp$1650 1'0 + assign \wp$1650 $1651 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 1 \addr_en$1653 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 1 $1654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1655 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1650 + connect \Y $1654 + end + process $group_649 + assign \addr_en$1653 1'0 + assign \addr_en$1653 $1654 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 $1656 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_dest3_o$149 + connect \B \fus_dest4_o$150 + connect \Y $1656 + end + process $group_650 + assign \state_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \state_data_i $1656 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 2 $1658 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 1 $1659 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \addr_en$1637 + connect \B \addr_en$1653 + connect \Y $1659 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $pos $1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A $1659 + connect \Y $1658 + end + process $group_651 + assign \state_nia_wen 2'00 + assign \state_nia_wen $1658 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_trap0_msr_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1662 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_msr_ok + connect \B \fus_cu_busy_o$10 + connect \Y $1662 + end + process $group_652 + assign \wrflag_trap0_msr_4 1'0 + assign \wrflag_trap0_msr_4 $1662 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1664 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$84 [4] + connect \B \fu_enable [3] + connect \Y $1664 + end + process $group_653 + assign \wrpick_STATE_msr_i 1'0 + assign \wrpick_STATE_msr_i $1664 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1667 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_STATE_msr_o + connect \B \wrpick_STATE_msr_en_o + connect \Y $1667 + end + process $group_654 + assign \wr_pick$1666 1'0 + assign \wr_pick$1666 $1667 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1669 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1669$next + process $group_655 + assign \wr_pick_dly$1669$next \wr_pick_dly$1669 + assign \wr_pick_dly$1669$next \wr_pick$1666 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1669$next 1'0 + end + sync init + update \wr_pick_dly$1669 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1669 \wr_pick_dly$1669$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1670 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1669 + connect \Y $1670 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1672 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1666 + connect \B $1670 + connect \Y $1672 + end + process $group_656 + assign \wr_pick_rise$878 1'0 + assign \wr_pick_rise$878 $1672 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1674 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1675 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1666 + connect \B \wrpick_STATE_msr_en_o + connect \Y $1675 + end + process $group_657 + assign \wp$1674 1'0 + assign \wp$1674 $1675 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 2 \addr_en$1677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 2 $1678 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1679 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1674 + connect \Y $1678 + end + process $group_658 + assign \addr_en$1677 2'00 + assign \addr_en$1677 $1678 + sync init + end + process $group_659 + assign \state_data_i$157 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \state_data_i$157 \fus_dest5_o$151 + sync init + end + process $group_660 + assign \state_wen 2'00 + assign \state_wen \addr_en$1677 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:351" + wire width 1 \wrflag_spr0_spr1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + wire width 1 $1680 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" + cell $and $1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_spr1_ok + connect \B \fus_cu_busy_o$16 + connect \Y $1680 + end + process $group_661 + assign \wrflag_spr0_spr1_1 1'0 + assign \wrflag_spr0_spr1_1 $1680 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + wire width 1 $1682 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" + cell $and $1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fus_cu_wr__rel_o$90 [1] + connect \B \fu_enable [5] + connect \Y $1682 + end + process $group_662 + assign \wrpick_SPR_spr1_i 1'0 + assign \wrpick_SPR_spr1_i $1682 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:359" + wire width 1 \wr_pick$1684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + wire width 1 $1685 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:360" + cell $and $1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_SPR_spr1_o + connect \B \wrpick_SPR_spr1_en_o + connect \Y $1685 + end + process $group_663 + assign \wr_pick$1684 1'0 + assign \wr_pick$1684 $1685 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1687 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire width 1 \wr_pick_dly$1687$next + process $group_664 + assign \wr_pick_dly$1687$next \wr_pick_dly$1687 + assign \wr_pick_dly$1687$next \wr_pick$1684 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \coresync_rst + case 1'1 + assign \wr_pick_dly$1687$next 1'0 + end + sync init + update \wr_pick_dly$1687 1'0 + sync posedge \coresync_clk + update \wr_pick_dly$1687 \wr_pick_dly$1687$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1688 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick_dly$1687 + connect \Y $1688 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + wire width 1 $1690 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1684 + connect \B $1688 + connect \Y $1690 + end + process $group_665 + assign \wr_pick_rise$919 1'0 + assign \wr_pick_rise$919 $1690 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:367" + wire width 1 \wp$1692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + wire width 1 $1693 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:368" + cell $and $1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1684 + connect \B \wrpick_SPR_spr1_en_o + connect \Y $1693 + end + process $group_666 + assign \wp$1692 1'0 + assign \wp$1692 $1693 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:366" + wire width 10 \addr_en$1695 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + wire width 10 $1696 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:369" + cell $mux $1697 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \spro + connect \S \wp$1692 + connect \Y $1696 + end + process $group_667 + assign \addr_en$1695 10'0000000000 + assign \addr_en$1695 $1696 + sync init + end + process $group_668 + assign \spr_spr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr_spr1__data_i \fus_dest2_o$152 + sync init + end + process $group_669 + assign \spr_spr1__addr$158 7'0000000 + assign \spr_spr1__addr$158 \addr_en$1695 [6:0] + sync init + end + process $group_670 + assign \spr_spr1__wen 1'0 + assign \spr_spr1__wen \wp$1692 + sync init + end + process $group_671 + assign \coresync_rst 1'0 + assign \coresync_rst \core_reset_i + sync init + end + connect \o_ok 1'0 + connect \ea_ok 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.imem" +module \imem + attribute \src "simple/issuer.py:101" + wire width 1 input 0 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 input 1 \a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire width 1 input 2 \a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire width 1 input 3 \f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire width 1 output 4 \f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 output 5 \f_instr_o + attribute \src "simple/issuer.py:101" + wire width 1 input 6 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 output 7 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 \ibus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 input 8 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 input 9 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 output 10 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 \ibus__stb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 11 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 \ibus__sel$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 12 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 13 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 \ibus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" + wire width 1 \a_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $5 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $5 + connect \B $7 + connect \Y $9 + end + process $group_0 + assign \ibus__cyc$next \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { $3 \ibus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + case 1'1 + assign \ibus__cyc$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + case 2'1- + assign \ibus__cyc$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \ibus__cyc$next 1'0 + end + sync init + update \ibus__cyc 1'0 + sync posedge \clk + update \ibus__cyc \ibus__cyc$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $15 + connect \B $17 + connect \Y $19 + end + process $group_1 + assign \ibus__stb$next \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { $13 \ibus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch { $19 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + case 1'1 + assign \ibus__stb$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + case 2'1- + assign \ibus__stb$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \ibus__stb$next 1'0 + end + sync init + update \ibus__stb 1'0 + sync posedge \clk + update \ibus__stb \ibus__stb$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B $21 + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $25 + connect \B $27 + connect \Y $29 + end + process $group_2 + assign \ibus__sel$next \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { $23 \ibus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch { $29 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + case 1'1 + assign \ibus__sel$next 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + case 2'1- + assign \ibus__sel$next 8'11111111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \ibus__sel$next 8'00000000 + end + sync init + update \ibus__sel 8'00000000 + sync posedge \clk + update \ibus__sel \ibus__sel$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" + wire width 64 \ibus_rdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" + wire width 64 \ibus_rdata$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B $31 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $35 + connect \B $37 + connect \Y $39 + end + process $group_3 + assign \ibus_rdata$next \ibus_rdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { $33 \ibus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch { $39 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + case 1'1 + assign \ibus_rdata$next \ibus__dat_r + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + case 2'1- + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \ibus_rdata$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \ibus_rdata 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ibus_rdata \ibus_rdata$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B $41 + connect \Y $43 + end + process $group_4 + assign \ibus__adr$next \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { $43 \ibus__cyc } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + case 2'1- + assign \ibus__adr$next \a_pc_i [47:3] + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \ibus__adr$next 45'000000000000000000000000000000000000000000000 + end + sync init + update \ibus__adr 45'000000000000000000000000000000000000000000000 + sync posedge \clk + update \ibus__adr \ibus__adr$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire width 1 \f_fetch_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire width 1 \f_fetch_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + cell $and $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" + wire width 1 \f_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + cell $not $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $47 + end + process $group_5 + assign \f_fetch_err_o$next \f_fetch_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + switch { $47 $45 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + case 2'-1 + assign \f_fetch_err_o$next 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + case 2'1- + assign \f_fetch_err_o$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \f_fetch_err_o$next 1'0 + end + sync init + update \f_fetch_err_o 1'0 + sync posedge \clk + update \f_fetch_err_o \f_fetch_err_o$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + cell $and $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + cell $not $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $51 + end + process $group_6 + assign \f_badaddr_o$next \f_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + switch { $51 $49 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + case 2'-1 + assign \f_badaddr_o$next \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + case 2'1- + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \f_badaddr_o$next 45'000000000000000000000000000000000000000000000 + end + sync init + update \f_badaddr_o 45'000000000000000000000000000000000000000000000 + sync posedge \clk + update \f_badaddr_o \f_badaddr_o$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" + wire width 1 \a_busy_o + process $group_7 + assign \a_busy_o 1'0 + assign \a_busy_o \ibus__cyc + sync init + end + process $group_8 + assign \f_busy_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \f_fetch_err_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + case 1'1 + assign \f_busy_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88" + case + assign \f_busy_o \ibus__cyc + end + sync init + end + process $group_9 + assign \f_instr_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \f_fetch_err_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88" + case + assign \f_instr_o \ibus_rdata + end + sync init + end + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dbg" +module \dbg + attribute \src "simple/issuer.py:101" + wire width 1 input 0 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" + wire width 1 output 1 \core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:84" + wire width 1 input 2 \terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 3 \core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 4 \core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 1 output 5 \core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:85" + wire width 1 input 6 \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:66" + wire width 1 output 7 \dbg_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" + wire width 7 output 8 \dbg_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" + wire width 64 input 9 \dbg_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:67" + wire width 1 input 10 \dbg_gpr_ack + attribute \src "simple/issuer.py:101" + wire width 1 input 11 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire width 1 output 12 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:55" + wire width 4 input 13 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 1 input 14 \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 64 output 15 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 1 input 16 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:56" + wire width 64 input 17 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" + wire width 1 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" + cell $eq $3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'101 + connect \Y $2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" + cell $mux $4 + parameter \WIDTH 1 + connect \A \dmi_req_i + connect \B \dbg_gpr_ack + connect \S $2 + connect \Y $1 + end + process $group_0 + assign \dmi_ack_o 1'0 + assign \dmi_ack_o $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + cell $eq $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" + cell $mux $8 + parameter \WIDTH 1 + connect \A 1'0 + connect \B \dmi_req_i + connect \S $6 + connect \Y $5 + end + process $group_1 + assign \dbg_gpr_req 1'0 + assign \dbg_gpr_req $5 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:109" + wire width 64 \stat_reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire width 64 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:112" + wire width 1 \stopping + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:112" + wire width 1 \stopping$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:116" + wire width 1 \terminated + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:116" + wire width 1 \terminated$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 64 + connect \A { \terminated \core_stopped_i \stopping } + connect \Y $9 + end + process $group_2 + assign \stat_reg 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \stat_reg $9 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" + wire width 32 \log_dmi_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" + wire width 32 \log_dmi_addr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:95" + wire width 32 \log_write_addr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:121" + wire width 64 \log_dmi_data + process $group_3 + assign \dmi_dout 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + switch \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + case 4'0001 + assign \dmi_dout \stat_reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + case 4'0010 + assign \dmi_dout \core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" + case 4'0011 + assign \dmi_dout \core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + case 4'0101 + assign \dmi_dout \dbg_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + case 4'0110 + assign \dmi_dout { \log_write_addr_o \log_dmi_addr } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:152" + case 4'0111 + assign \dmi_dout \log_dmi_data + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:113" + wire width 1 \do_step + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:113" + wire width 1 \do_step$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:106" + wire width 1 \dmi_req_i_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:106" + wire width 1 \dmi_req_i_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $not $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $and $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:124" + wire width 1 \dmi_read_log_data_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:124" + wire width 1 \dmi_read_log_data_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" + wire width 1 \dmi_read_log_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" + wire width 1 \dmi_read_log_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $not $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $and $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B $15 + connect \Y $17 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + cell $eq $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $19 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + cell $eq $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + cell $eq $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $23 + end + process $group_4 + assign \do_step$next \do_step + assign \do_step$next 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + switch { $17 $13 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + switch { \dmi_we_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + switch { $23 $21 $19 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + case 3'--1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" + switch { \dmi_din [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" + case 1'1 + assign \do_step$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + case 3'-1- + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + case 3'1-- + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + case 2'1- + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \do_step$next 1'0 + end + sync init + update \do_step 1'0 + sync posedge \clk + update \do_step \do_step$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114" + wire width 1 \do_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114" + wire width 1 \do_reset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $and $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B $25 + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $and $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B $29 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + cell $eq $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + cell $eq $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + cell $eq $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $37 + end + process $group_5 + assign \do_reset$next \do_reset + assign \do_reset$next 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + switch { $31 $27 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + switch { \dmi_we_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + switch { $37 $35 $33 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + case 3'--1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" + switch { \dmi_din [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" + case 1'1 + assign \do_reset$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + case 3'-1- + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + case 3'1-- + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + case 2'1- + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \do_reset$next 1'0 + end + sync init + update \do_reset 1'0 + sync posedge \clk + update \do_reset \do_reset$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:115" + wire width 1 \do_icreset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:115" + wire width 1 \do_icreset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $not $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $and $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B $39 + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $not $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $and $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B $43 + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + cell $eq $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + cell $eq $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + cell $eq $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $51 + end + process $group_6 + assign \do_icreset$next \do_icreset + assign \do_icreset$next 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + switch { $45 $41 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + switch { \dmi_we_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + switch { $51 $49 $47 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + case 3'--1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:180" + switch { \dmi_din [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:180" + case 1'1 + assign \do_icreset$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + case 3'-1- + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + case 3'1-- + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + case 2'1- + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \do_icreset$next 1'0 + end + sync init + update \do_icreset 1'0 + sync posedge \clk + update \do_icreset \do_icreset$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" + wire width 1 \do_dmi_log_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" + wire width 1 \do_dmi_log_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $not $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $53 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $and $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B $53 + connect \Y $55 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $not $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $57 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $and $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B $57 + connect \Y $59 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + cell $eq $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $61 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + cell $eq $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $63 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + wire width 1 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + cell $eq $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $65 + end + process $group_7 + assign \do_dmi_log_rd$next \do_dmi_log_rd + assign \do_dmi_log_rd$next 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + switch { $59 $55 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + switch { \dmi_we_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + switch { $65 $63 $61 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + case 3'--1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + case 3'-1- + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + case 3'1-- + assign \do_dmi_log_rd$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + case 2'1- + assign \do_dmi_log_rd$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \do_dmi_log_rd$next 1'0 + end + sync init + update \do_dmi_log_rd 1'0 + sync posedge \clk + update \do_dmi_log_rd \do_dmi_log_rd$next + end + process $group_8 + assign \dmi_req_i_1$next \dmi_req_i_1 + assign \dmi_req_i_1$next \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \dmi_req_i_1$next 1'0 + end + sync init + update \dmi_req_i_1 1'0 + sync posedge \clk + update \dmi_req_i_1 \dmi_req_i_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $not $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $67 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $and $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B $67 + connect \Y $69 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $not $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $71 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $and $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B $71 + connect \Y $73 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + cell $eq $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $75 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + cell $eq $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $77 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + cell $eq $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $79 + end + process $group_9 + assign \terminated$next \terminated + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + switch { $73 $69 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + switch { \dmi_we_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + switch { $79 $77 $75 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + case 3'--1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" + switch { \dmi_din [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" + case 1'1 + assign \terminated$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" + switch { \dmi_din [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" + case 1'1 + assign \terminated$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" + switch { \dmi_din [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" + case 1'1 + assign \terminated$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + case 3'-1- + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + case 3'1-- + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + case 2'1- + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch { \terminate_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + case 1'1 + assign \terminated$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \terminated$next 1'0 + end + sync init + update \terminated 1'0 + sync posedge \clk + update \terminated \terminated$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $not $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $81 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $and $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B $81 + connect \Y $83 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $not $86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $85 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $and $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B $85 + connect \Y $87 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + cell $eq $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $89 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + wire width 1 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + cell $eq $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $91 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + wire width 1 $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + cell $eq $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $93 + end + process $group_10 + assign \stopping$next \stopping + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + switch { $87 $83 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + switch { \dmi_we_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + switch { $93 $91 $89 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + case 3'--1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:175" + switch { \dmi_din [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:175" + case 1'1 + assign \stopping$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" + switch { \dmi_din [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" + case 1'1 + assign \stopping$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + case 3'-1- + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + case 3'1-- + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + case 2'1- + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch { \terminate_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + case 1'1 + assign \stopping$next 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \stopping$next 1'0 + end + sync init + update \stopping 1'0 + sync posedge \clk + update \stopping \stopping$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:118" + wire width 7 \gspr_index + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:118" + wire width 7 \gspr_index$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $not $96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $95 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $and $98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B $95 + connect \Y $97 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $not $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $99 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $and $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B $99 + connect \Y $101 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + cell $eq $104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $103 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + cell $eq $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $105 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + cell $eq $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $107 + end + process $group_11 + assign \gspr_index$next \gspr_index + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + switch { $101 $97 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + switch { \dmi_we_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + switch { $107 $105 $103 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + case 3'--1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + case 3'-1- + assign \gspr_index$next \dmi_din [6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + case 3'1-- + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + case 2'1- + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \gspr_index$next 7'0000000 + end + sync init + update \gspr_index 7'0000000 + sync posedge \clk + update \gspr_index \gspr_index$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $not $110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $109 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + cell $and $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B $109 + connect \Y $111 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $not $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $113 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + cell $and $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B $113 + connect \Y $115 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + cell $eq $118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $117 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + cell $eq $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $119 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + cell $eq $122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $121 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + wire width 3 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + wire width 3 $124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + cell $add $125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \log_dmi_addr [1:0] + connect \B 1'1 + connect \Y $124 + end + connect $123 $124 + process $group_12 + assign \log_dmi_addr$next \log_dmi_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + switch { $115 $111 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" + case 2'-1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + switch { \dmi_we_i } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + switch { $121 $119 $117 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" + case 3'--1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" + case 3'-1- + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" + case 3'1-- + assign \log_dmi_addr$next \dmi_din [31:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" + case 2'1- + assign \log_dmi_addr$next [1:0] $123 [1:0] + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \log_dmi_addr$next 32'00000000000000000000000000000000 + end + sync init + update \log_dmi_addr 32'00000000000000000000000000000000 + sync posedge \clk + update \log_dmi_addr \log_dmi_addr$next + end + process $group_13 + assign \dmi_read_log_data_1$next \dmi_read_log_data_1 + assign \dmi_read_log_data_1$next \dmi_read_log_data + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \dmi_read_log_data_1$next 1'0 + end + sync init + update \dmi_read_log_data_1 1'0 + sync posedge \clk + update \dmi_read_log_data_1 \dmi_read_log_data_1$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" + wire width 1 $126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" + cell $eq $127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'111 + connect \Y $126 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" + wire width 1 $128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" + cell $and $129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B $126 + connect \Y $128 + end + process $group_14 + assign \dmi_read_log_data$next \dmi_read_log_data + assign \dmi_read_log_data$next $128 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \dmi_read_log_data$next 1'0 + end + sync init + update \dmi_read_log_data 1'0 + sync posedge \clk + update \dmi_read_log_data \dmi_read_log_data$next + end + process $group_15 + assign \dbg_gpr_addr 7'0000000 + assign \dbg_gpr_addr \gspr_index + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + wire width 1 $130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + cell $not $131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \do_step + connect \Y $130 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + wire width 1 $132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + cell $and $133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \stopping + connect \B $130 + connect \Y $132 + end + process $group_16 + assign \core_stop_o 1'0 + assign \core_stop_o $132 + sync init + end + process $group_17 + assign \core_rst_o 1'0 + assign \core_rst_o \do_reset + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:81" + wire width 1 \icache_rst_o + process $group_18 + assign \icache_rst_o 1'0 + assign \icache_rst_o \do_icreset + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + wire width 1 \terminated_o + process $group_19 + assign \terminated_o 1'0 + assign \terminated_o \terminated + sync init + end + connect \log_write_addr_o 32'00000000000000000000000000000000 + connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec19" +module \dec19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch$1 + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \function_unit 11'00000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \function_unit 11'00000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \function_unit 11'00000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \function_unit 11'00010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \function_unit 11'00010000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \function_unit 11'00000000010 + end + sync init + end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \form 5'01001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \form 5'01001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \form 5'00111 + end + sync init + end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \internal_op 7'0101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \internal_op 7'1000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \internal_op 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \internal_op 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \internal_op 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \internal_op 7'0100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \internal_op 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \internal_op 7'1000110 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \internal_op 7'0000000 + end + sync init + end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \in1_sel 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \in1_sel 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \in1_sel 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \in1_sel 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \in1_sel 3'011 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in1_sel 3'000 + end + sync init + end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \in2_sel 4'1100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \in2_sel 4'1100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \in2_sel 4'1100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \in2_sel 4'1100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \in2_sel 4'1100 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in2_sel 4'0000 + end + sync init + end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \in3_sel 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in3_sel 2'00 + end + sync init + end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \out_sel 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \out_sel 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \out_sel 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \out_sel 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \out_sel 2'00 + end + sync init + end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \cr_in 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \cr_in 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \cr_in 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \cr_in 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \cr_in 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \cr_in 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_in 3'000 + end + sync init + end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \cr_out 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \cr_out 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_out 3'000 + end + sync init + end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \ldst_len 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \ldst_len 4'0000 + end + sync init + end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \upd 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \upd 2'00 + end + sync init + end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \rc_sel 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rc_sel 2'10 + end + sync init + end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \cry_in 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_in 2'00 + end + sync init + end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \asmcode 8'01101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \asmcode 8'00100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \asmcode 8'00100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \asmcode 8'00100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \asmcode 8'00101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \asmcode 8'00101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \asmcode 8'00101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \asmcode 8'00101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \asmcode 8'00101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \asmcode 8'00010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \asmcode 8'00010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \asmcode 8'00011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \asmcode 8'01001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \asmcode 8'10010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \asmcode 8'01001000 + end + sync init + end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \inv_a 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_a 1'0 + end + sync init + end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \inv_out 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_out 1'0 + end + sync init + end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \cry_out 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_out 1'0 + end + sync init + end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \br 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \br 1'0 + end + sync init + end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \sgn_ext 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn_ext 1'0 + end + sync init + end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \rsrv 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rsrv 1'0 + end + sync init + end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \is_32b 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \is_32b 1'0 + end + sync init + end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \sgn 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn 1'0 + end + sync init + end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \lk 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \lk 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \lk 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \lk 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \lk 1'0 + end + sync init + end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000000000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100000001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010000001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100100001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011100001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000100001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0111000001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0110100001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0011000001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000010000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'1000110000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0010010110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0000010010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 10'0100010010 + assign \sgl_pipe 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgl_pipe 1'1 + end + sync init + end + process $group_25 + assign \opcode_switch$1 5'00000 + assign \opcode_switch$1 \opcode_in [5:1] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec30" +module \dec30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 4 \opcode_switch + process $group_0 + assign \opcode_switch 4'0000 + assign \opcode_switch \opcode_in [4:1] + sync init + end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \function_unit 11'00000001000 + end + sync init + end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \form 5'10101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \form 5'10101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \form 5'10100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \form 5'10100 + end + sync init + end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \internal_op 7'0111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \internal_op 7'0111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \internal_op 7'0111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \internal_op 7'0111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \internal_op 7'0111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \internal_op 7'0111010 + end + sync init + end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \in1_sel 3'000 + end + sync init + end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \in2_sel 4'0001 + end + sync init + end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \in3_sel 2'01 + end + sync init + end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \out_sel 2'10 + end + sync init + end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \cr_in 3'000 + end + sync init + end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \cr_out 3'001 + end + sync init + end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \ldst_len 4'0000 + end + sync init + end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \upd 2'00 + end + sync init + end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \rc_sel 2'10 + end + sync init + end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \cry_in 2'00 + end + sync init + end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \asmcode 8'10010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \asmcode 8'10010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \asmcode 8'10010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \asmcode 8'10010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \asmcode 8'10010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \asmcode 8'10010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \asmcode 8'10010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \asmcode 8'10010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \asmcode 8'10010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \asmcode 8'10010010 + end + sync init + end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \inv_a 1'0 + end + sync init + end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \inv_out 1'0 + end + sync init + end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \cry_out 1'0 + end + sync init + end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \br 1'0 + end + sync init + end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \sgn_ext 1'0 + end + sync init + end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \rsrv 1'0 + end + sync init + end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \is_32b 1'0 + end + sync init + end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \sgn 1'0 + end + sync init + end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \lk 1'0 + end + sync init + end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0011 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0110 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'0111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 4'1001 + assign \sgl_pipe 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub10" +module \dec_sub10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \function_unit 11'00000000010 + end + sync init + end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \form 5'10001 + end + sync init + end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \internal_op 7'0000010 + end + sync init + end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in1_sel 3'001 + end + sync init + end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in2_sel 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in2_sel 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in2_sel 4'0000 + end + sync init + end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in3_sel 2'00 + end + sync init + end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \out_sel 2'01 + end + sync init + end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cr_in 3'000 + end + sync init + end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cr_out 3'001 + end + sync init + end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \ldst_len 4'0000 + end + sync init + end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \upd 2'00 + end + sync init + end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \rc_sel 2'10 + end + sync init + end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cry_in 2'10 + end + sync init + end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \asmcode 8'00000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \asmcode 8'00001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'00000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \asmcode 8'00000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \asmcode 8'00000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \asmcode 8'00000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \asmcode 8'00001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \asmcode 8'00001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \asmcode 8'00001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \asmcode 8'00001110 + end + sync init + end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \inv_a 1'0 + end + sync init + end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \inv_out 1'0 + end + sync init + end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cry_out 1'1 + end + sync init + end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \br 1'0 + end + sync init + end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgn_ext 1'0 + end + sync init + end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \rsrv 1'0 + end + sync init + end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \is_32b 1'0 + end + sync init + end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgn 1'0 + end + sync init + end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \lk 1'0 + end + sync init + end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgl_pipe 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub28" +module \dec_sub28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \function_unit 11'00000010000 + end + sync init + end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \form 5'01000 + end + sync init + end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \internal_op 7'0001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \internal_op 7'0001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \internal_op 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \internal_op 7'1000011 + end + sync init + end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \in1_sel 3'100 + end + sync init + end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \in2_sel 4'0001 + end + sync init + end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \in3_sel 2'00 + end + sync init + end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \out_sel 2'10 + end + sync init + end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cr_in 3'000 + end + sync init + end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cr_out 3'001 + end + sync init + end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \ldst_len 4'0000 + end + sync init + end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \upd 2'00 + end + sync init + end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \rc_sel 2'10 + end + sync init + end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cry_in 2'00 + end + sync init + end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'00001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \asmcode 8'00010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \asmcode 8'00011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \asmcode 8'00011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \asmcode 8'01000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \asmcode 8'10000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \asmcode 8'10000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \asmcode 8'10000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \asmcode 8'10001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \asmcode 8'11001011 + end + sync init + end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \inv_a 1'0 + end + sync init + end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \inv_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \inv_out 1'0 + end + sync init + end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cry_out 1'0 + end + sync init + end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \br 1'0 + end + sync init + end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \sgn_ext 1'0 + end + sync init + end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \rsrv 1'0 + end + sync init + end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \is_32b 1'0 + end + sync init + end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \sgn 1'0 + end + sync init + end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \lk 1'0 + end + sync init + end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \sgl_pipe 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub0" +module \dec_sub0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \function_unit 11'00001000000 + end + sync init + end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \form 5'11000 + end + sync init + end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \internal_op 7'0001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \internal_op 7'0111011 + end + sync init + end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in1_sel 3'000 + end + sync init + end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in2_sel 4'0000 + end + sync init + end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in3_sel 2'00 + end + sync init + end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \out_sel 2'01 + end + sync init + end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_in 3'011 + end + sync init + end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_out 3'000 + end + sync init + end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \ldst_len 4'0000 + end + sync init + end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \upd 2'00 + end + sync init + end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rc_sel 2'00 + end + sync init + end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_in 2'00 + end + sync init + end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'00011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \asmcode 8'00011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \asmcode 8'00011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \asmcode 8'10011010 + end + sync init + end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_a 1'0 + end + sync init + end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_out 1'0 + end + sync init + end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_out 1'0 + end + sync init + end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \br 1'0 + end + sync init + end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn_ext 1'0 + end + sync init + end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rsrv 1'0 + end + sync init + end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \is_32b 1'0 + end + sync init + end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn 1'0 + end + sync init + end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \lk 1'0 + end + sync init + end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgl_pipe 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub26" +module \dec_sub26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \function_unit 11'00000001000 + end + sync init + end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \form 5'10000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \form 5'10000 + end + sync init + end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \internal_op 7'0001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \internal_op 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \internal_op 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \internal_op 7'0011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \internal_op 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \internal_op 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \internal_op 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \internal_op 7'0110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \internal_op 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \internal_op 7'0110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \internal_op 7'0111101 + end + sync init + end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in1_sel 3'000 + end + sync init + end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in2_sel 4'1010 + end + sync init + end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in3_sel 2'01 + end + sync init + end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \out_sel 2'10 + end + sync init + end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cr_in 3'000 + end + sync init + end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cr_out 3'001 + end + sync init + end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \ldst_len 4'0000 + end + sync init + end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \upd 2'00 + end + sync init + end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \rc_sel 2'10 + end + sync init + end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cry_in 2'00 + end + sync init + end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \asmcode 8'00100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'00100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \asmcode 8'00100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \asmcode 8'00100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \asmcode 8'01000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \asmcode 8'01000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \asmcode 8'01000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \asmcode 8'01000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \asmcode 8'10001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \asmcode 8'10001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \asmcode 8'10001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \asmcode 8'10001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \asmcode 8'10001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \asmcode 8'10011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \asmcode 8'10011111 + end + sync init + end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \inv_a 1'0 + end + sync init + end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \inv_out 1'0 + end + sync init + end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cry_out 1'1 + end + sync init + end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \br 1'0 + end + sync init + end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgn_ext 1'0 + end + sync init + end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \rsrv 1'0 + end + sync init + end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \is_32b 1'0 + end + sync init + end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgn 1'1 + end + sync init + end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \lk 1'0 + end + sync init + end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgl_pipe 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub19" +module \dec_sub19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \function_unit 11'00010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \function_unit 11'10000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \function_unit 11'10000000000 + end + sync init + end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \form 5'01010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \form 5'01010 + end + sync init + end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \internal_op 7'1000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \internal_op 7'0101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \internal_op 7'0110001 + end + sync init + end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in1_sel 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in1_sel 3'100 + end + sync init + end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in2_sel 4'0000 + end + sync init + end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in3_sel 2'00 + end + sync init + end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \out_sel 2'11 + end + sync init + end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cr_in 3'000 + end + sync init + end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cr_out 3'000 + end + sync init + end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \ldst_len 4'0000 + end + sync init + end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \upd 2'00 + end + sync init + end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \rc_sel 2'00 + end + sync init + end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cry_in 2'00 + end + sync init + end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'01101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \asmcode 8'01101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \asmcode 8'01110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \asmcode 8'01111000 + end + sync init + end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \inv_a 1'0 + end + sync init + end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \inv_out 1'0 + end + sync init + end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cry_out 1'0 + end + sync init + end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \br 1'0 + end + sync init + end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgn_ext 1'0 + end + sync init + end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \rsrv 1'0 + end + sync init + end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \is_32b 1'0 + end + sync init + end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgn 1'0 + end + sync init + end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \lk 1'0 + end + sync init + end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgl_pipe 1'0 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub22" +module \dec_sub22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \function_unit 11'00000000010 + end + sync init + end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \form 5'01000 + end + sync init + end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \internal_op 7'0100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \internal_op 7'0000001 + end + sync init + end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in1_sel 3'000 + end + sync init + end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in2_sel 4'0000 + end + sync init + end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in3_sel 2'00 + end + sync init + end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \out_sel 2'00 + end + sync init + end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cr_in 3'000 + end + sync init + end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cr_out 3'000 + end + sync init + end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \ldst_len 4'0000 + end + sync init + end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \upd 2'00 + end + sync init + end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \rc_sel 2'00 + end + sync init + end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cry_in 2'00 + end + sync init + end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \asmcode 8'00101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \asmcode 8'00101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \asmcode 8'00110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \asmcode 8'00110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \asmcode 8'01001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'01001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \asmcode 8'01011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \asmcode 8'01100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \asmcode 8'10100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \asmcode 8'10101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \asmcode 8'10110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \asmcode 8'10110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \asmcode 8'10110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \asmcode 8'10110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \asmcode 8'11000110 + end + sync init + end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \inv_a 1'0 + end + sync init + end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \inv_out 1'0 + end + sync init + end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cry_out 1'0 + end + sync init + end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \br 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \br 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \br 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \br 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \br 1'0 + end + sync init + end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgn_ext 1'0 + end + sync init + end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \rsrv 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \rsrv 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \rsrv 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rsrv 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \rsrv 1'0 + end + sync init end - cell \l0 \l0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i - connect \ldst_port0_data_len \fus_ldst_port0_data_len - connect \ldst_port0_addr_i \fus_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok - connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o - connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok - connect \dbus__cyc \dbus__cyc - connect \dbus__ack \dbus__ack - connect \dbus__err \dbus__err - connect \dbus__stb \dbus__stb - connect \dbus__sel \dbus__sel - connect \dbus__dat_r \dbus__dat_r - connect \dbus__adr \dbus__adr - connect \dbus__we \dbus__we - connect \dbus__dat_w \dbus__dat_w + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \is_32b 1'0 + end + sync init + end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgn 1'0 + end + sync init + end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \lk 1'0 + end + sync init + end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgl_pipe 1'1 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub9" +module \dec_sub9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \function_unit 11'00100000000 + end + sync init + end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \form 5'10001 + end + sync init + end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \internal_op 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \internal_op 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \internal_op 7'0110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \internal_op 7'0110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \internal_op 7'0110010 + end + sync init + end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in1_sel 3'001 + end + sync init + end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in2_sel 4'0001 + end + sync init + end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in3_sel 2'00 + end + sync init + end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \out_sel 2'01 + end + sync init + end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cr_in 3'000 + end + sync init + end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cr_out 3'001 + end + sync init + end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \ldst_len 4'0000 + end + sync init + end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \upd 2'00 + end + sync init + end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \rc_sel 2'10 + end + sync init + end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cry_in 2'00 + end + sync init + end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \asmcode 8'00110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \asmcode 8'00110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \asmcode 8'00110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \asmcode 8'00110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \asmcode 8'00111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \asmcode 8'00111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \asmcode 8'00110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \asmcode 8'00111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \asmcode 8'01110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \asmcode 8'01110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \asmcode 8'01111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'01111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \asmcode 8'01111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \asmcode 8'01111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \asmcode 8'01111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \asmcode 8'01111110 + end + sync init + end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \inv_a 1'0 + end + sync init + end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \inv_out 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \int_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \int_dest1__wen - cell \int \int - connect \coresync_clk \coresync_clk - connect \dmi__ren \dmi__ren - connect \dmi__data_o \dmi__data_o - connect \src1__data_o \int_src1__data_o - connect \src1__addr \int_src1__addr - connect \src1__ren \int_src1__ren - connect \dest1__data_i \int_dest1__data_i - connect \dest1__addr \int_dest1__addr - connect \dest1__wen \int_dest1__wen + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cry_out 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \cr_full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \cr_full_wr__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_full_wr__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_wen - cell \cr \cr - connect \coresync_clk \coresync_clk - connect \full_rd__data_o \cr_full_rd__data_o - connect \full_rd__ren \cr_full_rd__ren - connect \src1__data_o \cr_src1__data_o - connect \src1__ren \cr_src1__ren - connect \src2__data_o \cr_src2__data_o - connect \src2__ren \cr_src2__ren - connect \src3__data_o \cr_src3__data_o - connect \src3__ren \cr_src3__ren - connect \full_wr__data_i \cr_full_wr__data_i - connect \full_wr__wen \cr_full_wr__wen - connect \data_i \cr_data_i - connect \wen \cr_wen - connect \coresync_rst \coresync_rst + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \br 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$153 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$154 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$155 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$156 - cell \xer \xer - connect \coresync_clk \coresync_clk - connect \src1__data_o \xer_src1__data_o - connect \src1__ren \xer_src1__ren - connect \src2__data_o \xer_src2__data_o - connect \src2__ren \xer_src2__ren - connect \src3__data_o \xer_src3__data_o - connect \src3__ren \xer_src3__ren - connect \data_i \xer_data_i - connect \wen \xer_wen - connect \data_i$1 \xer_data_i$153 - connect \wen$2 \xer_wen$154 - connect \data_i$3 \xer_data_i$155 - connect \wen$4 \xer_wen$156 - connect \coresync_rst \coresync_rst + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgn_ext 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \fast_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \fast_wen - cell \fast \fast - connect \coresync_clk \coresync_clk - connect \src1__data_o \fast_src1__data_o - connect \src1__ren \fast_src1__ren - connect \data_i \fast_data_i - connect \wen \fast_wen - connect \coresync_rst \coresync_rst + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \rsrv 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i$157 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \state_wen - cell \state \state - connect \coresync_clk \coresync_clk - connect \cia__ren \cia__ren - connect \cia__data_o \cia__data_o - connect \msr__ren \msr__ren - connect \msr__data_o \msr__data_o - connect \state_nia_wen \state_nia_wen - connect \wen \wen - connect \data_i \data_i - connect \data_i$1 \state_data_i - connect \data_i$2 \state_data_i$157 - connect \wen$3 \state_wen - connect \coresync_rst \coresync_rst + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \is_32b 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \spr_spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \spr_spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \spr_spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr$158 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \spr_spr1__wen - cell \spr \spr - connect \coresync_clk \coresync_clk - connect \spr1__data_o \spr_spr1__data_o - connect \spr1__addr \spr_spr1__addr - connect \spr1__ren \spr_spr1__ren - connect \spr1__data_i \spr_spr1__data_i - connect \spr1__addr$1 \spr_spr1__addr$158 - connect \spr1__wen \spr_spr1__wen + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgn 1'1 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 19 \rdpick_INT_rabc_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 19 \rdpick_INT_rabc_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_INT_rabc_en_o - cell \rdpick_INT_rabc \rdpick_INT_rabc - connect \i \rdpick_INT_rabc_i - connect \o \rdpick_INT_rabc_o - connect \en_o \rdpick_INT_rabc_en_o + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \lk 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 \rdpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 \rdpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_XER_xer_so_en_o - cell \rdpick_XER_xer_so \rdpick_XER_xer_so - connect \i \rdpick_XER_xer_so_i - connect \o \rdpick_XER_xer_so_o - connect \en_o \rdpick_XER_xer_so_en_o + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgl_pipe 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 3 \rdpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 3 \rdpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_XER_xer_ca_en_o - cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca - connect \i \rdpick_XER_xer_ca_i - connect \o \rdpick_XER_xer_ca_o - connect \en_o \rdpick_XER_xer_ca_en_o +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub11" +module \dec_sub11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \rdpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \rdpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_XER_xer_ov_en_o - cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov - connect \i \rdpick_XER_xer_ov_i - connect \o \rdpick_XER_xer_ov_o - connect \en_o \rdpick_XER_xer_ov_en_o + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \function_unit 11'01000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \function_unit 11'00100000000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \rdpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \rdpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_CR_full_cr_en_o - cell \rdpick_CR_full_cr \rdpick_CR_full_cr - connect \i \rdpick_CR_full_cr_i - connect \o \rdpick_CR_full_cr_o - connect \en_o \rdpick_CR_full_cr_en_o + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \form 5'10001 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 \rdpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 \rdpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_CR_cr_a_en_o - cell \rdpick_CR_cr_a \rdpick_CR_cr_a - connect \i \rdpick_CR_cr_a_i - connect \o \rdpick_CR_cr_a_o - connect \en_o \rdpick_CR_cr_a_en_o + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \internal_op 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \internal_op 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \internal_op 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \internal_op 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \internal_op 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \internal_op 7'0110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \internal_op 7'0110010 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \rdpick_CR_cr_b_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \rdpick_CR_cr_b_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_CR_cr_b_en_o - cell \rdpick_CR_cr_b \rdpick_CR_cr_b - connect \i \rdpick_CR_cr_b_i - connect \o \rdpick_CR_cr_b_o - connect \en_o \rdpick_CR_cr_b_en_o + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in1_sel 3'001 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \rdpick_CR_cr_c_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \rdpick_CR_cr_c_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_CR_cr_c_en_o - cell \rdpick_CR_cr_c \rdpick_CR_cr_c - connect \i \rdpick_CR_cr_c_i - connect \o \rdpick_CR_cr_c_o - connect \en_o \rdpick_CR_cr_c_en_o + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in2_sel 4'0001 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 5 \rdpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 5 \rdpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_FAST_fast1_en_o - cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 - connect \i \rdpick_FAST_fast1_i - connect \o \rdpick_FAST_fast1_o - connect \en_o \rdpick_FAST_fast1_en_o + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in3_sel 2'00 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \rdpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \rdpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_SPR_spr1_en_o - cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 - connect \i \rdpick_SPR_spr1_i - connect \o \rdpick_SPR_spr1_o - connect \en_o \rdpick_SPR_spr1_en_o + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \out_sel 2'01 + end + sync init + end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cr_in 3'000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 10 \wrpick_INT_o_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 10 \wrpick_INT_o_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_INT_o_en_o - cell \wrpick_INT_o \wrpick_INT_o - connect \i \wrpick_INT_o_i - connect \o \wrpick_INT_o_o - connect \en_o \wrpick_INT_o_en_o + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cr_out 3'001 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \wrpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \wrpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_CR_full_cr_en_o - cell \wrpick_CR_full_cr \wrpick_CR_full_cr - connect \i \wrpick_CR_full_cr_i - connect \o \wrpick_CR_full_cr_o - connect \en_o \wrpick_CR_full_cr_en_o + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \ldst_len 4'0000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 \wrpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 \wrpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_CR_cr_a_en_o - cell \wrpick_CR_cr_a \wrpick_CR_cr_a - connect \i \wrpick_CR_cr_a_i - connect \o \wrpick_CR_cr_a_o - connect \en_o \wrpick_CR_cr_a_en_o + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \upd 2'00 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 \wrpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 \wrpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_XER_xer_ca_en_o - cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca - connect \i \wrpick_XER_xer_ca_i - connect \o \wrpick_XER_xer_ca_o - connect \en_o \wrpick_XER_xer_ca_en_o + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \rc_sel 2'10 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 \wrpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 \wrpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_XER_xer_ov_en_o - cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov - connect \i \wrpick_XER_xer_ov_i - connect \o \wrpick_XER_xer_ov_o - connect \en_o \wrpick_XER_xer_ov_en_o + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cry_in 2'00 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 \wrpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 \wrpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_XER_xer_so_en_o - cell \wrpick_XER_xer_so \wrpick_XER_xer_so - connect \i \wrpick_XER_xer_so_i - connect \o \wrpick_XER_xer_so_o - connect \en_o \wrpick_XER_xer_so_en_o + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \asmcode 8'00111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \asmcode 8'00111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \asmcode 8'00111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \asmcode 8'00111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \asmcode 8'01000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \asmcode 8'01000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \asmcode 8'00111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \asmcode 8'01000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \asmcode 8'01110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \asmcode 8'01110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \asmcode 8'01111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'01111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \asmcode 8'01111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \asmcode 8'01111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \asmcode 8'10000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \asmcode 8'10000001 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 5 \wrpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 5 \wrpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_FAST_fast1_en_o - cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 - connect \i \wrpick_FAST_fast1_i - connect \o \wrpick_FAST_fast1_o - connect \en_o \wrpick_FAST_fast1_en_o + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \inv_a 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 \wrpick_STATE_nia_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 \wrpick_STATE_nia_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_STATE_nia_en_o - cell \wrpick_STATE_nia \wrpick_STATE_nia - connect \i \wrpick_STATE_nia_i - connect \o \wrpick_STATE_nia_o - connect \en_o \wrpick_STATE_nia_en_o + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \inv_out 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \wrpick_STATE_msr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \wrpick_STATE_msr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_STATE_msr_en_o - cell \wrpick_STATE_msr \wrpick_STATE_msr - connect \i \wrpick_STATE_msr_i - connect \o \wrpick_STATE_msr_o - connect \en_o \wrpick_STATE_msr_en_o + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cry_out 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \wrpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \wrpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_SPR_spr1_en_o - cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 - connect \i \wrpick_SPR_spr1_i - connect \o \wrpick_SPR_spr1_o - connect \en_o \wrpick_SPR_spr1_en_o + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \br 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140" - wire width 1 \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 1 $159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 11 $160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $and $161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 11 - connect \A \pdecode2_fn_unit - connect \B 2'10 - connect \Y $160 + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgn_ext 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $reduce_bool $162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $160 - connect \Y $159 + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \rsrv 1'0 + end + sync init end - process $group_0 - assign \en_alu0 1'0 - assign \en_alu0 $159 + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \is_32b 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:130" - wire width 10 \fu_enable - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140" - wire width 1 \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140" - wire width 1 \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140" - wire width 1 \en_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140" - wire width 1 \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140" - wire width 1 \en_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140" - wire width 1 \en_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140" - wire width 1 \en_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140" - wire width 1 \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140" - wire width 1 \en_ldst0 - process $group_1 - assign \fu_enable 10'0000000000 - assign \fu_enable [0] \en_alu0 - assign \fu_enable [1] \en_cr0 - assign \fu_enable [2] \en_branch0 - assign \fu_enable [3] \en_trap0 - assign \fu_enable [4] \en_logical0 - assign \fu_enable [5] \en_spr0 - assign \fu_enable [6] \en_div0 - assign \fu_enable [7] \en_mul0 - assign \fu_enable [8] \en_shiftrot0 - assign \fu_enable [9] \en_ldst0 + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgn 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 1 $163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 11 $164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $and $165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 11 - connect \A \pdecode2_fn_unit - connect \B 7'1000000 - connect \Y $164 + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \lk 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $reduce_bool $166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $164 - connect \Y $163 + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgl_pipe 1'0 + end + sync init end - process $group_2 - assign \en_cr0 1'0 - assign \en_cr0 $163 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub27" +module \dec_sub27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 1 $167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 11 $168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $and $169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 11 - connect \A \pdecode2_fn_unit - connect \B 6'100000 - connect \Y $168 + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \function_unit 11'00000001000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $reduce_bool $170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $168 - connect \Y $167 + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \form 5'10000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \form 5'10000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \form 5'01000 + end + sync init end process $group_3 - assign \en_branch0 1'0 - assign \en_branch0 $167 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \internal_op 7'0100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \internal_op 7'0111101 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 1 $171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 11 $172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $and $173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 11 - connect \A \pdecode2_fn_unit - connect \B 8'10000000 - connect \Y $172 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $reduce_bool $174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $172 - connect \Y $171 - end process $group_4 - assign \en_trap0 1'0 - assign \en_trap0 $171 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in1_sel 3'000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 1 $175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 11 $176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $and $177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 11 - connect \A \pdecode2_fn_unit - connect \B 5'10000 - connect \Y $176 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $reduce_bool $178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $176 - connect \Y $175 - end process $group_5 - assign \en_logical0 1'0 - assign \en_logical0 $175 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in2_sel 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in2_sel 4'0001 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 1 $179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 11 $180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $and $181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 11 - parameter \Y_WIDTH 11 - connect \A \pdecode2_fn_unit - connect \B 11'10000000000 - connect \Y $180 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $reduce_bool $182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $180 - connect \Y $179 - end process $group_6 - assign \en_spr0 1'0 - assign \en_spr0 $179 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in3_sel 2'01 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 1 $183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 11 $184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $and $185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 11 - connect \A \pdecode2_fn_unit - connect \B 10'1000000000 - connect \Y $184 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $reduce_bool $186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $184 - connect \Y $183 - end process $group_7 - assign \en_div0 1'0 - assign \en_div0 $183 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \out_sel 2'10 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 1 $187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 11 $188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $and $189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 9 - parameter \Y_WIDTH 11 - connect \A \pdecode2_fn_unit - connect \B 9'100000000 - connect \Y $188 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $reduce_bool $190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $188 - connect \Y $187 - end process $group_8 - assign \en_mul0 1'0 - assign \en_mul0 $187 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_in 3'000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 1 $191 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 11 $192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $and $193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 11 - connect \A \pdecode2_fn_unit - connect \B 4'1000 - connect \Y $192 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $reduce_bool $194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $192 - connect \Y $191 - end process $group_9 - assign \en_shiftrot0 1'0 - assign \en_shiftrot0 $191 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_out 3'001 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 1 $195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - wire width 11 $196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $and $197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 11 - connect \A \pdecode2_fn_unit - connect \B 3'100 - connect \Y $196 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141" - cell $reduce_bool $198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $196 - connect \Y $195 - end process $group_10 - assign \en_ldst0 1'0 - assign \en_ldst0 $195 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \ldst_len 4'0000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145" - wire width 2 \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145" - wire width 2 \counter$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146" - wire width 1 $199 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146" - cell $ne $200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \counter - connect \B 1'0 - connect \Y $199 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" - wire width 3 $201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" - wire width 3 $202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147" - cell $sub $203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \counter - connect \B 1'1 - connect \Y $202 - end - connect $201 $202 process $group_11 - assign \counter$next \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146" - switch { $199 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146" - case 1'1 - assign \counter$next $201 [1:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - assign \counter$next 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \counter$next 2'00 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \upd 2'00 end sync init - update \counter 2'00 - sync posedge \coresync_clk - update \counter \counter$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146" - wire width 1 $204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146" - cell $ne $205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \counter - connect \B 1'0 - connect \Y $204 end process $group_12 - assign \corebusy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146" - switch { $204 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:146" - case 1'1 - assign \corebusy_o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - assign \corebusy_o 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \corebusy_o \fus_cu_busy_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$10 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$13 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$16 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$19 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$22 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$28 - end - end + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rc_sel 2'10 end sync init end process $group_13 - assign \core_terminate_o$next \core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - assign \core_terminate_o$next 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \core_terminate_o$next 1'0 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_in 2'00 end sync init - update \core_terminate_o 1'0 - sync posedge \coresync_clk - update \core_terminate_o \core_terminate_o$next end process $group_14 - assign \fus_oper_i_alu_alu0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__insn_type \insn_type - end - end + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \asmcode 8'01000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'10011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \asmcode 8'10011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \asmcode 8'10100010 end sync init end process $group_15 - assign \fus_oper_i_alu_alu0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__fn_unit \pdecode2_fn_unit - end - end + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_a 1'0 end sync init end process $group_16 - assign \fus_oper_i_alu_alu0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_alu0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm } - end - end - end - sync init - end - process $group_18 - assign \fus_oper_i_alu_alu0__rc__rc 1'0 - assign \fus_oper_i_alu_alu0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc } - end - end + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_out 1'0 end sync init end - process $group_20 - assign \fus_oper_i_alu_alu0__oe__oe 1'0 - assign \fus_oper_i_alu_alu0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe } - end - end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_out 1'0 end sync init end - process $group_22 - assign \fus_oper_i_alu_alu0__invert_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__invert_a \pdecode2_invert_a - end - end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \br 1'0 end sync init end - process $group_23 - assign \fus_oper_i_alu_alu0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__zero_a \pdecode2_zero_a - end - end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn_ext 1'0 end sync init end - process $group_24 - assign \fus_oper_i_alu_alu0__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__invert_out \pdecode2_invert_out - end - end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rsrv 1'0 end sync init end - process $group_25 - assign \fus_oper_i_alu_alu0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__write_cr0 \pdecode2_write_cr0 - end - end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \is_32b 1'0 end sync init end - process $group_26 - assign \fus_oper_i_alu_alu0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__input_carry \pdecode2_input_carry - end - end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn 1'0 end sync init end - process $group_27 - assign \fus_oper_i_alu_alu0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__output_carry \pdecode2_output_carry - end - end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \lk 1'0 end sync init end - process $group_28 - assign \fus_oper_i_alu_alu0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__is_32bit \pdecode2_is_32bit - end - end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgl_pipe 1'0 end sync init end - process $group_29 - assign \fus_oper_i_alu_alu0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__is_signed \pdecode2_is_signed - end - end - end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub15" +module \dec_sub15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] sync init end - process $group_30 - assign \fus_oper_i_alu_alu0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__data_len \pdecode2_data_len - end - end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \function_unit 11'00001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \function_unit 11'00001000000 end sync init end - process $group_31 - assign \fus_oper_i_alu_alu0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_alu0__insn \pdecode2_insn - end - end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \form 5'10010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \form 5'10010 end sync init end - process $group_32 - assign \fus_cu_issue_i 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_issue_i \issue_i - end - end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \internal_op 7'0100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \internal_op 7'0100011 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 4 $206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pdecode2_oe - connect \B \pdecode2_oe_ok - connect \Y $207 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $209 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $207 - connect \B \pdecode2_xer_in - connect \Y $209 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $211 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $eq $212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \pdecode2_input_carry - connect \B 2'10 - connect \Y $211 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $213 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $or $214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $211 - connect \B \pdecode2_xer_in - connect \Y $213 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $not $215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { $213 $209 \pdecode2_reg2_ok \pdecode2_reg1_ok } - connect \Y $206 - end - process $group_33 - assign \fus_cu_rdmaskn_i 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_rdmaskn_i $206 - end - end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in1_sel 3'010 end sync init end - process $group_34 - assign \fus_oper_i_alu_cr0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_cr0__insn_type \insn_type - end - end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in2_sel 4'0001 end sync init end - process $group_35 - assign \fus_oper_i_alu_cr0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_cr0__fn_unit \pdecode2_fn_unit - end - end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in3_sel 2'00 end sync init end - process $group_36 - assign \fus_oper_i_alu_cr0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_cr0__insn \pdecode2_insn - end - end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \out_sel 2'01 end sync init end - process $group_37 - assign \fus_oper_i_alu_cr0__read_cr_whole 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_cr0__read_cr_whole \pdecode2_read_cr_whole - end - end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_in 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cr_in 3'101 end sync init end - process $group_38 - assign \fus_oper_i_alu_cr0__write_cr_whole 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_cr0__write_cr_whole \pdecode2_write_cr_whole - end - end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cr_out 3'000 end sync init end - process $group_39 - assign \fus_cu_issue_i$3 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_issue_i$3 \issue_i - end - end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \ldst_len 4'0000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 6 $216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $not $217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { \pdecode2_cr_in2_ok$1 \pdecode2_cr_in2_ok \pdecode2_cr_in1_ok \pdecode2_read_cr_whole \pdecode2_reg2_ok \pdecode2_reg1_ok } - connect \Y $216 - end - process $group_40 - assign \fus_cu_rdmaskn_i$5 6'000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_rdmaskn_i$5 $216 - end - end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \upd 2'00 end sync init end - process $group_41 - assign \fus_oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_branch0__cia \pdecode2_cia - end - end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \rc_sel 2'00 end sync init end - process $group_42 - assign \fus_oper_i_alu_branch0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_branch0__insn_type \insn_type - end - end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cry_in 2'00 end sync init end - process $group_43 - assign \fus_oper_i_alu_branch0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_branch0__fn_unit \pdecode2_fn_unit - end - end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \asmcode 8'01001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \asmcode 8'01001011 end sync init end - process $group_44 - assign \fus_oper_i_alu_branch0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_branch0__insn \pdecode2_insn - end - end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \inv_a 1'0 end sync init end - process $group_45 - assign \fus_oper_i_alu_branch0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_branch0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm } - end - end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \inv_out 1'0 end sync init end - process $group_47 - assign \fus_oper_i_alu_branch0__lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_branch0__lk \pdecode2_lk - end - end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cry_out 1'0 end sync init end - process $group_48 - assign \fus_oper_i_alu_branch0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_branch0__is_32bit \pdecode2_is_32bit - end - end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \br 1'0 end sync init end - process $group_49 - assign \fus_cu_issue_i$6 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_issue_i$6 \issue_i - end - end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgn_ext 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 3 $218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $not $219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { \pdecode2_cr_in1_ok \pdecode2_fast2_ok \pdecode2_fast1_ok } - connect \Y $218 - end - process $group_50 - assign \fus_cu_rdmaskn_i$8 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_rdmaskn_i$8 $218 - end - end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \rsrv 1'0 end sync init end - process $group_51 - assign \fus_oper_i_alu_trap0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_trap0__insn_type \insn_type - end - end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \is_32b 1'0 end sync init end - process $group_52 - assign \fus_oper_i_alu_trap0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_trap0__fn_unit \pdecode2_fn_unit - end - end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgn 1'0 end sync init end - process $group_53 - assign \fus_oper_i_alu_trap0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_trap0__insn \pdecode2_insn - end - end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \lk 1'0 end sync init end - process $group_54 - assign \fus_oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_trap0__msr \pdecode2_msr - end - end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01111 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgl_pipe 1'1 end sync init end - process $group_55 - assign \fus_oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_trap0__cia \pdecode2_cia - end - end - end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub20" +module \dec_sub20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] sync init end - process $group_56 - assign \fus_oper_i_alu_trap0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_trap0__is_32bit \pdecode2_is_32bit - end - end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \function_unit 11'00000000100 end sync init end - process $group_57 - assign \fus_oper_i_alu_trap0__traptype 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_trap0__traptype \pdecode2_traptype - end - end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \form 5'01000 end sync init end - process $group_58 - assign \fus_oper_i_alu_trap0__trapaddr 13'0000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_trap0__trapaddr \pdecode2_trapaddr - end - end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \internal_op 7'0100110 end sync init end - process $group_59 - assign \fus_cu_issue_i$9 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_issue_i$9 \issue_i - end - end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in1_sel 3'010 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 4 $220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $not $221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { \pdecode2_fast2_ok \pdecode2_fast1_ok \pdecode2_reg2_ok \pdecode2_reg1_ok } - connect \Y $220 - end - process $group_60 - assign \fus_cu_rdmaskn_i$11 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_rdmaskn_i$11 $220 - end - end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in2_sel 4'0001 end sync init end - process $group_61 - assign \fus_oper_i_alu_logical0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__insn_type \insn_type - end - end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in3_sel 2'01 end sync init end - process $group_62 - assign \fus_oper_i_alu_logical0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__fn_unit \pdecode2_fn_unit - end - end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \out_sel 2'00 end sync init end - process $group_63 - assign \fus_oper_i_alu_logical0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_logical0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm } - end - end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cr_in 3'000 end sync init end - process $group_65 - assign \fus_oper_i_alu_logical0__rc__rc 1'0 - assign \fus_oper_i_alu_logical0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc } - end - end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cr_out 3'000 end sync init end - process $group_67 - assign \fus_oper_i_alu_logical0__oe__oe 1'0 - assign \fus_oper_i_alu_logical0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe } - end - end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \ldst_len 4'1000 end sync init end - process $group_69 - assign \fus_oper_i_alu_logical0__invert_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__invert_a \pdecode2_invert_a - end - end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \upd 2'00 end sync init end - process $group_70 - assign \fus_oper_i_alu_logical0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__zero_a \pdecode2_zero_a - end - end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \rc_sel 2'00 end sync init end - process $group_71 - assign \fus_oper_i_alu_logical0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__input_carry \pdecode2_input_carry - end - end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cry_in 2'00 end sync init end - process $group_72 - assign \fus_oper_i_alu_logical0__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__invert_out \pdecode2_invert_out - end - end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \asmcode 8'01001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \asmcode 8'01010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \asmcode 8'01010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \asmcode 8'01011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'01100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \asmcode 8'10101010 end sync init end - process $group_73 - assign \fus_oper_i_alu_logical0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__write_cr0 \pdecode2_write_cr0 - end - end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \inv_a 1'0 end sync init end - process $group_74 - assign \fus_oper_i_alu_logical0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__output_carry \pdecode2_output_carry - end - end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \inv_out 1'0 end sync init end - process $group_75 - assign \fus_oper_i_alu_logical0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__is_32bit \pdecode2_is_32bit - end - end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cry_out 1'0 end sync init end - process $group_76 - assign \fus_oper_i_alu_logical0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__is_signed \pdecode2_is_signed - end - end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \br 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \br 1'1 end sync init end - process $group_77 - assign \fus_oper_i_alu_logical0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__data_len \pdecode2_data_len - end - end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgn_ext 1'0 end sync init end - process $group_78 - assign \fus_oper_i_alu_logical0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_logical0__insn \pdecode2_insn - end - end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rsrv 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rsrv 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rsrv 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \rsrv 1'0 end sync init end - process $group_79 - assign \fus_cu_issue_i$12 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_issue_i$12 \issue_i - end - end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \is_32b 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 2 $222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $not $223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A { \pdecode2_reg2_ok \pdecode2_reg1_ok } - connect \Y $222 - end - process $group_80 - assign \fus_cu_rdmaskn_i$14 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_rdmaskn_i$14 $222 - end - end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgn 1'0 end sync init end - process $group_81 - assign \fus_oper_i_alu_spr0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_spr0__insn_type \insn_type - end - end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \lk 1'0 end sync init end - process $group_82 - assign \fus_oper_i_alu_spr0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_spr0__fn_unit \pdecode2_fn_unit - end - end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgl_pipe 1'1 end sync init end - process $group_83 - assign \fus_oper_i_alu_spr0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_spr0__insn \pdecode2_insn - end - end - end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub21" +module \dec_sub21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] sync init end - process $group_84 - assign \fus_oper_i_alu_spr0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_spr0__is_32bit \pdecode2_is_32bit - end - end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \function_unit 11'00000000100 end sync init end - process $group_85 - assign \fus_cu_issue_i$15 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_issue_i$15 \issue_i - end - end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \form 5'01000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 6 $224 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $225 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pdecode2_oe - connect \B \pdecode2_oe_ok - connect \Y $225 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $227 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $225 - connect \B \pdecode2_xer_in - connect \Y $227 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pdecode2_oe - connect \B \pdecode2_oe_ok - connect \Y $229 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $231 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $229 - connect \B \pdecode2_xer_in - connect \Y $231 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $233 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $eq $234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \pdecode2_input_carry - connect \B 2'10 - connect \Y $233 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $235 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $or $236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $233 - connect \B \pdecode2_xer_in - connect \Y $235 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $not $237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { $235 $231 $227 \pdecode2_fast1_ok \pdecode2_spr1_ok \pdecode2_reg1_ok } - connect \Y $224 - end - process $group_86 - assign \fus_cu_rdmaskn_i$17 6'000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_rdmaskn_i$17 $224 - end - end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \internal_op 7'0100110 end sync init end - process $group_87 - assign \fus_oper_i_alu_div0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__insn_type \insn_type - end - end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in1_sel 3'010 end sync init end - process $group_88 - assign \fus_oper_i_alu_div0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__fn_unit \pdecode2_fn_unit - end - end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in2_sel 4'0001 end sync init end - process $group_89 - assign \fus_oper_i_alu_div0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_div0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_div0__imm_data__imm_ok \fus_oper_i_alu_div0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm } - end - end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \in3_sel 2'01 end sync init end - process $group_91 - assign \fus_oper_i_alu_div0__rc__rc 1'0 - assign \fus_oper_i_alu_div0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_div0__rc__rc_ok \fus_oper_i_alu_div0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc } - end - end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \out_sel 2'00 end sync init end - process $group_93 - assign \fus_oper_i_alu_div0__oe__oe 1'0 - assign \fus_oper_i_alu_div0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_div0__oe__oe_ok \fus_oper_i_alu_div0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe } - end - end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_in 3'000 end sync init end - process $group_95 - assign \fus_oper_i_alu_div0__invert_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__invert_a \pdecode2_invert_a - end - end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cr_out 3'000 end sync init end - process $group_96 - assign \fus_oper_i_alu_div0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__zero_a \pdecode2_zero_a - end - end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \ldst_len 4'0100 end sync init end - process $group_97 - assign \fus_oper_i_alu_div0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__input_carry \pdecode2_input_carry - end - end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \upd 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \upd 2'10 end sync init end - process $group_98 - assign \fus_oper_i_alu_div0__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__invert_out \pdecode2_invert_out - end - end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rc_sel 2'00 end sync init end - process $group_99 - assign \fus_oper_i_alu_div0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__write_cr0 \pdecode2_write_cr0 - end - end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_in 2'00 end sync init end - process $group_100 - assign \fus_oper_i_alu_div0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__output_carry \pdecode2_output_carry - end - end + process $group_14 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_a 1'0 end sync init end - process $group_101 - assign \fus_oper_i_alu_div0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__is_32bit \pdecode2_is_32bit - end - end + process $group_15 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \inv_out 1'0 end sync init end - process $group_102 - assign \fus_oper_i_alu_div0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__is_signed \pdecode2_is_signed - end - end + process $group_16 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \cry_out 1'0 end sync init end - process $group_103 - assign \fus_oper_i_alu_div0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__data_len \pdecode2_data_len - end - end + process $group_17 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \br 1'0 end sync init end - process $group_104 - assign \fus_oper_i_alu_div0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_div0__insn \pdecode2_insn - end - end + process $group_18 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn_ext 1'0 end sync init end - process $group_105 - assign \fus_cu_issue_i$18 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_issue_i$18 \issue_i - end - end + process $group_19 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \rsrv 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 3 $238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $239 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pdecode2_oe - connect \B \pdecode2_oe_ok - connect \Y $239 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $241 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $239 - connect \B \pdecode2_xer_in - connect \Y $241 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $not $243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { $241 \pdecode2_reg2_ok \pdecode2_reg1_ok } - connect \Y $238 - end - process $group_106 - assign \fus_cu_rdmaskn_i$20 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_rdmaskn_i$20 $238 - end - end + process $group_20 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \is_32b 1'0 end sync init end - process $group_107 - assign \fus_oper_i_alu_mul0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_mul0__insn_type \insn_type - end - end + process $group_21 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgn 1'0 end sync init end - process $group_108 - assign \fus_oper_i_alu_mul0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_mul0__fn_unit \pdecode2_fn_unit - end - end + process $group_22 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \lk 1'0 end sync init end - process $group_109 - assign \fus_oper_i_alu_mul0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_mul0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm } - end - end + process $group_23 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 + assign \sgl_pipe 1'1 end sync init end - process $group_111 - assign \fus_oper_i_alu_mul0__rc__rc 1'0 - assign \fus_oper_i_alu_mul0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc } - end - end + process $group_24 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \asmcode 8'01010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'01010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \asmcode 8'01100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \asmcode 8'01100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \asmcode 8'10101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \asmcode 8'10101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11100 end sync init end - process $group_113 - assign \fus_oper_i_alu_mul0__oe__oe 1'0 - assign \fus_oper_i_alu_mul0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe } - end - end - end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub23" +module \dec_sub23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] sync init end - process $group_115 - assign \fus_oper_i_alu_mul0__invert_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_mul0__invert_a \pdecode2_invert_a - end - end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \function_unit 11'00000000100 end sync init end - process $group_116 - assign \fus_oper_i_alu_mul0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_mul0__zero_a \pdecode2_zero_a - end - end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \form 5'01000 end sync init end - process $group_117 - assign \fus_oper_i_alu_mul0__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_mul0__invert_out \pdecode2_invert_out - end - end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \internal_op 7'0100110 end sync init end - process $group_118 - assign \fus_oper_i_alu_mul0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_mul0__write_cr0 \pdecode2_write_cr0 - end - end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in1_sel 3'010 end sync init end - process $group_119 - assign \fus_oper_i_alu_mul0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_mul0__is_32bit \pdecode2_is_32bit - end - end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in2_sel 4'0001 end sync init end - process $group_120 - assign \fus_oper_i_alu_mul0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_mul0__is_signed \pdecode2_is_signed - end - end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in3_sel 2'01 end sync init end - process $group_121 - assign \fus_oper_i_alu_mul0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_mul0__insn \pdecode2_insn - end - end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \out_sel 2'00 end sync init end - process $group_122 - assign \fus_cu_issue_i$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_issue_i$21 \issue_i - end - end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_in 3'000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 3 $244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $245 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pdecode2_oe - connect \B \pdecode2_oe_ok - connect \Y $245 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $245 - connect \B \pdecode2_xer_in - connect \Y $247 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $not $249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { $247 \pdecode2_reg2_ok \pdecode2_reg1_ok } - connect \Y $244 - end - process $group_123 - assign \fus_cu_rdmaskn_i$23 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_rdmaskn_i$23 $244 - end - end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_out 3'000 end sync init end - process $group_124 - assign \fus_oper_i_alu_shift_rot0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__insn_type \insn_type - end - end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \ldst_len 4'0100 end sync init end - process $group_125 - assign \fus_oper_i_alu_shift_rot0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__fn_unit \pdecode2_fn_unit - end - end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \upd 2'00 end sync init end - process $group_126 - assign \fus_oper_i_alu_shift_rot0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_shift_rot0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm } - end - end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rc_sel 2'00 end sync init end - process $group_128 - assign \fus_oper_i_alu_shift_rot0__rc__rc 1'0 - assign \fus_oper_i_alu_shift_rot0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc } - end - end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_in 2'00 end sync init end - process $group_130 - assign \fus_oper_i_alu_shift_rot0__oe__oe 1'0 - assign \fus_oper_i_alu_shift_rot0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe } - end - end + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \asmcode 8'01010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \asmcode 8'01010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \asmcode 8'01011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \asmcode 8'01011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \asmcode 8'01100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \asmcode 8'01100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \asmcode 8'01101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'01101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \asmcode 8'10100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \asmcode 8'10101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \asmcode 8'10110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \asmcode 8'10110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \asmcode 8'10111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \asmcode 8'10111010 end sync init end - process $group_132 - assign { } 0'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { } {} - end - end + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_a 1'0 end sync init end - process $group_133 - assign \fus_oper_i_alu_shift_rot0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__input_carry \pdecode2_input_carry - end - end + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_out 1'0 end sync init end - process $group_134 - assign \fus_oper_i_alu_shift_rot0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__output_carry \pdecode2_output_carry - end - end + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_out 1'0 end sync init end - process $group_135 - assign \fus_oper_i_alu_shift_rot0__input_cr 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__input_cr \pdecode2_input_cr - end - end + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \br 1'0 end sync init end - process $group_136 - assign \fus_oper_i_alu_shift_rot0__output_cr 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__output_cr \pdecode2_output_cr - end - end + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn_ext 1'0 end sync init end - process $group_137 - assign \fus_oper_i_alu_shift_rot0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__is_32bit \pdecode2_is_32bit - end - end + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rsrv 1'0 end sync init end - process $group_138 - assign \fus_oper_i_alu_shift_rot0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__is_signed \pdecode2_is_signed - end - end + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \is_32b 1'0 end sync init end - process $group_139 - assign \fus_oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__insn \pdecode2_insn - end - end + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn 1'0 end sync init end - process $group_140 - assign \fus_cu_issue_i$24 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_issue_i$24 \issue_i - end - end + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \lk 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 4 $250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $eq $252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \pdecode2_input_carry - connect \B 2'10 - connect \Y $251 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $253 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $or $254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $251 - connect \B \pdecode2_xer_in - connect \Y $253 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $not $255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { $253 \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok } - connect \Y $250 - end - process $group_141 - assign \fus_cu_rdmaskn_i$26 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_rdmaskn_i$26 $250 - end - end + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'01100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgl_pipe 1'1 end sync init end - process $group_142 - assign \fus_oper_i_ldst_ldst0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_ldst_ldst0__insn_type \insn_type - end - end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub16" +module \dec_sub16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init + end + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \function_unit 11'00001000000 end sync init end - process $group_143 - assign \fus_oper_i_ldst_ldst0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_ldst_ldst0__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm } - end - end + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \form 5'01010 end sync init end - process $group_145 - assign \fus_oper_i_ldst_ldst0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_ldst_ldst0__zero_a \pdecode2_zero_a - end - end + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \internal_op 7'0110000 end sync init end - process $group_146 - assign \fus_oper_i_ldst_ldst0__rc__rc 1'0 - assign \fus_oper_i_ldst_ldst0__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc } - end - end + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in1_sel 3'100 end sync init end - process $group_148 - assign \fus_oper_i_ldst_ldst0__oe__oe 1'0 - assign \fus_oper_i_ldst_ldst0__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign { \fus_oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe } - end - end + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in2_sel 4'0000 end sync init end - process $group_150 - assign \fus_oper_i_ldst_ldst0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_ldst_ldst0__is_32bit \pdecode2_is_32bit - end - end + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in3_sel 2'00 end sync init end - process $group_151 - assign \fus_oper_i_ldst_ldst0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_ldst_ldst0__is_signed \pdecode2_is_signed - end - end + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \out_sel 2'00 end sync init end - process $group_152 - assign \fus_oper_i_ldst_ldst0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_ldst_ldst0__data_len \pdecode2_data_len - end - end + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_in 3'110 end sync init end - process $group_153 - assign \fus_oper_i_ldst_ldst0__byte_reverse 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_ldst_ldst0__byte_reverse \pdecode2_byte_reverse - end - end + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_out 3'100 end sync init end - process $group_154 - assign \fus_oper_i_ldst_ldst0__sign_extend 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_ldst_ldst0__sign_extend \pdecode2_sign_extend - end - end + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \ldst_len 4'0000 end sync init end - process $group_155 - assign \fus_oper_i_ldst_ldst0__ldst_mode 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_oper_i_ldst_ldst0__ldst_mode \pdecode2_ldst_mode - end - end + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \upd 2'00 end sync init end - process $group_156 - assign \fus_cu_issue_i$27 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_issue_i$27 \issue_i - end - end + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rc_sel 2'00 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 3 $256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $not $257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok } - connect \Y $256 - end - process $group_157 - assign \fus_cu_rdmaskn_i$29 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - switch { \valid } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:150" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" - switch \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:156" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:166" - case 1'1 - assign \fus_cu_rdmaskn_i$29 $256 - end - end + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_in 2'00 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_INT_rabc_0 - process $group_158 - assign \rdflag_INT_rabc_0 1'0 - assign \rdflag_INT_rabc_0 \pdecode2_reg2_ok + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \asmcode 8'01110101 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_INT_rabc_1 - process $group_159 - assign \rdflag_INT_rabc_1 1'0 - assign \rdflag_INT_rabc_1 \pdecode2_reg3_ok + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_a 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_INT_rabc_2 - process $group_160 - assign \rdflag_INT_rabc_2 1'0 - assign \rdflag_INT_rabc_2 \pdecode2_reg1_ok + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_out 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $258 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [1] - connect \B \fu_enable [0] - connect \Y $258 + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_out 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $260 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $258 - connect \B \rdflag_INT_rabc_0 - connect \Y $260 + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \br 1'0 + end + sync init end - process $group_161 - assign \pick 1'0 - assign \pick $260 + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn_ext 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$266 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$269 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$271 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$272 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$273 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$274 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$275 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$277 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$278 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$279 - process $group_162 - assign \rdpick_INT_rabc_i 19'0000000000000000000 - assign \rdpick_INT_rabc_i [0] \pick - assign \rdpick_INT_rabc_i [1] \pick$262 - assign \rdpick_INT_rabc_i [2] \pick$263 - assign \rdpick_INT_rabc_i [3] \pick$264 - assign \rdpick_INT_rabc_i [4] \pick$265 - assign \rdpick_INT_rabc_i [5] \pick$266 - assign \rdpick_INT_rabc_i [6] \pick$267 - assign \rdpick_INT_rabc_i [7] \pick$268 - assign \rdpick_INT_rabc_i [8] \pick$269 - assign \rdpick_INT_rabc_i [9] \pick$270 - assign \rdpick_INT_rabc_i [10] \pick$271 - assign \rdpick_INT_rabc_i [11] \pick$272 - assign \rdpick_INT_rabc_i [12] \pick$273 - assign \rdpick_INT_rabc_i [13] \pick$274 - assign \rdpick_INT_rabc_i [14] \pick$275 - assign \rdpick_INT_rabc_i [15] \pick$276 - assign \rdpick_INT_rabc_i [16] \pick$277 - assign \rdpick_INT_rabc_i [17] \pick$278 - assign \rdpick_INT_rabc_i [18] \pick$279 + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rsrv 1'0 + end sync init end - process $group_163 - assign \fus_cu_rd__go_i 4'0000 - assign \fus_cu_rd__go_i [1] \rdpick_INT_rabc_o [0] - assign \fus_cu_rd__go_i [0] \rdpick_INT_rabc_o [10] - assign \fus_cu_rd__go_i [2] \rdpick_XER_xer_so_o [0] - assign \fus_cu_rd__go_i [3] \rdpick_XER_xer_ca_o [0] + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \is_32b 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $280 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [0] - connect \B \rdpick_INT_rabc_en_o - connect \Y $280 + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn 1'0 + end + sync init end - process $group_164 - assign \rp_INT_rabc_alu0_0 1'0 - assign \rp_INT_rabc_alu0_0 $280 + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \lk 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $282 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $283 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg2 - connect \S \rp_INT_rabc_alu0_0 - connect \Y $282 + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgl_pipe 1'0 + end + sync init end - process $group_165 - assign \addr_en_INT_rabc_alu0_0 5'00000 - assign \addr_en_INT_rabc_alu0_0 $282 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub18" +module \dec_sub18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] sync init end - process $group_166 - assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src2_i \int_src1__data_o + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \function_unit 11'00010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \function_unit 11'00010000000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [1] - connect \B \fu_enable [1] - connect \Y $284 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $286 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $284 - connect \B \rdflag_INT_rabc_0 - connect \Y $286 + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \form 5'01000 + end + sync init end - process $group_167 - assign \pick$262 1'0 - assign \pick$262 $286 + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \internal_op 7'1001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \internal_op 7'1001010 + end sync init end - process $group_168 - assign \fus_cu_rd__go_i$31 6'000000 - assign \fus_cu_rd__go_i$31 [1] \rdpick_INT_rabc_o [1] - assign \fus_cu_rd__go_i$31 [0] \rdpick_INT_rabc_o [11] - assign \fus_cu_rd__go_i$31 [2] \rdpick_CR_full_cr_o - assign \fus_cu_rd__go_i$31 [3] \rdpick_CR_cr_a_o [0] - assign \fus_cu_rd__go_i$31 [4] \rdpick_CR_cr_b_o - assign \fus_cu_rd__go_i$31 [5] \rdpick_CR_cr_c_o + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in1_sel 3'100 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $288 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [1] - connect \B \rdpick_INT_rabc_en_o - connect \Y $288 + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in2_sel 4'0000 + end + sync init end - process $group_169 - assign \rp_INT_rabc_cr0_1 1'0 - assign \rp_INT_rabc_cr0_1 $288 + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in3_sel 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $291 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg2 - connect \S \rp_INT_rabc_cr0_1 - connect \Y $290 + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \out_sel 2'00 + end + sync init end - process $group_170 - assign \addr_en_INT_rabc_cr0_1 5'00000 - assign \addr_en_INT_rabc_cr0_1 $290 + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_in 3'000 + end sync init end - process $group_171 - assign \fus_src2_i$32 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_cr0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src2_i$32 \int_src1__data_o + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_out 3'000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $292 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [1] - connect \B \fu_enable [3] - connect \Y $292 + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \ldst_len 4'0000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $294 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $292 - connect \B \rdflag_INT_rabc_0 - connect \Y $294 + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \upd 2'00 + end + sync init end - process $group_172 - assign \pick$263 1'0 - assign \pick$263 $294 + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rc_sel 2'00 + end sync init end - process $group_173 - assign \fus_cu_rd__go_i$34 4'0000 - assign \fus_cu_rd__go_i$34 [1] \rdpick_INT_rabc_o [2] - assign \fus_cu_rd__go_i$34 [0] \rdpick_INT_rabc_o [12] - assign \fus_cu_rd__go_i$34 [2] \rdpick_FAST_fast1_o [1] - assign \fus_cu_rd__go_i$34 [3] \rdpick_FAST_fast1_o [4] + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_in 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $296 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [2] - connect \B \rdpick_INT_rabc_en_o - connect \Y $296 + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \asmcode 8'01110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \asmcode 8'01110110 + end + sync init end - process $group_174 - assign \rp_INT_rabc_trap0_2 1'0 - assign \rp_INT_rabc_trap0_2 $296 + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_a 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $298 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $299 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg2 - connect \S \rp_INT_rabc_trap0_2 - connect \Y $298 + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_out 1'0 + end + sync init end - process $group_175 - assign \addr_en_INT_rabc_trap0_2 5'00000 - assign \addr_en_INT_rabc_trap0_2 $298 + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_out 1'0 + end sync init end - process $group_176 - assign \fus_src2_i$35 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_trap0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src2_i$35 \int_src1__data_o + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \br 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $300 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$36 [1] - connect \B \fu_enable [4] - connect \Y $300 + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn_ext 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $302 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $300 - connect \B \rdflag_INT_rabc_0 - connect \Y $302 + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rsrv 1'0 + end + sync init end - process $group_177 - assign \pick$264 1'0 - assign \pick$264 $302 + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \is_32b 1'0 + end sync init end - process $group_178 - assign \fus_cu_rd__go_i$37 2'00 - assign \fus_cu_rd__go_i$37 [1] \rdpick_INT_rabc_o [3] - assign \fus_cu_rd__go_i$37 [0] \rdpick_INT_rabc_o [13] + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $304 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [3] - connect \B \rdpick_INT_rabc_en_o - connect \Y $304 + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \lk 1'0 + end + sync init end - process $group_179 - assign \rp_INT_rabc_logical0_3 1'0 - assign \rp_INT_rabc_logical0_3 $304 + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgl_pipe 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $306 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $307 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg2 - connect \S \rp_INT_rabc_logical0_3 - connect \Y $306 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub8" +module \dec_sub8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] + sync init end - process $group_180 - assign \addr_en_INT_rabc_logical0_3 5'00000 - assign \addr_en_INT_rabc_logical0_3 $306 + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \function_unit 11'00000000010 + end sync init end - process $group_181 - assign \fus_src2_i$38 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_logical0_3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src2_i$38 \int_src1__data_o + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \form 5'10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \form 5'10001 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $308 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [1] - connect \B \fu_enable [6] - connect \Y $308 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $310 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $308 - connect \B \rdflag_INT_rabc_0 - connect \Y $310 - end - process $group_182 - assign \pick$265 1'0 - assign \pick$265 $310 + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \internal_op 7'0000010 + end sync init end - process $group_183 - assign \fus_cu_rd__go_i$40 3'000 - assign \fus_cu_rd__go_i$40 [1] \rdpick_INT_rabc_o [4] - assign \fus_cu_rd__go_i$40 [0] \rdpick_INT_rabc_o [15] - assign \fus_cu_rd__go_i$40 [2] \rdpick_XER_xer_so_o [2] + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in1_sel 3'001 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $312 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [4] - connect \B \rdpick_INT_rabc_en_o - connect \Y $312 - end - process $group_184 - assign \rp_INT_rabc_div0_4 1'0 - assign \rp_INT_rabc_div0_4 $312 + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in2_sel 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in2_sel 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in2_sel 4'0000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $314 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $315 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg2 - connect \S \rp_INT_rabc_div0_4 - connect \Y $314 - end - process $group_185 - assign \addr_en_INT_rabc_div0_4 5'00000 - assign \addr_en_INT_rabc_div0_4 $314 + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \in3_sel 2'00 + end sync init end - process $group_186 - assign \fus_src2_i$41 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_div0_4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src2_i$41 \int_src1__data_o + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \out_sel 2'01 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $316 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$42 [1] - connect \B \fu_enable [7] - connect \Y $316 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $318 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $316 - connect \B \rdflag_INT_rabc_0 - connect \Y $318 - end - process $group_187 - assign \pick$266 1'0 - assign \pick$266 $318 + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cr_in 3'000 + end sync init end - process $group_188 - assign \fus_cu_rd__go_i$43 3'000 - assign \fus_cu_rd__go_i$43 [1] \rdpick_INT_rabc_o [5] - assign \fus_cu_rd__go_i$43 [0] \rdpick_INT_rabc_o [16] - assign \fus_cu_rd__go_i$43 [2] \rdpick_XER_xer_so_o [3] + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cr_out 3'001 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $320 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [5] - connect \B \rdpick_INT_rabc_en_o - connect \Y $320 - end - process $group_189 - assign \rp_INT_rabc_mul0_5 1'0 - assign \rp_INT_rabc_mul0_5 $320 + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \ldst_len 4'0000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $322 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $323 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg2 - connect \S \rp_INT_rabc_mul0_5 - connect \Y $322 - end - process $group_190 - assign \addr_en_INT_rabc_mul0_5 5'00000 - assign \addr_en_INT_rabc_mul0_5 $322 + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \upd 2'00 + end sync init end - process $group_191 - assign \fus_src2_i$44 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_mul0_5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src2_i$44 \int_src1__data_o + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \rc_sel 2'10 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $324 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$45 [1] - connect \B \fu_enable [8] - connect \Y $324 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $326 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $324 - connect \B \rdflag_INT_rabc_0 - connect \Y $326 - end - process $group_192 - assign \pick$267 1'0 - assign \pick$267 $326 + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cry_in 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cry_in 2'10 + end sync init end - process $group_193 - assign \fus_cu_rd__go_i$46 4'0000 - assign \fus_cu_rd__go_i$46 [1] \rdpick_INT_rabc_o [6] - assign \fus_cu_rd__go_i$46 [2] \rdpick_INT_rabc_o [8] - assign \fus_cu_rd__go_i$46 [0] \rdpick_INT_rabc_o [17] - assign \fus_cu_rd__go_i$46 [3] \rdpick_XER_xer_ca_o [2] + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \asmcode 8'10000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \asmcode 8'10000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \asmcode 8'10111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \asmcode 8'11000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'10111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \asmcode 8'10111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \asmcode 8'10111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \asmcode 8'10111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \asmcode 8'11000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \asmcode 8'11000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \asmcode 8'11000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \asmcode 8'11000101 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $328 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [6] - connect \B \rdpick_INT_rabc_en_o - connect \Y $328 - end - process $group_194 - assign \rp_INT_rabc_shiftrot0_6 1'0 - assign \rp_INT_rabc_shiftrot0_6 $328 + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \inv_a 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $330 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $331 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg2 - connect \S \rp_INT_rabc_shiftrot0_6 - connect \Y $330 - end - process $group_195 - assign \addr_en_INT_rabc_shiftrot0_6 5'00000 - assign \addr_en_INT_rabc_shiftrot0_6 $330 + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \inv_out 1'0 + end sync init end - process $group_196 - assign \fus_src2_i$47 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_shiftrot0_6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src2_i$47 \int_src1__data_o + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \cry_out 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $332 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$48 [1] - connect \B \fu_enable [9] - connect \Y $332 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $334 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $332 - connect \B \rdflag_INT_rabc_0 - connect \Y $334 - end - process $group_197 - assign \pick$268 1'0 - assign \pick$268 $334 + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \br 1'0 + end sync init end - process $group_198 - assign \fus_cu_rd__go_i$49 3'000 - assign \fus_cu_rd__go_i$49 [1] \rdpick_INT_rabc_o [7] - assign \fus_cu_rd__go_i$49 [2] \rdpick_INT_rabc_o [9] - assign \fus_cu_rd__go_i$49 [0] \rdpick_INT_rabc_o [18] + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgn_ext 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $336 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [7] - connect \B \rdpick_INT_rabc_en_o - connect \Y $336 - end - process $group_199 - assign \rp_INT_rabc_ldst0_7 1'0 - assign \rp_INT_rabc_ldst0_7 $336 + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \rsrv 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $338 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $339 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg2 - connect \S \rp_INT_rabc_ldst0_7 - connect \Y $338 - end - process $group_200 - assign \addr_en_INT_rabc_ldst0_7 5'00000 - assign \addr_en_INT_rabc_ldst0_7 $338 + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \is_32b 1'0 + end sync init end - process $group_201 - assign \fus_src2_i$50 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_ldst0_7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src2_i$50 \int_src1__data_o + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgn 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $340 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$45 [2] - connect \B \fu_enable [8] - connect \Y $340 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $342 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $340 - connect \B \rdflag_INT_rabc_1 - connect \Y $342 - end - process $group_202 - assign \pick$269 1'0 - assign \pick$269 $342 + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \lk 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_shiftrot0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $344 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [8] - connect \B \rdpick_INT_rabc_en_o - connect \Y $344 - end - process $group_203 - assign \rp_INT_rabc_shiftrot0_8 1'0 - assign \rp_INT_rabc_shiftrot0_8 $344 + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00011 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10011 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00110 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10110 + assign \sgl_pipe 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_shiftrot0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $346 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $347 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg3 - connect \S \rp_INT_rabc_shiftrot0_8 - connect \Y $346 - end - process $group_204 - assign \addr_en_INT_rabc_shiftrot0_8 5'00000 - assign \addr_en_INT_rabc_shiftrot0_8 $346 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub24" +module \dec_sub24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] sync init end - process $group_205 - assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_shiftrot0_8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src3_i \int_src1__data_o + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \function_unit 11'00000001000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $348 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$48 [2] - connect \B \fu_enable [9] - connect \Y $348 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $350 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $348 - connect \B \rdflag_INT_rabc_1 - connect \Y $350 - end - process $group_206 - assign \pick$270 1'0 - assign \pick$270 $350 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_ldst0_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $352 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [9] - connect \B \rdpick_INT_rabc_en_o - connect \Y $352 - end - process $group_207 - assign \rp_INT_rabc_ldst0_9 1'0 - assign \rp_INT_rabc_ldst0_9 $352 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_ldst0_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $354 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $355 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg3 - connect \S \rp_INT_rabc_ldst0_9 - connect \Y $354 - end - process $group_208 - assign \addr_en_INT_rabc_ldst0_9 5'00000 - assign \addr_en_INT_rabc_ldst0_9 $354 - sync init - end - process $group_209 - assign \fus_src3_i$51 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_ldst0_9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src3_i$51 \int_src1__data_o + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \form 5'01000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $356 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [0] - connect \B \fu_enable [0] - connect \Y $356 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $358 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $356 - connect \B \rdflag_INT_rabc_2 - connect \Y $358 - end - process $group_210 - assign \pick$271 1'0 - assign \pick$271 $358 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_alu0_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $360 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [10] - connect \B \rdpick_INT_rabc_en_o - connect \Y $360 - end - process $group_211 - assign \rp_INT_rabc_alu0_10 1'0 - assign \rp_INT_rabc_alu0_10 $360 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_alu0_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $362 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $363 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg1 - connect \S \rp_INT_rabc_alu0_10 - connect \Y $362 - end - process $group_212 - assign \addr_en_INT_rabc_alu0_10 5'00000 - assign \addr_en_INT_rabc_alu0_10 $362 - sync init - end - process $group_213 - assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_alu0_10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src1_i \int_src1__data_o + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \internal_op 7'0111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \internal_op 7'0111101 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $364 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [0] - connect \B \fu_enable [1] - connect \Y $364 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $366 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $364 - connect \B \rdflag_INT_rabc_2 - connect \Y $366 - end - process $group_214 - assign \pick$272 1'0 - assign \pick$272 $366 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_cr0_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $368 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [11] - connect \B \rdpick_INT_rabc_en_o - connect \Y $368 - end - process $group_215 - assign \rp_INT_rabc_cr0_11 1'0 - assign \rp_INT_rabc_cr0_11 $368 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_cr0_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $370 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $371 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg1 - connect \S \rp_INT_rabc_cr0_11 - connect \Y $370 - end - process $group_216 - assign \addr_en_INT_rabc_cr0_11 5'00000 - assign \addr_en_INT_rabc_cr0_11 $370 - sync init - end - process $group_217 - assign \fus_src1_i$52 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_cr0_11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src1_i$52 \int_src1__data_o + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in1_sel 3'000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $372 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [0] - connect \B \fu_enable [3] - connect \Y $372 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $374 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $372 - connect \B \rdflag_INT_rabc_2 - connect \Y $374 - end - process $group_218 - assign \pick$273 1'0 - assign \pick$273 $374 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_trap0_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [12] - connect \B \rdpick_INT_rabc_en_o - connect \Y $376 - end - process $group_219 - assign \rp_INT_rabc_trap0_12 1'0 - assign \rp_INT_rabc_trap0_12 $376 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_trap0_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $378 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $379 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg1 - connect \S \rp_INT_rabc_trap0_12 - connect \Y $378 - end - process $group_220 - assign \addr_en_INT_rabc_trap0_12 5'00000 - assign \addr_en_INT_rabc_trap0_12 $378 - sync init - end - process $group_221 - assign \fus_src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_trap0_12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src1_i$53 \int_src1__data_o + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in2_sel 4'1011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in2_sel 4'0001 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $380 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$36 [0] - connect \B \fu_enable [4] - connect \Y $380 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $382 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $380 - connect \B \rdflag_INT_rabc_2 - connect \Y $382 - end - process $group_222 - assign \pick$274 1'0 - assign \pick$274 $382 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_logical0_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $384 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [13] - connect \B \rdpick_INT_rabc_en_o - connect \Y $384 - end - process $group_223 - assign \rp_INT_rabc_logical0_13 1'0 - assign \rp_INT_rabc_logical0_13 $384 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_logical0_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $386 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $387 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg1 - connect \S \rp_INT_rabc_logical0_13 - connect \Y $386 - end - process $group_224 - assign \addr_en_INT_rabc_logical0_13 5'00000 - assign \addr_en_INT_rabc_logical0_13 $386 + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \in3_sel 2'01 + end sync init end - process $group_225 - assign \fus_src1_i$54 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_logical0_13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src1_i$54 \int_src1__data_o + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \out_sel 2'10 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $388 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$55 [0] - connect \B \fu_enable [5] - connect \Y $388 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $390 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $388 - connect \B \rdflag_INT_rabc_2 - connect \Y $390 - end - process $group_226 - assign \pick$275 1'0 - assign \pick$275 $390 + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_in 3'000 + end sync init end - process $group_227 - assign \fus_cu_rd__go_i$56 6'000000 - assign \fus_cu_rd__go_i$56 [0] \rdpick_INT_rabc_o [14] - assign \fus_cu_rd__go_i$56 [3] \rdpick_XER_xer_so_o [1] - assign \fus_cu_rd__go_i$56 [5] \rdpick_XER_xer_ca_o [1] - assign \fus_cu_rd__go_i$56 [4] \rdpick_XER_xer_ov_o - assign \fus_cu_rd__go_i$56 [2] \rdpick_FAST_fast1_o [2] - assign \fus_cu_rd__go_i$56 [1] \rdpick_SPR_spr1_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_spr0_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $392 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [14] - connect \B \rdpick_INT_rabc_en_o - connect \Y $392 - end - process $group_228 - assign \rp_INT_rabc_spr0_14 1'0 - assign \rp_INT_rabc_spr0_14 $392 + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cr_out 3'001 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_spr0_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $394 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $395 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg1 - connect \S \rp_INT_rabc_spr0_14 - connect \Y $394 - end - process $group_229 - assign \addr_en_INT_rabc_spr0_14 5'00000 - assign \addr_en_INT_rabc_spr0_14 $394 + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \ldst_len 4'0000 + end sync init end - process $group_230 - assign \fus_src1_i$57 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_spr0_14 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src1_i$57 \int_src1__data_o + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \upd 2'00 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $396 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [0] - connect \B \fu_enable [6] - connect \Y $396 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $398 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $396 - connect \B \rdflag_INT_rabc_2 - connect \Y $398 - end - process $group_231 - assign \pick$276 1'0 - assign \pick$276 $398 + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rc_sel 2'10 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_div0_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $400 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [15] - connect \B \rdpick_INT_rabc_en_o - connect \Y $400 - end - process $group_232 - assign \rp_INT_rabc_div0_15 1'0 - assign \rp_INT_rabc_div0_15 $400 + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_in 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_div0_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $402 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $403 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg1 - connect \S \rp_INT_rabc_div0_15 - connect \Y $402 - end - process $group_233 - assign \addr_en_INT_rabc_div0_15 5'00000 - assign \addr_en_INT_rabc_div0_15 $402 + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'10011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \asmcode 8'10100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \asmcode 8'10100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \asmcode 8'10100011 + end sync init end - process $group_234 - assign \fus_src1_i$58 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_div0_15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src1_i$58 \int_src1__data_o + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_a 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $404 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$42 [0] - connect \B \fu_enable [7] - connect \Y $404 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $406 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $404 - connect \B \rdflag_INT_rabc_2 - connect \Y $406 - end - process $group_235 - assign \pick$277 1'0 - assign \pick$277 $406 + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \inv_out 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_mul0_16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $408 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [16] - connect \B \rdpick_INT_rabc_en_o - connect \Y $408 - end - process $group_236 - assign \rp_INT_rabc_mul0_16 1'0 - assign \rp_INT_rabc_mul0_16 $408 + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \cry_out 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_mul0_16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $410 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $411 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg1 - connect \S \rp_INT_rabc_mul0_16 - connect \Y $410 - end - process $group_237 - assign \addr_en_INT_rabc_mul0_16 5'00000 - assign \addr_en_INT_rabc_mul0_16 $410 + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \br 1'0 + end sync init end - process $group_238 - assign \fus_src1_i$59 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_mul0_16 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src1_i$59 \int_src1__data_o + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn_ext 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $412 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$45 [0] - connect \B \fu_enable [8] - connect \Y $412 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $414 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $412 - connect \B \rdflag_INT_rabc_2 - connect \Y $414 - end - process $group_239 - assign \pick$278 1'0 - assign \pick$278 $414 + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \rsrv 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_shiftrot0_17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $416 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [17] - connect \B \rdpick_INT_rabc_en_o - connect \Y $416 - end - process $group_240 - assign \rp_INT_rabc_shiftrot0_17 1'0 - assign \rp_INT_rabc_shiftrot0_17 $416 + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \is_32b 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_shiftrot0_17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $418 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $419 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg1 - connect \S \rp_INT_rabc_shiftrot0_17 - connect \Y $418 - end - process $group_241 - assign \addr_en_INT_rabc_shiftrot0_17 5'00000 - assign \addr_en_INT_rabc_shiftrot0_17 $418 + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgn 1'0 + end sync init end - process $group_242 - assign \fus_src1_i$60 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_shiftrot0_17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src1_i$60 \int_src1__data_o + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \lk 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $420 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$48 [0] - connect \B \fu_enable [9] - connect \Y $420 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $422 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $420 - connect \B \rdflag_INT_rabc_2 - connect \Y $422 - end - process $group_243 - assign \pick$279 1'0 - assign \pick$279 $422 + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'11001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'10000 + assign \sgl_pipe 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_INT_rabc_ldst0_18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $424 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rabc_o [18] - connect \B \rdpick_INT_rabc_en_o - connect \Y $424 - end - process $group_244 - assign \rp_INT_rabc_ldst0_18 1'0 - assign \rp_INT_rabc_ldst0_18 $424 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub4" +module \dec_sub4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 5 \opcode_switch + process $group_0 + assign \opcode_switch 5'00000 + assign \opcode_switch \opcode_in [10:6] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 5 \addr_en_INT_rabc_ldst0_18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 5 $426 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $427 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_reg1 - connect \S \rp_INT_rabc_ldst0_18 - connect \Y $426 - end - process $group_245 - assign \addr_en_INT_rabc_ldst0_18 5'00000 - assign \addr_en_INT_rabc_ldst0_18 $426 + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \function_unit 11'00010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \function_unit 11'00010000000 + end sync init end - process $group_246 - assign \fus_src1_i$61 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_INT_rabc_ldst0_18 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src1_i$61 \int_src1__data_o + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \form 5'01000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \form 5'01000 end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $428 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_alu0_0 - connect \B \addr_en_INT_rabc_cr0_1 - connect \Y $428 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $430 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_trap0_2 - connect \B \addr_en_INT_rabc_logical0_3 - connect \Y $430 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $432 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $428 - connect \B $430 - connect \Y $432 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $434 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_div0_4 - connect \B \addr_en_INT_rabc_mul0_5 - connect \Y $434 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $436 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_ldst0_7 - connect \B \addr_en_INT_rabc_shiftrot0_8 - connect \Y $436 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $438 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_shiftrot0_6 - connect \B $436 - connect \Y $438 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $440 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $434 - connect \B $438 - connect \Y $440 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $442 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $432 - connect \B $440 - connect \Y $442 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $444 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_ldst0_9 - connect \B \addr_en_INT_rabc_alu0_10 - connect \Y $444 + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \internal_op 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \internal_op 7'0111111 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $446 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_trap0_12 - connect \B \addr_en_INT_rabc_logical0_13 - connect \Y $446 + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in1_sel 3'001 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $448 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_cr0_11 - connect \B $446 - connect \Y $448 + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in2_sel 4'0001 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $450 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $444 - connect \B $448 - connect \Y $450 + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \in3_sel 2'00 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $452 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_spr0_14 - connect \B \addr_en_INT_rabc_div0_15 - connect \Y $452 + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \out_sel 2'00 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $454 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_shiftrot0_17 - connect \B \addr_en_INT_rabc_ldst0_18 - connect \Y $454 + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_in 3'000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $456 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rabc_mul0_16 - connect \B $454 - connect \Y $456 + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cr_out 3'000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $458 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $452 - connect \B $456 - connect \Y $458 + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \ldst_len 4'0000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $460 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $450 - connect \B $458 - connect \Y $460 + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \upd 2'00 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $462 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $442 - connect \B $460 - connect \Y $462 + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rc_sel 2'00 + end + sync init end - process $group_247 - assign \int_src1__addr 5'00000 - assign \int_src1__addr $462 + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_in 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" - wire width 1 $464 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" - cell $reduce_bool $465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 19 - parameter \Y_WIDTH 1 - connect \A { \rp_INT_rabc_ldst0_18 \rp_INT_rabc_shiftrot0_17 \rp_INT_rabc_mul0_16 \rp_INT_rabc_div0_15 \rp_INT_rabc_spr0_14 \rp_INT_rabc_logical0_13 \rp_INT_rabc_trap0_12 \rp_INT_rabc_cr0_11 \rp_INT_rabc_alu0_10 \rp_INT_rabc_ldst0_9 \rp_INT_rabc_shiftrot0_8 \rp_INT_rabc_ldst0_7 \rp_INT_rabc_shiftrot0_6 \rp_INT_rabc_mul0_5 \rp_INT_rabc_div0_4 \rp_INT_rabc_logical0_3 \rp_INT_rabc_trap0_2 \rp_INT_rabc_cr0_1 \rp_INT_rabc_alu0_0 } - connect \Y $464 + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \asmcode 8'11000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \asmcode 8'11001001 + end + sync init end - process $group_248 - assign \int_src1__ren 1'0 - assign \int_src1__ren $464 + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_a 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_XER_xer_so_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $and $467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pdecode2_oe - connect \B \pdecode2_oe_ok - connect \Y $466 + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \inv_out 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - wire width 1 $468 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79" - cell $or $469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $466 - connect \B \pdecode2_xer_in - connect \Y $468 + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \cry_out 1'0 + end + sync init end - process $group_249 - assign \rdflag_XER_xer_so_0 1'0 - assign \rdflag_XER_xer_so_0 $468 + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \br 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$470 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $471 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [2] - connect \B \fu_enable [0] - connect \Y $471 + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn_ext 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $473 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $471 - connect \B \rdflag_XER_xer_so_0 - connect \Y $473 + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \rsrv 1'0 + end + sync init end - process $group_250 - assign \pick$470 1'0 - assign \pick$470 $473 + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \is_32b 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$475 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$476 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$477 - process $group_251 - assign \rdpick_XER_xer_so_i 4'0000 - assign \rdpick_XER_xer_so_i [0] \pick$470 - assign \rdpick_XER_xer_so_i [1] \pick$475 - assign \rdpick_XER_xer_so_i [2] \pick$476 - assign \rdpick_XER_xer_so_i [3] \pick$477 + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgn 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $478 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [0] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $478 + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \lk 1'0 + end + sync init end - process $group_252 - assign \rp_XER_xer_so_alu0_0 1'0 - assign \rp_XER_xer_so_alu0_0 $478 + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 5'00000 + assign \sgl_pipe 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 \addr_en_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 $480 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $481 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_alu0_0 - connect \Y $480 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31" +module \dec31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub10_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub10_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub10_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub10_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub10_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub10_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub10_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub10_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub10_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub10_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub10_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub10_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub10_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub10_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub10_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub10_asmcode + cell \dec_sub10 \dec_sub10 + connect \opcode_in \dec_sub10_opcode_in + connect \function_unit \dec_sub10_function_unit + connect \form \dec_sub10_form + connect \internal_op \dec_sub10_internal_op + connect \in1_sel \dec_sub10_in1_sel + connect \in2_sel \dec_sub10_in2_sel + connect \in3_sel \dec_sub10_in3_sel + connect \out_sel \dec_sub10_out_sel + connect \cr_in \dec_sub10_cr_in + connect \cr_out \dec_sub10_cr_out + connect \rc_sel \dec_sub10_rc_sel + connect \ldst_len \dec_sub10_ldst_len + connect \upd \dec_sub10_upd + connect \cry_in \dec_sub10_cry_in + connect \inv_a \dec_sub10_inv_a + connect \inv_out \dec_sub10_inv_out + connect \cry_out \dec_sub10_cry_out + connect \br \dec_sub10_br + connect \sgn_ext \dec_sub10_sgn_ext + connect \rsrv \dec_sub10_rsrv + connect \is_32b \dec_sub10_is_32b + connect \sgn \dec_sub10_sgn + connect \lk \dec_sub10_lk + connect \sgl_pipe \dec_sub10_sgl_pipe + connect \asmcode \dec_sub10_asmcode + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub28_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub28_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub28_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub28_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub28_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub28_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub28_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub28_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub28_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub28_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub28_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub28_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub28_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub28_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub28_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub28_asmcode + cell \dec_sub28 \dec_sub28 + connect \opcode_in \dec_sub28_opcode_in + connect \function_unit \dec_sub28_function_unit + connect \form \dec_sub28_form + connect \internal_op \dec_sub28_internal_op + connect \in1_sel \dec_sub28_in1_sel + connect \in2_sel \dec_sub28_in2_sel + connect \in3_sel \dec_sub28_in3_sel + connect \out_sel \dec_sub28_out_sel + connect \cr_in \dec_sub28_cr_in + connect \cr_out \dec_sub28_cr_out + connect \rc_sel \dec_sub28_rc_sel + connect \ldst_len \dec_sub28_ldst_len + connect \upd \dec_sub28_upd + connect \cry_in \dec_sub28_cry_in + connect \inv_a \dec_sub28_inv_a + connect \inv_out \dec_sub28_inv_out + connect \cry_out \dec_sub28_cry_out + connect \br \dec_sub28_br + connect \sgn_ext \dec_sub28_sgn_ext + connect \rsrv \dec_sub28_rsrv + connect \is_32b \dec_sub28_is_32b + connect \sgn \dec_sub28_sgn + connect \lk \dec_sub28_lk + connect \sgl_pipe \dec_sub28_sgl_pipe + connect \asmcode \dec_sub28_asmcode end - process $group_253 - assign \addr_en_XER_xer_so_alu0_0 1'0 - assign \addr_en_XER_xer_so_alu0_0 $480 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub0_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub0_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub0_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub0_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub0_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub0_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub0_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub0_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub0_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub0_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub0_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub0_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub0_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub0_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub0_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub0_asmcode + cell \dec_sub0 \dec_sub0 + connect \opcode_in \dec_sub0_opcode_in + connect \function_unit \dec_sub0_function_unit + connect \form \dec_sub0_form + connect \internal_op \dec_sub0_internal_op + connect \in1_sel \dec_sub0_in1_sel + connect \in2_sel \dec_sub0_in2_sel + connect \in3_sel \dec_sub0_in3_sel + connect \out_sel \dec_sub0_out_sel + connect \cr_in \dec_sub0_cr_in + connect \cr_out \dec_sub0_cr_out + connect \rc_sel \dec_sub0_rc_sel + connect \ldst_len \dec_sub0_ldst_len + connect \upd \dec_sub0_upd + connect \cry_in \dec_sub0_cry_in + connect \inv_a \dec_sub0_inv_a + connect \inv_out \dec_sub0_inv_out + connect \cry_out \dec_sub0_cry_out + connect \br \dec_sub0_br + connect \sgn_ext \dec_sub0_sgn_ext + connect \rsrv \dec_sub0_rsrv + connect \is_32b \dec_sub0_is_32b + connect \sgn \dec_sub0_sgn + connect \lk \dec_sub0_lk + connect \sgl_pipe \dec_sub0_sgl_pipe + connect \asmcode \dec_sub0_asmcode end - process $group_254 - assign \fus_src3_i$62 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_XER_xer_so_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src3_i$62 \xer_src1__data_o [0] - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub26_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub26_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub26_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub26_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub26_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub26_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub26_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub26_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub26_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub26_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub26_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub26_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub26_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub26_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub26_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub26_asmcode + cell \dec_sub26 \dec_sub26 + connect \opcode_in \dec_sub26_opcode_in + connect \function_unit \dec_sub26_function_unit + connect \form \dec_sub26_form + connect \internal_op \dec_sub26_internal_op + connect \in1_sel \dec_sub26_in1_sel + connect \in2_sel \dec_sub26_in2_sel + connect \in3_sel \dec_sub26_in3_sel + connect \out_sel \dec_sub26_out_sel + connect \cr_in \dec_sub26_cr_in + connect \cr_out \dec_sub26_cr_out + connect \rc_sel \dec_sub26_rc_sel + connect \ldst_len \dec_sub26_ldst_len + connect \upd \dec_sub26_upd + connect \cry_in \dec_sub26_cry_in + connect \inv_a \dec_sub26_inv_a + connect \inv_out \dec_sub26_inv_out + connect \cry_out \dec_sub26_cry_out + connect \br \dec_sub26_br + connect \sgn_ext \dec_sub26_sgn_ext + connect \rsrv \dec_sub26_rsrv + connect \is_32b \dec_sub26_is_32b + connect \sgn \dec_sub26_sgn + connect \lk \dec_sub26_lk + connect \sgl_pipe \dec_sub26_sgl_pipe + connect \asmcode \dec_sub26_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $482 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$55 [3] - connect \B \fu_enable [5] - connect \Y $482 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub19_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub19_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub19_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub19_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub19_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub19_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub19_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub19_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub19_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub19_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub19_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub19_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub19_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub19_asmcode + cell \dec_sub19 \dec_sub19 + connect \opcode_in \dec_sub19_opcode_in + connect \function_unit \dec_sub19_function_unit + connect \form \dec_sub19_form + connect \internal_op \dec_sub19_internal_op + connect \in1_sel \dec_sub19_in1_sel + connect \in2_sel \dec_sub19_in2_sel + connect \in3_sel \dec_sub19_in3_sel + connect \out_sel \dec_sub19_out_sel + connect \cr_in \dec_sub19_cr_in + connect \cr_out \dec_sub19_cr_out + connect \rc_sel \dec_sub19_rc_sel + connect \ldst_len \dec_sub19_ldst_len + connect \upd \dec_sub19_upd + connect \cry_in \dec_sub19_cry_in + connect \inv_a \dec_sub19_inv_a + connect \inv_out \dec_sub19_inv_out + connect \cry_out \dec_sub19_cry_out + connect \br \dec_sub19_br + connect \sgn_ext \dec_sub19_sgn_ext + connect \rsrv \dec_sub19_rsrv + connect \is_32b \dec_sub19_is_32b + connect \sgn \dec_sub19_sgn + connect \lk \dec_sub19_lk + connect \sgl_pipe \dec_sub19_sgl_pipe + connect \asmcode \dec_sub19_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $484 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $482 - connect \B \rdflag_XER_xer_so_0 - connect \Y $484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub22_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub22_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub22_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub22_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub22_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub22_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub22_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub22_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub22_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub22_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub22_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub22_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub22_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub22_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub22_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub22_asmcode + cell \dec_sub22 \dec_sub22 + connect \opcode_in \dec_sub22_opcode_in + connect \function_unit \dec_sub22_function_unit + connect \form \dec_sub22_form + connect \internal_op \dec_sub22_internal_op + connect \in1_sel \dec_sub22_in1_sel + connect \in2_sel \dec_sub22_in2_sel + connect \in3_sel \dec_sub22_in3_sel + connect \out_sel \dec_sub22_out_sel + connect \cr_in \dec_sub22_cr_in + connect \cr_out \dec_sub22_cr_out + connect \rc_sel \dec_sub22_rc_sel + connect \ldst_len \dec_sub22_ldst_len + connect \upd \dec_sub22_upd + connect \cry_in \dec_sub22_cry_in + connect \inv_a \dec_sub22_inv_a + connect \inv_out \dec_sub22_inv_out + connect \cry_out \dec_sub22_cry_out + connect \br \dec_sub22_br + connect \sgn_ext \dec_sub22_sgn_ext + connect \rsrv \dec_sub22_rsrv + connect \is_32b \dec_sub22_is_32b + connect \sgn \dec_sub22_sgn + connect \lk \dec_sub22_lk + connect \sgl_pipe \dec_sub22_sgl_pipe + connect \asmcode \dec_sub22_asmcode end - process $group_255 - assign \pick$475 1'0 - assign \pick$475 $484 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub9_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub9_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub9_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub9_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub9_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub9_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub9_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub9_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub9_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub9_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub9_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub9_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub9_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub9_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub9_asmcode + cell \dec_sub9 \dec_sub9 + connect \opcode_in \dec_sub9_opcode_in + connect \function_unit \dec_sub9_function_unit + connect \form \dec_sub9_form + connect \internal_op \dec_sub9_internal_op + connect \in1_sel \dec_sub9_in1_sel + connect \in2_sel \dec_sub9_in2_sel + connect \in3_sel \dec_sub9_in3_sel + connect \out_sel \dec_sub9_out_sel + connect \cr_in \dec_sub9_cr_in + connect \cr_out \dec_sub9_cr_out + connect \rc_sel \dec_sub9_rc_sel + connect \ldst_len \dec_sub9_ldst_len + connect \upd \dec_sub9_upd + connect \cry_in \dec_sub9_cry_in + connect \inv_a \dec_sub9_inv_a + connect \inv_out \dec_sub9_inv_out + connect \cry_out \dec_sub9_cry_out + connect \br \dec_sub9_br + connect \sgn_ext \dec_sub9_sgn_ext + connect \rsrv \dec_sub9_rsrv + connect \is_32b \dec_sub9_is_32b + connect \sgn \dec_sub9_sgn + connect \lk \dec_sub9_lk + connect \sgl_pipe \dec_sub9_sgl_pipe + connect \asmcode \dec_sub9_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_XER_xer_so_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $486 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [1] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $486 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub11_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub11_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub11_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub11_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub11_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub11_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub11_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub11_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub11_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub11_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub11_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub11_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub11_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub11_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub11_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub11_asmcode + cell \dec_sub11 \dec_sub11 + connect \opcode_in \dec_sub11_opcode_in + connect \function_unit \dec_sub11_function_unit + connect \form \dec_sub11_form + connect \internal_op \dec_sub11_internal_op + connect \in1_sel \dec_sub11_in1_sel + connect \in2_sel \dec_sub11_in2_sel + connect \in3_sel \dec_sub11_in3_sel + connect \out_sel \dec_sub11_out_sel + connect \cr_in \dec_sub11_cr_in + connect \cr_out \dec_sub11_cr_out + connect \rc_sel \dec_sub11_rc_sel + connect \ldst_len \dec_sub11_ldst_len + connect \upd \dec_sub11_upd + connect \cry_in \dec_sub11_cry_in + connect \inv_a \dec_sub11_inv_a + connect \inv_out \dec_sub11_inv_out + connect \cry_out \dec_sub11_cry_out + connect \br \dec_sub11_br + connect \sgn_ext \dec_sub11_sgn_ext + connect \rsrv \dec_sub11_rsrv + connect \is_32b \dec_sub11_is_32b + connect \sgn \dec_sub11_sgn + connect \lk \dec_sub11_lk + connect \sgl_pipe \dec_sub11_sgl_pipe + connect \asmcode \dec_sub11_asmcode end - process $group_256 - assign \rp_XER_xer_so_spr0_1 1'0 - assign \rp_XER_xer_so_spr0_1 $486 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub27_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub27_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub27_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub27_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub27_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub27_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub27_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub27_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub27_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub27_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub27_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub27_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub27_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub27_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub27_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub27_asmcode + cell \dec_sub27 \dec_sub27 + connect \opcode_in \dec_sub27_opcode_in + connect \function_unit \dec_sub27_function_unit + connect \form \dec_sub27_form + connect \internal_op \dec_sub27_internal_op + connect \in1_sel \dec_sub27_in1_sel + connect \in2_sel \dec_sub27_in2_sel + connect \in3_sel \dec_sub27_in3_sel + connect \out_sel \dec_sub27_out_sel + connect \cr_in \dec_sub27_cr_in + connect \cr_out \dec_sub27_cr_out + connect \rc_sel \dec_sub27_rc_sel + connect \ldst_len \dec_sub27_ldst_len + connect \upd \dec_sub27_upd + connect \cry_in \dec_sub27_cry_in + connect \inv_a \dec_sub27_inv_a + connect \inv_out \dec_sub27_inv_out + connect \cry_out \dec_sub27_cry_out + connect \br \dec_sub27_br + connect \sgn_ext \dec_sub27_sgn_ext + connect \rsrv \dec_sub27_rsrv + connect \is_32b \dec_sub27_is_32b + connect \sgn \dec_sub27_sgn + connect \lk \dec_sub27_lk + connect \sgl_pipe \dec_sub27_sgl_pipe + connect \asmcode \dec_sub27_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 \addr_en_XER_xer_so_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 $488 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $489 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_spr0_1 - connect \Y $488 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub15_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub15_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub15_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub15_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub15_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub15_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub15_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub15_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub15_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub15_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub15_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub15_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub15_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub15_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub15_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub15_asmcode + cell \dec_sub15 \dec_sub15 + connect \opcode_in \dec_sub15_opcode_in + connect \function_unit \dec_sub15_function_unit + connect \form \dec_sub15_form + connect \internal_op \dec_sub15_internal_op + connect \in1_sel \dec_sub15_in1_sel + connect \in2_sel \dec_sub15_in2_sel + connect \in3_sel \dec_sub15_in3_sel + connect \out_sel \dec_sub15_out_sel + connect \cr_in \dec_sub15_cr_in + connect \cr_out \dec_sub15_cr_out + connect \rc_sel \dec_sub15_rc_sel + connect \ldst_len \dec_sub15_ldst_len + connect \upd \dec_sub15_upd + connect \cry_in \dec_sub15_cry_in + connect \inv_a \dec_sub15_inv_a + connect \inv_out \dec_sub15_inv_out + connect \cry_out \dec_sub15_cry_out + connect \br \dec_sub15_br + connect \sgn_ext \dec_sub15_sgn_ext + connect \rsrv \dec_sub15_rsrv + connect \is_32b \dec_sub15_is_32b + connect \sgn \dec_sub15_sgn + connect \lk \dec_sub15_lk + connect \sgl_pipe \dec_sub15_sgl_pipe + connect \asmcode \dec_sub15_asmcode end - process $group_257 - assign \addr_en_XER_xer_so_spr0_1 1'0 - assign \addr_en_XER_xer_so_spr0_1 $488 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub20_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub20_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub20_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub20_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub20_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub20_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub20_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub20_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub20_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub20_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub20_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub20_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub20_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub20_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub20_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub20_asmcode + cell \dec_sub20 \dec_sub20 + connect \opcode_in \dec_sub20_opcode_in + connect \function_unit \dec_sub20_function_unit + connect \form \dec_sub20_form + connect \internal_op \dec_sub20_internal_op + connect \in1_sel \dec_sub20_in1_sel + connect \in2_sel \dec_sub20_in2_sel + connect \in3_sel \dec_sub20_in3_sel + connect \out_sel \dec_sub20_out_sel + connect \cr_in \dec_sub20_cr_in + connect \cr_out \dec_sub20_cr_out + connect \rc_sel \dec_sub20_rc_sel + connect \ldst_len \dec_sub20_ldst_len + connect \upd \dec_sub20_upd + connect \cry_in \dec_sub20_cry_in + connect \inv_a \dec_sub20_inv_a + connect \inv_out \dec_sub20_inv_out + connect \cry_out \dec_sub20_cry_out + connect \br \dec_sub20_br + connect \sgn_ext \dec_sub20_sgn_ext + connect \rsrv \dec_sub20_rsrv + connect \is_32b \dec_sub20_is_32b + connect \sgn \dec_sub20_sgn + connect \lk \dec_sub20_lk + connect \sgl_pipe \dec_sub20_sgl_pipe + connect \asmcode \dec_sub20_asmcode end - process $group_258 - assign \fus_src4_i 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_XER_xer_so_spr0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src4_i \xer_src1__data_o [0] - end - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub21_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub21_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub21_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub21_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub21_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub21_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub21_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub21_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub21_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub21_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub21_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub21_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub21_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub21_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub21_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub21_asmcode + cell \dec_sub21 \dec_sub21 + connect \opcode_in \dec_sub21_opcode_in + connect \function_unit \dec_sub21_function_unit + connect \form \dec_sub21_form + connect \internal_op \dec_sub21_internal_op + connect \in1_sel \dec_sub21_in1_sel + connect \in2_sel \dec_sub21_in2_sel + connect \in3_sel \dec_sub21_in3_sel + connect \out_sel \dec_sub21_out_sel + connect \cr_in \dec_sub21_cr_in + connect \cr_out \dec_sub21_cr_out + connect \rc_sel \dec_sub21_rc_sel + connect \ldst_len \dec_sub21_ldst_len + connect \upd \dec_sub21_upd + connect \cry_in \dec_sub21_cry_in + connect \inv_a \dec_sub21_inv_a + connect \inv_out \dec_sub21_inv_out + connect \cry_out \dec_sub21_cry_out + connect \br \dec_sub21_br + connect \sgn_ext \dec_sub21_sgn_ext + connect \rsrv \dec_sub21_rsrv + connect \is_32b \dec_sub21_is_32b + connect \sgn \dec_sub21_sgn + connect \lk \dec_sub21_lk + connect \sgl_pipe \dec_sub21_sgl_pipe + connect \asmcode \dec_sub21_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $490 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$39 [2] - connect \B \fu_enable [6] - connect \Y $490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub23_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub23_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub23_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub23_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub23_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub23_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub23_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub23_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub23_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub23_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub23_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub23_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub23_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub23_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub23_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub23_asmcode + cell \dec_sub23 \dec_sub23 + connect \opcode_in \dec_sub23_opcode_in + connect \function_unit \dec_sub23_function_unit + connect \form \dec_sub23_form + connect \internal_op \dec_sub23_internal_op + connect \in1_sel \dec_sub23_in1_sel + connect \in2_sel \dec_sub23_in2_sel + connect \in3_sel \dec_sub23_in3_sel + connect \out_sel \dec_sub23_out_sel + connect \cr_in \dec_sub23_cr_in + connect \cr_out \dec_sub23_cr_out + connect \rc_sel \dec_sub23_rc_sel + connect \ldst_len \dec_sub23_ldst_len + connect \upd \dec_sub23_upd + connect \cry_in \dec_sub23_cry_in + connect \inv_a \dec_sub23_inv_a + connect \inv_out \dec_sub23_inv_out + connect \cry_out \dec_sub23_cry_out + connect \br \dec_sub23_br + connect \sgn_ext \dec_sub23_sgn_ext + connect \rsrv \dec_sub23_rsrv + connect \is_32b \dec_sub23_is_32b + connect \sgn \dec_sub23_sgn + connect \lk \dec_sub23_lk + connect \sgl_pipe \dec_sub23_sgl_pipe + connect \asmcode \dec_sub23_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $492 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $490 - connect \B \rdflag_XER_xer_so_0 - connect \Y $492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub16_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub16_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub16_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub16_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub16_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub16_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub16_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub16_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub16_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub16_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub16_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub16_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub16_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub16_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub16_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub16_asmcode + cell \dec_sub16 \dec_sub16 + connect \opcode_in \dec_sub16_opcode_in + connect \function_unit \dec_sub16_function_unit + connect \form \dec_sub16_form + connect \internal_op \dec_sub16_internal_op + connect \in1_sel \dec_sub16_in1_sel + connect \in2_sel \dec_sub16_in2_sel + connect \in3_sel \dec_sub16_in3_sel + connect \out_sel \dec_sub16_out_sel + connect \cr_in \dec_sub16_cr_in + connect \cr_out \dec_sub16_cr_out + connect \rc_sel \dec_sub16_rc_sel + connect \ldst_len \dec_sub16_ldst_len + connect \upd \dec_sub16_upd + connect \cry_in \dec_sub16_cry_in + connect \inv_a \dec_sub16_inv_a + connect \inv_out \dec_sub16_inv_out + connect \cry_out \dec_sub16_cry_out + connect \br \dec_sub16_br + connect \sgn_ext \dec_sub16_sgn_ext + connect \rsrv \dec_sub16_rsrv + connect \is_32b \dec_sub16_is_32b + connect \sgn \dec_sub16_sgn + connect \lk \dec_sub16_lk + connect \sgl_pipe \dec_sub16_sgl_pipe + connect \asmcode \dec_sub16_asmcode end - process $group_259 - assign \pick$476 1'0 - assign \pick$476 $492 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub18_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub18_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub18_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub18_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub18_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub18_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub18_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub18_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub18_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub18_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub18_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub18_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub18_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub18_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub18_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub18_asmcode + cell \dec_sub18 \dec_sub18 + connect \opcode_in \dec_sub18_opcode_in + connect \function_unit \dec_sub18_function_unit + connect \form \dec_sub18_form + connect \internal_op \dec_sub18_internal_op + connect \in1_sel \dec_sub18_in1_sel + connect \in2_sel \dec_sub18_in2_sel + connect \in3_sel \dec_sub18_in3_sel + connect \out_sel \dec_sub18_out_sel + connect \cr_in \dec_sub18_cr_in + connect \cr_out \dec_sub18_cr_out + connect \rc_sel \dec_sub18_rc_sel + connect \ldst_len \dec_sub18_ldst_len + connect \upd \dec_sub18_upd + connect \cry_in \dec_sub18_cry_in + connect \inv_a \dec_sub18_inv_a + connect \inv_out \dec_sub18_inv_out + connect \cry_out \dec_sub18_cry_out + connect \br \dec_sub18_br + connect \sgn_ext \dec_sub18_sgn_ext + connect \rsrv \dec_sub18_rsrv + connect \is_32b \dec_sub18_is_32b + connect \sgn \dec_sub18_sgn + connect \lk \dec_sub18_lk + connect \sgl_pipe \dec_sub18_sgl_pipe + connect \asmcode \dec_sub18_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_XER_xer_so_div0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $494 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [2] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub8_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub8_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub8_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub8_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub8_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub8_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub8_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub8_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub8_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub8_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub8_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub8_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub8_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub8_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub8_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub8_asmcode + cell \dec_sub8 \dec_sub8 + connect \opcode_in \dec_sub8_opcode_in + connect \function_unit \dec_sub8_function_unit + connect \form \dec_sub8_form + connect \internal_op \dec_sub8_internal_op + connect \in1_sel \dec_sub8_in1_sel + connect \in2_sel \dec_sub8_in2_sel + connect \in3_sel \dec_sub8_in3_sel + connect \out_sel \dec_sub8_out_sel + connect \cr_in \dec_sub8_cr_in + connect \cr_out \dec_sub8_cr_out + connect \rc_sel \dec_sub8_rc_sel + connect \ldst_len \dec_sub8_ldst_len + connect \upd \dec_sub8_upd + connect \cry_in \dec_sub8_cry_in + connect \inv_a \dec_sub8_inv_a + connect \inv_out \dec_sub8_inv_out + connect \cry_out \dec_sub8_cry_out + connect \br \dec_sub8_br + connect \sgn_ext \dec_sub8_sgn_ext + connect \rsrv \dec_sub8_rsrv + connect \is_32b \dec_sub8_is_32b + connect \sgn \dec_sub8_sgn + connect \lk \dec_sub8_lk + connect \sgl_pipe \dec_sub8_sgl_pipe + connect \asmcode \dec_sub8_asmcode end - process $group_260 - assign \rp_XER_xer_so_div0_2 1'0 - assign \rp_XER_xer_so_div0_2 $494 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub24_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub24_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub24_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub24_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub24_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub24_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub24_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub24_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub24_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub24_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub24_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub24_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub24_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub24_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub24_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub24_asmcode + cell \dec_sub24 \dec_sub24 + connect \opcode_in \dec_sub24_opcode_in + connect \function_unit \dec_sub24_function_unit + connect \form \dec_sub24_form + connect \internal_op \dec_sub24_internal_op + connect \in1_sel \dec_sub24_in1_sel + connect \in2_sel \dec_sub24_in2_sel + connect \in3_sel \dec_sub24_in3_sel + connect \out_sel \dec_sub24_out_sel + connect \cr_in \dec_sub24_cr_in + connect \cr_out \dec_sub24_cr_out + connect \rc_sel \dec_sub24_rc_sel + connect \ldst_len \dec_sub24_ldst_len + connect \upd \dec_sub24_upd + connect \cry_in \dec_sub24_cry_in + connect \inv_a \dec_sub24_inv_a + connect \inv_out \dec_sub24_inv_out + connect \cry_out \dec_sub24_cry_out + connect \br \dec_sub24_br + connect \sgn_ext \dec_sub24_sgn_ext + connect \rsrv \dec_sub24_rsrv + connect \is_32b \dec_sub24_is_32b + connect \sgn \dec_sub24_sgn + connect \lk \dec_sub24_lk + connect \sgl_pipe \dec_sub24_sgl_pipe + connect \asmcode \dec_sub24_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 \addr_en_XER_xer_so_div0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 $496 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $497 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_div0_2 - connect \Y $496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_sub4_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_sub4_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec_sub4_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_sub4_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_sub4_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_sub4_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_sub4_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_sub4_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_sub4_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_sub4_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub4_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub4_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub4_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub4_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub4_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec_sub4_asmcode + cell \dec_sub4 \dec_sub4 + connect \opcode_in \dec_sub4_opcode_in + connect \function_unit \dec_sub4_function_unit + connect \form \dec_sub4_form + connect \internal_op \dec_sub4_internal_op + connect \in1_sel \dec_sub4_in1_sel + connect \in2_sel \dec_sub4_in2_sel + connect \in3_sel \dec_sub4_in3_sel + connect \out_sel \dec_sub4_out_sel + connect \cr_in \dec_sub4_cr_in + connect \cr_out \dec_sub4_cr_out + connect \rc_sel \dec_sub4_rc_sel + connect \ldst_len \dec_sub4_ldst_len + connect \upd \dec_sub4_upd + connect \cry_in \dec_sub4_cry_in + connect \inv_a \dec_sub4_inv_a + connect \inv_out \dec_sub4_inv_out + connect \cry_out \dec_sub4_cry_out + connect \br \dec_sub4_br + connect \sgn_ext \dec_sub4_sgn_ext + connect \rsrv \dec_sub4_rsrv + connect \is_32b \dec_sub4_is_32b + connect \sgn \dec_sub4_sgn + connect \lk \dec_sub4_lk + connect \sgl_pipe \dec_sub4_sgl_pipe + connect \asmcode \dec_sub4_asmcode end - process $group_261 - assign \addr_en_XER_xer_so_div0_2 1'0 - assign \addr_en_XER_xer_so_div0_2 $496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 10 \opcode_switch + process $group_0 + assign \opcode_switch 10'0000000000 + assign \opcode_switch \opcode_in [10:1] sync init end - process $group_262 - assign \fus_src3_i$63 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_XER_xer_so_div0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src3_i$63 \xer_src1__data_o [0] - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:280" + wire width 5 \opc_in + process $group_1 + assign \opc_in 5'00000 + assign \opc_in \opcode_switch [4:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $498 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$42 [2] - connect \B \fu_enable [7] - connect \Y $498 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $500 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $498 - connect \B \rdflag_XER_xer_so_0 - connect \Y $500 - end - process $group_263 - assign \pick$477 1'0 - assign \pick$477 $500 + process $group_2 + assign \dec_sub10_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub10_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_XER_xer_so_mul0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $502 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [3] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $502 - end - process $group_264 - assign \rp_XER_xer_so_mul0_3 1'0 - assign \rp_XER_xer_so_mul0_3 $502 + process $group_3 + assign \dec_sub28_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub28_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 \addr_en_XER_xer_so_mul0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 $504 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $505 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_mul0_3 - connect \Y $504 - end - process $group_265 - assign \addr_en_XER_xer_so_mul0_3 1'0 - assign \addr_en_XER_xer_so_mul0_3 $504 + process $group_4 + assign \dec_sub0_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub0_opcode_in \opcode_in sync init end - process $group_266 - assign \fus_src3_i$64 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_XER_xer_so_mul0_3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src3_i$64 \xer_src1__data_o [0] - end + process $group_5 + assign \dec_sub26_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub26_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $506 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $507 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_alu0_0 - connect \B \addr_en_XER_xer_so_spr0_1 - connect \Y $507 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $509 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_div0_2 - connect \B \addr_en_XER_xer_so_mul0_3 - connect \Y $509 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $511 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $507 - connect \B $509 - connect \Y $511 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A $511 - connect \Y $506 - end - process $group_267 - assign \xer_src1__ren 3'000 - assign \xer_src1__ren $506 + process $group_6 + assign \dec_sub19_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub19_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $514 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $eq $515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \pdecode2_input_carry - connect \B 2'10 - connect \Y $514 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $516 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $or $517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $514 - connect \B \pdecode2_xer_in - connect \Y $516 - end - process $group_268 - assign \rdflag_XER_xer_ca_0 1'0 - assign \rdflag_XER_xer_ca_0 $516 + process $group_7 + assign \dec_sub22_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub22_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$518 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $519 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [3] - connect \B \fu_enable [0] - connect \Y $519 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $521 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $519 - connect \B \rdflag_XER_xer_ca_0 - connect \Y $521 - end - process $group_269 - assign \pick$518 1'0 - assign \pick$518 $521 + process $group_8 + assign \dec_sub9_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub9_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$523 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$524 - process $group_270 - assign \rdpick_XER_xer_ca_i 3'000 - assign \rdpick_XER_xer_ca_i [0] \pick$518 - assign \rdpick_XER_xer_ca_i [1] \pick$523 - assign \rdpick_XER_xer_ca_i [2] \pick$524 + process $group_9 + assign \dec_sub11_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub11_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $525 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [0] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $525 - end - process $group_271 - assign \rp_XER_xer_ca_alu0_0 1'0 - assign \rp_XER_xer_ca_alu0_0 $525 + process $group_10 + assign \dec_sub27_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub27_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 2 \addr_en_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 2 $527 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $528 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $527 - end - process $group_272 - assign \addr_en_XER_xer_ca_alu0_0 2'00 - assign \addr_en_XER_xer_ca_alu0_0 $527 + process $group_11 + assign \dec_sub15_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub15_opcode_in \opcode_in sync init end - process $group_273 - assign \fus_src4_i$65 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_XER_xer_ca_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src4_i$65 \xer_src2__data_o - end + process $group_12 + assign \dec_sub20_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub20_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $529 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$55 [5] - connect \B \fu_enable [5] - connect \Y $529 + process $group_13 + assign \dec_sub21_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub21_opcode_in \opcode_in + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $531 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $529 - connect \B \rdflag_XER_xer_ca_0 - connect \Y $531 + process $group_14 + assign \dec_sub23_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub23_opcode_in \opcode_in + sync init end - process $group_274 - assign \pick$523 1'0 - assign \pick$523 $531 + process $group_15 + assign \dec_sub16_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub16_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $533 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [1] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $533 + process $group_16 + assign \dec_sub18_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub18_opcode_in \opcode_in + sync init end - process $group_275 - assign \rp_XER_xer_ca_spr0_1 1'0 - assign \rp_XER_xer_ca_spr0_1 $533 + process $group_17 + assign \dec_sub8_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub8_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 2 \addr_en_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 2 $535 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $536 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $535 + process $group_18 + assign \dec_sub24_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub24_opcode_in \opcode_in + sync init end - process $group_276 - assign \addr_en_XER_xer_ca_spr0_1 2'00 - assign \addr_en_XER_xer_ca_spr0_1 $535 + process $group_19 + assign \dec_sub4_opcode_in 32'00000000000000000000000000000000 + assign \dec_sub4_opcode_in \opcode_in sync init end - process $group_277 - assign \fus_src6_i 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_XER_xer_ca_spr0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src6_i \xer_src2__data_o + process $group_20 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \function_unit \dec_sub10_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \function_unit \dec_sub28_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \function_unit \dec_sub0_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \function_unit \dec_sub26_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \function_unit \dec_sub19_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \function_unit \dec_sub22_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \function_unit \dec_sub9_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \function_unit \dec_sub11_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \function_unit \dec_sub27_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \function_unit \dec_sub15_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \function_unit \dec_sub20_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \function_unit \dec_sub21_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \function_unit \dec_sub23_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \function_unit \dec_sub16_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \function_unit \dec_sub18_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \function_unit \dec_sub8_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \function_unit \dec_sub24_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \function_unit \dec_sub4_function_unit end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $537 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$45 [3] - connect \B \fu_enable [8] - connect \Y $537 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $539 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $537 - connect \B \rdflag_XER_xer_ca_0 - connect \Y $539 + process $group_21 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \form \dec_sub10_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \form \dec_sub28_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \form \dec_sub0_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \form \dec_sub26_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \form \dec_sub19_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \form \dec_sub22_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \form \dec_sub9_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \form \dec_sub11_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \form \dec_sub27_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \form \dec_sub15_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \form \dec_sub20_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \form \dec_sub21_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \form \dec_sub23_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \form \dec_sub16_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \form \dec_sub18_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \form \dec_sub8_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \form \dec_sub24_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \form \dec_sub4_form + end + sync init end - process $group_278 - assign \pick$524 1'0 - assign \pick$524 $539 + process $group_22 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \internal_op \dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \internal_op \dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \internal_op \dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \internal_op \dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \internal_op \dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \internal_op \dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \internal_op \dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \internal_op \dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \internal_op \dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \internal_op \dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \internal_op \dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \internal_op \dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \internal_op \dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \internal_op \dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \internal_op \dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \internal_op \dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \internal_op \dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \internal_op \dec_sub4_internal_op + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $541 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [2] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $541 + process $group_23 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \in1_sel \dec_sub10_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \in1_sel \dec_sub28_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \in1_sel \dec_sub0_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \in1_sel \dec_sub26_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \in1_sel \dec_sub19_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \in1_sel \dec_sub22_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \in1_sel \dec_sub9_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \in1_sel \dec_sub11_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \in1_sel \dec_sub27_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \in1_sel \dec_sub15_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \in1_sel \dec_sub20_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \in1_sel \dec_sub21_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \in1_sel \dec_sub23_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \in1_sel \dec_sub16_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \in1_sel \dec_sub18_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \in1_sel \dec_sub8_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \in1_sel \dec_sub24_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \in1_sel \dec_sub4_in1_sel + end + sync init end - process $group_279 - assign \rp_XER_xer_ca_shiftrot0_2 1'0 - assign \rp_XER_xer_ca_shiftrot0_2 $541 + process $group_24 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \in2_sel \dec_sub10_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \in2_sel \dec_sub28_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \in2_sel \dec_sub0_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \in2_sel \dec_sub26_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \in2_sel \dec_sub19_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \in2_sel \dec_sub22_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \in2_sel \dec_sub9_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \in2_sel \dec_sub11_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \in2_sel \dec_sub27_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \in2_sel \dec_sub15_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \in2_sel \dec_sub20_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \in2_sel \dec_sub21_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \in2_sel \dec_sub23_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \in2_sel \dec_sub16_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \in2_sel \dec_sub18_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \in2_sel \dec_sub8_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \in2_sel \dec_sub24_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \in2_sel \dec_sub4_in2_sel + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 2 $543 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $544 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $543 + process $group_25 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \in3_sel \dec_sub10_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \in3_sel \dec_sub28_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \in3_sel \dec_sub0_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \in3_sel \dec_sub26_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \in3_sel \dec_sub19_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \in3_sel \dec_sub22_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \in3_sel \dec_sub9_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \in3_sel \dec_sub11_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \in3_sel \dec_sub27_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \in3_sel \dec_sub15_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \in3_sel \dec_sub20_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \in3_sel \dec_sub21_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \in3_sel \dec_sub23_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \in3_sel \dec_sub16_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \in3_sel \dec_sub18_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \in3_sel \dec_sub8_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \in3_sel \dec_sub24_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \in3_sel \dec_sub4_in3_sel + end + sync init end - process $group_280 - assign \addr_en_XER_xer_ca_shiftrot0_2 2'00 - assign \addr_en_XER_xer_ca_shiftrot0_2 $543 + process $group_26 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \out_sel \dec_sub10_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \out_sel \dec_sub28_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \out_sel \dec_sub0_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \out_sel \dec_sub26_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \out_sel \dec_sub19_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \out_sel \dec_sub22_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \out_sel \dec_sub9_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \out_sel \dec_sub11_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \out_sel \dec_sub27_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \out_sel \dec_sub15_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \out_sel \dec_sub20_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \out_sel \dec_sub21_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \out_sel \dec_sub23_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \out_sel \dec_sub16_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \out_sel \dec_sub18_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \out_sel \dec_sub8_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \out_sel \dec_sub24_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \out_sel \dec_sub4_out_sel + end sync init end - process $group_281 - assign \fus_src4_i$66 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_XER_xer_ca_shiftrot0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src4_i$66 \xer_src2__data_o + process $group_27 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \cr_in \dec_sub10_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \cr_in \dec_sub28_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \cr_in \dec_sub0_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \cr_in \dec_sub26_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \cr_in \dec_sub19_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \cr_in \dec_sub22_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \cr_in \dec_sub9_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \cr_in \dec_sub11_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \cr_in \dec_sub27_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \cr_in \dec_sub15_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \cr_in \dec_sub20_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \cr_in \dec_sub21_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \cr_in \dec_sub23_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \cr_in \dec_sub16_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \cr_in \dec_sub18_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \cr_in \dec_sub8_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \cr_in \dec_sub24_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \cr_in \dec_sub4_cr_in end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $545 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $546 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en_XER_xer_ca_spr0_1 - connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $546 + process $group_28 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \cr_out \dec_sub10_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \cr_out \dec_sub28_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \cr_out \dec_sub0_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \cr_out \dec_sub26_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \cr_out \dec_sub19_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \cr_out \dec_sub22_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \cr_out \dec_sub9_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \cr_out \dec_sub11_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \cr_out \dec_sub27_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \cr_out \dec_sub15_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \cr_out \dec_sub20_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \cr_out \dec_sub21_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \cr_out \dec_sub23_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \cr_out \dec_sub16_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \cr_out \dec_sub18_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \cr_out \dec_sub8_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \cr_out \dec_sub24_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \cr_out \dec_sub4_cr_out + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $548 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en_XER_xer_ca_alu0_0 - connect \B $546 - connect \Y $548 + process $group_29 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \rc_sel \dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \rc_sel \dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \rc_sel \dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \rc_sel \dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \rc_sel \dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \rc_sel \dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \rc_sel \dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \rc_sel \dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \rc_sel \dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \rc_sel \dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \rc_sel \dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \rc_sel \dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \rc_sel \dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \rc_sel \dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \rc_sel \dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \rc_sel \dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \rc_sel \dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \rc_sel \dec_sub4_rc_sel + end + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A $548 - connect \Y $545 + process $group_30 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \ldst_len \dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \ldst_len \dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \ldst_len \dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \ldst_len \dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \ldst_len \dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \ldst_len \dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \ldst_len \dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \ldst_len \dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \ldst_len \dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \ldst_len \dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \ldst_len \dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \ldst_len \dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \ldst_len \dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \ldst_len \dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \ldst_len \dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \ldst_len \dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \ldst_len \dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \ldst_len \dec_sub4_ldst_len + end + sync init end - process $group_282 - assign \xer_src2__ren 3'000 - assign \xer_src2__ren $545 + process $group_31 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \upd \dec_sub10_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \upd \dec_sub28_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \upd \dec_sub0_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \upd \dec_sub26_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \upd \dec_sub19_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \upd \dec_sub22_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \upd \dec_sub9_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \upd \dec_sub11_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \upd \dec_sub27_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \upd \dec_sub15_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \upd \dec_sub20_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \upd \dec_sub21_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \upd \dec_sub23_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \upd \dec_sub16_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \upd \dec_sub18_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \upd \dec_sub8_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \upd \dec_sub24_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \upd \dec_sub4_upd + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_XER_xer_ov_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $551 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pdecode2_oe - connect \B \pdecode2_oe_ok - connect \Y $551 + process $group_32 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \cry_in \dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \cry_in \dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \cry_in \dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \cry_in \dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \cry_in \dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \cry_in \dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \cry_in \dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \cry_in \dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \cry_in \dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \cry_in \dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \cry_in \dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \cry_in \dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \cry_in \dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \cry_in \dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \cry_in \dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \cry_in \dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \cry_in \dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \cry_in \dec_sub4_cry_in + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $553 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $551 - connect \B \pdecode2_xer_in - connect \Y $553 + process $group_33 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \inv_a \dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \inv_a \dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \inv_a \dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \inv_a \dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \inv_a \dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \inv_a \dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \inv_a \dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \inv_a \dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \inv_a \dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \inv_a \dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \inv_a \dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \inv_a \dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \inv_a \dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \inv_a \dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \inv_a \dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \inv_a \dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \inv_a \dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \inv_a \dec_sub4_inv_a + end + sync init end - process $group_283 - assign \rdflag_XER_xer_ov_0 1'0 - assign \rdflag_XER_xer_ov_0 $553 + process $group_34 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \inv_out \dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \inv_out \dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \inv_out \dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \inv_out \dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \inv_out \dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \inv_out \dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \inv_out \dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \inv_out \dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \inv_out \dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \inv_out \dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \inv_out \dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \inv_out \dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \inv_out \dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \inv_out \dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \inv_out \dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \inv_out \dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \inv_out \dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \inv_out \dec_sub4_inv_out + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$555 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $556 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$55 [4] - connect \B \fu_enable [5] - connect \Y $556 + process $group_35 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \cry_out \dec_sub10_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \cry_out \dec_sub28_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \cry_out \dec_sub0_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \cry_out \dec_sub26_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \cry_out \dec_sub19_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \cry_out \dec_sub22_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \cry_out \dec_sub9_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \cry_out \dec_sub11_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \cry_out \dec_sub27_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \cry_out \dec_sub15_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \cry_out \dec_sub20_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \cry_out \dec_sub21_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \cry_out \dec_sub23_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \cry_out \dec_sub16_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \cry_out \dec_sub18_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \cry_out \dec_sub8_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \cry_out \dec_sub24_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \cry_out \dec_sub4_cry_out + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $558 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $556 - connect \B \rdflag_XER_xer_ov_0 - connect \Y $558 + process $group_36 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \br \dec_sub10_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \br \dec_sub28_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \br \dec_sub0_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \br \dec_sub26_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \br \dec_sub19_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \br \dec_sub22_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \br \dec_sub9_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \br \dec_sub11_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \br \dec_sub27_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \br \dec_sub15_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \br \dec_sub20_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \br \dec_sub21_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \br \dec_sub23_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \br \dec_sub16_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \br \dec_sub18_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \br \dec_sub8_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \br \dec_sub24_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \br \dec_sub4_br + end + sync init end - process $group_284 - assign \pick$555 1'0 - assign \pick$555 $558 + process $group_37 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \sgn_ext \dec_sub10_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \sgn_ext \dec_sub28_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \sgn_ext \dec_sub0_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \sgn_ext \dec_sub26_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \sgn_ext \dec_sub19_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \sgn_ext \dec_sub22_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \sgn_ext \dec_sub9_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \sgn_ext \dec_sub11_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \sgn_ext \dec_sub27_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \sgn_ext \dec_sub15_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \sgn_ext \dec_sub20_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \sgn_ext \dec_sub21_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \sgn_ext \dec_sub23_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \sgn_ext \dec_sub16_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \sgn_ext \dec_sub18_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \sgn_ext \dec_sub8_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \sgn_ext \dec_sub24_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \sgn_ext \dec_sub4_sgn_ext + end sync init end - process $group_285 - assign \rdpick_XER_xer_ov_i 1'0 - assign \rdpick_XER_xer_ov_i \pick$555 + process $group_38 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \rsrv \dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \rsrv \dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \rsrv \dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \rsrv \dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \rsrv \dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \rsrv \dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \rsrv \dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \rsrv \dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \rsrv \dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \rsrv \dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \rsrv \dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \rsrv \dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \rsrv \dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \rsrv \dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \rsrv \dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \rsrv \dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \rsrv \dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \rsrv \dec_sub4_rsrv + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $560 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ov_o - connect \B \rdpick_XER_xer_ov_en_o - connect \Y $560 + process $group_39 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \is_32b \dec_sub10_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \is_32b \dec_sub28_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \is_32b \dec_sub0_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \is_32b \dec_sub26_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \is_32b \dec_sub19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \is_32b \dec_sub22_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \is_32b \dec_sub9_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \is_32b \dec_sub11_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \is_32b \dec_sub27_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \is_32b \dec_sub15_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \is_32b \dec_sub20_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \is_32b \dec_sub21_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \is_32b \dec_sub23_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \is_32b \dec_sub16_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \is_32b \dec_sub18_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \is_32b \dec_sub8_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \is_32b \dec_sub24_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \is_32b \dec_sub4_is_32b + end + sync init end - process $group_286 - assign \rp_XER_xer_ov_spr0_0 1'0 - assign \rp_XER_xer_ov_spr0_0 $560 + process $group_40 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \sgn \dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \sgn \dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \sgn \dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \sgn \dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \sgn \dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \sgn \dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \sgn \dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \sgn \dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \sgn \dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \sgn \dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \sgn \dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \sgn \dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \sgn \dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \sgn \dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \sgn \dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \sgn \dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \sgn \dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \sgn \dec_sub4_sgn + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 3 \addr_en_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 3 $562 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $563 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $562 - end - process $group_287 - assign \addr_en_XER_xer_ov_spr0_0 3'000 - assign \addr_en_XER_xer_ov_spr0_0 $562 + process $group_41 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \lk \dec_sub10_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \lk \dec_sub28_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \lk \dec_sub0_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \lk \dec_sub26_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \lk \dec_sub19_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \lk \dec_sub22_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \lk \dec_sub9_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \lk \dec_sub11_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \lk \dec_sub27_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \lk \dec_sub15_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \lk \dec_sub20_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \lk \dec_sub21_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \lk \dec_sub23_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \lk \dec_sub16_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \lk \dec_sub18_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \lk \dec_sub8_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \lk \dec_sub24_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \lk \dec_sub4_lk + end sync init end - process $group_288 - assign \fus_src5_i 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_XER_xer_ov_spr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src5_i \xer_src3__data_o + process $group_42 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \sgl_pipe \dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \sgl_pipe \dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \sgl_pipe \dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \sgl_pipe \dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \sgl_pipe \dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \sgl_pipe \dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \sgl_pipe \dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \sgl_pipe \dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \sgl_pipe \dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \sgl_pipe \dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \sgl_pipe \dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \sgl_pipe \dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \sgl_pipe \dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \sgl_pipe \dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \sgl_pipe \dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \sgl_pipe \dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \sgl_pipe \dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \sgl_pipe \dec_sub4_sgl_pipe end sync init end - process $group_289 - assign \xer_src3__ren 3'000 - assign \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 + process $group_43 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + switch \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01010 + assign \asmcode \dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11100 + assign \asmcode \dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00000 + assign \asmcode \dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11010 + assign \asmcode \dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10011 + assign \asmcode \dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10110 + assign \asmcode \dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01001 + assign \asmcode \dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01011 + assign \asmcode \dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11011 + assign \asmcode \dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01111 + assign \asmcode \dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10100 + assign \asmcode \dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10101 + assign \asmcode \dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10111 + assign \asmcode \dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10000 + assign \asmcode \dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'10010 + assign \asmcode \dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'01000 + assign \asmcode \dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'11000 + assign \asmcode \dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:293" + case 5'00100 + assign \asmcode \dec_sub4_asmcode + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_CR_full_cr_0 - process $group_290 - assign \rdflag_CR_full_cr_0 1'0 - assign \rdflag_CR_full_cr_0 \pdecode2_read_cr_whole +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec58" +module \dec58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$564 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $565 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [2] - connect \B \fu_enable [1] - connect \Y $565 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $567 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $565 - connect \B \rdflag_CR_full_cr_0 - connect \Y $567 - end - process $group_291 - assign \pick$564 1'0 - assign \pick$564 $567 + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \function_unit 11'00000000100 + end sync init end - process $group_292 - assign \rdpick_CR_full_cr_i 1'0 - assign \rdpick_CR_full_cr_i \pick$564 + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \form 5'00101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \form 5'00101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \form 5'00101 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $569 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_full_cr_o - connect \B \rdpick_CR_full_cr_en_o - connect \Y $569 - end - process $group_293 - assign \rp_CR_full_cr_cr0_0 1'0 - assign \rp_CR_full_cr_cr0_0 $569 + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \internal_op 7'0100101 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 8 \addr_en_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 8 $571 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $572 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B 8'11111111 - connect \S \rp_CR_full_cr_cr0_0 - connect \Y $571 - end - process $group_294 - assign \addr_en_CR_full_cr_cr0_0 8'00000000 - assign \addr_en_CR_full_cr_cr0_0 $571 + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \in1_sel 3'010 + end sync init end - process $group_295 - assign \fus_src3_i$67 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_CR_full_cr_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src3_i$67 \cr_full_rd__data_o + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \in2_sel 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \in2_sel 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \in2_sel 4'1000 end sync init end - process $group_296 - assign \cr_full_rd__ren 8'00000000 - assign \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \in3_sel 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_CR_cr_a_0 - process $group_297 - assign \rdflag_CR_cr_a_0 1'0 - assign \rdflag_CR_cr_a_0 \pdecode2_cr_in1_ok + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \out_sel 2'01 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$573 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $574 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [3] - connect \B \fu_enable [1] - connect \Y $574 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $576 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $574 - connect \B \rdflag_CR_cr_a_0 - connect \Y $576 - end - process $group_298 - assign \pick$573 1'0 - assign \pick$573 $576 + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \cr_in 3'000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$578 - process $group_299 - assign \rdpick_CR_cr_a_i 2'00 - assign \rdpick_CR_cr_a_i [0] \pick$573 - assign \rdpick_CR_cr_a_i [1] \pick$578 + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \cr_out 3'000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $579 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_a_o [0] - connect \B \rdpick_CR_cr_a_en_o - connect \Y $579 - end - process $group_300 - assign \rp_CR_cr_a_cr0_0 1'0 - assign \rp_CR_cr_a_cr0_0 $579 + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \ldst_len 4'0100 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 16 \addr_en_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 4 $581 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sub $582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_in1 - connect \Y $581 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 16 $583 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sshl $584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $581 - connect \Y $583 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 16 $585 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $586 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $583 - connect \S \rp_CR_cr_a_cr0_0 - connect \Y $585 - end - process $group_301 - assign \addr_en_CR_cr_a_cr0_0 16'0000000000000000 - assign \addr_en_CR_cr_a_cr0_0 $585 + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \upd 2'00 + end sync init end - process $group_302 - assign \fus_src4_i$68 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_CR_cr_a_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src4_i$68 \cr_src1__data_o + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \rc_sel 2'00 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $587 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$69 [2] - connect \B \fu_enable [2] - connect \Y $587 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $589 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $587 - connect \B \rdflag_CR_cr_a_0 - connect \Y $589 - end - process $group_303 - assign \pick$578 1'0 - assign \pick$578 $589 + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \cry_in 2'00 + end sync init end - process $group_304 - assign \fus_cu_rd__go_i$70 3'000 - assign \fus_cu_rd__go_i$70 [2] \rdpick_CR_cr_a_o [1] - assign \fus_cu_rd__go_i$70 [0] \rdpick_FAST_fast1_o [0] - assign \fus_cu_rd__go_i$70 [1] \rdpick_FAST_fast1_o [3] + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \asmcode 8'01010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \asmcode 8'01010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \asmcode 8'01100010 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $591 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_a_o [1] - connect \B \rdpick_CR_cr_a_en_o - connect \Y $591 - end - process $group_305 - assign \rp_CR_cr_a_branch0_1 1'0 - assign \rp_CR_cr_a_branch0_1 $591 + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \inv_a 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 16 \addr_en_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 4 $593 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sub $594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_in1 - connect \Y $593 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - wire width 16 $595 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65" - cell $sshl $596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $593 - connect \Y $595 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 16 $597 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $598 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $595 - connect \S \rp_CR_cr_a_branch0_1 - connect \Y $597 - end - process $group_306 - assign \addr_en_CR_cr_a_branch0_1 16'0000000000000000 - assign \addr_en_CR_cr_a_branch0_1 $597 + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \inv_out 1'0 + end sync init end - process $group_307 - assign \fus_src3_i$71 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_CR_cr_a_branch0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src3_i$71 \cr_src1__data_o + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \cry_out 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $599 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $600 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en_CR_cr_a_cr0_0 - connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $600 - end - connect $599 $600 - process $group_308 - assign \cr_src1__ren 8'00000000 - assign \cr_src1__ren $599 [7:0] + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \br 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_CR_cr_b_0 - process $group_309 - assign \rdflag_CR_cr_b_0 1'0 - assign \rdflag_CR_cr_b_0 \pdecode2_cr_in2_ok + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \sgn_ext 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$602 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $603 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [4] - connect \B \fu_enable [1] - connect \Y $603 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $605 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $603 - connect \B \rdflag_CR_cr_b_0 - connect \Y $605 - end - process $group_310 - assign \pick$602 1'0 - assign \pick$602 $605 + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \rsrv 1'0 + end sync init end - process $group_311 - assign \rdpick_CR_cr_b_i 1'0 - assign \rdpick_CR_cr_b_i \pick$602 + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \is_32b 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $607 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_b_o - connect \B \rdpick_CR_cr_b_en_o - connect \Y $607 - end - process $group_312 - assign \rp_CR_cr_b_cr0_0 1'0 - assign \rp_CR_cr_b_cr0_0 $607 + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \sgn 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 16 \addr_en_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - wire width 4 $609 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - cell $sub $610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_in2 - connect \Y $609 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - wire width 16 $611 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67" - cell $sshl $612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $609 - connect \Y $611 + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \lk 1'0 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 16 $613 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $614 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $611 - connect \S \rp_CR_cr_b_cr0_0 - connect \Y $613 + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'10 + assign \sgl_pipe 1'1 + end + sync init end - process $group_313 - assign \addr_en_CR_cr_b_cr0_0 16'0000000000000000 - assign \addr_en_CR_cr_b_cr0_0 $613 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec62" +module \dec62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 input 0 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 1 \function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 output 2 \form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 3 \internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 4 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 5 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 6 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 7 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 10 \rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 11 \ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 12 \upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 13 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 15 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 20 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 23 \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 2 \opcode_switch + process $group_0 + assign \opcode_switch 2'00 + assign \opcode_switch \opcode_in [1:0] sync init end - process $group_314 - assign \fus_src5_i$72 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_CR_cr_b_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src5_i$72 \cr_src2__data_o + process $group_1 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \function_unit 11'00000000100 end sync init end - process $group_315 - assign \cr_src2__ren 8'00000000 - assign \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_CR_cr_c_0 - process $group_316 - assign \rdflag_CR_cr_c_0 1'0 - assign \rdflag_CR_cr_c_0 \pdecode2_cr_in2_ok$1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$615 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $616 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$30 [5] - connect \B \fu_enable [1] - connect \Y $616 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $618 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $616 - connect \B \rdflag_CR_cr_c_0 - connect \Y $618 - end - process $group_317 - assign \pick$615 1'0 - assign \pick$615 $618 - sync init - end - process $group_318 - assign \rdpick_CR_cr_c_i 1'0 - assign \rdpick_CR_cr_c_i \pick$615 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $620 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_c_o - connect \B \rdpick_CR_cr_c_en_o - connect \Y $620 - end - process $group_319 - assign \rp_CR_cr_c_cr0_0 1'0 - assign \rp_CR_cr_c_cr0_0 $620 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 16 \addr_en_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - wire width 4 $622 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - cell $sub $623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_in2$2 - connect \Y $622 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - wire width 16 $624 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69" - cell $sshl $625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $622 - connect \Y $624 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 16 $626 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $627 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $624 - connect \S \rp_CR_cr_c_cr0_0 - connect \Y $626 - end - process $group_320 - assign \addr_en_CR_cr_c_cr0_0 16'0000000000000000 - assign \addr_en_CR_cr_c_cr0_0 $626 - sync init - end - process $group_321 - assign \fus_src6_i$73 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_CR_cr_c_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src6_i$73 \cr_src3__data_o + process $group_2 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \form 5'00101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \form 5'00101 end sync init end - process $group_322 - assign \cr_src3__ren 8'00000000 - assign \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_FAST_fast1_0 - process $group_323 - assign \rdflag_FAST_fast1_0 1'0 - assign \rdflag_FAST_fast1_0 \pdecode2_fast1_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_FAST_fast1_1 - process $group_324 - assign \rdflag_FAST_fast1_1 1'0 - assign \rdflag_FAST_fast1_1 \pdecode2_fast2_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$628 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $629 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$69 [0] - connect \B \fu_enable [2] - connect \Y $629 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $631 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $629 - connect \B \rdflag_FAST_fast1_0 - connect \Y $631 - end - process $group_325 - assign \pick$628 1'0 - assign \pick$628 $631 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$633 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$634 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$635 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$636 - process $group_326 - assign \rdpick_FAST_fast1_i 5'00000 - assign \rdpick_FAST_fast1_i [0] \pick$628 - assign \rdpick_FAST_fast1_i [1] \pick$633 - assign \rdpick_FAST_fast1_i [2] \pick$634 - assign \rdpick_FAST_fast1_i [3] \pick$635 - assign \rdpick_FAST_fast1_i [4] \pick$636 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $637 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [0] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $637 - end - process $group_327 - assign \rp_FAST_fast1_branch0_0 1'0 - assign \rp_FAST_fast1_branch0_0 $637 + process $group_3 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \internal_op 7'0100110 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 8 \addr_en_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - wire width 8 $639 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - cell $sshl $640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fast1 - connect \Y $639 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 8 $641 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $642 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B $639 - connect \S \rp_FAST_fast1_branch0_0 - connect \Y $641 - end - process $group_328 - assign \addr_en_FAST_fast1_branch0_0 8'00000000 - assign \addr_en_FAST_fast1_branch0_0 $641 + process $group_4 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \in1_sel 3'010 + end sync init end - process $group_329 - assign \fus_src1_i$74 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_FAST_fast1_branch0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src1_i$74 \fast_src1__data_o + process $group_5 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \in2_sel 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \in2_sel 4'1000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $643 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [2] - connect \B \fu_enable [3] - connect \Y $643 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $645 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $643 - connect \B \rdflag_FAST_fast1_0 - connect \Y $645 - end - process $group_330 - assign \pick$633 1'0 - assign \pick$633 $645 + process $group_6 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \in3_sel 2'01 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $647 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [1] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $647 - end - process $group_331 - assign \rp_FAST_fast1_trap0_1 1'0 - assign \rp_FAST_fast1_trap0_1 $647 + process $group_7 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \out_sel 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 8 \addr_en_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - wire width 8 $649 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - cell $sshl $650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fast1 - connect \Y $649 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 8 $651 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $652 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B $649 - connect \S \rp_FAST_fast1_trap0_1 - connect \Y $651 - end - process $group_332 - assign \addr_en_FAST_fast1_trap0_1 8'00000000 - assign \addr_en_FAST_fast1_trap0_1 $651 + process $group_8 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \cr_in 3'000 + end sync init end - process $group_333 - assign \fus_src3_i$75 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_FAST_fast1_trap0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src3_i$75 \fast_src1__data_o + process $group_9 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \cr_out 3'000 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $653 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$55 [2] - connect \B \fu_enable [5] - connect \Y $653 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $655 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $653 - connect \B \rdflag_FAST_fast1_0 - connect \Y $655 - end - process $group_334 - assign \pick$634 1'0 - assign \pick$634 $655 + process $group_10 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \ldst_len 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \ldst_len 4'1000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $657 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [2] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $657 - end - process $group_335 - assign \rp_FAST_fast1_spr0_2 1'0 - assign \rp_FAST_fast1_spr0_2 $657 + process $group_11 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \upd 2'01 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 8 \addr_en_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - wire width 8 $659 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:106" - cell $sshl $660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fast1 - connect \Y $659 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 8 $661 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $662 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B $659 - connect \S \rp_FAST_fast1_spr0_2 - connect \Y $661 - end - process $group_336 - assign \addr_en_FAST_fast1_spr0_2 8'00000000 - assign \addr_en_FAST_fast1_spr0_2 $661 + process $group_12 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \rc_sel 2'00 + end sync init end - process $group_337 - assign \fus_src3_i$76 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_FAST_fast1_spr0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src3_i$76 \fast_src1__data_o + process $group_13 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \cry_in 2'00 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $663 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$69 [1] - connect \B \fu_enable [2] - connect \Y $663 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $665 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $663 - connect \B \rdflag_FAST_fast1_1 - connect \Y $665 - end - process $group_338 - assign \pick$635 1'0 - assign \pick$635 $665 + process $group_14 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \asmcode 8'10101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \asmcode 8'10101100 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_FAST_fast1_branch0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $667 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [3] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $667 - end - process $group_339 - assign \rp_FAST_fast1_branch0_3 1'0 - assign \rp_FAST_fast1_branch0_3 $667 + process $group_15 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \inv_a 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 8 \addr_en_FAST_fast1_branch0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - wire width 8 $669 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - cell $sshl $670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fast2 - connect \Y $669 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 8 $671 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $672 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B $669 - connect \S \rp_FAST_fast1_branch0_3 - connect \Y $671 - end - process $group_340 - assign \addr_en_FAST_fast1_branch0_3 8'00000000 - assign \addr_en_FAST_fast1_branch0_3 $671 + process $group_16 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \inv_out 1'0 + end sync init end - process $group_341 - assign \fus_src2_i$77 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_FAST_fast1_branch0_3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src2_i$77 \fast_src1__data_o + process $group_17 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \cry_out 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $673 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$33 [3] - connect \B \fu_enable [3] - connect \Y $673 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $675 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $673 - connect \B \rdflag_FAST_fast1_1 - connect \Y $675 - end - process $group_342 - assign \pick$636 1'0 - assign \pick$636 $675 + process $group_18 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \br 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_FAST_fast1_trap0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $677 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [4] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $677 - end - process $group_343 - assign \rp_FAST_fast1_trap0_4 1'0 - assign \rp_FAST_fast1_trap0_4 $677 + process $group_19 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \sgn_ext 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 8 \addr_en_FAST_fast1_trap0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - wire width 8 $679 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - cell $sshl $680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fast2 - connect \Y $679 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 8 $681 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $682 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B $679 - connect \S \rp_FAST_fast1_trap0_4 - connect \Y $681 - end - process $group_344 - assign \addr_en_FAST_fast1_trap0_4 8'00000000 - assign \addr_en_FAST_fast1_trap0_4 $681 + process $group_20 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \rsrv 1'0 + end sync init end - process $group_345 - assign \fus_src4_i$78 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_FAST_fast1_trap0_4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src4_i$78 \fast_src1__data_o + process $group_21 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \is_32b 1'0 end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 8 $683 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 8 $684 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \addr_en_FAST_fast1_branch0_0 - connect \B \addr_en_FAST_fast1_trap0_1 - connect \Y $684 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 8 $686 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \addr_en_FAST_fast1_branch0_3 - connect \B \addr_en_FAST_fast1_trap0_4 - connect \Y $686 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 8 $688 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \addr_en_FAST_fast1_spr0_2 - connect \B $686 - connect \Y $688 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 8 $690 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $684 - connect \B $688 - connect \Y $690 - end - connect $683 $690 - process $group_346 - assign \fast_src1__ren 5'00000 - assign \fast_src1__ren $683 [4:0] + process $group_22 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \sgn 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" - wire width 1 \rdflag_SPR_spr1_0 - process $group_347 - assign \rdflag_SPR_spr1_0 1'0 - assign \rdflag_SPR_spr1_0 \pdecode2_spr1_ok + process $group_23 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \lk 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:227" - wire width 1 \pick$692 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $693 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$55 [1] - connect \B \fu_enable [5] - connect \Y $693 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - wire width 1 $695 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:228" - cell $and $696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $693 - connect \B \rdflag_SPR_spr1_0 - connect \Y $695 - end - process $group_348 - assign \pick$692 1'0 - assign \pick$692 $695 + process $group_24 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'00 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 2'01 + assign \sgl_pipe 1'1 + end sync init end - process $group_349 - assign \rdpick_SPR_spr1_i 1'0 - assign \rdpick_SPR_spr1_i \pick$692 - sync init +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec" +module \dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + wire width 1 input 0 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:337" + wire width 32 input 1 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 output 2 \opcode_in + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 output 3 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 output 4 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 output 5 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 output 6 \out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 output 7 \rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 output 8 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 output 9 \cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 output 10 \internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 output 11 \function_unit + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 output 12 \ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 13 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 14 \inv_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 output 15 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 16 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 17 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 18 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 19 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 1 output 20 \LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 21 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 output 22 \sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 output 23 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 24 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 25 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 26 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 27 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 16 output 28 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 16 output 29 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 30 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 6 output 31 \sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 24 output 32 \LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 1 output 33 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 1 output 34 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 14 output 35 \BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 36 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 37 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 38 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 39 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 40 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 14 output 41 \DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 output 42 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 10 output 43 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 output 44 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 output 45 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 output 46 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 output 47 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec19_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec19_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec19_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec19_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec19_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec19_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec19_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec19_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec19_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec19_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec19_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec19_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec19_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec19_asmcode + cell \dec19 \dec19 + connect \opcode_in \dec19_opcode_in + connect \function_unit \dec19_function_unit + connect \form \dec19_form + connect \internal_op \dec19_internal_op + connect \in1_sel \dec19_in1_sel + connect \in2_sel \dec19_in2_sel + connect \in3_sel \dec19_in3_sel + connect \out_sel \dec19_out_sel + connect \cr_in \dec19_cr_in + connect \cr_out \dec19_cr_out + connect \rc_sel \dec19_rc_sel + connect \ldst_len \dec19_ldst_len + connect \upd \dec19_upd + connect \cry_in \dec19_cry_in + connect \inv_a \dec19_inv_a + connect \inv_out \dec19_inv_out + connect \cry_out \dec19_cry_out + connect \br \dec19_br + connect \sgn_ext \dec19_sgn_ext + connect \rsrv \dec19_rsrv + connect \is_32b \dec19_is_32b + connect \sgn \dec19_sgn + connect \lk \dec19_lk + connect \sgl_pipe \dec19_sgl_pipe + connect \asmcode \dec19_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:237" - wire width 1 \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - wire width 1 $697 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:239" - cell $and $698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_SPR_spr1_o - connect \B \rdpick_SPR_spr1_en_o - connect \Y $697 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec30_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec30_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec30_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec30_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec30_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec30_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec30_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec30_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec30_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec30_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec30_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec30_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec30_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec30_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec30_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec30_asmcode + cell \dec30 \dec30 + connect \opcode_in \dec30_opcode_in + connect \function_unit \dec30_function_unit + connect \form \dec30_form + connect \internal_op \dec30_internal_op + connect \in1_sel \dec30_in1_sel + connect \in2_sel \dec30_in2_sel + connect \in3_sel \dec30_in3_sel + connect \out_sel \dec30_out_sel + connect \cr_in \dec30_cr_in + connect \cr_out \dec30_cr_out + connect \rc_sel \dec30_rc_sel + connect \ldst_len \dec30_ldst_len + connect \upd \dec30_upd + connect \cry_in \dec30_cry_in + connect \inv_a \dec30_inv_a + connect \inv_out \dec30_inv_out + connect \cry_out \dec30_cry_out + connect \br \dec30_br + connect \sgn_ext \dec30_sgn_ext + connect \rsrv \dec30_rsrv + connect \is_32b \dec30_is_32b + connect \sgn \dec30_sgn + connect \lk \dec30_lk + connect \sgl_pipe \dec30_sgl_pipe + connect \asmcode \dec30_asmcode end - process $group_350 - assign \rp_SPR_spr1_spr0_0 1'0 - assign \rp_SPR_spr1_spr0_0 $697 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec31_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec31_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec31_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec31_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec31_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec31_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec31_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec31_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec31_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec31_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec31_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec31_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec31_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec31_asmcode + cell \dec31 \dec31 + connect \opcode_in \dec31_opcode_in + connect \function_unit \dec31_function_unit + connect \form \dec31_form + connect \internal_op \dec31_internal_op + connect \in1_sel \dec31_in1_sel + connect \in2_sel \dec31_in2_sel + connect \in3_sel \dec31_in3_sel + connect \out_sel \dec31_out_sel + connect \cr_in \dec31_cr_in + connect \cr_out \dec31_cr_out + connect \rc_sel \dec31_rc_sel + connect \ldst_len \dec31_ldst_len + connect \upd \dec31_upd + connect \cry_in \dec31_cry_in + connect \inv_a \dec31_inv_a + connect \inv_out \dec31_inv_out + connect \cry_out \dec31_cry_out + connect \br \dec31_br + connect \sgn_ext \dec31_sgn_ext + connect \rsrv \dec31_rsrv + connect \is_32b \dec31_is_32b + connect \sgn \dec31_sgn + connect \lk \dec31_lk + connect \sgl_pipe \dec31_sgl_pipe + connect \asmcode \dec31_asmcode end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 10 \addr_en_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 10 $699 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - cell $mux $700 - parameter \WIDTH 10 - connect \A 10'0000000000 - connect \B \pdecode2_spr1 - connect \S \rp_SPR_spr1_spr0_0 - connect \Y $699 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec58_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec58_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec58_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec58_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec58_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec58_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec58_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec58_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec58_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec58_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec58_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec58_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec58_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec58_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec58_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec58_asmcode + cell \dec58 \dec58 + connect \opcode_in \dec58_opcode_in + connect \function_unit \dec58_function_unit + connect \form \dec58_form + connect \internal_op \dec58_internal_op + connect \in1_sel \dec58_in1_sel + connect \in2_sel \dec58_in2_sel + connect \in3_sel \dec58_in3_sel + connect \out_sel \dec58_out_sel + connect \cr_in \dec58_cr_in + connect \cr_out \dec58_cr_out + connect \rc_sel \dec58_rc_sel + connect \ldst_len \dec58_ldst_len + connect \upd \dec58_upd + connect \cry_in \dec58_cry_in + connect \inv_a \dec58_inv_a + connect \inv_out \dec58_inv_out + connect \cry_out \dec58_cry_out + connect \br \dec58_br + connect \sgn_ext \dec58_sgn_ext + connect \rsrv \dec58_rsrv + connect \is_32b \dec58_is_32b + connect \sgn \dec58_sgn + connect \lk \dec58_lk + connect \sgl_pipe \dec58_sgl_pipe + connect \asmcode \dec58_asmcode end - process $group_351 - assign \addr_en_SPR_spr1_spr0_0 10'0000000000 - assign \addr_en_SPR_spr1_spr0_0 $699 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec62_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec62_function_unit + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \dec62_form + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec62_internal_op + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec62_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec62_out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec62_cr_out + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec62_rc_sel + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec62_ldst_len + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec62_upd + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec62_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec62_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec62_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec62_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec62_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \dec62_asmcode + cell \dec62 \dec62 + connect \opcode_in \dec62_opcode_in + connect \function_unit \dec62_function_unit + connect \form \dec62_form + connect \internal_op \dec62_internal_op + connect \in1_sel \dec62_in1_sel + connect \in2_sel \dec62_in2_sel + connect \in3_sel \dec62_in3_sel + connect \out_sel \dec62_out_sel + connect \cr_in \dec62_cr_in + connect \cr_out \dec62_cr_out + connect \rc_sel \dec62_rc_sel + connect \ldst_len \dec62_ldst_len + connect \upd \dec62_upd + connect \cry_in \dec62_cry_in + connect \inv_a \dec62_inv_a + connect \inv_out \dec62_inv_out + connect \cry_out \dec62_cry_out + connect \br \dec62_br + connect \sgn_ext \dec62_sgn_ext + connect \rsrv \dec62_rsrv + connect \is_32b \dec62_is_32b + connect \sgn \dec62_sgn + connect \lk \dec62_lk + connect \sgl_pipe \dec62_sgl_pipe + connect \asmcode \dec62_asmcode end - process $group_352 - assign \fus_src2_i$79 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - switch { \rp_SPR_spr1_spr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - case 1'1 - assign \fus_src2_i$79 \spr_spr1__data_o - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 6 \opcode_switch + process $group_0 + assign \opcode_switch 6'000000 + assign \opcode_switch \opcode_in [31:26] sync init end - process $group_353 - assign \spr_spr1__addr 7'0000000 - assign \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] + process $group_1 + assign \dec19_opcode_in 32'00000000000000000000000000000000 + assign \dec19_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" - wire width 1 $701 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" - cell $reduce_bool $702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \rp_SPR_spr1_spr0_0 } - connect \Y $701 - end - process $group_354 - assign \spr_spr1__ren 1'0 - assign \spr_spr1__ren $701 + process $group_2 + assign \dec30_opcode_in 32'00000000000000000000000000000000 + assign \dec30_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $703 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok - connect \B \fus_cu_busy_o - connect \Y $703 - end - process $group_355 - assign \wrflag_alu0_o_0 1'0 - assign \wrflag_alu0_o_0 $703 + process $group_3 + assign \dec31_opcode_in 32'00000000000000000000000000000000 + assign \dec31_opcode_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $705 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [0] - connect \B \fu_enable [0] - connect \Y $705 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $707 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$81 [0] - connect \B \fu_enable [1] - connect \Y $707 + process $group_4 + assign \dec58_opcode_in 32'00000000000000000000000000000000 + assign \dec58_opcode_in \opcode_in + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $709 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [0] - connect \B \fu_enable [3] - connect \Y $709 + process $group_5 + assign \dec62_opcode_in 32'00000000000000000000000000000000 + assign \dec62_opcode_in \opcode_in + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $711 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [0] - connect \B \fu_enable [4] - connect \Y $711 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:276" + wire width 32 \opcode_switch$1 + process $group_6 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \function_unit \dec19_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \function_unit \dec30_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \function_unit \dec31_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \function_unit \dec58_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \function_unit \dec62_function_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \function_unit 11'00010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \function_unit 11'00000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \function_unit 11'00000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \function_unit 11'00100000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \function_unit 11'00000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \function_unit 11'00000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \function_unit 11'00000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \function_unit 11'00010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \function_unit 11'00010000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \function_unit 11'00000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \function_unit 11'00000010000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \function_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \function_unit 11'00000000000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $713 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [0] - connect \B \fu_enable [5] - connect \Y $713 + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 5 \form + process $group_7 + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \form \dec19_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \form \dec30_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \form \dec31_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \form \dec58_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \form \dec62_form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \form 5'00011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \form 5'00010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \form 5'00010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \form 5'00001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \form 5'00010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \form 5'10011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \form 5'10011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \form 5'10011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \form 5'00100 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \form 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \form 5'00100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \form 5'00000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $715 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [0] - connect \B \fu_enable [6] - connect \Y $715 + process $group_8 + assign \internal_op 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \internal_op \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \internal_op \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \internal_op \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \internal_op \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \internal_op \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \internal_op 7'1001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \internal_op 7'0000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \internal_op 7'0000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \internal_op 7'0000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \internal_op 7'0001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \internal_op 7'0100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \internal_op 7'0110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \internal_op 7'0110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \internal_op 7'0111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \internal_op 7'0100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \internal_op 7'0000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \internal_op 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \internal_op 7'0111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \internal_op 7'1000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \internal_op 7'1000011 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \internal_op 7'0000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \internal_op 7'0000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \internal_op 7'1000100 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $717 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [0] - connect \B \fu_enable [7] - connect \Y $717 + process $group_9 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \in1_sel \dec19_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \in1_sel \dec30_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \in1_sel \dec31_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \in1_sel \dec58_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \in1_sel \dec62_in1_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \in1_sel 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \in1_sel 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \in1_sel 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \in1_sel 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \in1_sel 3'100 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \in1_sel 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \in1_sel 3'000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $719 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [0] - connect \B \fu_enable [8] - connect \Y $719 + process $group_10 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \in2_sel \dec19_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \in2_sel \dec30_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \in2_sel \dec31_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \in2_sel \dec58_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \in2_sel \dec62_in2_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \in2_sel 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \in2_sel 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \in2_sel 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \in2_sel 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \in2_sel 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \in2_sel 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \in2_sel 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \in2_sel 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \in2_sel 4'1011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \in2_sel 4'1011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \in2_sel 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \in2_sel 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \in2_sel 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \in2_sel 4'0100 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \in2_sel 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \in2_sel 4'0000 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $721 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$101 [0] - connect \B \fu_enable [9] - connect \Y $721 + process $group_11 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \in3_sel \dec19_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \in3_sel \dec30_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \in3_sel \dec31_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \in3_sel \dec58_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \in3_sel \dec62_in3_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \in3_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \in3_sel 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \in3_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \in3_sel 2'00 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $723 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$101 [1] - connect \B \fu_enable [9] - connect \Y $723 + process $group_12 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \out_sel \dec19_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \out_sel \dec30_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \out_sel \dec31_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \out_sel \dec58_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \out_sel \dec62_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \out_sel 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \out_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \out_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \out_sel 2'10 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \out_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \out_sel 2'01 + end + sync init end - process $group_356 - assign \wrpick_INT_o_i 10'0000000000 - assign \wrpick_INT_o_i [0] $705 - assign \wrpick_INT_o_i [1] $707 - assign \wrpick_INT_o_i [2] $709 - assign \wrpick_INT_o_i [3] $711 - assign \wrpick_INT_o_i [4] $713 - assign \wrpick_INT_o_i [5] $715 - assign \wrpick_INT_o_i [6] $717 - assign \wrpick_INT_o_i [7] $719 - assign \wrpick_INT_o_i [8] $721 - assign \wrpick_INT_o_i [9] $723 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $725 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [0] - connect \B \wrpick_INT_o_en_o - connect \Y $725 + process $group_13 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \cr_in \dec19_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \cr_in \dec30_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \cr_in \dec31_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \cr_in \dec58_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \cr_in \dec62_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \cr_in 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \cr_in 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \cr_in 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \cr_in 3'000 + end + sync init end - process $group_357 - assign \wr_pick 1'0 - assign \wr_pick $725 + process $group_14 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \cr_out \dec19_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \cr_out \dec30_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \cr_out \dec31_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \cr_out \dec58_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \cr_out \dec62_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \cr_out 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \cr_out 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \cr_out 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \cr_out 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \cr_out 3'000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$next - process $group_358 - assign \wr_pick_dly$next \wr_pick_dly - assign \wr_pick_dly$next \wr_pick - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$next 1'0 + process $group_15 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \rc_sel \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \rc_sel \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \rc_sel \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \rc_sel \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \rc_sel \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \rc_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \rc_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \rc_sel 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \rc_sel 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \rc_sel 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \rc_sel 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \rc_sel 2'00 end sync init - update \wr_pick_dly 1'0 - sync posedge \coresync_clk - update \wr_pick_dly \wr_pick_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $727 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly - connect \Y $727 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $729 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick - connect \B $727 - connect \Y $729 end - process $group_359 - assign \wr_pick_rise 1'0 - assign \wr_pick_rise $729 + process $group_16 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \ldst_len \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \ldst_len \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \ldst_len \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \ldst_len \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \ldst_len \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \ldst_len 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \ldst_len 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \ldst_len 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \ldst_len 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \ldst_len 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \ldst_len 4'0000 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$731 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$732 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$733 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$734 - process $group_360 - assign \fus_cu_wr__go_i 5'00000 - assign \fus_cu_wr__go_i [0] \wr_pick_rise - assign \fus_cu_wr__go_i [1] \wr_pick_rise$731 - assign \fus_cu_wr__go_i [2] \wr_pick_rise$732 - assign \fus_cu_wr__go_i [3] \wr_pick_rise$733 - assign \fus_cu_wr__go_i [4] \wr_pick_rise$734 + process $group_17 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \upd \dec19_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \upd \dec30_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \upd \dec31_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \upd \dec58_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \upd \dec62_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \upd 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \upd 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \upd 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \upd 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $735 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick - connect \B \wrpick_INT_o_en_o - connect \Y $735 - end - process $group_361 - assign \wp 1'0 - assign \wp $735 + process $group_18 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \cry_in \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \cry_in \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \cry_in \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \cry_in \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \cry_in \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \cry_in 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \cry_in 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \cry_in 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \cry_in 2'00 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 5 \addr_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 5 $737 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $738 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_rego - connect \S \wp - connect \Y $737 + process $group_19 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \inv_a \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \inv_a \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \inv_a \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \inv_a \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \inv_a \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \inv_a 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \inv_a 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \inv_a 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \inv_a 1'0 + end + sync init end - process $group_362 - assign \addr_en 5'00000 - assign \addr_en $737 + process $group_20 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \inv_out \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \inv_out \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \inv_out \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \inv_out \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \inv_out \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \inv_out 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \inv_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \inv_out 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $739 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$80 - connect \B \fus_cu_busy_o$4 - connect \Y $739 + process $group_21 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \cry_out \dec19_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \cry_out \dec30_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \cry_out \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \cry_out \dec58_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \cry_out \dec62_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \cry_out 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \cry_out 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \cry_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \cry_out 1'0 + end + sync init end - process $group_363 - assign \wrflag_cr0_o_0 1'0 - assign \wrflag_cr0_o_0 $739 + process $group_22 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \br \dec19_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \br \dec30_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \br \dec31_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \br \dec58_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \br \dec62_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \br 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \br 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \br 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$741 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $742 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [1] - connect \B \wrpick_INT_o_en_o - connect \Y $742 + process $group_23 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \sgn_ext \dec19_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \sgn_ext \dec30_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \sgn_ext \dec31_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \sgn_ext \dec58_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \sgn_ext \dec62_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \sgn_ext 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \sgn_ext 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \sgn_ext 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \sgn_ext 1'0 + end + sync init end - process $group_364 - assign \wr_pick$741 1'0 - assign \wr_pick$741 $742 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \rsrv + process $group_24 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \rsrv \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \rsrv \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \rsrv \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \rsrv \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \rsrv \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \rsrv 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \rsrv 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \rsrv 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$744 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$744$next - process $group_365 - assign \wr_pick_dly$744$next \wr_pick_dly$744 - assign \wr_pick_dly$744$next \wr_pick$741 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$744$next 1'0 + process $group_25 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \is_32b \dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \is_32b \dec30_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \is_32b \dec31_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \is_32b \dec58_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \is_32b \dec62_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \is_32b 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \is_32b 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \is_32b 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \is_32b 1'0 end sync init - update \wr_pick_dly$744 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$744 \wr_pick_dly$744$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$745 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $746 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$744 - connect \Y $746 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $748 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$741 - connect \B $746 - connect \Y $748 end - process $group_366 - assign \wr_pick_rise$745 1'0 - assign \wr_pick_rise$745 $748 + process $group_26 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \sgn \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \sgn \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \sgn \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \sgn \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \sgn \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \sgn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \sgn 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \sgn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \sgn 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$750 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$751 - process $group_367 - assign \fus_cu_wr__go_i$82 3'000 - assign \fus_cu_wr__go_i$82 [0] \wr_pick_rise$745 - assign \fus_cu_wr__go_i$82 [1] \wr_pick_rise$750 - assign \fus_cu_wr__go_i$82 [2] \wr_pick_rise$751 + process $group_27 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \lk \dec19_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \lk \dec30_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \lk \dec31_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \lk \dec58_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \lk \dec62_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \lk 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \lk 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \lk 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \lk 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \lk 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$752 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $753 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$741 - connect \B \wrpick_INT_o_en_o - connect \Y $753 - end - process $group_368 - assign \wp$752 1'0 - assign \wp$752 $753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \sgl_pipe + process $group_28 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \sgl_pipe \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \sgl_pipe \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \sgl_pipe \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \sgl_pipe \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \sgl_pipe \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \sgl_pipe 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \sgl_pipe 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \sgl_pipe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \sgl_pipe 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 5 \addr_en$755 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 5 $756 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $757 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_rego - connect \S \wp$752 - connect \Y $756 - end - process $group_369 - assign \addr_en$755 5'00000 - assign \addr_en$755 $756 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 8 \asmcode + process $group_29 + assign \asmcode 8'00000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'010011 + assign \asmcode \dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011110 + assign \asmcode \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'011111 + assign \asmcode \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111010 + assign \asmcode \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + case 6'111110 + assign \asmcode \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001100 + assign \asmcode 8'00000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001101 + assign \asmcode 8'00001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001110 + assign \asmcode 8'00000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001111 + assign \asmcode 8'00001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011100 + assign \asmcode 8'00010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011101 + assign \asmcode 8'00010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010010 + assign \asmcode 8'00010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010000 + assign \asmcode 8'00010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001011 + assign \asmcode 8'00011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001010 + assign \asmcode 8'00011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100010 + assign \asmcode 8'01001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100011 + assign \asmcode 8'01001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101010 + assign \asmcode 8'01011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101011 + assign \asmcode 8'01011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101000 + assign \asmcode 8'01011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101001 + assign \asmcode 8'01011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100000 + assign \asmcode 8'01100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100001 + assign \asmcode 8'01101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000111 + assign \asmcode 8'01111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011000 + assign \asmcode 8'10001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011001 + assign \asmcode 8'10001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010100 + assign \asmcode 8'10010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010101 + assign \asmcode 8'10011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'010111 + assign \asmcode 8'10011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100110 + assign \asmcode 8'10100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100111 + assign \asmcode 8'10100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101100 + assign \asmcode 8'10101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'101101 + assign \asmcode 8'10110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100100 + assign \asmcode 8'10110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'100101 + assign \asmcode 8'10111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'001000 + assign \asmcode 8'11000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000010 + assign \asmcode 8'11001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'000011 + assign \asmcode 8'11001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011010 + assign \asmcode 8'11001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 6'011011 + assign \asmcode 8'11001101 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298" + switch \opcode_switch$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000000---------------0100000000- + assign \asmcode 8'00010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'01100000000000000000000000000000 + assign \asmcode 8'10000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:307" + case 32'000001---------------0000000011- + assign \asmcode 8'10011011 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_trap0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $758 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$83 - connect \B \fus_cu_busy_o$10 - connect \Y $758 - end - process $group_370 - assign \wrflag_trap0_o_0 1'0 - assign \wrflag_trap0_o_0 $758 + process $group_30 + assign \opcode_switch$1 32'00000000000000000000000000000000 + assign \opcode_switch$1 \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$760 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $761 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [2] - connect \B \wrpick_INT_o_en_o - connect \Y $761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:370" + wire width 32 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:370" + cell $mux $3 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $2 end - process $group_371 - assign \wr_pick$760 1'0 - assign \wr_pick$760 $761 + process $group_31 + assign \opcode_in 32'00000000000000000000000000000000 + assign \opcode_in $2 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$763 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$763$next - process $group_372 - assign \wr_pick_dly$763$next \wr_pick_dly$763 - assign \wr_pick_dly$763$next \wr_pick$760 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$763$next 1'0 - end + process $group_32 + assign \RS 5'00000 + assign \RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init - update \wr_pick_dly$763 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$763 \wr_pick_dly$763$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$764 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $765 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$763 - connect \Y $765 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $767 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$760 - connect \B $765 - connect \Y $767 end - process $group_373 - assign \wr_pick_rise$764 1'0 - assign \wr_pick_rise$764 $767 + process $group_33 + assign \RT 5'00000 + assign \RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$769 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$770 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$771 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$772 - process $group_374 - assign \fus_cu_wr__go_i$85 5'00000 - assign \fus_cu_wr__go_i$85 [0] \wr_pick_rise$764 - assign \fus_cu_wr__go_i$85 [1] \wr_pick_rise$769 - assign \fus_cu_wr__go_i$85 [2] \wr_pick_rise$770 - assign \fus_cu_wr__go_i$85 [3] \wr_pick_rise$771 - assign \fus_cu_wr__go_i$85 [4] \wr_pick_rise$772 + process $group_34 + assign \RA 5'00000 + assign \RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$773 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $774 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$760 - connect \B \wrpick_INT_o_en_o - connect \Y $774 - end - process $group_375 - assign \wp$773 1'0 - assign \wp$773 $774 + process $group_35 + assign \RB 5'00000 + assign \RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 5 \addr_en$776 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 5 $777 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $778 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_rego - connect \S \wp$773 - connect \Y $777 - end - process $group_376 - assign \addr_en$776 5'00000 - assign \addr_en$776 $777 + process $group_36 + assign \SI 16'0000000000000000 + assign \SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $779 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$86 - connect \B \fus_cu_busy_o$13 - connect \Y $779 - end - process $group_377 - assign \wrflag_logical0_o_0 1'0 - assign \wrflag_logical0_o_0 $779 + process $group_37 + assign \UI 16'0000000000000000 + assign \UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$781 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $782 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [3] - connect \B \wrpick_INT_o_en_o - connect \Y $782 - end - process $group_378 - assign \wr_pick$781 1'0 - assign \wr_pick$781 $782 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 1 \L + process $group_38 + assign \L 1'0 + assign \L { \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$784 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$784$next - process $group_379 - assign \wr_pick_dly$784$next \wr_pick_dly$784 - assign \wr_pick_dly$784$next \wr_pick$781 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$784$next 1'0 - end + process $group_39 + assign \SH32 5'00000 + assign \SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init - update \wr_pick_dly$784 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$784 \wr_pick_dly$784$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$785 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $786 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$784 - connect \Y $786 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $788 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$781 - connect \B $786 - connect \Y $788 end - process $group_380 - assign \wr_pick_rise$785 1'0 - assign \wr_pick_rise$785 $788 + process $group_40 + assign \sh 6'000000 + assign \sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$790 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$791 - process $group_381 - assign \fus_cu_wr__go_i$88 3'000 - assign \fus_cu_wr__go_i$88 [0] \wr_pick_rise$785 - assign \fus_cu_wr__go_i$88 [1] \wr_pick_rise$790 - assign \fus_cu_wr__go_i$88 [2] \wr_pick_rise$791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \MB32 + process $group_41 + assign \MB32 5'00000 + assign \MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$792 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $793 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$781 - connect \B \wrpick_INT_o_en_o - connect \Y $793 - end - process $group_382 - assign \wp$792 1'0 - assign \wp$792 $793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \ME32 + process $group_42 + assign \ME32 5'00000 + assign \ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 5 \addr_en$795 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 5 $796 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $797 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_rego - connect \S \wp$792 - connect \Y $796 - end - process $group_383 - assign \addr_en$795 5'00000 - assign \addr_en$795 $796 + process $group_43 + assign \LI 24'000000000000000000000000 + assign \LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $798 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$89 - connect \B \fus_cu_busy_o$16 - connect \Y $798 - end - process $group_384 - assign \wrflag_spr0_o_0 1'0 - assign \wrflag_spr0_o_0 $798 + process $group_44 + assign \LK 1'0 + assign \LK { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$800 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $801 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [4] - connect \B \wrpick_INT_o_en_o - connect \Y $801 - end - process $group_385 - assign \wr_pick$800 1'0 - assign \wr_pick$800 $801 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 1 \AA + process $group_45 + assign \AA 1'0 + assign \AA { \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$803 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$803$next - process $group_386 - assign \wr_pick_dly$803$next \wr_pick_dly$803 - assign \wr_pick_dly$803$next \wr_pick$800 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$803$next 1'0 - end + process $group_46 + assign \Rc 1'0 + assign \Rc { \opcode_in [0] } sync init - update \wr_pick_dly$803 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$803 \wr_pick_dly$803$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$804 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $805 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$803 - connect \Y $805 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $807 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$800 - connect \B $805 - connect \Y $807 end - process $group_387 - assign \wr_pick_rise$804 1'0 - assign \wr_pick_rise$804 $807 + process $group_47 + assign \OE 1'0 + assign \OE { \opcode_in [10] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$809 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$810 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$811 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$812 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$813 - process $group_388 - assign \fus_cu_wr__go_i$91 6'000000 - assign \fus_cu_wr__go_i$91 [0] \wr_pick_rise$804 - assign \fus_cu_wr__go_i$91 [5] \wr_pick_rise$809 - assign \fus_cu_wr__go_i$91 [4] \wr_pick_rise$810 - assign \fus_cu_wr__go_i$91 [3] \wr_pick_rise$811 - assign \fus_cu_wr__go_i$91 [2] \wr_pick_rise$812 - assign \fus_cu_wr__go_i$91 [1] \wr_pick_rise$813 + process $group_48 + assign \BD 14'00000000000000 + assign \BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$814 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $815 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$800 - connect \B \wrpick_INT_o_en_o - connect \Y $815 - end - process $group_389 - assign \wp$814 1'0 - assign \wp$814 $815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 3 \BF + process $group_49 + assign \BF 3'000 + assign \BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 5 \addr_en$817 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 5 $818 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $819 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_rego - connect \S \wp$814 - connect \Y $818 - end - process $group_390 - assign \addr_en$817 5'00000 - assign \addr_en$817 $818 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 10 \CR + process $group_50 + assign \CR 10'0000000000 + assign \CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $820 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$92 - connect \B \fus_cu_busy_o$19 - connect \Y $820 - end - process $group_391 - assign \wrflag_div0_o_0 1'0 - assign \wrflag_div0_o_0 $820 + process $group_51 + assign \BB 5'00000 + assign \BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$822 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $823 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [5] - connect \B \wrpick_INT_o_en_o - connect \Y $823 - end - process $group_392 - assign \wr_pick$822 1'0 - assign \wr_pick$822 $823 + process $group_52 + assign \BA 5'00000 + assign \BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$825 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$825$next - process $group_393 - assign \wr_pick_dly$825$next \wr_pick_dly$825 - assign \wr_pick_dly$825$next \wr_pick$822 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$825$next 1'0 - end + process $group_53 + assign \BT 5'00000 + assign \BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init - update \wr_pick_dly$825 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$825 \wr_pick_dly$825$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$826 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $827 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$825 - connect \Y $827 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $829 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$822 - connect \B $827 - connect \Y $829 end - process $group_394 - assign \wr_pick_rise$826 1'0 - assign \wr_pick_rise$826 $829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 8 \FXM + process $group_54 + assign \FXM 8'00000000 + assign \FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$831 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$832 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$833 - process $group_395 - assign \fus_cu_wr__go_i$94 4'0000 - assign \fus_cu_wr__go_i$94 [0] \wr_pick_rise$826 - assign \fus_cu_wr__go_i$94 [1] \wr_pick_rise$831 - assign \fus_cu_wr__go_i$94 [2] \wr_pick_rise$832 - assign \fus_cu_wr__go_i$94 [3] \wr_pick_rise$833 + process $group_55 + assign \BO 5'00000 + assign \BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$834 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $835 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$822 - connect \B \wrpick_INT_o_en_o - connect \Y $835 - end - process $group_396 - assign \wp$834 1'0 - assign \wp$834 $835 + process $group_56 + assign \BI 5'00000 + assign \BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 5 \addr_en$837 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 5 $838 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $839 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_rego - connect \S \wp$834 - connect \Y $838 - end - process $group_397 - assign \addr_en$837 5'00000 - assign \addr_en$837 $838 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 2 \BH + process $group_57 + assign \BH 2'00 + assign \BH { \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $840 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$95 - connect \B \fus_cu_busy_o$22 - connect \Y $840 - end - process $group_398 - assign \wrflag_mul0_o_0 1'0 - assign \wrflag_mul0_o_0 $840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 16 \D + process $group_58 + assign \D 16'0000000000000000 + assign \D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$842 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $843 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [6] - connect \B \wrpick_INT_o_en_o - connect \Y $843 - end - process $group_399 - assign \wr_pick$842 1'0 - assign \wr_pick$842 $843 + process $group_59 + assign \DS 14'00000000000000 + assign \DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$845 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$845$next - process $group_400 - assign \wr_pick_dly$845$next \wr_pick_dly$845 - assign \wr_pick_dly$845$next \wr_pick$842 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$845$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \TO + process $group_60 + assign \TO 5'00000 + assign \TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init - update \wr_pick_dly$845 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$845 \wr_pick_dly$845$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$846 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $847 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$845 - connect \Y $847 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $849 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$842 - connect \B $847 - connect \Y $849 end - process $group_401 - assign \wr_pick_rise$846 1'0 - assign \wr_pick_rise$846 $849 + process $group_61 + assign \BC 5'00000 + assign \BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$851 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$852 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$853 - process $group_402 - assign \fus_cu_wr__go_i$97 4'0000 - assign \fus_cu_wr__go_i$97 [0] \wr_pick_rise$846 - assign \fus_cu_wr__go_i$97 [1] \wr_pick_rise$851 - assign \fus_cu_wr__go_i$97 [2] \wr_pick_rise$852 - assign \fus_cu_wr__go_i$97 [3] \wr_pick_rise$853 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \SH + process $group_62 + assign \SH 5'00000 + assign \SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$854 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $855 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$842 - connect \B \wrpick_INT_o_en_o - connect \Y $855 - end - process $group_403 - assign \wp$854 1'0 - assign \wp$854 $855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \ME + process $group_63 + assign \ME 5'00000 + assign \ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 5 \addr_en$857 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 5 $858 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $859 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_rego - connect \S \wp$854 - connect \Y $858 - end - process $group_404 - assign \addr_en$857 5'00000 - assign \addr_en$857 $858 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \MB + process $group_64 + assign \MB 5'00000 + assign \MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $860 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$98 - connect \B \fus_cu_busy_o$25 - connect \Y $860 - end - process $group_405 - assign \wrflag_shiftrot0_o_0 1'0 - assign \wrflag_shiftrot0_o_0 $860 + process $group_65 + assign \SPR 10'0000000000 + assign \SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$862 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $863 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [7] - connect \B \wrpick_INT_o_en_o - connect \Y $863 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_A + process $group_66 + assign \X_A 1'0 + assign \X_A { \opcode_in [25] } + sync init end - process $group_406 - assign \wr_pick$862 1'0 - assign \wr_pick$862 $863 + process $group_67 + assign \X_BF 3'000 + assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$865 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$865$next - process $group_407 - assign \wr_pick_dly$865$next \wr_pick_dly$865 - assign \wr_pick_dly$865$next \wr_pick$862 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$865$next 1'0 - end + process $group_68 + assign \X_BFA 3'000 + assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } sync init - update \wr_pick_dly$865 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$865 \wr_pick_dly$865$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$866 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $867 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$865 - connect \Y $867 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_BO + process $group_69 + assign \X_BO 5'00000 + assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $869 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$862 - connect \B $867 - connect \Y $869 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \X_CT + process $group_70 + assign \X_CT 4'0000 + assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_408 - assign \wr_pick_rise$866 1'0 - assign \wr_pick_rise$866 $869 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 7 \X_DCMX + process $group_71 + assign \X_DCMX 7'0000000 + assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$871 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$872 - process $group_409 - assign \fus_cu_wr__go_i$100 3'000 - assign \fus_cu_wr__go_i$100 [0] \wr_pick_rise$866 - assign \fus_cu_wr__go_i$100 [1] \wr_pick_rise$871 - assign \fus_cu_wr__go_i$100 [2] \wr_pick_rise$872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \X_DRM + process $group_72 + assign \X_DRM 3'000 + assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$873 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $874 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$862 - connect \B \wrpick_INT_o_en_o - connect \Y $874 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_E + process $group_73 + assign \X_E 1'0 + assign \X_E { \opcode_in [15] } + sync init end - process $group_410 - assign \wp$873 1'0 - assign \wp$873 $874 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \X_E_1 + process $group_74 + assign \X_E_1 4'0000 + assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 5 \addr_en$876 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 5 $877 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $878 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_rego - connect \S \wp$873 - connect \Y $877 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \X_EO + process $group_75 + assign \X_EO 2'00 + assign \X_EO { \opcode_in [20] \opcode_in [19] } + sync init end - process $group_411 - assign \addr_en$876 5'00000 - assign \addr_en$876 $877 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_EO_1 + process $group_76 + assign \X_EO_1 5'00000 + assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_ldst0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $879 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \fus_cu_busy_o$28 - connect \Y $879 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_EX + process $group_77 + assign \X_EX 1'0 + assign \X_EX { \opcode_in [0] } + sync init end - process $group_412 - assign \wrflag_ldst0_o_0 1'0 - assign \wrflag_ldst0_o_0 $879 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_FC + process $group_78 + assign \X_FC 5'00000 + assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$881 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $882 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [8] - connect \B \wrpick_INT_o_en_o - connect \Y $882 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_FRA + process $group_79 + assign \X_FRA 5'00000 + assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_413 - assign \wr_pick$881 1'0 - assign \wr_pick$881 $882 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_FRAp + process $group_80 + assign \X_FRAp 5'00000 + assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$884 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$884$next - process $group_414 - assign \wr_pick_dly$884$next \wr_pick_dly$884 - assign \wr_pick_dly$884$next \wr_pick$881 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$884$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_FRB + process $group_81 + assign \X_FRB 5'00000 + assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init - update \wr_pick_dly$884 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$884 \wr_pick_dly$884$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$885 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $886 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$884 - connect \Y $886 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_FRBp + process $group_82 + assign \X_FRBp 5'00000 + assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $888 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$881 - connect \B $886 - connect \Y $888 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_FRS + process $group_83 + assign \X_FRS 5'00000 + assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_415 - assign \wr_pick_rise$885 1'0 - assign \wr_pick_rise$885 $888 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_FRSp + process $group_84 + assign \X_FRSp 5'00000 + assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$890 - process $group_416 - assign \fus_cu_wr__go_i$102 2'00 - assign \fus_cu_wr__go_i$102 [0] \wr_pick_rise$885 - assign \fus_cu_wr__go_i$102 [1] \wr_pick_rise$890 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_FRT + process $group_85 + assign \X_FRT 5'00000 + assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$891 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $892 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$881 - connect \B \wrpick_INT_o_en_o - connect \Y $892 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_FRTp + process $group_86 + assign \X_FRTp 5'00000 + assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_417 - assign \wp$891 1'0 - assign \wp$891 $892 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \X_IH + process $group_87 + assign \X_IH 3'000 + assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 5 \addr_en$894 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 5 $895 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $896 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_rego - connect \S \wp$891 - connect \Y $895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 8 \X_IMM8 + process $group_88 + assign \X_IMM8 8'00000000 + assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_418 - assign \addr_en$894 5'00000 - assign \addr_en$894 $895 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \X_L + process $group_89 + assign \X_L 2'00 + assign \X_L { \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_ldst0_o_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $897 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ea_ok - connect \B \fus_cu_busy_o$28 - connect \Y $897 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_L_1 + process $group_90 + assign \X_L_1 1'0 + assign \X_L_1 { \opcode_in [21] } + sync init end - process $group_419 - assign \wrflag_ldst0_o_1 1'0 - assign \wrflag_ldst0_o_1 $897 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_L_2 + process $group_91 + assign \X_L_2 1'0 + assign \X_L_2 { \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$899 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $900 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [9] - connect \B \wrpick_INT_o_en_o - connect \Y $900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \X_L_3 + process $group_92 + assign \X_L_3 2'00 + assign \X_L_3 { \opcode_in [17] \opcode_in [16] } + sync init end - process $group_420 - assign \wr_pick$899 1'0 - assign \wr_pick$899 $900 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_MO + process $group_93 + assign \X_MO 5'00000 + assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$902 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$902$next - process $group_421 - assign \wr_pick_dly$902$next \wr_pick_dly$902 - assign \wr_pick_dly$902$next \wr_pick$899 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$902$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_NB + process $group_94 + assign \X_NB 5'00000 + assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init - update \wr_pick_dly$902 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$902 \wr_pick_dly$902$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $903 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$902 - connect \Y $903 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_PRS + process $group_95 + assign \X_PRS 1'0 + assign \X_PRS { \opcode_in [17] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $905 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$899 - connect \B $903 - connect \Y $905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_R + process $group_96 + assign \X_R 1'0 + assign \X_R { \opcode_in [21] } + sync init end - process $group_422 - assign \wr_pick_rise$890 1'0 - assign \wr_pick_rise$890 $905 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_R_1 + process $group_97 + assign \X_R_1 1'0 + assign \X_R_1 { \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$907 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $908 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$899 - connect \B \wrpick_INT_o_en_o - connect \Y $908 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_RA + process $group_98 + assign \X_RA 5'00000 + assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_423 - assign \wp$907 1'0 - assign \wp$907 $908 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_RB + process $group_99 + assign \X_RB 5'00000 + assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 5 \addr_en$910 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 5 $911 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $912 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \pdecode2_ea - connect \S \wp$907 - connect \Y $911 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_Rc + process $group_100 + assign \X_Rc 1'0 + assign \X_Rc { \opcode_in [0] } + sync init end - process $group_424 - assign \addr_en$910 5'00000 - assign \addr_en$910 $911 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \X_RIC + process $group_101 + assign \X_RIC 2'00 + assign \X_RIC { \opcode_in [19] \opcode_in [18] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $913 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $914 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o - connect \B \fus_dest1_o$103 - connect \Y $914 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \X_RM + process $group_102 + assign \X_RM 2'00 + assign \X_RM { \opcode_in [12] \opcode_in [11] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $916 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$105 - connect \B \fus_dest1_o$106 - connect \Y $916 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_RO + process $group_103 + assign \X_RO 1'0 + assign \X_RO { \opcode_in [0] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $918 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$104 - connect \B $916 - connect \Y $918 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_RS + process $group_104 + assign \X_RS 5'00000 + assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $920 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $914 - connect \B $918 - connect \Y $920 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_RSp + process $group_105 + assign \X_RSp 5'00000 + assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $922 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$107 - connect \B \fus_dest1_o$108 - connect \Y $922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_RT + process $group_106 + assign \X_RT 5'00000 + assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 65 $924 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A { \o_ok \fus_o } - connect \B { \ea_ok \fus_ea } - connect \Y $924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_RTp + process $group_107 + assign \X_RTp 5'00000 + assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $926 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A \fus_dest1_o$109 - connect \B $924 - connect \Y $926 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_S + process $group_108 + assign \X_S 5'00000 + assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $928 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $922 - connect \B $926 - connect \Y $928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_SH + process $group_109 + assign \X_SH 5'00000 + assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $930 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $920 - connect \B $928 - connect \Y $930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_SI + process $group_110 + assign \X_SI 5'00000 + assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - connect $913 $930 - process $group_425 - assign \int_dest1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \int_dest1__data_i $913 [63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \X_SP + process $group_111 + assign \X_SP 2'00 + assign \X_SP { \opcode_in [20] \opcode_in [19] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $932 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en - connect \B \addr_en$755 - connect \Y $932 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \X_SR + process $group_112 + assign \X_SR 4'0000 + assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $934 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en$795 - connect \B \addr_en$817 - connect \Y $934 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_SX + process $group_113 + assign \X_SX 1'0 + assign \X_SX { \opcode_in [0] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $936 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en$776 - connect \B $934 - connect \Y $936 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \X_SX_S + process $group_114 + assign \X_SX_S 6'000000 + assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $938 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $932 - connect \B $936 - connect \Y $938 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_T + process $group_115 + assign \X_T 5'00000 + assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $940 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en$837 - connect \B \addr_en$857 - connect \Y $940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \X_TBR + process $group_116 + assign \X_TBR 10'0000000000 + assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $942 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en$894 - connect \B \addr_en$910 - connect \Y $942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_TH + process $group_117 + assign \X_TH 5'00000 + assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $944 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en$876 - connect \B $942 - connect \Y $944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_TO + process $group_118 + assign \X_TO 5'00000 + assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $946 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $940 - connect \B $944 - connect \Y $946 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_TX + process $group_119 + assign \X_TX 1'0 + assign \X_TX { \opcode_in [0] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $948 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $938 - connect \B $946 - connect \Y $948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \X_TX_T + process $group_120 + assign \X_TX_T 6'000000 + assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_426 - assign \int_dest1__addr 5'00000 - assign \int_dest1__addr $948 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \X_U + process $group_121 + assign \X_U 4'0000 + assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $950 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp - connect \B \wp$752 - connect \Y $950 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_UIM + process $group_122 + assign \X_UIM 5'00000 + assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $952 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$792 - connect \B \wp$814 - connect \Y $952 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_VRS + process $group_123 + assign \X_VRS 5'00000 + assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $954 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$773 - connect \B $952 - connect \Y $954 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \X_VRT + process $group_124 + assign \X_VRT 5'00000 + assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $956 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $950 - connect \B $954 - connect \Y $956 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \X_W + process $group_125 + assign \X_W 1'0 + assign \X_W { \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $958 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$834 - connect \B \wp$854 - connect \Y $958 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \X_WC + process $group_126 + assign \X_WC 2'00 + assign \X_WC { \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $960 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$891 - connect \B \wp$907 - connect \Y $960 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \X_XO + process $group_127 + assign \X_XO 10'0000000000 + assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $962 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$873 - connect \B $960 - connect \Y $962 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 8 \X_XO_1 + process $group_128 + assign \X_XO_1 8'00000000 + assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $964 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $958 - connect \B $962 - connect \Y $964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \B_AA + process $group_129 + assign \B_AA 1'0 + assign \B_AA { \opcode_in [1] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $966 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $956 - connect \B $964 - connect \Y $966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 14 \B_BD + process $group_130 + assign \B_BD 14'00000000000000 + assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init end - process $group_427 - assign \int_dest1__wen 1'0 - assign \int_dest1__wen $966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \B_BI + process $group_131 + assign \B_BI 5'00000 + assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $968 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_full_cr_ok - connect \B \fus_cu_busy_o$4 - connect \Y $968 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \B_BO + process $group_132 + assign \B_BO 5'00000 + assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_428 - assign \wrflag_cr0_full_cr_1 1'0 - assign \wrflag_cr0_full_cr_1 $968 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \B_LK + process $group_133 + assign \B_LK 1'0 + assign \B_LK { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $970 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$81 [1] - connect \B \fu_enable [1] - connect \Y $970 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \I_AA + process $group_134 + assign \I_AA 1'0 + assign \I_AA { \opcode_in [1] } + sync init end - process $group_429 - assign \wrpick_CR_full_cr_i 1'0 - assign \wrpick_CR_full_cr_i $970 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 24 \I_LI + process $group_135 + assign \I_LI 24'000000000000000000000000 + assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$972 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $973 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_full_cr_o - connect \B \wrpick_CR_full_cr_en_o - connect \Y $973 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \I_LK + process $group_136 + assign \I_LK 1'0 + assign \I_LK { \opcode_in [0] } + sync init end - process $group_430 - assign \wr_pick$972 1'0 - assign \wr_pick$972 $973 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX3_AX + process $group_137 + assign \XX3_AX 1'0 + assign \XX3_AX { \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$975 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$975$next - process $group_431 - assign \wr_pick_dly$975$next \wr_pick_dly$975 - assign \wr_pick_dly$975$next \wr_pick$972 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$975$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX3_A + process $group_138 + assign \XX3_A 5'00000 + assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init - update \wr_pick_dly$975 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$975 \wr_pick_dly$975$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $976 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$975 - connect \Y $976 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \XX3_AX_A + process $group_139 + assign \XX3_AX_A 6'000000 + assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $978 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$972 - connect \B $976 - connect \Y $978 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \XX3_BF + process $group_140 + assign \XX3_BF 3'000 + assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init end - process $group_432 - assign \wr_pick_rise$750 1'0 - assign \wr_pick_rise$750 $978 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX3_BX + process $group_141 + assign \XX3_BX 1'0 + assign \XX3_BX { \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$980 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $981 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$972 - connect \B \wrpick_CR_full_cr_en_o - connect \Y $981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX3_B + process $group_142 + assign \XX3_B 5'00000 + assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_433 - assign \wp$980 1'0 - assign \wp$980 $981 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \XX3_BX_B + process $group_143 + assign \XX3_BX_B 6'000000 + assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 8 \addr_en$983 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 8 $984 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $985 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B 8'11111111 - connect \S \wp$980 - connect \Y $984 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \XX3_DM + process $group_144 + assign \XX3_DM 2'00 + assign \XX3_DM { \opcode_in [9] \opcode_in [8] } + sync init end - process $group_434 - assign \addr_en$983 8'00000000 - assign \addr_en$983 $984 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX3_Rc + process $group_145 + assign \XX3_Rc 1'0 + assign \XX3_Rc { \opcode_in [10] } sync init end - process $group_435 - assign \cr_full_wr__data_i 32'00000000000000000000000000000000 - assign \cr_full_wr__data_i \fus_dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \XX3_SHW + process $group_146 + assign \XX3_SHW 2'00 + assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } sync init end - process $group_436 - assign \cr_full_wr__wen 8'00000000 - assign \cr_full_wr__wen \addr_en$983 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX3_TX + process $group_147 + assign \XX3_TX 1'0 + assign \XX3_TX { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $986 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok - connect \B \fus_cu_busy_o - connect \Y $986 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX3_T + process $group_148 + assign \XX3_T 5'00000 + assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_437 - assign \wrflag_alu0_cr_a_1 1'0 - assign \wrflag_alu0_cr_a_1 $986 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \XX3_TX_T + process $group_149 + assign \XX3_TX_T 6'000000 + assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $988 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [1] - connect \B \fu_enable [0] - connect \Y $988 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \XX3_XO + process $group_150 + assign \XX3_XO 4'0000 + assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $990 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$81 [2] - connect \B \fu_enable [1] - connect \Y $990 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 8 \XX3_XO_1 + process $group_151 + assign \XX3_XO_1 8'00000000 + assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $992 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [1] - connect \B \fu_enable [4] - connect \Y $992 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 9 \XX3_XO_2 + process $group_152 + assign \XX3_XO_2 9'000000000 + assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $994 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [1] - connect \B \fu_enable [6] - connect \Y $994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX4_AX + process $group_153 + assign \XX4_AX 1'0 + assign \XX4_AX { \opcode_in [2] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $996 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [1] - connect \B \fu_enable [7] - connect \Y $996 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX4_A + process $group_154 + assign \XX4_A 5'00000 + assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $998 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [1] - connect \B \fu_enable [8] - connect \Y $998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \XX4_AX_A + process $group_155 + assign \XX4_AX_A 6'000000 + assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_438 - assign \wrpick_CR_cr_a_i 6'000000 - assign \wrpick_CR_cr_a_i [0] $988 - assign \wrpick_CR_cr_a_i [1] $990 - assign \wrpick_CR_cr_a_i [2] $992 - assign \wrpick_CR_cr_a_i [3] $994 - assign \wrpick_CR_cr_a_i [4] $996 - assign \wrpick_CR_cr_a_i [5] $998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX4_BX + process $group_156 + assign \XX4_BX 1'0 + assign \XX4_BX { \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [0] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX4_B + process $group_157 + assign \XX4_B 5'00000 + assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_439 - assign \wr_pick$1000 1'0 - assign \wr_pick$1000 $1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \XX4_BX_B + process $group_158 + assign \XX4_BX_B 6'000000 + assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1003 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1003$next - process $group_440 - assign \wr_pick_dly$1003$next \wr_pick_dly$1003 - assign \wr_pick_dly$1003$next \wr_pick$1000 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1003$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX4_CX + process $group_159 + assign \XX4_CX 1'0 + assign \XX4_CX { \opcode_in [3] } sync init - update \wr_pick_dly$1003 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1003 \wr_pick_dly$1003$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1004 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1003 - connect \Y $1004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX4_C + process $group_160 + assign \XX4_C 5'00000 + assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1006 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1000 - connect \B $1004 - connect \Y $1006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \XX4_CX_C + process $group_161 + assign \XX4_CX_C 6'000000 + assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init end - process $group_441 - assign \wr_pick_rise$731 1'0 - assign \wr_pick_rise$731 $1006 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX4_TX + process $group_162 + assign \XX4_TX 1'0 + assign \XX4_TX { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1008 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1009 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1000 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1009 - end - process $group_442 - assign \wp$1008 1'0 - assign \wp$1008 $1009 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX4_T + process $group_163 + assign \XX4_T 5'00000 + assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 16 \addr_en$1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $1012 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $1013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_out - connect \Y $1012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \XX4_TX_T + process $group_164 + assign \XX4_TX_T 6'000000 + assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $1014 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $1015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1012 - connect \Y $1014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \XX4_XO + process $group_165 + assign \XX4_XO 2'00 + assign \XX4_XO { \opcode_in [5] \opcode_in [4] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 16 $1016 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1017 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1014 - connect \S \wp$1008 - connect \Y $1016 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XL_BA + process $group_166 + assign \XL_BA 5'00000 + assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_443 - assign \addr_en$1011 16'0000000000000000 - assign \addr_en$1011 $1016 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XL_BB + process $group_167 + assign \XL_BB 5'00000 + assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1018 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$110 - connect \B \fus_cu_busy_o$4 - connect \Y $1018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \XL_BF + process $group_168 + assign \XL_BF 3'000 + assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init end - process $group_444 - assign \wrflag_cr0_cr_a_2 1'0 - assign \wrflag_cr0_cr_a_2 $1018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \XL_BFA + process $group_169 + assign \XL_BFA 3'000 + assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1020 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1021 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [1] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \XL_BH + process $group_170 + assign \XL_BH 2'00 + assign \XL_BH { \opcode_in [12] \opcode_in [11] } + sync init end - process $group_445 - assign \wr_pick$1020 1'0 - assign \wr_pick$1020 $1021 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XL_BI + process $group_171 + assign \XL_BI 5'00000 + assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1023 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1023$next - process $group_446 - assign \wr_pick_dly$1023$next \wr_pick_dly$1023 - assign \wr_pick_dly$1023$next \wr_pick$1020 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1023$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XL_BO + process $group_172 + assign \XL_BO 5'00000 + assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init - update \wr_pick_dly$1023 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1023 \wr_pick_dly$1023$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1024 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1023 - connect \Y $1024 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XL_BO_1 + process $group_173 + assign \XL_BO_1 5'00000 + assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1026 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1020 - connect \B $1024 - connect \Y $1026 + process $group_174 + assign \XL_BT 5'00000 + assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_447 - assign \wr_pick_rise$751 1'0 - assign \wr_pick_rise$751 $1026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XL_LK + process $group_175 + assign \XL_LK 1'0 + assign \XL_LK { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1028 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1029 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1020 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1029 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 15 \XL_OC + process $group_176 + assign \XL_OC 15'000000000000000 + assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_448 - assign \wp$1028 1'0 - assign \wp$1028 $1029 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XL_S + process $group_177 + assign \XL_S 1'0 + assign \XL_S { \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 16 \addr_en$1031 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $1032 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $1033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_out - connect \Y $1032 + process $group_178 + assign \XL_XO 10'0000000000 + assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $1034 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $1035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1032 - connect \Y $1034 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \A_BC + process $group_179 + assign \A_BC 5'00000 + assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 16 $1036 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1037 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1034 - connect \S \wp$1028 - connect \Y $1036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \A_FRA + process $group_180 + assign \A_FRA 5'00000 + assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_449 - assign \addr_en$1031 16'0000000000000000 - assign \addr_en$1031 $1036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \A_FRB + process $group_181 + assign \A_FRB 5'00000 + assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1038 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$111 - connect \B \fus_cu_busy_o$13 - connect \Y $1038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \A_FRC + process $group_182 + assign \A_FRC 5'00000 + assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init end - process $group_450 - assign \wrflag_logical0_cr_a_1 1'0 - assign \wrflag_logical0_cr_a_1 $1038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \A_FRT + process $group_183 + assign \A_FRT 5'00000 + assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1040 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1041 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [2] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1041 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \A_RA + process $group_184 + assign \A_RA 5'00000 + assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_451 - assign \wr_pick$1040 1'0 - assign \wr_pick$1040 $1041 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \A_RB + process $group_185 + assign \A_RB 5'00000 + assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1043 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1043$next - process $group_452 - assign \wr_pick_dly$1043$next \wr_pick_dly$1043 - assign \wr_pick_dly$1043$next \wr_pick$1040 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1043$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \A_Rc + process $group_186 + assign \A_Rc 1'0 + assign \A_Rc { \opcode_in [0] } sync init - update \wr_pick_dly$1043 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1043 \wr_pick_dly$1043$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1044 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1043 - connect \Y $1044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \A_RT + process $group_187 + assign \A_RT 5'00000 + assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1046 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1040 - connect \B $1044 - connect \Y $1046 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \A_XO + process $group_188 + assign \A_XO 5'00000 + assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init end - process $group_453 - assign \wr_pick_rise$790 1'0 - assign \wr_pick_rise$790 $1046 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \D_BF + process $group_189 + assign \D_BF 3'000 + assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1048 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1049 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1040 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1049 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 16 \D_D + process $group_190 + assign \D_D 16'0000000000000000 + assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init end - process $group_454 - assign \wp$1048 1'0 - assign \wp$1048 $1049 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \D_FRS + process $group_191 + assign \D_FRS 5'00000 + assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 16 \addr_en$1051 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $1052 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $1053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_out - connect \Y $1052 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \D_FRT + process $group_192 + assign \D_FRT 5'00000 + assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $1054 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $1055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1052 - connect \Y $1054 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \D_L + process $group_193 + assign \D_L 1'0 + assign \D_L { \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 16 $1056 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1057 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1054 - connect \S \wp$1048 - connect \Y $1056 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \D_RA + process $group_194 + assign \D_RA 5'00000 + assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_455 - assign \addr_en$1051 16'0000000000000000 - assign \addr_en$1051 $1056 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \D_RS + process $group_195 + assign \D_RS 5'00000 + assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1058 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$112 - connect \B \fus_cu_busy_o$19 - connect \Y $1058 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \D_RT + process $group_196 + assign \D_RT 5'00000 + assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_456 - assign \wrflag_div0_cr_a_1 1'0 - assign \wrflag_div0_cr_a_1 $1058 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 16 \D_SI + process $group_197 + assign \D_SI 16'0000000000000000 + assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1060 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1061 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [3] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1061 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \D_TO + process $group_198 + assign \D_TO 5'00000 + assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_457 - assign \wr_pick$1060 1'0 - assign \wr_pick$1060 $1061 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 16 \D_UI + process $group_199 + assign \D_UI 16'0000000000000000 + assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1063 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1063$next - process $group_458 - assign \wr_pick_dly$1063$next \wr_pick_dly$1063 - assign \wr_pick_dly$1063$next \wr_pick$1060 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1063$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \XX2_BF + process $group_200 + assign \XX2_BF 3'000 + assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } sync init - update \wr_pick_dly$1063 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1063 \wr_pick_dly$1063$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1064 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1063 - connect \Y $1064 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX2_BX + process $group_201 + assign \XX2_BX 1'0 + assign \XX2_BX { \opcode_in [1] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1066 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1060 - connect \B $1064 - connect \Y $1066 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX2_B + process $group_202 + assign \XX2_B 5'00000 + assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_459 - assign \wr_pick_rise$831 1'0 - assign \wr_pick_rise$831 $1066 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \XX2_BX_B + process $group_203 + assign \XX2_BX_B 6'000000 + assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1068 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1069 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1060 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1069 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX2_dc + process $group_204 + assign \XX2_dc 1'0 + assign \XX2_dc { \opcode_in [6] } + sync init end - process $group_460 - assign \wp$1068 1'0 - assign \wp$1068 $1069 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX2_dm + process $group_205 + assign \XX2_dm 1'0 + assign \XX2_dm { \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 16 \addr_en$1071 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $1072 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $1073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_out - connect \Y $1072 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX2_dx + process $group_206 + assign \XX2_dx 5'00000 + assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $1074 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $1075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1072 - connect \Y $1074 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 7 \XX2_dc_dm_dx + process $group_207 + assign \XX2_dc_dm_dx 7'0000000 + assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 16 $1076 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1077 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1074 - connect \S \wp$1068 - connect \Y $1076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 7 \XX2_DCMX + process $group_208 + assign \XX2_DCMX 7'0000000 + assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_461 - assign \addr_en$1071 16'0000000000000000 - assign \addr_en$1071 $1076 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX2_EO + process $group_209 + assign \XX2_EO 5'00000 + assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1078 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$113 - connect \B \fus_cu_busy_o$22 - connect \Y $1078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX2_RT + process $group_210 + assign \XX2_RT 5'00000 + assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_462 - assign \wrflag_mul0_cr_a_1 1'0 - assign \wrflag_mul0_cr_a_1 $1078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XX2_TX + process $group_211 + assign \XX2_TX 1'0 + assign \XX2_TX { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1080 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1081 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [4] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1081 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XX2_T + process $group_212 + assign \XX2_T 5'00000 + assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_463 - assign \wr_pick$1080 1'0 - assign \wr_pick$1080 $1081 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \XX2_TX_T + process $group_213 + assign \XX2_TX_T 6'000000 + assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1083 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1083$next - process $group_464 - assign \wr_pick_dly$1083$next \wr_pick_dly$1083 - assign \wr_pick_dly$1083$next \wr_pick$1080 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1083$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \XX2_UIM + process $group_214 + assign \XX2_UIM 4'0000 + assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init - update \wr_pick_dly$1083 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1083 \wr_pick_dly$1083$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1084 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1083 - connect \Y $1084 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \XX2_UIM_1 + process $group_215 + assign \XX2_UIM_1 2'00 + assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1086 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1080 - connect \B $1084 - connect \Y $1086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 7 \XX2_XO + process $group_216 + assign \XX2_XO 7'0000000 + assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } + sync init end - process $group_465 - assign \wr_pick_rise$851 1'0 - assign \wr_pick_rise$851 $1086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 9 \XX2_XO_1 + process $group_217 + assign \XX2_XO_1 9'000000000 + assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1088 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1089 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1080 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \Z22_BF + process $group_218 + assign \Z22_BF 3'000 + assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } + sync init end - process $group_466 - assign \wp$1088 1'0 - assign \wp$1088 $1089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \Z22_DCM + process $group_219 + assign \Z22_DCM 6'000000 + assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 16 \addr_en$1091 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $1092 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $1093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_out - connect \Y $1092 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \Z22_DGM + process $group_220 + assign \Z22_DGM 6'000000 + assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $1094 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $1095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1092 - connect \Y $1094 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z22_FRA + process $group_221 + assign \Z22_FRA 5'00000 + assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 16 $1096 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1097 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1094 - connect \S \wp$1088 - connect \Y $1096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z22_FRAp + process $group_222 + assign \Z22_FRAp 5'00000 + assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_467 - assign \addr_en$1091 16'0000000000000000 - assign \addr_en$1091 $1096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z22_FRT + process $group_223 + assign \Z22_FRT 5'00000 + assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1098 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$114 - connect \B \fus_cu_busy_o$25 - connect \Y $1098 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z22_FRTp + process $group_224 + assign \Z22_FRTp 5'00000 + assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_468 - assign \wrflag_shiftrot0_cr_a_1 1'0 - assign \wrflag_shiftrot0_cr_a_1 $1098 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \Z22_Rc + process $group_225 + assign \Z22_Rc 1'0 + assign \Z22_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [5] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \Z22_SH + process $group_226 + assign \Z22_SH 6'000000 + assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } + sync init end - process $group_469 - assign \wr_pick$1100 1'0 - assign \wr_pick$1100 $1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 9 \Z22_XO + process $group_227 + assign \Z22_XO 9'000000000 + assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1103$next - process $group_470 - assign \wr_pick_dly$1103$next \wr_pick_dly$1103 - assign \wr_pick_dly$1103$next \wr_pick$1100 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1103$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \EVS_BFA + process $group_228 + assign \EVS_BFA 3'000 + assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init - update \wr_pick_dly$1103 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1103 \wr_pick_dly$1103$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1104 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1103 - connect \Y $1104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \XFX_BHRBE + process $group_229 + assign \XFX_BHRBE 10'0000000000 + assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1106 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1100 - connect \B $1104 - connect \Y $1106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XFX_DUI + process $group_230 + assign \XFX_DUI 5'00000 + assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_471 - assign \wr_pick_rise$871 1'0 - assign \wr_pick_rise$871 $1106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \XFX_DUIS + process $group_231 + assign \XFX_DUIS 10'0000000000 + assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1100 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 8 \XFX_FXM + process $group_232 + assign \XFX_FXM 8'00000000 + assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } + sync init end - process $group_472 - assign \wp$1108 1'0 - assign \wp$1108 $1109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XFX_RS + process $group_233 + assign \XFX_RS 5'00000 + assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 16 \addr_en$1111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 4 $1112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sub $1113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \pdecode2_cr_out - connect \Y $1112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XFX_RT + process $group_234 + assign \XFX_RT 5'00000 + assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - wire width 16 $1114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:141" - cell $sshl $1115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1112 - connect \Y $1114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \XFX_SPR + process $group_235 + assign \XFX_SPR 10'0000000000 + assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 16 $1116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1117 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1114 - connect \S \wp$1108 - connect \Y $1116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \XFX_XO + process $group_236 + assign \XFX_XO 10'0000000000 + assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init end - process $group_473 - assign \addr_en$1111 16'0000000000000000 - assign \addr_en$1111 $1116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \DX_d0 + process $group_237 + assign \DX_d0 10'0000000000 + assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $1118 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest3_o - connect \B \fus_dest2_o$116 - connect \Y $1118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DX_d1 + process $group_238 + assign \DX_d1 5'00000 + assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1120 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$115 - connect \B $1118 - connect \Y $1120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \DX_d2 + process $group_239 + assign \DX_d2 1'0 + assign \DX_d2 { \opcode_in [0] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $1122 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$118 - connect \B \fus_dest2_o$119 - connect \Y $1122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 16 \DX_d0_d1_d2 + process $group_240 + assign \DX_d0_d1_d2 16'0000000000000000 + assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1124 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$117 - connect \B $1122 - connect \Y $1124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DX_RT + process $group_241 + assign \DX_RT 5'00000 + assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1126 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $1120 - connect \B $1124 - connect \Y $1126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DX_XO + process $group_242 + assign \DX_XO 5'00000 + assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init end - process $group_474 - assign \cr_data_i 4'0000 - assign \cr_data_i $1126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 12 \DQ_DQ + process $group_243 + assign \DQ_DQ 12'000000000000 + assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1128 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $1129 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1031 - connect \B \addr_en$1051 - connect \Y $1129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \DQ_PT + process $group_244 + assign \DQ_PT 4'0000 + assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1131 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1011 - connect \B $1129 - connect \Y $1131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DQ_RA + process $group_245 + assign \DQ_RA 5'00000 + assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $1133 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1091 - connect \B \addr_en$1111 - connect \Y $1133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DQ_RTp + process $group_246 + assign \DQ_RTp 5'00000 + assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1135 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1071 - connect \B $1133 - connect \Y $1135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \DQ_SX + process $group_247 + assign \DQ_SX 1'0 + assign \DQ_SX { \opcode_in [3] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1137 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A $1131 - connect \B $1135 - connect \Y $1137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DQ_S + process $group_248 + assign \DQ_S 5'00000 + assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - connect $1128 $1137 - process $group_475 - assign \cr_wen 8'00000000 - assign \cr_wen $1128 [7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \DQ_SX_S + process $group_249 + assign \DQ_SX_S 6'000000 + assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok - connect \B \fus_cu_busy_o - connect \Y $1139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \DQ_TX + process $group_250 + assign \DQ_TX 1'0 + assign \DQ_TX { \opcode_in [3] } + sync init end - process $group_476 - assign \wrflag_alu0_xer_ca_2 1'0 - assign \wrflag_alu0_xer_ca_2 $1139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DQ_T + process $group_251 + assign \DQ_T 5'00000 + assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [2] - connect \B \fu_enable [0] - connect \Y $1141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \DQ_TX_T + process $group_252 + assign \DQ_TX_T 6'000000 + assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [2] - connect \B \fu_enable [4] - connect \Y $1143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \DQ_XO + process $group_253 + assign \DQ_XO 3'000 + assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [5] - connect \B \fu_enable [5] - connect \Y $1145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 14 \DS_DS + process $group_254 + assign \DS_DS 14'00000000000000 + assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [2] - connect \B \fu_enable [8] - connect \Y $1147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DS_FRSp + process $group_255 + assign \DS_FRSp 5'00000 + assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_477 - assign \wrpick_XER_xer_ca_i 4'0000 - assign \wrpick_XER_xer_ca_i [0] $1141 - assign \wrpick_XER_xer_ca_i [1] $1143 - assign \wrpick_XER_xer_ca_i [2] $1145 - assign \wrpick_XER_xer_ca_i [3] $1147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DS_FRTp + process $group_256 + assign \DS_FRTp 5'00000 + assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [0] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DS_RA + process $group_257 + assign \DS_RA 5'00000 + assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_478 - assign \wr_pick$1149 1'0 - assign \wr_pick$1149 $1150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DS_RS + process $group_258 + assign \DS_RS 5'00000 + assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1152 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1152$next - process $group_479 - assign \wr_pick_dly$1152$next \wr_pick_dly$1152 - assign \wr_pick_dly$1152$next \wr_pick$1149 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1152$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DS_RSp + process $group_259 + assign \DS_RSp 5'00000 + assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init - update \wr_pick_dly$1152 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1152 \wr_pick_dly$1152$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1153 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1152 - connect \Y $1153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DS_RT + process $group_260 + assign \DS_RT 5'00000 + assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1155 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1149 - connect \B $1153 - connect \Y $1155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DS_VRS + process $group_261 + assign \DS_VRS 5'00000 + assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_480 - assign \wr_pick_rise$732 1'0 - assign \wr_pick_rise$732 $1155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DS_VRT + process $group_262 + assign \DS_VRT 5'00000 + assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1149 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \DS_XO + process $group_263 + assign \DS_XO 2'00 + assign \DS_XO { \opcode_in [1] \opcode_in [0] } + sync init end - process $group_481 - assign \wp$1157 1'0 - assign \wp$1157 $1158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VX_EO + process $group_264 + assign \VX_EO 5'00000 + assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 2 \addr_en$1160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 2 $1161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1162 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1157 - connect \Y $1161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \VX_PS + process $group_265 + assign \VX_PS 1'0 + assign \VX_PS { \opcode_in [9] } + sync init end - process $group_482 - assign \addr_en$1160 2'00 - assign \addr_en$1160 $1161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VX_RA + process $group_266 + assign \VX_RA 5'00000 + assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_logical0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$120 - connect \B \fus_cu_busy_o$13 - connect \Y $1163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VX_RT + process $group_267 + assign \VX_RT 5'00000 + assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_483 - assign \wrflag_logical0_xer_ca_2 1'0 - assign \wrflag_logical0_xer_ca_2 $1163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VX_SIM + process $group_268 + assign \VX_SIM 5'00000 + assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [1] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VX_UIM + process $group_269 + assign \VX_UIM 5'00000 + assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_484 - assign \wr_pick$1165 1'0 - assign \wr_pick$1165 $1166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \VX_UIM_1 + process $group_270 + assign \VX_UIM_1 4'0000 + assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1168 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1168$next - process $group_485 - assign \wr_pick_dly$1168$next \wr_pick_dly$1168 - assign \wr_pick_dly$1168$next \wr_pick$1165 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1168$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \VX_UIM_2 + process $group_271 + assign \VX_UIM_2 3'000 + assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init - update \wr_pick_dly$1168 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1168 \wr_pick_dly$1168$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1168 - connect \Y $1169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \VX_UIM_3 + process $group_272 + assign \VX_UIM_3 2'00 + assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1171 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1165 - connect \B $1169 - connect \Y $1171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VX_VRA + process $group_273 + assign \VX_VRA 5'00000 + assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_486 - assign \wr_pick_rise$791 1'0 - assign \wr_pick_rise$791 $1171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VX_VRB + process $group_274 + assign \VX_VRB 5'00000 + assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1165 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VX_VRT + process $group_275 + assign \VX_VRT 5'00000 + assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_487 - assign \wp$1173 1'0 - assign \wp$1173 $1174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \VX_XO + process $group_276 + assign \VX_XO 10'0000000000 + assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 2 \addr_en$1176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 2 $1177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1178 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1173 - connect \Y $1177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 11 \VX_XO_1 + process $group_277 + assign \VX_XO_1 11'00000000000 + assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init end - process $group_488 - assign \addr_en$1176 2'00 - assign \addr_en$1176 $1177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 8 \XFL_FLM + process $group_278 + assign \XFL_FLM 8'00000000 + assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$121 - connect \B \fus_cu_busy_o$16 - connect \Y $1179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XFL_FRB + process $group_279 + assign \XFL_FRB 5'00000 + assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_489 - assign \wrflag_spr0_xer_ca_5 1'0 - assign \wrflag_spr0_xer_ca_5 $1179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XFL_L + process $group_280 + assign \XFL_L 1'0 + assign \XFL_L { \opcode_in [25] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [2] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XFL_Rc + process $group_281 + assign \XFL_Rc 1'0 + assign \XFL_Rc { \opcode_in [0] } + sync init end - process $group_490 - assign \wr_pick$1181 1'0 - assign \wr_pick$1181 $1182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XFL_W + process $group_282 + assign \XFL_W 1'0 + assign \XFL_W { \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1184 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1184$next - process $group_491 - assign \wr_pick_dly$1184$next \wr_pick_dly$1184 - assign \wr_pick_dly$1184$next \wr_pick$1181 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1184$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \XFL_XO + process $group_283 + assign \XFL_XO 10'0000000000 + assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init - update \wr_pick_dly$1184 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1184 \wr_pick_dly$1184$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1185 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1184 - connect \Y $1185 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z23_FRA + process $group_284 + assign \Z23_FRA 5'00000 + assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1187 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1181 - connect \B $1185 - connect \Y $1187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z23_FRAp + process $group_285 + assign \Z23_FRAp 5'00000 + assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_492 - assign \wr_pick_rise$809 1'0 - assign \wr_pick_rise$809 $1187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z23_FRB + process $group_286 + assign \Z23_FRB 5'00000 + assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1181 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z23_FRBp + process $group_287 + assign \Z23_FRBp 5'00000 + assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_493 - assign \wp$1189 1'0 - assign \wp$1189 $1190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z23_FRT + process $group_288 + assign \Z23_FRT 5'00000 + assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 2 \addr_en$1192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 2 $1193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1194 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1189 - connect \Y $1193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z23_FRTp + process $group_289 + assign \Z23_FRTp 5'00000 + assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_494 - assign \addr_en$1192 2'00 - assign \addr_en$1192 $1193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \Z23_R + process $group_290 + assign \Z23_R 1'0 + assign \Z23_R { \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$122 - connect \B \fus_cu_busy_o$25 - connect \Y $1195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \Z23_Rc + process $group_291 + assign \Z23_Rc 1'0 + assign \Z23_Rc { \opcode_in [0] } + sync init end - process $group_495 - assign \wrflag_shiftrot0_xer_ca_2 1'0 - assign \wrflag_shiftrot0_xer_ca_2 $1195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \Z23_RMC + process $group_292 + assign \Z23_RMC 2'00 + assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [3] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \Z23_TE + process $group_293 + assign \Z23_TE 5'00000 + assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_496 - assign \wr_pick$1197 1'0 - assign \wr_pick$1197 $1198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 8 \Z23_XO + process $group_294 + assign \Z23_XO 8'00000000 + assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1200$next - process $group_497 - assign \wr_pick_dly$1200$next \wr_pick_dly$1200 - assign \wr_pick_dly$1200$next \wr_pick$1197 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1200$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \MDS_IB + process $group_295 + assign \MDS_IB 5'00000 + assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init - update \wr_pick_dly$1200 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1200 \wr_pick_dly$1200$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1201 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1200 - connect \Y $1201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \MDS_IS + process $group_296 + assign \MDS_IS 5'00000 + assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1203 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1197 - connect \B $1201 - connect \Y $1203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \MDS_mb + process $group_297 + assign \MDS_mb 6'000000 + assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init end - process $group_498 - assign \wr_pick_rise$872 1'0 - assign \wr_pick_rise$872 $1203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \MDS_me + process $group_298 + assign \MDS_me 6'000000 + assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1197 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \MDS_RA + process $group_299 + assign \MDS_RA 5'00000 + assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_499 - assign \wp$1205 1'0 - assign \wp$1205 $1206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \MDS_RB + process $group_300 + assign \MDS_RB 5'00000 + assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 2 \addr_en$1208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 2 $1209 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1210 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1205 - connect \Y $1209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \MDS_Rc + process $group_301 + assign \MDS_Rc 1'0 + assign \MDS_Rc { \opcode_in [0] } + sync init end - process $group_500 - assign \addr_en$1208 2'00 - assign \addr_en$1208 $1209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \MDS_RS + process $group_302 + assign \MDS_RS 5'00000 + assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1211 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$123 - connect \B \fus_dest3_o$124 - connect \Y $1211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \MDS_XBI + process $group_303 + assign \MDS_XBI 4'0000 + assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1213 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest6_o - connect \B \fus_dest3_o$125 - connect \Y $1213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \MDS_XBI_1 + process $group_304 + assign \MDS_XBI_1 4'0000 + assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1215 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $1211 - connect \B $1213 - connect \Y $1215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \MDS_XO + process $group_305 + assign \MDS_XO 4'0000 + assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init end - process $group_501 - assign \xer_data_i 2'00 - assign \xer_data_i $1215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 7 \SC_LEV + process $group_306 + assign \SC_LEV 7'0000000 + assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1217 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1218 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en$1160 - connect \B \addr_en$1176 - connect \Y $1218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \SC_XO + process $group_307 + assign \SC_XO 1'0 + assign \SC_XO { \opcode_in [1] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1220 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en$1192 - connect \B \addr_en$1208 - connect \Y $1220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \SC_XO_1 + process $group_308 + assign \SC_XO_1 2'00 + assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1222 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $1218 - connect \B $1220 - connect \Y $1222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \M_MB + process $group_309 + assign \M_MB 5'00000 + assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $1224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A $1222 - connect \Y $1217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \M_ME + process $group_310 + assign \M_ME 5'00000 + assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init end - process $group_502 - assign \xer_wen 3'000 - assign \xer_wen $1217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \M_RA + process $group_311 + assign \M_RA 5'00000 + assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1225 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok - connect \B \fus_cu_busy_o - connect \Y $1225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \M_RB + process $group_312 + assign \M_RB 5'00000 + assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_503 - assign \wrflag_alu0_xer_ov_3 1'0 - assign \wrflag_alu0_xer_ov_3 $1225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \M_Rc + process $group_313 + assign \M_Rc 1'0 + assign \M_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1227 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [3] - connect \B \fu_enable [0] - connect \Y $1227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \M_RS + process $group_314 + assign \M_RS 5'00000 + assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [4] - connect \B \fu_enable [5] - connect \Y $1229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \M_SH + process $group_315 + assign \M_SH 5'00000 + assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1231 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [2] - connect \B \fu_enable [6] - connect \Y $1231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \MD_mb + process $group_316 + assign \MD_mb 6'000000 + assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1233 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [2] - connect \B \fu_enable [7] - connect \Y $1233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \MD_me + process $group_317 + assign \MD_me 6'000000 + assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } + sync init end - process $group_504 - assign \wrpick_XER_xer_ov_i 4'0000 - assign \wrpick_XER_xer_ov_i [0] $1227 - assign \wrpick_XER_xer_ov_i [1] $1229 - assign \wrpick_XER_xer_ov_i [2] $1231 - assign \wrpick_XER_xer_ov_i [3] $1233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \MD_RA + process $group_318 + assign \MD_RA 5'00000 + assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1235 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [0] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \MD_Rc + process $group_319 + assign \MD_Rc 1'0 + assign \MD_Rc { \opcode_in [0] } + sync init end - process $group_505 - assign \wr_pick$1235 1'0 - assign \wr_pick$1235 $1236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \MD_RS + process $group_320 + assign \MD_RS 5'00000 + assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1238 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1238$next - process $group_506 - assign \wr_pick_dly$1238$next \wr_pick_dly$1238 - assign \wr_pick_dly$1238$next \wr_pick$1235 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1238$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \MD_sh + process $group_321 + assign \MD_sh 6'000000 + assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init - update \wr_pick_dly$1238 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1238 \wr_pick_dly$1238$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1239 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1238 - connect \Y $1239 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \MD_XO + process $group_322 + assign \MD_XO 3'000 + assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1241 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1235 - connect \B $1239 - connect \Y $1241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \all_OPCD + process $group_323 + assign \all_OPCD 6'000000 + assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } + sync init end - process $group_507 - assign \wr_pick_rise$733 1'0 - assign \wr_pick_rise$733 $1241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \all_PO + process $group_324 + assign \all_PO 6'000000 + assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1243 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1235 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XO_OE + process $group_325 + assign \XO_OE 1'0 + assign \XO_OE { \opcode_in [10] } + sync init end - process $group_508 - assign \wp$1243 1'0 - assign \wp$1243 $1244 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XO_RA + process $group_326 + assign \XO_RA 5'00000 + assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 3 \addr_en$1246 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 3 $1247 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1248 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1243 - connect \Y $1247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XO_RB + process $group_327 + assign \XO_RB 5'00000 + assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_509 - assign \addr_en$1246 3'000 - assign \addr_en$1246 $1247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XO_Rc + process $group_328 + assign \XO_Rc 1'0 + assign \XO_Rc { \opcode_in [0] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$126 - connect \B \fus_cu_busy_o$16 - connect \Y $1249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XO_RT + process $group_329 + assign \XO_RT 5'00000 + assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_510 - assign \wrflag_spr0_xer_ov_4 1'0 - assign \wrflag_spr0_xer_ov_4 $1249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 9 \XO_XO + process $group_330 + assign \XO_XO 9'000000000 + assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1252 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [1] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DQE_RA + process $group_331 + assign \DQE_RA 5'00000 + assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_511 - assign \wr_pick$1251 1'0 - assign \wr_pick$1251 $1252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \DQE_RT + process $group_332 + assign \DQE_RT 5'00000 + assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1254 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1254$next - process $group_512 - assign \wr_pick_dly$1254$next \wr_pick_dly$1254 - assign \wr_pick_dly$1254$next \wr_pick$1251 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1254$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 2 \DQE_XO + process $group_333 + assign \DQE_XO 2'00 + assign \DQE_XO { \opcode_in [1] \opcode_in [0] } sync init - update \wr_pick_dly$1254 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1254 \wr_pick_dly$1254$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1255 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1254 - connect \Y $1255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \TX_RA + process $group_334 + assign \TX_RA 5'00000 + assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1257 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1251 - connect \B $1255 - connect \Y $1257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \TX_UI + process $group_335 + assign \TX_UI 5'00000 + assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_513 - assign \wr_pick_rise$810 1'0 - assign \wr_pick_rise$810 $1257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \TX_XBI + process $group_336 + assign \TX_XBI 4'0000 + assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1259 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1260 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1251 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \TX_XO + process $group_337 + assign \TX_XO 6'000000 + assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } + sync init end - process $group_514 - assign \wp$1259 1'0 - assign \wp$1259 $1260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VA_RA + process $group_338 + assign \VA_RA 5'00000 + assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 3 \addr_en$1262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 3 $1263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1264 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1259 - connect \Y $1263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VA_RB + process $group_339 + assign \VA_RB 5'00000 + assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_515 - assign \addr_en$1262 3'000 - assign \addr_en$1262 $1263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VA_RC + process $group_340 + assign \VA_RC 5'00000 + assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$127 - connect \B \fus_cu_busy_o$19 - connect \Y $1265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VA_RT + process $group_341 + assign \VA_RT 5'00000 + assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - process $group_516 - assign \wrflag_div0_xer_ov_2 1'0 - assign \wrflag_div0_xer_ov_2 $1265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 4 \VA_SHB + process $group_342 + assign \VA_SHB 4'0000 + assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [2] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VA_VRA + process $group_343 + assign \VA_VRA 5'00000 + assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } + sync init end - process $group_517 - assign \wr_pick$1267 1'0 - assign \wr_pick$1267 $1268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VA_VRB + process $group_344 + assign \VA_VRB 5'00000 + assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1270 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1270$next - process $group_518 - assign \wr_pick_dly$1270$next \wr_pick_dly$1270 - assign \wr_pick_dly$1270$next \wr_pick$1267 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1270$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VA_VRC + process $group_345 + assign \VA_VRC 5'00000 + assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } sync init - update \wr_pick_dly$1270 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1270 \wr_pick_dly$1270$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1271 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1270 - connect \Y $1271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VA_VRT + process $group_346 + assign \VA_VRT 5'00000 + assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1273 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1267 - connect \B $1271 - connect \Y $1273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \VA_XO + process $group_347 + assign \VA_XO 6'000000 + assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init end - process $group_519 - assign \wr_pick_rise$832 1'0 - assign \wr_pick_rise$832 $1273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XS_RA + process $group_348 + assign \XS_RA 5'00000 + assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1275 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1267 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \XS_Rc + process $group_349 + assign \XS_Rc 1'0 + assign \XS_Rc { \opcode_in [0] } + sync init end - process $group_520 - assign \wp$1275 1'0 - assign \wp$1275 $1276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \XS_RS + process $group_350 + assign \XS_RS 5'00000 + assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 3 \addr_en$1278 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 3 $1279 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1280 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1275 - connect \Y $1279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 6 \XS_sh + process $group_351 + assign \XS_sh 6'000000 + assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_521 - assign \addr_en$1278 3'000 - assign \addr_en$1278 $1279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 9 \XS_XO + process $group_352 + assign \XS_XO 9'000000000 + assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1281 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$128 - connect \B \fus_cu_busy_o$22 - connect \Y $1281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 1 \VC_Rc + process $group_353 + assign \VC_Rc 1'0 + assign \VC_Rc { \opcode_in [10] } + sync init end - process $group_522 - assign \wrflag_mul0_xer_ov_2 1'0 - assign \wrflag_mul0_xer_ov_2 $1281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VC_VRA + process $group_354 + assign \VC_VRA 5'00000 + assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1283 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [3] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VC_VRB + process $group_355 + assign \VC_VRB 5'00000 + assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } + sync init end - process $group_523 - assign \wr_pick$1283 1'0 - assign \wr_pick$1283 $1284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \VC_VRT + process $group_356 + assign \VC_VRT 5'00000 + assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1286 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1286$next - process $group_524 - assign \wr_pick_dly$1286$next \wr_pick_dly$1286 - assign \wr_pick_dly$1286$next \wr_pick$1283 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1286$next 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \VC_XO + process $group_357 + assign \VC_XO 10'0000000000 + assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_a.sprmap" +module \sprmap + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" + wire width 10 input 0 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" + wire width 10 output 1 \spr_o + process $group_0 + assign \spr_o 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61" + switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000000001 + assign \spr_o 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000000011 + assign \spr_o 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000001000 + assign \spr_o 10'0000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000001001 + assign \spr_o 10'0000000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000001101 + assign \spr_o 10'0000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000010001 + assign \spr_o 10'0000000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000010010 + assign \spr_o 10'0000000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000010011 + assign \spr_o 10'0000000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000010110 + assign \spr_o 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000011010 + assign \spr_o 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000011011 + assign \spr_o 10'0000001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000011100 + assign \spr_o 10'0000001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000011101 + assign \spr_o 10'0000001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000110000 + assign \spr_o 10'0000001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000111101 + assign \spr_o 10'0000001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010000000 + assign \spr_o 10'0000001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010000001 + assign \spr_o 10'0000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010000010 + assign \spr_o 10'0000010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010000011 + assign \spr_o 10'0000010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010001000 + assign \spr_o 10'0000010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010010000 + assign \spr_o 10'0000010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010011000 + assign \spr_o 10'0000010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010011001 + assign \spr_o 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010011101 + assign \spr_o 10'0000010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010011110 + assign \spr_o 10'0000011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010011111 + assign \spr_o 10'0000011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010110000 + assign \spr_o 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010110100 + assign \spr_o 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010111010 + assign \spr_o 10'0000011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010111011 + assign \spr_o 10'0000011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010111100 + assign \spr_o 10'0000011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010111110 + assign \spr_o 10'0000011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100000000 + assign \spr_o 10'0000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100000011 + assign \spr_o 10'0000100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100001100 + assign \spr_o 10'0000100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100001101 + assign \spr_o 10'0000100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100010000 + assign \spr_o 10'0000100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100010001 + assign \spr_o 10'0000100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100010010 + assign \spr_o 10'0000100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100010011 + assign \spr_o 10'0000100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100011011 + assign \spr_o 10'0000101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100011100 + assign \spr_o 10'0000101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100011101 + assign \spr_o 10'0000101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100011110 + assign \spr_o 10'0000101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100011111 + assign \spr_o 10'0000101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110000 + assign \spr_o 10'0000101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110001 + assign \spr_o 10'0000101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110010 + assign \spr_o 10'0000101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110011 + assign \spr_o 10'0000110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110100 + assign \spr_o 10'0000110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110101 + assign \spr_o 10'0000110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110110 + assign \spr_o 10'0000110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100111001 + assign \spr_o 10'0000110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100111010 + assign \spr_o 10'0000110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100111011 + assign \spr_o 10'0000110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100111110 + assign \spr_o 10'0000110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100111111 + assign \spr_o 10'0000111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0101010000 + assign \spr_o 10'0000111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0101010001 + assign \spr_o 10'0000111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0101010010 + assign \spr_o 10'0000111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0101010011 + assign \spr_o 10'0000111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0101011101 + assign \spr_o 10'0000111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0110111110 + assign \spr_o 10'0000111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0111010000 + assign \spr_o 10'0000111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000000 + assign \spr_o 10'0001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000001 + assign \spr_o 10'0001000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000010 + assign \spr_o 10'0001000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000011 + assign \spr_o 10'0001000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000100 + assign \spr_o 10'0001000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000101 + assign \spr_o 10'0001000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000110 + assign \spr_o 10'0001000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000111 + assign \spr_o 10'0001000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100001000 + assign \spr_o 10'0001001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100001011 + assign \spr_o 10'0001001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100001100 + assign \spr_o 10'0001001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100001101 + assign \spr_o 10'0001001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100001110 + assign \spr_o 10'0001001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010000 + assign \spr_o 10'0001001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010001 + assign \spr_o 10'0001001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010010 + assign \spr_o 10'0001001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010011 + assign \spr_o 10'0001010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010100 + assign \spr_o 10'0001010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010101 + assign \spr_o 10'0001010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010110 + assign \spr_o 10'0001010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010111 + assign \spr_o 10'0001010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100011000 + assign \spr_o 10'0001010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100011011 + assign \spr_o 10'0001010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100011100 + assign \spr_o 10'0001010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100011101 + assign \spr_o 10'0001011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100011110 + assign \spr_o 10'0001011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100000 + assign \spr_o 10'0001011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100001 + assign \spr_o 10'0001011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100010 + assign \spr_o 10'0001011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100011 + assign \spr_o 10'0001011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100100 + assign \spr_o 10'0001011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100101 + assign \spr_o 10'0001011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100110 + assign \spr_o 10'0001100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100101000 + assign \spr_o 10'0001100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100101001 + assign \spr_o 10'0001100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100101010 + assign \spr_o 10'0001100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100101011 + assign \spr_o 10'0001100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100101111 + assign \spr_o 10'0001100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100110000 + assign \spr_o 10'0001100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100110111 + assign \spr_o 10'0001100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1101010000 + assign \spr_o 10'0001101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1101010001 + assign \spr_o 10'0001101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1101010111 + assign \spr_o 10'0001101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1110000000 + assign \spr_o 10'0001101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1110000010 + assign \spr_o 10'0001101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1111111111 + assign \spr_o 10'0001101101 end sync init - update \wr_pick_dly$1286 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1286 \wr_pick_dly$1286$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1287 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1288 - parameter \A_SIGNED 0 - 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attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute 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attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" 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attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 5 \spr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 6 \spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 7 \fast_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 8 \fast_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 9 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 10 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 11 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 10 input 12 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 input 13 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" + wire width 10 \sprmap_spr_o + cell \sprmap \sprmap + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o end - process $group_528 - assign \xer_data_i$153 2'00 - assign \xer_data_i$153 $1301 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 5 \ra + process $group_0 + assign \ra 5'00000 + assign \ra \RA sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $1303 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1246 - connect \B \addr_en$1262 - connect \Y $1303 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $1305 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + cell $eq $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1278 - connect \B \addr_en$1294 - connect \Y $1305 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1307 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" + cell $eq $4 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $1303 - connect \B $1305 - connect \Y $1307 - end - process $group_529 - assign \xer_wen$154 3'000 - assign \xer_wen$154 $1307 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1309 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok - connect \B \fus_cu_busy_o - connect \Y $1309 - end - process $group_530 - assign \wrflag_alu0_xer_so_4 1'0 - assign \wrflag_alu0_xer_so_4 $1309 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1311 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [4] - connect \B \fu_enable [0] - connect \Y $1311 + connect \A \sel_in + connect \B 3'010 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1313 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + cell $ne $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [3] - connect \B \fu_enable [5] - connect \Y $1313 + connect \A \ra + connect \B 5'00000 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1315 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + cell $and $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [3] - connect \B \fu_enable [6] - connect \Y $1315 + connect \A $3 + connect \B $5 + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1317 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + cell $or $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [3] - connect \B \fu_enable [7] - connect \Y $1317 - end - process $group_531 - assign \wrpick_XER_xer_so_i 4'0000 - assign \wrpick_XER_xer_so_i [0] $1311 - assign \wrpick_XER_xer_so_i [1] $1313 - assign \wrpick_XER_xer_so_i [2] $1315 - assign \wrpick_XER_xer_so_i [3] $1317 - sync init + connect \A $1 + connect \B $7 + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1319 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1320 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $eq $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [0] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1320 - end - process $group_532 - assign \wr_pick$1319 1'0 - assign \wr_pick$1319 $1320 - sync init + connect \A \sel_in + connect \B 3'100 + connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1322 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1322$next - process $group_533 - assign \wr_pick_dly$1322$next \wr_pick_dly$1322 - assign \wr_pick_dly$1322$next \wr_pick$1319 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + process $group_1 + assign \reg_a 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" case 1'1 - assign \wr_pick_dly$1322$next 1'0 + assign \reg_a \ra end - sync init - update \wr_pick_dly$1322 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1322 \wr_pick_dly$1322$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1323 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1322 - connect \Y $1323 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1325 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1319 - connect \B $1323 - connect \Y $1325 - end - process $group_534 - assign \wr_pick_rise$734 1'0 - assign \wr_pick_rise$734 $1325 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1327 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1328 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1319 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1328 - end - process $group_535 - assign \wp$1327 1'0 - assign \wp$1327 $1328 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 1 \addr_en$1330 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 1 $1331 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1332 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1327 - connect \Y $1331 - end - process $group_536 - assign \addr_en$1330 1'0 - assign \addr_en$1330 $1331 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1333 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$131 - connect \B \fus_cu_busy_o$16 - connect \Y $1333 - end - process $group_537 - assign \wrflag_spr0_xer_so_3 1'0 - assign \wrflag_spr0_xer_so_3 $1333 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1335 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1336 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [1] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1336 - end - process $group_538 - assign \wr_pick$1335 1'0 - assign \wr_pick$1335 $1336 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1338 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1338$next - process $group_539 - assign \wr_pick_dly$1338$next \wr_pick_dly$1338 - assign \wr_pick_dly$1338$next \wr_pick$1335 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch { $11 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" case 1'1 - assign \wr_pick_dly$1338$next 1'0 + assign \reg_a \RS end - sync init - update \wr_pick_dly$1338 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1338 \wr_pick_dly$1338$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1339 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1338 - connect \Y $1339 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1341 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1335 - connect \B $1339 - connect \Y $1341 - end - process $group_540 - assign \wr_pick_rise$811 1'0 - assign \wr_pick_rise$811 $1341 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1343 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1344 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + cell $eq $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \wr_pick$1335 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1344 - end - process $group_541 - assign \wp$1343 1'0 - assign \wp$1343 $1344 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 1 \addr_en$1346 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 1 $1347 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1348 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1343 - connect \Y $1347 - end - process $group_542 - assign \addr_en$1346 1'0 - assign \addr_en$1346 $1347 - sync init + connect \A \sel_in + connect \B 3'001 + connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1349 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" + cell $eq $16 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$132 - connect \B \fus_cu_busy_o$19 - connect \Y $1349 - end - process $group_543 - assign \wrflag_div0_xer_so_3 1'0 - assign \wrflag_div0_xer_so_3 $1349 - sync init + connect \A \sel_in + connect \B 3'010 + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1351 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1352 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + cell $ne $18 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [2] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1352 - end - process $group_544 - assign \wr_pick$1351 1'0 - assign \wr_pick$1351 $1352 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1354 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1354$next - process $group_545 - assign \wr_pick_dly$1354$next \wr_pick_dly$1354 - assign \wr_pick_dly$1354$next \wr_pick$1351 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1354$next 1'0 - end - sync init - update \wr_pick_dly$1354 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1354 \wr_pick_dly$1354$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1355 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1354 - connect \Y $1355 + connect \A \ra + connect \B 5'00000 + connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1357 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1351 - connect \B $1355 - connect \Y $1357 - end - process $group_546 - assign \wr_pick_rise$833 1'0 - assign \wr_pick_rise$833 $1357 - sync init + connect \A $15 + connect \B $17 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1359 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1360 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + cell $or $22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1351 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1360 - end - process $group_547 - assign \wp$1359 1'0 - assign \wp$1359 $1360 - sync init + connect \A $13 + connect \B $19 + connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 1 \addr_en$1362 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 1 $1363 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1364 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1359 - connect \Y $1363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $eq $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $23 end - process $group_548 - assign \addr_en$1362 1'0 - assign \addr_en$1362 $1363 + process $group_2 + assign \reg_a_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + switch { $21 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + case 1'1 + assign \reg_a_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch { $23 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + case 1'1 + assign \reg_a_ok 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + cell $eq $26 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$133 - connect \B \fus_cu_busy_o$22 - connect \Y $1365 + connect \A \sel_in + connect \B 3'010 + connect \Y $25 end - process $group_549 - assign \wrflag_mul0_xer_so_3 1'0 - assign \wrflag_mul0_xer_so_3 $1365 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + cell $eq $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \reg_a + connect \B 5'00000 + connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1367 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1368 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [3] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1368 - end - process $group_550 - assign \wr_pick$1367 1'0 - assign \wr_pick$1367 $1368 - sync init + connect \A $25 + connect \B $27 + connect \Y $29 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1370 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1370$next - process $group_551 - assign \wr_pick_dly$1370$next \wr_pick_dly$1370 - assign \wr_pick_dly$1370$next \wr_pick$1367 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + process $group_3 + assign \immz_out 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + switch { $29 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" case 1'1 - assign \wr_pick_dly$1370$next 1'0 + assign \immz_out 1'1 end sync init - update \wr_pick_dly$1370 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1370 \wr_pick_dly$1370$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1371 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $not $32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1370 - connect \Y $1371 + connect \A \BO [2] + connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1373 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1374 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + cell $not $34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1367 - connect \B $1371 - connect \Y $1373 - end - process $group_552 - assign \wr_pick_rise$853 1'0 - assign \wr_pick_rise$853 $1373 - sync init + connect \A \XL_XO [5] + connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1375 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + cell $and $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1367 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1376 - end - process $group_553 - assign \wp$1375 1'0 - assign \wp$1375 $1376 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 1 \addr_en$1378 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 1 $1379 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1380 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1375 - connect \Y $1379 + connect \A \XL_XO [9] + connect \B $33 + connect \Y $35 end - process $group_554 - assign \addr_en$1378 1'0 - assign \addr_en$1378 $1379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" + wire width 10 \spr + process $group_4 + assign \fast_a 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \nmigen.decoding "OP_BC/7" + case 7'0000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + switch { $31 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + case 1'1 + assign \fast_a 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + attribute \nmigen.decoding "OP_BCREG/8" + case 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + switch { $35 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + case 1'1 + assign \fast_a 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" + case 10'0000001001 + assign \fast_a 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" + case 10'0000001000 + assign \fast_a 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + case 10'1100101111 + assign \fast_a 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" + case 10'0000011010 + assign \fast_a 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" + case 10'0000011011 + assign \fast_a 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + case + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1381 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1382 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_dest5_o$134 - connect \B \fus_dest4_o$135 - connect \Y $1382 + connect \A \BO [2] + connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1384 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + cell $not $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fus_dest4_o$136 - connect \B \fus_dest4_o$137 - connect \Y $1384 + connect \A \XL_XO [5] + connect \Y $39 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1386 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + cell $and $42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $1382 - connect \B $1384 - connect \Y $1386 + connect \A \XL_XO [9] + connect \B $39 + connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $1388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A $1386 - connect \Y $1381 + process $group_5 + assign \fast_a_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \nmigen.decoding "OP_BC/7" + case 7'0000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + switch { $37 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + case 1'1 + assign \fast_a_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + attribute \nmigen.decoding "OP_BCREG/8" + case 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + switch { $41 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + case 1'1 + assign \fast_a_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" + case 10'0000001001 + assign \fast_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" + case 10'0000001000 + assign \fast_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + case 10'1100101111 + assign \fast_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" + case 10'0000011010 + assign \fast_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" + case 10'0000011011 + assign \fast_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + case + end + end + sync init end - process $group_555 - assign \xer_data_i$155 2'00 - assign \xer_data_i$155 $1381 + process $group_6 + assign \spr 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \nmigen.decoding "OP_BC/7" + case 7'0000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + attribute \nmigen.decoding "OP_BCREG/8" + case 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + assign \spr { \SPR [4:0] \SPR [9:5] } + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1389 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1390 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1391 + process $group_7 + assign \sprmap_spr_i 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \nmigen.decoding "OP_BC/7" + case 7'0000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + attribute \nmigen.decoding "OP_BCREG/8" + case 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + case + assign \sprmap_spr_i \spr + end + end + sync init + end + process $group_8 + assign \spr_a 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \nmigen.decoding "OP_BC/7" + case 7'0000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + attribute \nmigen.decoding "OP_BCREG/8" + case 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + case + assign \spr_a \sprmap_spr_o + end + end + sync init + end + process $group_9 + assign \spr_a_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" + attribute \nmigen.decoding "OP_BC/7" + case 7'0000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + attribute \nmigen.decoding "OP_BCREG/8" + case 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" + case + assign \spr_a_ok 1'1 + end + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_b" +module \dec_b + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170" + wire width 4 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \reg_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 4 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 5 \imm_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \fast_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 7 \fast_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 8 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 9 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 16 input 10 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 16 input 11 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 12 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 6 input 13 \sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 24 input 14 \LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 14 input 15 \BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 14 input 16 \DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 input 17 \XL_XO + process $group_0 + assign \reg_b 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \nmigen.decoding "RB/1" + case 4'0001 + assign \reg_b \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \nmigen.decoding "RS/13" + case 4'1101 + assign \reg_b \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + process $group_1 + assign \reg_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \nmigen.decoding "RB/1" + case 4'0001 + assign \reg_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \nmigen.decoding "RS/13" + case 4'1101 + assign \reg_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 64 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + cell $pos $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en$1330 - connect \B \addr_en$1346 - connect \Y $1390 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \UI + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1392 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" + wire width 64 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" + wire width 47 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" + cell $sshl $5 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 16 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en$1362 - connect \B \addr_en$1378 - connect \Y $1392 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1394 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205" + cell $pos $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1390 - connect \B $1392 - connect \Y $1394 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A $4 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $1396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208" + wire width 26 \li + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" + wire width 64 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223" + cell $not $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A $1394 - connect \Y $1389 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \Y $7 end - process $group_556 - assign \xer_wen$156 3'000 - assign \xer_wen$156 $1389 - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 64 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + cell $pos $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \sh + connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1397 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 64 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + cell $pos $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok - connect \B \fus_cu_busy_o$7 - connect \Y $1397 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \SH32 + connect \Y $11 end - process $group_557 - assign \wrflag_branch0_fast1_0 1'0 - assign \wrflag_branch0_fast1_0 $1397 + process $group_2 + assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \nmigen.decoding "RB/1" + case 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \nmigen.decoding "RS/13" + case 4'1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b $11 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1399 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$138 [0] - connect \B \fu_enable [2] - connect \Y $1399 + process $group_3 + assign \imm_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \nmigen.decoding "RB/1" + case 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \nmigen.decoding "RS/13" + case 4'1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + assign \imm_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + assign \imm_b_ok 1'1 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [1] - connect \B \fu_enable [3] - connect \Y $1401 + process $group_4 + assign \si 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \nmigen.decoding "RB/1" + case 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \nmigen.decoding "RS/13" + case 4'1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + assign \si \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1403 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1404 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" + wire width 47 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" + wire width 47 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" + cell $sshl $15 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 16 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [2] - connect \B \fu_enable [5] - connect \Y $1403 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \SI + connect \B 5'10000 + connect \Y $14 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1405 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1406 + connect $13 $14 + process $group_5 + assign \si_hi 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \nmigen.decoding "RB/1" + case 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \nmigen.decoding "RS/13" + case 4'1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + assign \si_hi $13 [31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + process $group_6 + assign \ui 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \nmigen.decoding "RB/1" + case 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \nmigen.decoding "RS/13" + case 4'1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + assign \ui \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" + wire width 27 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" + wire width 27 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" + cell $sshl $18 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$138 [1] - connect \B \fu_enable [2] - connect \Y $1405 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LI + connect \B 2'10 + connect \Y $17 + end + connect $16 $17 + process $group_7 + assign \li 26'00000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \nmigen.decoding "RB/1" + case 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \nmigen.decoding "RS/13" + case 4'1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + assign \li $16 [25:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1407 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214" + wire width 17 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214" + wire width 17 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214" + cell $sshl $21 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [2] - connect \B \fu_enable [3] - connect \Y $1407 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BD + connect \B 2'10 + connect \Y $20 end - process $group_558 - assign \wrpick_FAST_fast1_i 5'00000 - assign \wrpick_FAST_fast1_i [0] $1399 - assign \wrpick_FAST_fast1_i [1] $1401 - assign \wrpick_FAST_fast1_i [2] $1403 - assign \wrpick_FAST_fast1_i [3] $1405 - assign \wrpick_FAST_fast1_i [4] $1407 + connect $19 $20 + process $group_8 + assign \bd 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \nmigen.decoding "RB/1" + case 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \nmigen.decoding "RS/13" + case 4'1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + assign \bd $19 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1409 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1410 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 17 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + wire width 17 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" + cell $sshl $24 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 14 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [0] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1410 - end - process $group_559 - assign \wr_pick$1409 1'0 - assign \wr_pick$1409 $1410 - sync init + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DS + connect \B 2'10 + connect \Y $23 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1412 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1412$next - process $group_560 - assign \wr_pick_dly$1412$next \wr_pick_dly$1412 - assign \wr_pick_dly$1412$next \wr_pick$1409 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1412$next 1'0 + connect $22 $23 + process $group_9 + assign \ds 16'0000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" + attribute \nmigen.decoding "RB/1" + case 4'0001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" + attribute \nmigen.decoding "RS/13" + case 4'1101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189" + attribute \nmigen.decoding "CONST_UI/2" + case 4'0010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + attribute \nmigen.decoding "CONST_SI/3" + case 4'0011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197" + attribute \nmigen.decoding "CONST_SI_HI/5" + case 4'0101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202" + attribute \nmigen.decoding "CONST_UI_HI/4" + case 4'0100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \nmigen.decoding "CONST_LI/6" + case 4'0110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" + attribute \nmigen.decoding "CONST_BD/7" + case 4'0111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217" + attribute \nmigen.decoding "CONST_DS/8" + case 4'1000 + assign \ds $22 [15:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" + attribute \nmigen.decoding "CONST_M1/9" + case 4'1001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" + attribute \nmigen.decoding "CONST_SH/10" + case 4'1010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + attribute \nmigen.decoding "CONST_SH32/11" + case 4'1011 end sync init - update \wr_pick_dly$1412 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1412 \wr_pick_dly$1412$next end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1413 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1414 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + cell $eq $26 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1412 - connect \Y $1414 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1416 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + cell $not $28 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_pick$1409 - connect \B $1414 - connect \Y $1416 - end - process $group_561 - assign \wr_pick_rise$1413 1'0 - assign \wr_pick_rise$1413 $1416 - sync init + connect \A \XL_XO [9] + connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1418 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1419 - process $group_562 - assign \fus_cu_wr__go_i$139 3'000 - assign \fus_cu_wr__go_i$139 [0] \wr_pick_rise$1413 - assign \fus_cu_wr__go_i$139 [1] \wr_pick_rise$1418 - assign \fus_cu_wr__go_i$139 [2] \wr_pick_rise$1419 + process $group_10 + assign \fast_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + switch { \XL_XO [5] $27 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + case 2'-1 + assign \fast_b 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + case 2'1- + assign \fast_b 3'010 + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1420 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1421 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + cell $eq $30 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \wr_pick$1409 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1421 - end - process $group_563 - assign \wp$1420 1'0 - assign \wp$1420 $1421 - sync init + connect \A \internal_op + connect \B 7'0001000 + connect \Y $29 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 8 \addr_en$1423 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - wire width 8 $1424 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - cell $sshl $1425 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + cell $not $32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fasto1 - connect \Y $1424 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 8 $1426 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1427 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B $1424 - connect \S \wp$1420 - connect \Y $1426 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $31 end - process $group_564 - assign \addr_en$1423 8'00000000 - assign \addr_en$1423 $1426 + process $group_11 + assign \fast_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + switch { $29 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + switch { \XL_XO [5] $31 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + case 2'-1 + assign \fast_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + case 2'1- + assign \fast_b_ok 1'1 + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1428 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$140 - connect \B \fus_cu_busy_o$10 - connect \Y $1428 - end - process $group_565 - assign \wrflag_trap0_fast1_1 1'0 - assign \wrflag_trap0_fast1_1 $1428 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_c" +module \dec_c + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 1 \reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \reg_c_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 3 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 4 \RB + process $group_0 + assign \reg_c 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:266" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:267" + attribute \nmigen.decoding "RB/2" + case 2'10 + assign \reg_c \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + attribute \nmigen.decoding "RS/1" + case 2'01 + assign \reg_c \RS + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1430 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1431 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [1] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1431 + process $group_1 + assign \reg_c_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:266" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:267" + attribute \nmigen.decoding "RB/2" + case 2'10 + assign \reg_c_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + attribute \nmigen.decoding "RS/1" + case 2'01 + assign \reg_c_ok 1'1 + end + sync init end - process $group_566 - assign \wr_pick$1430 1'0 - assign \wr_pick$1430 $1431 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o.sprmap" +module \sprmap$419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" + wire width 10 input 0 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" + wire width 10 output 1 \spr_o + process $group_0 + assign \spr_o 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61" + switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000000001 + assign \spr_o 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000000011 + assign \spr_o 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000001000 + assign \spr_o 10'0000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000001001 + assign \spr_o 10'0000000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000001101 + assign \spr_o 10'0000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000010001 + assign \spr_o 10'0000000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000010010 + assign \spr_o 10'0000000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000010011 + assign \spr_o 10'0000000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000010110 + assign \spr_o 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000011010 + assign \spr_o 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000011011 + assign \spr_o 10'0000001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000011100 + assign \spr_o 10'0000001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000011101 + assign \spr_o 10'0000001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000110000 + assign \spr_o 10'0000001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0000111101 + assign \spr_o 10'0000001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010000000 + assign \spr_o 10'0000001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010000001 + assign \spr_o 10'0000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010000010 + assign \spr_o 10'0000010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010000011 + assign \spr_o 10'0000010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010001000 + assign \spr_o 10'0000010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010010000 + assign \spr_o 10'0000010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010011000 + assign \spr_o 10'0000010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010011001 + assign \spr_o 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010011101 + assign \spr_o 10'0000010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010011110 + assign \spr_o 10'0000011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010011111 + assign \spr_o 10'0000011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010110000 + assign \spr_o 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010110100 + assign \spr_o 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010111010 + assign \spr_o 10'0000011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010111011 + assign \spr_o 10'0000011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010111100 + assign \spr_o 10'0000011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0010111110 + assign \spr_o 10'0000011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100000000 + assign \spr_o 10'0000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100000011 + assign \spr_o 10'0000100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100001100 + assign \spr_o 10'0000100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100001101 + assign \spr_o 10'0000100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100010000 + assign \spr_o 10'0000100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100010001 + assign \spr_o 10'0000100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100010010 + assign \spr_o 10'0000100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100010011 + assign \spr_o 10'0000100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100011011 + assign \spr_o 10'0000101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100011100 + assign \spr_o 10'0000101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100011101 + assign \spr_o 10'0000101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100011110 + assign \spr_o 10'0000101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100011111 + assign \spr_o 10'0000101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110000 + assign \spr_o 10'0000101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110001 + assign \spr_o 10'0000101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110010 + assign \spr_o 10'0000101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110011 + assign \spr_o 10'0000110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110100 + assign \spr_o 10'0000110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110101 + assign \spr_o 10'0000110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100110110 + assign \spr_o 10'0000110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100111001 + assign \spr_o 10'0000110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100111010 + assign \spr_o 10'0000110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100111011 + assign \spr_o 10'0000110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100111110 + assign \spr_o 10'0000110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0100111111 + assign \spr_o 10'0000111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0101010000 + assign \spr_o 10'0000111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0101010001 + assign \spr_o 10'0000111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0101010010 + assign \spr_o 10'0000111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0101010011 + assign \spr_o 10'0000111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0101011101 + assign \spr_o 10'0000111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0110111110 + assign \spr_o 10'0000111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'0111010000 + assign \spr_o 10'0000111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000000 + assign \spr_o 10'0001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000001 + assign \spr_o 10'0001000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000010 + assign \spr_o 10'0001000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000011 + assign \spr_o 10'0001000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000100 + assign \spr_o 10'0001000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000101 + assign \spr_o 10'0001000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000110 + assign \spr_o 10'0001000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100000111 + assign \spr_o 10'0001000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100001000 + assign \spr_o 10'0001001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100001011 + assign \spr_o 10'0001001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100001100 + assign \spr_o 10'0001001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100001101 + assign \spr_o 10'0001001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100001110 + assign \spr_o 10'0001001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010000 + assign \spr_o 10'0001001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010001 + assign \spr_o 10'0001001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010010 + assign \spr_o 10'0001001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010011 + assign \spr_o 10'0001010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010100 + assign \spr_o 10'0001010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010101 + assign \spr_o 10'0001010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010110 + assign \spr_o 10'0001010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100010111 + assign \spr_o 10'0001010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100011000 + assign \spr_o 10'0001010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100011011 + assign \spr_o 10'0001010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100011100 + assign \spr_o 10'0001010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100011101 + assign \spr_o 10'0001011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100011110 + assign \spr_o 10'0001011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100000 + assign \spr_o 10'0001011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100001 + assign \spr_o 10'0001011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100010 + assign \spr_o 10'0001011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100011 + assign \spr_o 10'0001011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100100 + assign \spr_o 10'0001011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100101 + assign \spr_o 10'0001011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100100110 + assign \spr_o 10'0001100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100101000 + assign \spr_o 10'0001100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100101001 + assign \spr_o 10'0001100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100101010 + assign \spr_o 10'0001100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100101011 + assign \spr_o 10'0001100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100101111 + assign \spr_o 10'0001100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100110000 + assign \spr_o 10'0001100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1100110111 + assign \spr_o 10'0001100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1101010000 + assign \spr_o 10'0001101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1101010001 + assign \spr_o 10'0001101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1101010111 + assign \spr_o 10'0001101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1110000000 + assign \spr_o 10'0001101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1110000010 + assign \spr_o 10'0001101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + case 10'1111111111 + assign \spr_o 10'0001101101 + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1433 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1433$next - process $group_567 - assign \wr_pick_dly$1433$next \wr_pick_dly$1433 - assign \wr_pick_dly$1433$next \wr_pick$1430 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1433$next 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o" +module \dec_o + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \reg_o_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 4 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 5 \spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 7 \fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 8 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" + wire width 10 \sprmap_spr_o + cell \sprmap$419 \sprmap + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + end + process $group_0 + assign \reg_o 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \nmigen.decoding "RT/1" + case 2'01 + assign \reg_o \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \nmigen.decoding "RA/2" + case 2'10 + assign \reg_o \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \nmigen.decoding "SPR/3" + case 2'11 end - sync init - update \wr_pick_dly$1433 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1433 \wr_pick_dly$1433$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1434 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1433 - connect \Y $1434 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1436 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1430 - connect \B $1434 - connect \Y $1436 - end - process $group_568 - assign \wr_pick_rise$769 1'0 - assign \wr_pick_rise$769 $1436 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1438 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1439 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1430 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1439 - end - process $group_569 - assign \wp$1438 1'0 - assign \wp$1438 $1439 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 8 \addr_en$1441 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - wire width 8 $1442 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - cell $sshl $1443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fasto1 - connect \Y $1442 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 8 $1444 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1445 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B $1442 - connect \S \wp$1438 - connect \Y $1444 - end - process $group_570 - assign \addr_en$1441 8'00000000 - assign \addr_en$1441 $1444 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1446 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$141 - connect \B \fus_cu_busy_o$16 - connect \Y $1446 - end - process $group_571 - assign \wrflag_spr0_fast1_2 1'0 - assign \wrflag_spr0_fast1_2 $1446 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1448 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [2] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1449 - end - process $group_572 - assign \wr_pick$1448 1'0 - assign \wr_pick$1448 $1449 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1451 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1451$next - process $group_573 - assign \wr_pick_dly$1451$next \wr_pick_dly$1451 - assign \wr_pick_dly$1451$next \wr_pick$1448 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1451$next 1'0 + process $group_1 + assign \reg_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \nmigen.decoding "RT/1" + case 2'01 + assign \reg_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \nmigen.decoding "RA/2" + case 2'10 + assign \reg_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \nmigen.decoding "SPR/3" + case 2'11 end - sync init - update \wr_pick_dly$1451 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1451 \wr_pick_dly$1451$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1452 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1451 - connect \Y $1452 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1454 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1448 - connect \B $1452 - connect \Y $1454 - end - process $group_574 - assign \wr_pick_rise$812 1'0 - assign \wr_pick_rise$812 $1454 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1456 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1457 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1448 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1457 - end - process $group_575 - assign \wp$1456 1'0 - assign \wp$1456 $1457 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 8 \addr_en$1459 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - wire width 8 $1460 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:178" - cell $sshl $1461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fasto1 - connect \Y $1460 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 8 $1462 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1463 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B $1460 - connect \S \wp$1456 - connect \Y $1462 - end - process $group_576 - assign \addr_en$1459 8'00000000 - assign \addr_en$1459 $1462 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1464 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast2_ok - connect \B \fus_cu_busy_o$7 - connect \Y $1464 - end - process $group_577 - assign \wrflag_branch0_fast1_1 1'0 - assign \wrflag_branch0_fast1_1 $1464 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [3] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1467 - end - process $group_578 - assign \wr_pick$1466 1'0 - assign \wr_pick$1466 $1467 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1469 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1469$next - process $group_579 - assign \wr_pick_dly$1469$next \wr_pick_dly$1469 - assign \wr_pick_dly$1469$next \wr_pick$1466 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1469$next 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307" + wire width 10 \spr + process $group_2 + assign \spr 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \nmigen.decoding "SPR/3" + case 2'11 + assign \spr { \SPR [4:0] \SPR [9:5] } end - sync init - update \wr_pick_dly$1469 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1469 \wr_pick_dly$1469$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1470 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1469 - connect \Y $1470 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1472 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1466 - connect \B $1470 - connect \Y $1472 - end - process $group_580 - assign \wr_pick_rise$1418 1'0 - assign \wr_pick_rise$1418 $1472 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1474 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1475 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1466 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1475 - end - process $group_581 - assign \wp$1474 1'0 - assign \wp$1474 $1475 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 8 \addr_en$1477 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" - wire width 8 $1478 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" - cell $sshl $1479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fasto2 - connect \Y $1478 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 8 $1480 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1481 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B $1478 - connect \S \wp$1474 - connect \Y $1480 - end - process $group_582 - assign \addr_en$1477 8'00000000 - assign \addr_en$1477 $1480 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1482 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1483 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \fus_fast2_ok$142 - connect \B \fus_cu_busy_o$10 - connect \Y $1482 - end - process $group_583 - assign \wrflag_trap0_fast1_2 1'0 - assign \wrflag_trap0_fast1_2 $1482 - sync init + connect \A \internal_op + connect \B 7'0110001 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1484 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1485 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1486 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + cell $not $4 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [4] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1485 - end - process $group_584 - assign \wr_pick$1484 1'0 - assign \wr_pick$1484 $1485 - sync init + connect \A \BO [2] + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1487 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1487$next - process $group_585 - assign \wr_pick_dly$1487$next \wr_pick_dly$1487 - assign \wr_pick_dly$1487$next \wr_pick$1484 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1487$next 1'0 + process $group_3 + assign \fast_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" + case 10'0000001001 + assign \fast_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" + case 10'0000001000 + assign \fast_o 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" + case 10'1100101111 + assign \fast_o 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" + case 10'0000011010 + assign \fast_o 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" + case 10'0000011011 + assign \fast_o 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + case + end + end end - sync init - update \wr_pick_dly$1487 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1487 \wr_pick_dly$1487$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1488 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1487 - connect \Y $1488 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1490 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1484 - connect \B $1488 - connect \Y $1490 - end - process $group_586 - assign \wr_pick_rise$770 1'0 - assign \wr_pick_rise$770 $1490 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1492 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1493 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1484 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1493 - end - process $group_587 - assign \wp$1492 1'0 - assign \wp$1492 $1493 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 8 \addr_en$1495 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" - wire width 8 $1496 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:180" - cell $sshl $1497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 8 - connect \A 1'1 - connect \B \pdecode2_fasto2 - connect \Y $1496 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 8 $1498 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1499 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B $1496 - connect \S \wp$1492 - connect \Y $1498 - end - process $group_588 - assign \addr_en$1495 8'00000000 - assign \addr_en$1495 $1498 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1500 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$143 - connect \B \fus_dest2_o$144 - connect \Y $1500 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1502 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest2_o$146 - connect \B \fus_dest3_o$147 - connect \Y $1502 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1504 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$145 - connect \B $1502 - connect \Y $1504 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1506 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $1500 - connect \B $1504 - connect \Y $1506 - end - process $group_589 - assign \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast_data_i $1506 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 8 $1508 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 8 $1509 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \addr_en$1423 - connect \B \addr_en$1441 - connect \Y $1509 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 8 $1511 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \addr_en$1477 - connect \B \addr_en$1495 - connect \Y $1511 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 8 $1513 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \addr_en$1459 - connect \B $1511 - connect \Y $1513 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 8 $1515 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $1509 - connect \B $1513 - connect \Y $1515 - end - connect $1508 $1515 - process $group_590 - assign \fast_wen 5'00000 - assign \fast_wen $1508 [4:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1517 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_nia_ok - connect \B \fus_cu_busy_o$7 - connect \Y $1517 - end - process $group_591 - assign \wrflag_branch0_nia_2 1'0 - assign \wrflag_branch0_nia_2 $1517 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1519 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$138 [2] - connect \B \fu_enable [2] - connect \Y $1519 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1521 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [3] - connect \B \fu_enable [3] - connect \Y $1521 - end - process $group_592 - assign \wrpick_STATE_nia_i 2'00 - assign \wrpick_STATE_nia_i [0] $1519 - assign \wrpick_STATE_nia_i [1] $1521 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1523 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1524 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_STATE_nia_o [0] - connect \B \wrpick_STATE_nia_en_o - connect \Y $1524 - end - process $group_593 - assign \wr_pick$1523 1'0 - assign \wr_pick$1523 $1524 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1526 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1526$next - process $group_594 - assign \wr_pick_dly$1526$next \wr_pick_dly$1526 - assign \wr_pick_dly$1526$next \wr_pick$1523 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1526$next 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" + attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8" + case 7'0000111, 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + switch { $3 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + case 1'1 + assign \fast_o 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + assign \fast_o 3'011 end - sync init - update \wr_pick_dly$1526 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1526 \wr_pick_dly$1526$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1527 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1526 - connect \Y $1527 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1529 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1523 - connect \B $1527 - connect \Y $1529 - end - process $group_595 - assign \wr_pick_rise$1419 1'0 - assign \wr_pick_rise$1419 $1529 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1531 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1532 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1523 - connect \B \wrpick_STATE_nia_en_o - connect \Y $1532 - end - process $group_596 - assign \wp$1531 1'0 - assign \wp$1531 $1532 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 1 \addr_en$1534 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 1 $1535 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1536 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1531 - connect \Y $1535 - end - process $group_597 - assign \addr_en$1534 1'0 - assign \addr_en$1534 $1535 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1537 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \fus_nia_ok$148 - connect \B \fus_cu_busy_o$10 - connect \Y $1537 - end - process $group_598 - assign \wrflag_trap0_nia_3 1'0 - assign \wrflag_trap0_nia_3 $1537 - sync init + connect \A \internal_op + connect \B 7'0110001 + connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1539 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1540 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1541 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + cell $not $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_STATE_nia_o [1] - connect \B \wrpick_STATE_nia_en_o - connect \Y $1540 - end - process $group_599 - assign \wr_pick$1539 1'0 - assign \wr_pick$1539 $1540 - sync init + connect \A \BO [2] + connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1542 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1542$next - process $group_600 - assign \wr_pick_dly$1542$next \wr_pick_dly$1542 - assign \wr_pick_dly$1542$next \wr_pick$1539 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1542$next 1'0 + process $group_4 + assign \fast_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + switch { $5 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" + case 10'0000001001 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" + case 10'0000001000 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" + case 10'1100101111 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" + case 10'0000011010 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" + case 10'0000011011 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + case + end + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" + attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8" + case 7'0000111, 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + case 1'1 + assign \fast_o_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + assign \fast_o_ok 1'1 end - sync init - update \wr_pick_dly$1542 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1542 \wr_pick_dly$1542$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1543 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1542 - connect \Y $1543 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1545 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1539 - connect \B $1543 - connect \Y $1545 - end - process $group_601 - assign \wr_pick_rise$771 1'0 - assign \wr_pick_rise$771 $1545 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1547 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1548 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + cell $eq $10 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \wr_pick$1539 - connect \B \wrpick_STATE_nia_en_o - connect \Y $1548 - end - process $group_602 - assign \wp$1547 1'0 - assign \wp$1547 $1548 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 1 \addr_en$1550 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 1 $1551 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1552 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1547 - connect \Y $1551 - end - process $group_603 - assign \addr_en$1550 1'0 - assign \addr_en$1550 $1551 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1553 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$149 - connect \B \fus_dest4_o$150 - connect \Y $1553 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $9 end - process $group_604 - assign \state_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \state_data_i $1553 + process $group_5 + assign \sprmap_spr_i 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + case + assign \sprmap_spr_i \spr + end + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1555 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1556 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + cell $eq $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \addr_en$1534 - connect \B \addr_en$1550 - connect \Y $1556 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $pos $1558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A $1556 - connect \Y $1555 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $11 end - process $group_605 - assign \state_nia_wen 2'00 - assign \state_nia_wen $1555 + process $group_6 + assign \spr_o 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + switch { $11 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + case + assign \spr_o \sprmap_spr_o + end + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1559 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + cell $eq $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \fus_msr_ok - connect \B \fus_cu_busy_o$10 - connect \Y $1559 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $13 end - process $group_606 - assign \wrflag_trap0_msr_4 1'0 - assign \wrflag_trap0_msr_4 $1559 + process $group_7 + assign \spr_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + case + assign \spr_o_ok 1'1 + end + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1561 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1562 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o2" +module \dec_o2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire width 1 input 0 \lk + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \reg_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 4 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 5 \fast_o_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 7 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + cell $eq $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [4] - connect \B \fu_enable [3] - connect \Y $1561 - end - process $group_607 - assign \wrpick_STATE_msr_i 1'0 - assign \wrpick_STATE_msr_i $1561 - sync init + connect \A \upd + connect \B 2'01 + connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1563 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1564 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 6 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + cell $pos $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_STATE_msr_o - connect \B \wrpick_STATE_msr_en_o - connect \Y $1564 - end - process $group_608 - assign \wr_pick$1563 1'0 - assign \wr_pick$1563 $1564 - sync init + parameter \A_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A \RA + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1566 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1566$next - process $group_609 - assign \wr_pick_dly$1566$next \wr_pick_dly$1566 - assign \wr_pick_dly$1566$next \wr_pick$1563 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst + process $group_0 + assign \reg_o 5'00000 + assign \reg_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" case 1'1 - assign \wr_pick_dly$1566$next 1'0 + assign { \reg_o_ok \reg_o } $3 + assign \reg_o_ok 1'1 end - sync init - update \wr_pick_dly$1566 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1566 \wr_pick_dly$1566$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1567 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1566 - connect \Y $1567 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1569 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1563 - connect \B $1567 - connect \Y $1569 - end - process $group_610 - assign \wr_pick_rise$772 1'0 - assign \wr_pick_rise$772 $1569 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1571 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1572 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1563 - connect \B \wrpick_STATE_msr_en_o - connect \Y $1572 - end - process $group_611 - assign \wp$1571 1'0 - assign \wp$1571 $1572 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 2 \addr_en$1574 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 2 $1575 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1576 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1571 - connect \Y $1575 - end - process $group_612 - assign \addr_en$1574 2'00 - assign \addr_en$1574 $1575 sync init end - process $group_613 - assign \state_data_i$157 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \state_data_i$157 \fus_dest5_o$151 + process $group_2 + assign \fast_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8" + case 7'0000111, 7'0000110, 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + switch { \lk } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + case 1'1 + assign \fast_o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + assign \fast_o 3'100 + end sync init end - process $group_614 - assign \state_wen 2'00 - assign \state_wen \addr_en$1574 + process $group_3 + assign \fast_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8" + case 7'0000111, 7'0000110, 7'0001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + switch { \lk } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + case 1'1 + assign \fast_o_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389" + attribute \nmigen.decoding "OP_RFID/70" + case 7'1000110 + assign \fast_o_ok 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:347" - wire width 1 \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - wire width 1 $1577 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:348" - cell $and $1578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_spr1_ok - connect \B \fus_cu_busy_o$16 - connect \Y $1577 - end - process $group_615 - assign \wrflag_spr0_spr1_1 1'0 - assign \wrflag_spr0_spr1_1 $1577 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_rc" +module \dec_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 1 input 3 \Rc + process $group_0 + assign \rc 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc 1'0 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - wire width 1 $1579 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:352" - cell $and $1580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [1] - connect \B \fu_enable [5] - connect \Y $1579 - end - process $group_616 - assign \wrpick_SPR_spr1_i 1'0 - assign \wrpick_SPR_spr1_i $1579 + process $group_1 + assign \rc_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \rc_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" + attribute \nmigen.decoding "NONE/0" + case 2'00 + assign \rc_ok 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:355" - wire width 1 \wr_pick$1581 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - wire width 1 $1582 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:356" - cell $and $1583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_SPR_spr1_o - connect \B \wrpick_SPR_spr1_en_o - connect \Y $1582 - end - process $group_617 - assign \wr_pick$1581 1'0 - assign \wr_pick$1581 $1582 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_oe" +module \dec_oe + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 0 \sel_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 1 input 4 \OE + process $group_0 + assign \oe 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52" + case 7'0110011, 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:460" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe \OE + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1584 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1584$next - process $group_618 - assign \wr_pick_dly$1584$next \wr_pick_dly$1584 - assign \wr_pick_dly$1584$next \wr_pick$1581 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1584$next 1'0 + process $group_1 + assign \oe_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453" + attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52" + case 7'0110011, 7'0110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457" + attribute \nmigen.decoding "" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:460" + attribute \nmigen.decoding "RC/2" + case 2'10 + assign \oe_ok 1'1 + end end sync init - update \wr_pick_dly$1584 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1584 \wr_pick_dly$1584$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1585 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1584 - connect \Y $1585 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1587 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1581 - connect \B $1585 - connect \Y $1587 end - process $group_619 - assign \wr_pick_rise$813 1'0 - assign \wr_pick_rise$813 $1587 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in" +module \dec_cr_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:476" + wire width 3 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 1 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 2 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 4 \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 5 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 6 \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481" + wire width 1 output 7 \whole_reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 8 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 9 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 10 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 11 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 input 12 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 input 13 \X_BFA + process $group_0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:363" - wire width 1 \wp$1589 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - wire width 1 $1590 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:364" - cell $and $1591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1581 - connect \B \wrpick_SPR_spr1_en_o - connect \Y $1590 - end - process $group_620 - assign \wp$1589 1'0 - assign \wp$1589 $1590 + process $group_1 + assign \cr_bitfield_b_ok 1'0 + assign \cr_bitfield_b_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:362" - wire width 10 \addr_en$1592 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - wire width 10 $1593 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:365" - cell $mux $1594 - parameter \WIDTH 10 - connect \A 10'0000000000 - connect \B \pdecode2_spro - connect \S \wp$1589 - connect \Y $1593 - end - process $group_621 - assign \addr_en$1592 10'0000000000 - assign \addr_en$1592 $1593 + process $group_2 + assign \whole_reg 1'0 + assign \whole_reg 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + assign \whole_reg 1'1 + end sync init end - process $group_622 - assign \spr_spr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr_spr1__data_i \fus_dest2_o$152 + process $group_3 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" + attribute \nmigen.decoding "BI/2" + case 3'010 + assign \cr_bitfield \BI [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \nmigen.decoding "BFA/3" + case 3'011 + assign \cr_bitfield \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield \BA [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" + attribute \nmigen.decoding "BC/5" + case 3'101 + assign \cr_bitfield \BC [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end sync init end - process $group_623 - assign \spr_spr1__addr$158 7'0000000 - assign \spr_spr1__addr$158 \addr_en$1592 [6:0] + process $group_4 + assign \cr_bitfield_b 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_b \BB [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end sync init end - process $group_624 - assign \spr_spr1__wen 1'0 - assign \spr_spr1__wen \wp$1589 + process $group_5 + assign \cr_bitfield_o 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o \BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end sync init end - process $group_625 - assign \coresync_rst 1'0 - assign \coresync_rst \core_reset_i + process $group_6 + assign \cr_bitfield_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496" + attribute \nmigen.decoding "BI/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" + attribute \nmigen.decoding "BFA/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + attribute \nmigen.decoding "BA_BB/4" + case 3'100 + assign \cr_bitfield_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509" + attribute \nmigen.decoding "BC/5" + case 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" + attribute \nmigen.decoding "WHOLE_REG/6" + case 3'110 + end sync init end - connect \o_ok 1'0 - connect \ea_ok 1'0 end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.imem" -module \imem - attribute \src "simple/issuer.py:88" - wire width 1 input 0 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 input 1 \a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire width 1 input 2 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire width 1 input 3 \f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire width 1 output 4 \f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 output 5 \f_instr_o - attribute \src "simple/issuer.py:88" - wire width 1 input 6 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 output 7 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 \ibus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 input 8 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 input 9 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 output 10 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 \ibus__stb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 11 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 \ibus__sel$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 12 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 13 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 \ibus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" - wire width 1 \a_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $5 - connect \B $7 - connect \Y $9 - end +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out" +module \dec_cr_out + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 3 input 0 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire width 1 input 1 \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 2 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 3 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:531" + wire width 1 output 4 \whole_reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 input 6 \XL_BT process $group_0 - assign \ibus__cyc$next \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { $3 \ibus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - case 1'1 - assign \ibus__cyc$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - case 2'1- - assign \ibus__cyc$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ibus__cyc$next 1'0 + assign \cr_bitfield_ok 1'0 + assign \cr_bitfield_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield_ok \rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 end sync init - update \ibus__cyc 1'0 - sync posedge \clk - update \ibus__cyc \ibus__cyc$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $11 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B $11 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $15 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $15 - connect \B $17 - connect \Y $19 end process $group_1 - assign \ibus__stb$next \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { $13 \ibus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - case 1'1 - assign \ibus__stb$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - case 2'1- - assign \ibus__stb$next 1'1 + assign \whole_reg 1'0 + assign \whole_reg 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" + attribute \nmigen.decoding "CR0/1" + case 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545" + attribute \nmigen.decoding "BF/2" + case 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + attribute \nmigen.decoding "BT/3" + case 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 + assign \whole_reg 1'1 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ibus__stb$next 1'0 + sync init + end + process $group_2 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" + attribute \nmigen.decoding "NONE/0" + case 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" + attribute \nmigen.decoding "CR0/1" + case 3'001 + assign \cr_bitfield 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545" + attribute \nmigen.decoding "BF/2" + case 3'010 + assign \cr_bitfield \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + attribute \nmigen.decoding "BT/3" + case 3'011 + assign \cr_bitfield \XL_BT [4:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551" + attribute \nmigen.decoding "WHOLE_REG/4" + case 3'100 end sync init - update \ibus__stb 1'0 - sync posedge \clk - update \ibus__stb \ibus__stb$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $21 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.dec2" +module \dec2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + wire width 1 input 0 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:337" + wire width 32 input 1 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 2 \dec2_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 3 \dec2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" + wire width 8 output 4 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 5 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 6 \rego_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 7 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 8 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 9 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 10 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 11 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 12 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 13 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 output 14 \reg3_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire width 1 output 60 \sign_extend + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" + wire width 2 output 61 \ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire width 5 output 62 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" + wire width 13 output 63 \trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" + wire width 1 output 64 \read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" + wire width 1 output 65 \write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" + wire width 1 output 66 \write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:238" + wire width 32 \dec_opcode_in + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 3 \dec_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132" + wire width 4 \dec_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133" + wire width 2 \dec_in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:134" + wire width 2 \dec_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:139" + wire width 2 \dec_rc_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 3 \dec_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136" + wire width 3 \dec_cr_out + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 7 \dec_internal_op + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 11 \dec_function_unit + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:137" + wire width 4 \dec_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_inv_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:140" + wire width 2 \dec_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 1 \dec_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:143" + wire width 1 \dec_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:138" + wire width 2 \dec_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 16 \dec_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 16 \dec_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 6 \dec_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 24 \dec_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 1 \dec_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 1 \dec_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 14 \dec_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 14 \dec_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 5 \dec_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:341" + wire width 10 \dec_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:354" + wire width 10 \dec_XL_XO + cell \dec \dec + connect \bigendian \bigendian + connect \raw_opcode_in \raw_opcode_in + connect \opcode_in \dec_opcode_in + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \out_sel \dec_out_sel + connect \rc_sel \dec_rc_sel + connect \cr_in \dec_cr_in + connect \cr_out \dec_cr_out + connect \internal_op \dec_internal_op + connect \function_unit \dec_function_unit + connect \ldst_len \dec_ldst_len + connect \inv_a \dec_inv_a + connect \inv_out \dec_inv_out + connect \cry_in \dec_cry_in + connect \cry_out \dec_cry_out + connect \is_32b \dec_is_32b + connect \sgn \dec_sgn + connect \lk \dec_lk + connect \LK \dec_LK + connect \br \dec_br + connect \sgn_ext \dec_sgn_ext + connect \upd \dec_upd + connect \RS \dec_RS + connect \RT \dec_RT + connect \RA \dec_RA + connect \RB \dec_RB + connect \SI \dec_SI + connect \UI \dec_UI + connect \SH32 \dec_SH32 + connect \sh \dec_sh + connect \LI \dec_LI + connect \Rc \dec_Rc + connect \OE \dec_OE + connect \BD \dec_BD + connect \BB \dec_BB + connect \BA \dec_BA + connect \BT \dec_BT + connect \BO \dec_BO + connect \BI \dec_BI + connect \DS \dec_DS + connect \BC \dec_BC + connect \SPR \dec_SPR + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \XL_BT \dec_XL_BT + connect \XL_XO \dec_XL_XO end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B $21 - connect \Y $23 + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:77" + wire width 3 \dec_a_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_a_reg_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_a_reg_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:80" + wire width 1 \dec_a_immz_out + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec_a_spr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_a_spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_a_fast_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_a_fast_a_ok + cell \dec_a \dec_a + connect \sel_in \dec_a_sel_in + connect \internal_op \dec_internal_op + connect \reg_a \dec_a_reg_a + connect \reg_a_ok \dec_a_reg_a_ok + connect \immz_out \dec_a_immz_out + connect \spr_a \dec_a_spr_a + connect \spr_a_ok \dec_a_spr_a_ok + connect \fast_a \dec_a_fast_a + connect \fast_a_ok \dec_a_fast_a_ok + connect \RS \dec_RS + connect \RA \dec_RA + connect \BO \dec_BO + connect \SPR \dec_SPR + connect \XL_XO \dec_XL_XO end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $25 + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170" + wire width 4 \dec_b_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_b_reg_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_b_reg_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_b_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_b_imm_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_b_fast_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_b_fast_b_ok + cell \dec_b \dec_b + connect \sel_in \dec_b_sel_in + connect \internal_op \dec_internal_op + connect \reg_b \dec_b_reg_b + connect \reg_b_ok \dec_b_reg_b_ok + connect \imm_b \dec_b_imm_b + connect \imm_b_ok \dec_b_imm_b_ok + connect \fast_b \dec_b_fast_b + connect \fast_b_ok \dec_b_fast_b_ok + connect \RS \dec_RS + connect \RB \dec_RB + connect \SI \dec_SI + connect \UI \dec_UI + connect \SH32 \dec_SH32 + connect \sh \dec_sh + connect \LI \dec_LI + connect \BD \dec_BD + connect \DS \dec_DS + connect \XL_XO \dec_XL_XO end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $27 + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" + wire width 2 \dec_c_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_c_reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_c_reg_c_ok + cell \dec_c \dec_c + connect \sel_in \dec_c_sel_in + connect \reg_c \dec_c_reg_c + connect \reg_c_ok \dec_c_reg_c_ok + connect \RS \dec_RS + connect \RB \dec_RB end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $25 - connect \B $27 - connect \Y $29 + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" + wire width 2 \dec_o_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_o_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_o_reg_o_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec_o_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_o_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_o_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_o_fast_o_ok + cell \dec_o \dec_o + connect \sel_in \dec_o_sel_in + connect \internal_op \dec_internal_op + connect \reg_o \dec_o_reg_o + connect \reg_o_ok \dec_o_reg_o_ok + connect \spr_o \dec_o_spr_o + connect \spr_o_ok \dec_o_spr_o_ok + connect \fast_o \dec_o_fast_o + connect \fast_o_ok \dec_o_fast_o_ok + connect \RT \dec_RT + connect \RA \dec_RA + connect \BO \dec_BO + connect \SPR \dec_SPR end - process $group_2 - assign \ibus__sel$next \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { $23 \ibus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - case 1'1 - assign \ibus__sel$next 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - case 2'1- - assign \ibus__sel$next 8'11111111 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ibus__sel$next 8'00000000 - end - sync init - update \ibus__sel 8'00000000 - sync posedge \clk - update \ibus__sel \ibus__sel$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire width 1 \dec_o2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_o2_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_o2_reg_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_o2_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_o2_fast_o_ok + cell \dec_o2 \dec_o2 + connect \lk \dec_o2_lk + connect \internal_op \dec_internal_op + connect \reg_o \dec_o2_reg_o + connect \reg_o_ok \dec_o2_reg_o_ok + connect \fast_o \dec_o2_fast_o + connect \fast_o_ok \dec_o2_fast_o_ok + connect \upd \dec_upd + connect \RA \dec_RA end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" - wire width 64 \ibus_rdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" - wire width 64 \ibus_rdata$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $31 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_rc_rc_ok + cell \dec_rc \dec_rc + connect \sel_in \dec_rc_sel_in + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \Rc \dec_Rc end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B $31 - connect \Y $33 + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_oe_oe_ok + cell \dec_oe \dec_oe + connect \sel_in \dec_oe_sel_in + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \OE \dec_OE end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $35 + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:476" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_in_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_in_cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_in_cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481" + wire width 1 \dec_cr_in_whole_reg + cell \dec_cr_in \dec_cr_in$3 + connect \sel_in \dec_cr_in_sel_in + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \whole_reg \dec_cr_in_whole_reg + connect \BB \dec_BB + connect \BA \dec_BA + connect \BT \dec_BT + connect \BI \dec_BI + connect \BC \dec_BC + connect \X_BFA \dec_X_BFA end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $37 + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" + wire width 1 \dec_cr_out_rc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_out_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:531" + wire width 1 \dec_cr_out_whole_reg + cell \dec_cr_out \dec_cr_out$4 + connect \sel_in \dec_cr_out_sel_in + connect \rc_in \dec_cr_out_rc_in + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \whole_reg \dec_cr_out_whole_reg + connect \X_BF \dec_X_BF + connect \XL_BT \dec_XL_BT end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $35 - connect \B $37 - connect \Y $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38" + wire width 32 \insn$5 + process $group_0 + assign \insn$5 32'00000000000000000000000000000000 + assign \insn$5 \dec_opcode_in + sync init end - process $group_3 - assign \ibus_rdata$next \ibus_rdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { $33 \ibus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch { $39 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - case 1'1 - assign \ibus_rdata$next \ibus__dat_r - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ibus_rdata$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78" + wire width 32 \insn_in + process $group_1 + assign \insn_in 32'00000000000000000000000000000000 + assign \insn_in \dec_opcode_in sync init - update \ibus_rdata 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \clk - update \ibus_rdata \ibus_rdata$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + wire width 32 \insn_in$6 + process $group_2 + assign \insn_in$6 32'00000000000000000000000000000000 + assign \insn_in$6 \dec_opcode_in + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B $41 - connect \Y $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" + wire width 32 \insn_in$7 + process $group_3 + assign \insn_in$7 32'00000000000000000000000000000000 + assign \insn_in$7 \dec_opcode_in + sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:287" + wire width 32 \insn_in$8 process $group_4 - assign \ibus__adr$next \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { $43 \ibus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - case 2'1- - assign \ibus__adr$next \a_pc_i [47:3] - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ibus__adr$next 45'000000000000000000000000000000000000000000000 - end + assign \insn_in$8 32'00000000000000000000000000000000 + assign \insn_in$8 \dec_opcode_in sync init - update \ibus__adr 45'000000000000000000000000000000000000000000000 - sync posedge \clk - update \ibus__adr \ibus__adr$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire width 1 \f_fetch_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire width 1 \f_fetch_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - cell $and $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" - wire width 1 \f_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - cell $not $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $47 end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + wire width 32 \insn_in$9 process $group_5 - assign \f_fetch_err_o$next \f_fetch_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - switch { $47 $45 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - case 2'-1 - assign \f_fetch_err_o$next 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - case 2'1- - assign \f_fetch_err_o$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \f_fetch_err_o$next 1'0 - end + assign \insn_in$9 32'00000000000000000000000000000000 + assign \insn_in$9 \dec_opcode_in sync init - update \f_fetch_err_o 1'0 - sync posedge \clk - update \f_fetch_err_o \f_fetch_err_o$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - cell $and $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - cell $not $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $51 end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in$10 process $group_6 - assign \f_badaddr_o$next \f_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - switch { $51 $49 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - case 2'-1 - assign \f_badaddr_o$next \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \f_badaddr_o$next 45'000000000000000000000000000000000000000000000 - end + assign \insn_in$10 32'00000000000000000000000000000000 + assign \insn_in$10 \dec_opcode_in sync init - update \f_badaddr_o 45'000000000000000000000000000000000000000000000 - sync posedge \clk - update \f_badaddr_o \f_badaddr_o$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" - wire width 1 \a_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$11 process $group_7 - assign \a_busy_o 1'0 - assign \a_busy_o \ibus__cyc + assign \insn_in$11 32'00000000000000000000000000000000 + assign \insn_in$11 \dec_opcode_in sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477" + wire width 32 \insn_in$12 process $group_8 - assign \f_busy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch { \f_fetch_err_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - case 1'1 - assign \f_busy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88" - case - assign \f_busy_o \ibus__cyc - end + assign \insn_in$12 32'00000000000000000000000000000000 + assign \insn_in$12 \dec_opcode_in sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529" + wire width 32 \insn_in$13 process $group_9 - assign \f_instr_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch { \f_fetch_err_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88" - case - assign \f_instr_o \ibus_rdata - end + assign \insn_in$13 32'00000000000000000000000000000000 + assign \insn_in$13 \dec_opcode_in sync init end - connect \a_stall_i 1'0 - connect \f_stall_i 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dbg" -module \dbg - attribute \src "simple/issuer.py:88" - wire width 1 input 0 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 1 output 1 \core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" - wire width 1 output 2 \core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:84" - wire width 1 input 3 \terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 4 \core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 5 \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:66" - wire width 1 output 6 \dbg_gpr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire width 7 output 7 \dbg_gpr_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire width 64 input 8 \dbg_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:67" - wire width 1 input 9 \dbg_gpr_ack - attribute \src "simple/issuer.py:88" - wire width 1 input 10 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire width 1 output 11 \dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:55" - wire width 4 input 12 \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 1 input 13 \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 64 output 14 \dmi_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 1 input 15 \dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:56" - wire width 64 input 16 \dmi_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" - wire width 1 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" - cell $eq $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'101 - connect \Y $2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" - cell $mux $4 - parameter \WIDTH 1 - connect \A \dmi_req_i - connect \B \dbg_gpr_ack - connect \S $2 - connect \Y $1 - end - process $group_0 - assign \dmi_ack_o 1'0 - assign \dmi_ack_o $1 + process $group_10 + assign \dec_a_sel_in 3'000 + assign \dec_a_sel_in \dec_in1_sel sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - cell $eq $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'101 - connect \Y $6 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" - cell $mux $8 - parameter \WIDTH 1 - connect \A 1'0 - connect \B \dmi_req_i - connect \S $6 - connect \Y $5 - end - process $group_1 - assign \dbg_gpr_req 1'0 - assign \dbg_gpr_req $5 + process $group_11 + assign \dec_b_sel_in 4'0000 + assign \dec_b_sel_in \dec_in2_sel sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:109" - wire width 64 \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:112" - wire width 1 \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:112" - wire width 1 \stopping$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:85" - wire width 1 \core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:116" - wire width 1 \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:116" - wire width 1 \terminated$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 64 - connect \A { \terminated \core_stopped_i \stopping } - connect \Y $9 - end - process $group_2 - assign \stat_reg 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \stat_reg $9 + process $group_12 + assign \dec_c_sel_in 2'00 + assign \dec_c_sel_in \dec_in3_sel sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" - wire width 32 \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" - wire width 32 \log_dmi_addr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:95" - wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:121" - wire width 64 \log_dmi_data - process $group_3 - assign \dmi_dout 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" - switch \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - case 4'0001 - assign \dmi_dout \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" - case 4'0010 - assign \dmi_dout \core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" - case 4'0011 - assign \dmi_dout \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" - case 4'0101 - assign \dmi_dout \dbg_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" - case 4'0110 - assign \dmi_dout { \log_write_addr_o \log_dmi_addr } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:152" - case 4'0111 - assign \dmi_dout \log_dmi_data - end + process $group_13 + assign \dec_o_sel_in 2'00 + assign \dec_o_sel_in \dec_out_sel sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:113" - wire width 1 \do_step - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:113" - wire width 1 \do_step$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:106" - wire width 1 \dmi_req_i_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:106" - wire width 1 \dmi_req_i_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $11 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $11 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:124" - wire width 1 \dmi_read_log_data_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:124" - wire width 1 \dmi_read_log_data_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" - wire width 1 \dmi_read_log_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" - wire width 1 \dmi_read_log_data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $15 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $15 - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $23 - end - process $group_4 - assign \do_step$next \do_step - assign \do_step$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $17 $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $23 $21 $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" - switch { \dmi_din [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" - case 1'1 - assign \do_step$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \do_step$next 1'0 - end + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" + wire width 2 \sel_in + process $group_14 + assign \sel_in 2'00 + assign \sel_in \dec_out_sel sync init - update \do_step 1'0 - sync posedge \clk - update \do_step \do_step$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114" - wire width 1 \do_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114" - wire width 1 \do_reset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $25 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $29 - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $37 end - process $group_5 - assign \do_reset$next \do_reset - assign \do_reset$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $31 $27 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $37 $35 $33 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" - switch { \dmi_din [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" - case 1'1 - assign \do_reset$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \do_reset$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 1 \lk$14 + process $group_15 + assign \dec_o2_lk 1'0 + assign \dec_o2_lk \lk$14 sync init - update \do_reset 1'0 - sync posedge \clk - update \do_reset \do_reset$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:115" - wire width 1 \do_icreset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:115" - wire width 1 \do_icreset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $39 - connect \Y $41 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $43 + process $group_16 + assign \dec_rc_sel_in 2'00 + assign \dec_rc_sel_in \dec_rc_sel + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $43 - connect \Y $45 + process $group_17 + assign \dec_oe_sel_in 2'00 + assign \dec_oe_sel_in \dec_rc_sel + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $47 + process $group_18 + assign \dec_cr_in_sel_in 3'000 + assign \dec_cr_in_sel_in \dec_cr_in + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $49 + process $group_19 + assign \dec_cr_out_sel_in 3'000 + assign \dec_cr_out_sel_in \dec_cr_out + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $51 + process $group_20 + assign \dec_cr_out_rc_in 1'0 + assign \dec_cr_out_rc_in \dec_rc_rc + sync init end - process $group_6 - assign \do_icreset$next \do_icreset - assign \do_icreset$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $45 $41 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $51 $49 $47 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:180" - switch { \dmi_din [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:180" - case 1'1 - assign \do_icreset$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \do_icreset$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" + wire width 64 \msr$15 + process $group_21 + assign \msr$15 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \msr$15 \dec2_msr sync init - update \do_icreset 1'0 - sync posedge \clk - update \do_icreset \do_icreset$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" - wire width 1 \do_dmi_log_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" - wire width 1 \do_dmi_log_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" + wire width 64 \cia$16 + process $group_22 + assign \cia$16 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \cia$16 \dec2_pc + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $53 - connect \Y $55 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39" + wire width 7 \insn_type$17 + process $group_23 + assign \insn_type$17 7'0000000 + assign \insn_type$17 \dec_internal_op + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $57 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40" + wire width 11 \fn_unit$18 + process $group_24 + assign \fn_unit$18 11'00000000000 + assign \fn_unit$18 \dec_function_unit + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $57 - connect \Y $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \reg1$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \reg1_ok$20 + process $group_25 + assign \reg1$19 5'00000 + assign \reg1_ok$20 1'0 + assign { \reg1_ok$20 \reg1$19 } { \dec_a_reg_a_ok \dec_a_reg_a } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \reg2$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \reg2_ok$22 + process $group_27 + assign \reg2$21 5'00000 + assign \reg2_ok$22 1'0 + assign { \reg2_ok$22 \reg2$21 } { \dec_b_reg_b_ok \dec_b_reg_b } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \reg3$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \reg3_ok$24 + process $group_29 + assign \reg3$23 5'00000 + assign \reg3_ok$24 1'0 + assign { \reg3_ok$24 \reg3$23 } { \dec_c_reg_c_ok \dec_c_reg_c } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \rego$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \rego_ok$26 + process $group_31 + assign \rego$25 5'00000 + assign \rego_ok$26 1'0 + assign { \rego_ok$26 \rego$25 } { \dec_o_reg_o_ok \dec_o_reg_o } + sync init end - process $group_7 - assign \do_dmi_log_rd$next \do_dmi_log_rd - assign \do_dmi_log_rd$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $59 $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $65 $63 $61 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - case 3'1-- - assign \do_dmi_log_rd$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - case 2'1- - assign \do_dmi_log_rd$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \do_dmi_log_rd$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \ea$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \ea_ok$28 + process $group_33 + assign \ea$27 5'00000 + assign \ea_ok$28 1'0 + assign { \ea_ok$28 \ea$27 } { \dec_o2_reg_o_ok \dec_o2_reg_o } sync init - update \do_dmi_log_rd 1'0 - sync posedge \clk - update \do_dmi_log_rd \do_dmi_log_rd$next end - process $group_8 - assign \dmi_req_i_1$next \dmi_req_i_1 - assign \dmi_req_i_1$next \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \dmi_req_i_1$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \imm$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \imm_ok$30 + process $group_35 + assign \imm$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \imm_ok$30 1'0 + assign { \imm_ok$30 \imm$29 } { \dec_b_imm_b_ok \dec_b_imm_b } sync init - update \dmi_req_i_1 1'0 - sync posedge \clk - update \dmi_req_i_1 \dmi_req_i_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 1 \zero_a$31 + process $group_37 + assign \zero_a$31 1'0 + assign \zero_a$31 \dec_a_immz_out + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $67 - connect \Y $69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \rc$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \rc_ok$33 + process $group_38 + assign \rc$32 1'0 + assign \rc_ok$33 1'0 + assign { \rc_ok$33 \rc$32 } { \dec_rc_rc_ok \dec_rc_rc } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \oe$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \oe_ok$35 + process $group_40 + assign \oe$34 1'0 + assign \oe_ok$35 1'0 + assign { \oe_ok$35 \oe$34 } { \dec_oe_oe_ok \dec_oe_oe } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $71 - connect \Y $73 + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \spr1$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \spr1_ok$37 + process $group_42 + assign \spr1$36 10'0000000000 + assign \spr1_ok$37 1'0 + assign { \spr1_ok$37 \spr1$36 } { \dec_a_spr_a_ok \dec_a_spr_a } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $75 + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \spro$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \spro_ok$39 + process $group_44 + assign \spro$38 10'0000000000 + assign \spro_ok$39 1'0 + assign { \spro_ok$39 \spro$38 } { \dec_o_spr_o_ok \dec_o_spr_o } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \fast1$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fast1_ok$41 + process $group_46 + assign \fast1$40 3'000 + assign \fast1_ok$41 1'0 + assign { \fast1_ok$41 \fast1$40 } { \dec_a_fast_a_ok \dec_a_fast_a } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \fast2$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fast2_ok$43 + process $group_48 + assign \fast2$42 3'000 + assign \fast2_ok$43 1'0 + assign { \fast2_ok$43 \fast2$42 } { \dec_b_fast_b_ok \dec_b_fast_b } + sync init end - process $group_9 - assign \terminated$next \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $73 $69 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $79 $77 $75 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" - switch { \dmi_din [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" - case 1'1 - assign \terminated$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" - switch { \dmi_din [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177" - case 1'1 - assign \terminated$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" - switch { \dmi_din [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" - case 1'1 - assign \terminated$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" - switch { \terminate_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" - case 1'1 - assign \terminated$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \terminated$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \fasto1$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fasto1_ok$45 + process $group_50 + assign \fasto1$44 3'000 + assign \fasto1_ok$45 1'0 + assign { \fasto1_ok$45 \fasto1$44 } { \dec_o_fast_o_ok \dec_o_fast_o } sync init - update \terminated 1'0 - sync posedge \clk - update \terminated \terminated$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \fasto2$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fasto2_ok$47 + process $group_52 + assign \fasto2$46 3'000 + assign \fasto2_ok$47 1'0 + assign { \fasto2_ok$47 \fasto2$46 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $81 - connect \Y $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_in1$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_in1_ok$49 + process $group_54 + assign \cr_in1$48 3'000 + assign \cr_in1_ok$49 1'0 + assign { \cr_in1_ok$49 \cr_in1$48 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_in2$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_in2_ok$51 + process $group_56 + assign \cr_in2$50 3'000 + assign \cr_in2_ok$51 1'0 + assign { \cr_in2_ok$51 \cr_in2$50 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $85 - connect \Y $87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_in2$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_in2_ok$53 + process $group_58 + assign \cr_in2$52 3'000 + assign \cr_in2_ok$53 1'0 + assign { \cr_in2_ok$53 \cr_in2$52 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_out$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_out_ok$55 + process $group_60 + assign \cr_out$54 3'000 + assign \cr_out_ok$55 1'0 + assign { \cr_out_ok$55 \cr_out$54 } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" + wire width 1 \read_cr_whole$56 + process $group_62 + assign \read_cr_whole$56 1'0 + assign \read_cr_whole$56 \dec_cr_in_whole_reg + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" + wire width 1 \write_cr_whole$57 + process $group_63 + assign \write_cr_whole$57 1'0 + assign \write_cr_whole$57 \dec_cr_out_whole_reg + sync init end - process $group_10 - assign \stopping$next \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $87 $83 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $93 $91 $89 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:175" - switch { \dmi_din [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:175" - case 1'1 - assign \stopping$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" - switch { \dmi_din [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182" - case 1'1 - assign \stopping$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" - switch { \terminate_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" - case 1'1 - assign \stopping$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \stopping$next 1'0 - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" + wire width 1 \write_cr0$58 + process $group_64 + assign \write_cr0$58 1'0 + assign \write_cr0$58 \dec_cr_out_cr_bitfield_ok sync init - update \stopping 1'0 - sync posedge \clk - update \stopping \stopping$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:118" - wire width 7 \gspr_index - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:118" - wire width 7 \gspr_index$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" + wire width 4 \data_len$59 + process $group_65 + assign \data_len$59 4'0000 + assign \data_len$59 \dec_ldst_len + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $95 - connect \Y $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 1 \invert_in$60 + process $group_66 + assign \invert_in$60 1'0 + assign \invert_in$60 \dec_inv_a + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 1 \invert_out$61 + process $group_67 + assign \invert_out$61 1'0 + assign \invert_out$61 \dec_inv_out + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $99 - connect \Y $101 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 2 \input_carry$62 + process $group_68 + assign \input_carry$62 2'00 + assign \input_carry$62 \dec_cry_in + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 1 \output_carry$63 + process $group_69 + assign \output_carry$63 1'0 + assign \output_carry$63 \dec_cry_out + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 1 \is_32bit$64 + process $group_70 + assign \is_32bit$64 1'0 + assign \is_32bit$64 \dec_is_32b + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 1 \is_signed$65 + process $group_71 + assign \is_signed$65 1'0 + assign \is_signed$65 \dec_sgn + sync init end - process $group_11 - assign \gspr_index$next \gspr_index - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $101 $97 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $107 $105 $103 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - case 3'-1- - assign \gspr_index$next \dmi_din [6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst + process $group_72 + assign \lk$14 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680" + switch { \dec_lk } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680" case 1'1 - assign \gspr_index$next 7'0000000 + assign \lk$14 \dec_LK end sync init - update \gspr_index 7'0000000 - sync posedge \clk - update \gspr_index \gspr_index$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $not $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 1 \byte_reverse$66 + process $group_73 + assign \byte_reverse$66 1'0 + assign \byte_reverse$66 \dec_br + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - cell $and $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $109 - connect \Y $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire width 1 \sign_extend$67 + process $group_74 + assign \sign_extend$67 1'0 + assign \sign_extend$67 \dec_sgn_ext + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $not $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $113 + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" + wire width 2 \ldst_mode$68 + process $group_75 + assign \ldst_mode$68 2'00 + assign \ldst_mode$68 \dec_upd + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - cell $and $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $113 - connect \Y $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire width 1 \input_cr$69 + process $group_76 + assign \input_cr$69 1'0 + assign \input_cr$69 \dec_cr_in [0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $eq $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" + wire width 1 \output_cr$70 + process $group_77 + assign \output_cr$70 1'0 + assign \output_cr$70 \dec_cr_out [0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - cell $eq $120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82" + wire width 1 \xer_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:694" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:694" + cell $eq $73 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $119 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $72 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - cell $eq $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $121 + process $group_78 + assign \xer_in$71 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:694" + switch { $72 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:694" + case 1'1 + assign \xer_in$71 1'1 + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - wire width 3 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - wire width 3 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - cell $add $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83" + wire width 1 \xer_out$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" + cell $eq $76 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \log_dmi_addr [1:0] - connect \B 1'1 - connect \Y $124 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $75 end - connect $123 $124 - process $group_12 - assign \log_dmi_addr$next \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - switch { $115 $111 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - switch { $121 $119 $117 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191" - case 3'1-- - assign \log_dmi_addr$next \dmi_din [31:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198" - case 2'1- - assign \log_dmi_addr$next [1:0] $123 [1:0] - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst + process $group_79 + assign \xer_out$74 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696" case 1'1 - assign \log_dmi_addr$next 32'00000000000000000000000000000000 + assign \xer_out$74 1'1 end sync init - update \log_dmi_addr 32'00000000000000000000000000000000 - sync posedge \clk - update \log_dmi_addr \log_dmi_addr$next end - process $group_13 - assign \dmi_read_log_data_1$next \dmi_read_log_data_1 - assign \dmi_read_log_data_1$next \dmi_read_log_data - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" + wire width 13 \trapaddr$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700" + cell $eq $79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $78 + end + process $group_80 + assign \trapaddr$77 13'0000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700" + switch { $78 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700" case 1'1 - assign \dmi_read_log_data_1$next 1'0 + assign \trapaddr$77 13'0000001110000 end sync init - update \dmi_read_log_data_1 1'0 - sync posedge \clk - update \dmi_read_log_data_1 \dmi_read_log_data_1$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" - wire width 1 $126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" - cell $eq $127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'111 - connect \Y $126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:38" + wire width 1 \is_priv_insn + process $group_81 + assign \is_priv_insn 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:39" + switch \dec_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" + attribute \nmigen.decoding "OP_ATTN/5|OP_MFMSR/71|OP_MTMSRD/72|OP_MTMSR/74|OP_RFID/70" + case 7'0000101, 7'1000111, 7'1001000, 7'1001010, 7'1000110 + assign \is_priv_insn 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45" + attribute \nmigen.decoding "OP_MFSPR/46|OP_MTSPR/49" + case 7'0101110, 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:46" + switch { \insn$5 [20] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:46" + case 1'1 + assign \is_priv_insn 1'1 + end + end + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" - wire width 1 $128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206" - cell $and $129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706" + wire width 1 $80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706" + cell $and $81 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $126 - connect \Y $128 + connect \A \is_priv_insn + connect \B \dec2_msr [14] + connect \Y $80 end - process $group_14 - assign \dmi_read_log_data$next \dmi_read_log_data - assign \dmi_read_log_data$next $128 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \dmi_read_log_data$next 1'0 - end - sync init - update \dmi_read_log_data 1'0 - sync posedge \clk - update \dmi_read_log_data \dmi_read_log_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" + wire width 1 $82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" + cell $eq $83 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $82 end - process $group_15 - assign \dbg_gpr_addr 7'0000000 - assign \dbg_gpr_addr \gspr_index - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" + wire width 8 \asmcode$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire width 5 \traptype$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:724" + wire width 1 $86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:724" + cell $eq $87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $86 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - wire width 1 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - cell $not $131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" + wire width 1 $88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" + cell $eq $89 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \do_step - connect \Y $130 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $88 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - wire width 1 $132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - cell $and $133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" + wire width 1 $90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" + cell $or $91 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \stopping - connect \B $130 - connect \Y $132 - end - process $group_16 - assign \core_stop_o 1'0 - assign \core_stop_o $132 - sync init - end - process $group_17 - assign \core_rst_o 1'0 - assign \core_rst_o \do_reset - sync init + connect \A $86 + connect \B $88 + connect \Y $90 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:81" - wire width 1 \icache_rst_o - process $group_18 - assign \icache_rst_o 1'0 - assign \icache_rst_o \do_icreset - sync init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:734" + wire width 1 $92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:734" + cell $eq $93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $92 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" - wire width 1 \terminated_o - process $group_19 - assign \terminated_o 1'0 - assign \terminated_o \terminated + process $group_82 + assign \asmcode 8'00000000 + assign \rego 5'00000 + assign \rego_ok 1'0 + assign \ea 5'00000 + assign \ea_ok 1'0 + assign \reg1 5'00000 + assign \reg1_ok 1'0 + assign \reg2 5'00000 + assign \reg2_ok 1'0 + assign \reg3 5'00000 + assign \reg3_ok 1'0 + assign \spro 10'0000000000 + assign \spro_ok 1'0 + assign \spr1 10'0000000000 + assign \spr1_ok 1'0 + assign \xer_in 1'0 + assign \xer_out 1'0 + assign \fast1 3'000 + assign \fast1_ok 1'0 + assign \fast2 3'000 + assign \fast2_ok 1'0 + assign \fasto1 3'000 + assign \fasto1_ok 1'0 + assign \fasto2 3'000 + assign \fasto2_ok 1'0 + assign \cr_in1 3'000 + assign \cr_in1_ok 1'0 + assign \cr_in2 3'000 + assign \cr_in2_ok 1'0 + assign \cr_in2$1 3'000 + assign \cr_in2_ok$2 1'0 + assign \cr_out 3'000 + assign \cr_out_ok 1'0 + assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \cia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \insn 32'00000000000000000000000000000000 + assign \insn_type 7'0000000 + assign \fn_unit 11'00000000000 + assign \imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \imm_ok 1'0 + assign \lk 1'0 + assign \rc 1'0 + assign \rc_ok 1'0 + assign \oe 1'0 + assign \oe_ok 1'0 + assign \invert_in 1'0 + assign \zero_a 1'0 + assign \input_carry 2'00 + assign \output_carry 1'0 + assign \input_cr 1'0 + assign \output_cr 1'0 + assign \invert_out 1'0 + assign \is_32bit 1'0 + assign \is_signed 1'0 + assign \data_len 4'0000 + assign \byte_reverse 1'0 + assign \sign_extend 1'0 + assign \ldst_mode 2'00 + assign \traptype 5'00000 + assign \trapaddr 13'0000000000000 + assign \read_cr_whole 1'0 + assign \write_cr_whole 1'0 + assign \write_cr0 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706" + switch { $82 $80 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706" + case 2'-1 + assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_in \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \insn \dec_opcode_in + assign \insn_type 7'0111111 + assign \fn_unit 11'00010000000 + assign \trapaddr 13'0000001110000 + assign \traptype 5'00010 + assign \msr \dec2_msr + assign \cia \dec2_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" + case 2'1- + assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_in \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \insn \dec_opcode_in + assign \insn_type 7'0111111 + assign \fn_unit 11'00010000000 + assign \trapaddr 13'0000001110000 + assign \traptype 5'10000 + assign \msr \dec2_msr + assign \cia \dec2_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + case + assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_in \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } { \write_cr0$58 \write_cr_whole$57 \read_cr_whole$56 \trapaddr$77 \traptype$85 \ldst_mode$68 \sign_extend$67 \byte_reverse$66 \data_len$59 \is_signed$65 \is_32bit$64 \invert_out$61 \output_cr$70 \input_cr$69 \output_carry$63 \input_carry$62 \zero_a$31 \invert_in$60 \oe_ok$35 \oe$34 \rc_ok$33 \rc$32 \lk$14 \imm_ok$30 \imm$29 \fn_unit$18 \insn_type$17 \insn$5 \cia$16 \msr$15 { \cr_out_ok$55 \cr_out$54 } { \cr_in2_ok$53 \cr_in2$52 } { \cr_in2_ok$51 \cr_in2$50 } { \cr_in1_ok$49 \cr_in1$48 } { \fasto2_ok$47 \fasto2$46 } { \fasto1_ok$45 \fasto1$44 } { \fast2_ok$43 \fast2$42 } { \fast1_ok$41 \fast1$40 } \xer_out$74 \xer_in$71 { \spr1_ok$37 \spr1$36 } { \spro_ok$39 \spro$38 } { \reg3_ok$24 \reg3$23 } { \reg2_ok$22 \reg2$21 } { \reg1_ok$20 \reg1$19 } { \ea_ok$28 \ea$27 } { \rego_ok$26 \rego$25 } \asmcode$84 } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" + switch { $90 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:725" + case 1'1 + assign \fasto1 3'011 + assign \fasto1_ok 1'1 + assign \fasto2 3'100 + assign \fasto2_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:734" + switch { $92 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:734" + case 1'1 + assign \fast1 3'011 + assign \fast1_ok 1'1 + assign \fast2 3'100 + assign \fast2_ok 1'1 + end sync init end - connect \core_stopped_i 1'0 - connect \log_write_addr_o 32'00000000000000000000000000000000 - connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \asmcode$84 8'00000000 + connect \traptype$85 5'00000 end attribute \generator "nMigen" attribute \top 1 attribute \nmigen.hierarchy "test_issuer" module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 0 \pc_i + wire width 64 input 0 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 input 1 \pc_i_ok + attribute \src "simple/issuer.py:62" + wire width 64 output 2 \pc_o + attribute \src "simple/issuer.py:66" + wire width 1 input 3 \memerr_o + attribute \src "simple/issuer.py:64" + wire width 1 input 4 \core_bigendian_i + attribute \src "simple/issuer.py:101" + wire width 1 input 5 \clk + attribute \src "simple/issuer.py:101" + wire width 1 input 6 \rst + attribute \src "simple/issuer.py:65" + wire width 1 output 7 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:55" + wire width 4 input 8 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:56" + wire width 64 input 9 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 64 output 10 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 1 input 11 \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 1 input 12 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire width 1 output 13 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 14 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 15 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 16 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 17 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 output 18 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 output 19 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 input 20 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 input 21 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 22 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 23 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 1 input 24 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 25 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 26 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 27 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 28 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 29 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 30 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 input 31 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 output 32 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 3 input 33 \dbus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 2 input 34 \dbus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 1 input 35 \dbus__err + attribute \src "simple/issuer.py:100" + wire width 1 \por_clk + attribute \src "simple/issuer.py:102" + wire width 1 \core_coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88" + wire width 1 \core_core_reset_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:84" + wire width 1 \core_corebusy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 \core_cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 \core_cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 \core_cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 1 \core_cu_st__go_i + attribute \src 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\core_zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 1 \core_zero_a$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 2 \core_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 2 \core_input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 1 \core_output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 1 \core_output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire width 1 \core_input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire width 1 \core_input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" + wire width 1 \core_output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" + wire width 1 \core_output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 1 \core_invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 1 \core_invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 1 \core_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 1 \core_is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 1 \core_is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 1 \core_is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" + wire width 4 \core_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" + wire width 4 \core_data_len$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 1 \core_byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 1 \core_byte_reverse$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire width 1 \core_sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire width 1 \core_sign_extend$next + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" + wire width 2 \core_ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" + wire width 2 \core_ldst_mode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire width 5 \core_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire width 5 \core_traptype$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" + wire width 13 \core_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" + wire width 13 \core_trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" + wire width 1 \core_read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" + wire width 1 \core_read_cr_whole$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" + wire width 1 \core_write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" + wire width 1 \core_write_cr_whole$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" + wire width 1 \core_write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" + wire width 1 \core_write_cr0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \core_msr__data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:82" + wire width 1 \core_ivalid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:83" + wire width 1 \core_issue_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \core_state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \core_dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \core_dmi__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \core_dmi__data_o + cell \core \core + connect \coresync_clk \core_coresync_clk + connect \core_reset_i \core_core_reset_i + connect \corebusy_o \core_corebusy_o + connect \cu_st__rel_o \core_cu_st__rel_o + connect \cu_ad__go_i \core_cu_ad__go_i + connect \cu_ad__rel_o \core_cu_ad__rel_o + connect \cu_st__go_i \core_cu_st__go_i + connect \cia__ren \core_cia__ren + connect \cia__data_o \core_cia__data_o + connect \wen \core_wen + connect \data_i \core_data_i + connect \msr__ren \core_msr__ren + connect \core_terminate_o \core_core_terminate_o + connect \rego \core_rego + connect \ea \core_ea + connect \reg1 \core_reg1 + connect \reg1_ok \core_reg1_ok + connect \reg2 \core_reg2 + connect \reg2_ok \core_reg2_ok + connect \reg3 \core_reg3 + connect \reg3_ok \core_reg3_ok + connect \spro \core_spro + connect \spr1 \core_spr1 + connect \spr1_ok \core_spr1_ok + connect \xer_in \core_xer_in + connect \fast1 \core_fast1 + connect \fast1_ok \core_fast1_ok + connect \fast2 \core_fast2 + connect \fast2_ok \core_fast2_ok + connect \fasto1 \core_fasto1 + connect \fasto2 \core_fasto2 + connect \cr_in1 \core_cr_in1 + connect \cr_in1_ok \core_cr_in1_ok + connect \cr_in2 \core_cr_in2 + connect \cr_in2_ok \core_cr_in2_ok + connect \cr_in2$1 \core_cr_in2$1 + connect \cr_in2_ok$2 \core_cr_in2_ok$2 + connect \cr_out \core_cr_out + connect \msr \core_msr + connect \cia \core_cia + connect \insn \core_insn + connect \insn_type \core_insn_type + connect \fn_unit \core_fn_unit + connect \imm \core_imm + connect \imm_ok \core_imm_ok + connect \lk \core_lk + connect \rc \core_rc + connect \rc_ok \core_rc_ok + connect \oe \core_oe + connect \oe_ok \core_oe_ok + connect \invert_in \core_invert_in + connect \zero_a \core_zero_a + connect \input_carry \core_input_carry + connect \output_carry \core_output_carry + connect \input_cr \core_input_cr + connect \output_cr \core_output_cr + connect \invert_out \core_invert_out + connect \is_32bit \core_is_32bit + connect \is_signed \core_is_signed + connect \data_len \core_data_len + connect \byte_reverse \core_byte_reverse + connect \sign_extend \core_sign_extend + connect \ldst_mode \core_ldst_mode + connect \traptype \core_traptype + connect \trapaddr \core_trapaddr + connect \read_cr_whole \core_read_cr_whole + connect \write_cr_whole \core_write_cr_whole + connect \write_cr0 \core_write_cr0 + connect \msr__data_o \core_msr__data_o + connect \ivalid_i \core_ivalid_i + connect \issue_i \core_issue_i + connect \state_nia_wen \core_state_nia_wen + connect \dmi__addr \core_dmi__addr + connect \dmi__ren \core_dmi__ren + connect \dmi__data_o \core_dmi__data_o + connect \dbus__cyc \dbus__cyc + connect \dbus__ack \dbus__ack + connect \dbus__err \dbus__err + connect \dbus__stb \dbus__stb + connect \dbus__sel \dbus__sel + connect \dbus__dat_r \dbus__dat_r + connect \dbus__adr \dbus__adr + connect \dbus__we \dbus__we + connect \dbus__dat_w \dbus__dat_w + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 \imem_a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire width 1 \imem_a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire width 1 \imem_f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire width 1 \imem_f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 \imem_f_instr_o + cell \imem \imem + connect \clk \clk + connect \a_pc_i \imem_a_pc_i + connect \a_valid_i \imem_a_valid_i + connect \f_valid_i \imem_f_valid_i + connect \f_busy_o \imem_f_busy_o + connect \f_instr_o \imem_f_instr_o + connect \rst \rst + connect \ibus__cyc \ibus__cyc + connect \ibus__ack \ibus__ack + connect \ibus__err \ibus__err + connect \ibus__stb \ibus__stb + connect \ibus__sel \ibus__sel + connect \ibus__dat_r \ibus__dat_r + connect \ibus__adr \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" + wire width 1 \dbg_core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:84" + wire width 1 \dbg_terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dbg_core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dbg_core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 1 \dbg_core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:85" + wire width 1 \dbg_core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:66" + wire width 1 \dbg_dbg_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" + wire width 7 \dbg_dbg_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" + wire width 64 \dbg_dbg_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:67" + wire width 1 \dbg_dbg_gpr_ack + cell \dbg \dbg + connect \clk \clk + connect \core_rst_o \dbg_core_rst_o + connect \terminate_i \dbg_terminate_i + connect \core_dbg_pc \dbg_core_dbg_pc + connect \core_dbg_msr \dbg_core_dbg_msr + connect \core_stop_o \dbg_core_stop_o + connect \core_stopped_i \dbg_core_stopped_i + connect \dbg_gpr_req \dbg_dbg_gpr_req + connect \dbg_gpr_addr \dbg_dbg_gpr_addr + connect \dbg_gpr_data \dbg_dbg_gpr_data + connect \dbg_gpr_ack \dbg_dbg_gpr_ack + connect \rst \rst + connect \dmi_ack_o \dmi_ack_o + connect \dmi_addr_i \dmi_addr_i + connect \dmi_req_i \dmi_req_i + connect \dmi_dout \dmi_dout + connect \dmi_we_i \dmi_we_i + connect \dmi_din \dmi_din + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" + wire width 1 \dec2_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:337" + wire width 32 \dec2_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dec2_dec2_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dec2_dec2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" + wire width 8 \dec2_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_rego_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec2_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_reg3_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute 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attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute 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attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec2_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_spro_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec2_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 1 \pc_i_ok - attribute \src "simple/issuer.py:56" - wire width 64 output 2 \pc_o - attribute \src "simple/issuer.py:60" - wire width 1 input 3 \memerr_o - attribute \src "simple/issuer.py:58" - wire width 1 input 4 \core_bigendian_i - attribute \src "simple/issuer.py:88" - wire width 1 input 5 \clk - attribute \src "simple/issuer.py:88" - wire width 1 input 6 \rst - attribute \src "simple/issuer.py:59" - wire width 1 output 7 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:55" - wire width 4 input 8 \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:56" - wire width 64 input 9 \dmi_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 64 output 10 \dmi_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 1 input 11 \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 1 input 12 \dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire width 1 output 13 \dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 14 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 15 \ibus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 16 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 17 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 output 18 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 output 19 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 input 20 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 input 21 \ibus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 3 input 22 \ibus__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 2 input 23 \ibus__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 input 24 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 45 output 25 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 output 26 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 input 27 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 8 output 28 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 29 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 30 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 31 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 32 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 3 input 33 \dbus__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 2 input 34 \dbus__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 35 \dbus__err - attribute \src "simple/issuer.py:87" - wire width 1 \por_clk - attribute \src "simple/issuer.py:89" - wire width 1 \core_coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:82" - wire width 1 \core_corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332" - wire width 1 \core_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 \core_cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 \core_cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 \core_cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 \core_cu_st__go_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \core_cia__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \core_cia__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:90" - wire width 1 \core_core_reset_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:91" - wire width 1 \core_core_terminate_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \core_msr__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \core_msr__ren$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \core_msr__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire width 1 \core_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:81" - wire width 1 \core_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331" - wire width 32 \core_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \core_dec2_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \core_dec2_msr + wire width 1 \dec2_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82" + wire width 1 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83" + wire width 1 \dec2_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_in2$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_cr_in2_ok$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec2_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" + wire width 64 \dec2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" + wire width 64 \dec2_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38" + wire width 32 \dec2_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -160306,123 +290550,157 @@ module \test_issuer attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39" - wire width 7 \core_insn_type - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \core_state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \core_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \core_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \core_dmi__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \core_dmi__data_o - cell \core \core - connect \coresync_clk \core_coresync_clk - connect \corebusy_o \core_corebusy_o - connect \bigendian \core_bigendian - connect \cu_st__rel_o \core_cu_st__rel_o - connect \cu_ad__go_i \core_cu_ad__go_i - connect \cu_ad__rel_o \core_cu_ad__rel_o - connect \cu_st__go_i \core_cu_st__go_i - connect \cia__ren \core_cia__ren - connect \cia__data_o \core_cia__data_o - connect \core_reset_i \core_core_reset_i - connect \core_terminate_o \core_core_terminate_o - connect \msr__ren \core_msr__ren - connect \msr__data_o \core_msr__data_o - connect \valid \core_valid - connect \issue_i \core_issue_i - connect \raw_opcode_in \core_raw_opcode_in - connect \dec2_pc \core_dec2_pc - connect \dec2_msr \core_dec2_msr - connect \insn_type \core_insn_type - connect \state_nia_wen \core_state_nia_wen - connect \wen \core_wen - connect \data_i \core_data_i - connect \dmi__ren \core_dmi__ren - connect \dmi__data_o \core_dmi__data_o - connect \dbus__cyc \dbus__cyc - connect \dbus__ack \dbus__ack - connect \dbus__err \dbus__err - connect \dbus__stb \dbus__stb - connect \dbus__sel \dbus__sel - connect \dbus__dat_r \dbus__dat_r - connect \dbus__adr \dbus__adr - connect \dbus__we \dbus__we - connect \dbus__dat_w \dbus__dat_w - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 \imem_a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire width 1 \imem_a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire width 1 \imem_f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire width 1 \imem_f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 \imem_f_instr_o - cell \imem \imem - connect \clk \clk - connect \a_pc_i \imem_a_pc_i - connect \a_valid_i \imem_a_valid_i - connect \f_valid_i \imem_f_valid_i - connect \f_busy_o \imem_f_busy_o - connect \f_instr_o \imem_f_instr_o - connect \rst \rst - connect \ibus__cyc \ibus__cyc - connect \ibus__ack \ibus__ack - connect \ibus__err \ibus__err - connect \ibus__stb \ibus__stb - connect \ibus__sel \ibus__sel - connect \ibus__dat_r \ibus__dat_r - connect \ibus__adr \ibus__adr - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 1 \dbg_core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" - wire width 1 \dbg_core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:84" - wire width 1 \dbg_terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dbg_core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dbg_core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:66" - wire width 1 \dbg_dbg_gpr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire width 7 \dbg_dbg_gpr_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire width 64 \dbg_dbg_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:67" - wire width 1 \dbg_dbg_gpr_ack - cell \dbg \dbg - connect \clk \clk - connect \core_stop_o \dbg_core_stop_o - connect \core_rst_o \dbg_core_rst_o - connect \terminate_i \dbg_terminate_i - connect \core_dbg_pc \dbg_core_dbg_pc - connect \core_dbg_msr \dbg_core_dbg_msr - connect \dbg_gpr_req \dbg_dbg_gpr_req - connect \dbg_gpr_addr \dbg_dbg_gpr_addr - connect \dbg_gpr_data \dbg_dbg_gpr_data - connect \dbg_gpr_ack \dbg_dbg_gpr_ack - connect \rst \rst - connect \dmi_ack_o \dmi_ack_o - connect \dmi_addr_i \dmi_addr_i - connect \dmi_req_i \dmi_req_i - connect \dmi_dout \dmi_dout - connect \dmi_we_i \dmi_we_i - connect \dmi_din \dmi_din - end - attribute \src "simple/issuer.py:92" + wire width 7 \dec2_insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:40" + wire width 11 \dec2_fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec2_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 1 \dec2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \dec2_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 1 \dec2_invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 1 \dec2_zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 2 \dec2_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 1 \dec2_output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire width 1 \dec2_input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" + wire width 1 \dec2_output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 1 \dec2_invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 1 \dec2_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 1 \dec2_is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" + wire width 4 \dec2_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 1 \dec2_byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire width 1 \dec2_sign_extend + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" + wire width 2 \dec2_ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire width 5 \dec2_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" + wire width 13 \dec2_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60" + wire width 1 \dec2_read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" + wire width 1 \dec2_write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" + wire width 1 \dec2_write_cr0 + cell \dec2 \dec2 + connect \bigendian \dec2_bigendian + connect \raw_opcode_in \dec2_raw_opcode_in + connect \dec2_pc \dec2_dec2_pc + connect \dec2_msr \dec2_dec2_msr + connect \asmcode \dec2_asmcode + connect \rego \dec2_rego + connect \rego_ok \dec2_rego_ok + connect \ea \dec2_ea + connect \ea_ok \dec2_ea_ok + connect \reg1 \dec2_reg1 + connect \reg1_ok \dec2_reg1_ok + connect \reg2 \dec2_reg2 + connect \reg2_ok \dec2_reg2_ok + connect \reg3 \dec2_reg3 + connect \reg3_ok \dec2_reg3_ok + connect \spro \dec2_spro + connect \spro_ok \dec2_spro_ok + connect \spr1 \dec2_spr1 + connect \spr1_ok \dec2_spr1_ok + connect \xer_in \dec2_xer_in + connect \xer_out \dec2_xer_out + connect \fast1 \dec2_fast1 + connect \fast1_ok \dec2_fast1_ok + connect \fast2 \dec2_fast2 + connect \fast2_ok \dec2_fast2_ok + connect \fasto1 \dec2_fasto1 + connect \fasto1_ok \dec2_fasto1_ok + connect \fasto2 \dec2_fasto2 + connect \fasto2_ok \dec2_fasto2_ok + connect \cr_in1 \dec2_cr_in1 + connect \cr_in1_ok \dec2_cr_in1_ok + connect \cr_in2 \dec2_cr_in2 + connect \cr_in2_ok \dec2_cr_in2_ok + connect \cr_in2$1 \dec2_cr_in2$3 + connect \cr_in2_ok$2 \dec2_cr_in2_ok$4 + connect \cr_out \dec2_cr_out + connect \cr_out_ok \dec2_cr_out_ok + connect \msr \dec2_msr + connect \cia \dec2_cia + connect \insn \dec2_insn + connect \insn_type \dec2_insn_type + connect \fn_unit \dec2_fn_unit + connect \imm \dec2_imm + connect \imm_ok \dec2_imm_ok + connect \lk \dec2_lk + connect \rc \dec2_rc + connect \rc_ok \dec2_rc_ok + connect \oe \dec2_oe + connect \oe_ok \dec2_oe_ok + connect \invert_in \dec2_invert_in + connect \zero_a \dec2_zero_a + connect \input_carry \dec2_input_carry + connect \output_carry \dec2_output_carry + connect \input_cr \dec2_input_cr + connect \output_cr \dec2_output_cr + connect \invert_out \dec2_invert_out + connect \is_32bit \dec2_is_32bit + connect \is_signed \dec2_is_signed + connect \data_len \dec2_data_len + connect \byte_reverse \dec2_byte_reverse + connect \sign_extend \dec2_sign_extend + connect \ldst_mode \dec2_ldst_mode + connect \traptype \dec2_traptype + connect \trapaddr \dec2_trapaddr + connect \read_cr_whole \dec2_read_cr_whole + connect \write_cr_whole \dec2_write_cr_whole + connect \write_cr0 \dec2_write_cr0 + end + attribute \src "simple/issuer.py:105" wire width 2 \delay - attribute \src "simple/issuer.py:92" + attribute \src "simple/issuer.py:105" wire width 2 \delay$next - attribute \src "simple/issuer.py:93" - wire width 1 $1 - attribute \src "simple/issuer.py:93" - cell $ne $2 + attribute \src "simple/issuer.py:106" + wire width 1 $5 + attribute \src "simple/issuer.py:106" + cell $ne $6 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -160430,14 +290708,14 @@ module \test_issuer parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 - connect \Y $1 + connect \Y $5 end - attribute \src "simple/issuer.py:94" - wire width 3 $3 - attribute \src "simple/issuer.py:94" - wire width 3 $4 - attribute \src "simple/issuer.py:94" - cell $sub $5 + attribute \src "simple/issuer.py:107" + wire width 3 $7 + attribute \src "simple/issuer.py:107" + wire width 3 $8 + attribute \src "simple/issuer.py:107" + cell $sub $9 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -160445,19 +290723,19 @@ module \test_issuer parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $4 + connect \Y $8 end - connect $3 $4 + connect $7 $8 process $group_0 assign \delay$next \delay - attribute \src "simple/issuer.py:93" - switch { $1 } - attribute \src "simple/issuer.py:93" + attribute \src "simple/issuer.py:106" + switch { $5 } + attribute \src "simple/issuer.py:106" case 1'1 - assign \delay$next $3 [1:0] + assign \delay$next $7 [1:0] end sync init - update \delay 2'01 + update \delay 2'11 sync posedge \por_clk update \delay \delay$next end @@ -160471,21 +290749,52 @@ module \test_issuer assign \core_coresync_clk \clk sync init end + attribute \src "simple/issuer.py:111" + wire width 1 $10 + attribute \src "simple/issuer.py:111" + cell $or $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \dbg_core_rst_o + connect \Y $10 + end + attribute \src "simple/issuer.py:111" + wire width 1 $12 + attribute \src "simple/issuer.py:111" + cell $ne $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \delay + connect \B $10 + connect \Y $12 + end process $group_3 + assign \core_core_reset_i 1'0 + assign \core_core_reset_i $12 + sync init + end + process $group_4 assign \busy_o 1'0 assign \busy_o \core_corebusy_o sync init end - process $group_4 - assign \core_bigendian 1'0 - assign \core_bigendian \core_bigendian_i + process $group_5 + assign \dec2_bigendian 1'0 + assign \dec2_bigendian \core_bigendian_i sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \cu_st__rel_o_dly attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" wire width 1 \cu_st__rel_o_dly$next - process $group_5 + process $group_6 assign \cu_st__rel_o_dly$next \cu_st__rel_o_dly assign \cu_st__rel_o_dly$next \core_cu_st__rel_o sync init @@ -160496,39 +290805,39 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" wire width 1 \cu_st__rel_o_rise attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $6 + wire width 1 $14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $7 + cell $not $15 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o_dly - connect \Y $6 + connect \Y $14 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $8 + wire width 1 $16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $9 + cell $and $17 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_cu_st__rel_o - connect \B $6 - connect \Y $8 + connect \B $14 + connect \Y $16 end - process $group_6 + process $group_7 assign \cu_st__rel_o_rise 1'0 - assign \cu_st__rel_o_rise $8 + assign \cu_st__rel_o_rise $16 sync init end - process $group_7 + process $group_8 assign \core_cu_ad__go_i 1'0 assign \core_cu_ad__go_i \core_cu_ad__rel_o sync init end - process $group_8 + process $group_9 assign \core_cu_st__go_i 1'0 assign \core_cu_st__go_i \cu_st__rel_o_rise sync init @@ -160537,19 +290846,19 @@ module \test_issuer wire width 64 \cur_pc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" wire width 64 \cur_pc$next - process $group_9 + process $group_10 assign \pc_o 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pc_o \cur_pc sync init end - attribute \src "simple/issuer.py:121" + attribute \src "simple/issuer.py:133" wire width 64 \nia - attribute \src "simple/issuer.py:122" - wire width 65 $10 - attribute \src "simple/issuer.py:122" - wire width 65 $11 - attribute \src "simple/issuer.py:122" - cell $add $12 + attribute \src "simple/issuer.py:134" + wire width 65 $18 + attribute \src "simple/issuer.py:134" + wire width 65 $19 + attribute \src "simple/issuer.py:134" + cell $add $20 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -160557,148 +290866,293 @@ module \test_issuer parameter \Y_WIDTH 65 connect \A \cur_pc connect \B 3'100 - connect \Y $11 + connect \Y $19 end - connect $10 $11 - process $group_10 + connect $18 $19 + process $group_11 assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia $10 [63:0] + assign \nia $18 [63:0] + sync init + end + attribute \src "simple/issuer.py:138" + wire width 1 \pc_ok_delay + attribute \src "simple/issuer.py:138" + wire width 1 \pc_ok_delay$next + attribute \src "simple/issuer.py:139" + wire width 1 $21 + attribute \src "simple/issuer.py:139" + cell $not $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_i_ok + connect \Y $21 + end + process $group_12 + assign \pc_ok_delay$next \pc_ok_delay + assign \pc_ok_delay$next $21 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \pc_ok_delay$next 1'0 + end sync init + update \pc_ok_delay 1'0 + sync posedge \clk + update \pc_ok_delay \pc_ok_delay$next end - attribute \src "simple/issuer.py:125" + attribute \src "simple/issuer.py:137" wire width 64 \pc - process $group_11 + process $group_13 assign \pc 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:126" + attribute \src "simple/issuer.py:140" switch { \pc_i_ok } - attribute \src "simple/issuer.py:126" + attribute \src "simple/issuer.py:140" case 1'1 assign \pc \pc_i - attribute \src "simple/issuer.py:129" + attribute \src "simple/issuer.py:143" case + end + attribute \src "simple/issuer.py:147" + switch { \pc_ok_delay } + attribute \src "simple/issuer.py:147" + case 1'1 assign \pc \core_cia__data_o end sync init end - process $group_12 + process $group_14 assign \core_cia__ren 2'00 - attribute \src "simple/issuer.py:126" + attribute \src "simple/issuer.py:140" switch { \pc_i_ok } - attribute \src "simple/issuer.py:126" + attribute \src "simple/issuer.py:140" case 1'1 - attribute \src "simple/issuer.py:129" + attribute \src "simple/issuer.py:143" case assign \core_cia__ren 2'01 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89" - wire width 1 \core_stopped_i - process $group_13 - assign \core_stopped_i 1'0 - assign \core_stopped_i \dbg_core_stop_o - sync init + attribute \src "simple/issuer.py:178" + wire width 2 \fsm_state + attribute \src "simple/issuer.py:178" + wire width 2 \fsm_state$next + attribute \src "simple/issuer.py:238" + wire width 1 $23 + attribute \src "simple/issuer.py:238" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $23 end - process $group_14 - assign \core_core_reset_i 1'0 - assign \core_core_reset_i \dbg_core_rst_o - sync init + attribute \src "simple/issuer.py:242" + wire width 1 $25 + attribute \src "simple/issuer.py:128" + wire width 1 \pc_changed + attribute \src "simple/issuer.py:128" + wire width 1 \pc_changed$next + attribute \src "simple/issuer.py:242" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $25 end process $group_15 - assign \dbg_terminate_i 1'0 - assign \dbg_terminate_i \core_core_terminate_o + assign \core_wen 2'00 + assign \core_wen 2'00 + attribute \src "simple/issuer.py:178" + switch \fsm_state + attribute \src "simple/issuer.py:181" + attribute \nmigen.decoding "IDLE/0" + case 2'00 + attribute \src "simple/issuer.py:203" + attribute \nmigen.decoding "INSN_READ/1" + case 2'01 + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" + case 2'10 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + attribute \src "simple/issuer.py:238" + switch { $23 } + attribute \src "simple/issuer.py:238" + case 1'1 + attribute \src "simple/issuer.py:242" + switch { $25 } + attribute \src "simple/issuer.py:242" + case 1'1 + assign \core_wen 2'01 + end + end + end sync init end - process $group_16 - assign \dbg_core_dbg_pc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \dbg_core_dbg_pc \pc - sync init + attribute \src "simple/issuer.py:238" + wire width 1 $27 + attribute \src "simple/issuer.py:238" + cell $not $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \cur_msr$next - process $group_17 - assign \dbg_core_dbg_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \dbg_core_dbg_msr \cur_msr + attribute \src "simple/issuer.py:242" + wire width 1 $29 + attribute \src "simple/issuer.py:242" + cell $not $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $29 + end + process $group_16 + assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "simple/issuer.py:178" + switch \fsm_state + attribute \src "simple/issuer.py:181" + attribute \nmigen.decoding "IDLE/0" + case 2'00 + attribute \src "simple/issuer.py:203" + attribute \nmigen.decoding "INSN_READ/1" + case 2'01 + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" + case 2'10 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + attribute \src "simple/issuer.py:238" + switch { $27 } + attribute \src "simple/issuer.py:238" + case 1'1 + attribute \src "simple/issuer.py:242" + switch { $29 } + attribute \src "simple/issuer.py:242" + case 1'1 + assign \core_data_i \nia + end + end + end sync init end - attribute \src "simple/issuer.py:160" - wire width 2 \fsm_state - attribute \src "simple/issuer.py:160" - wire width 2 \fsm_state$next - attribute \src "simple/issuer.py:165" - wire width 1 $13 - attribute \src "simple/issuer.py:165" - cell $not $14 + attribute \src "simple/issuer.py:184" + wire width 1 $31 + attribute \src "simple/issuer.py:184" + cell $not $32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $13 + connect \Y $31 end - process $group_18 - assign \core_msr__ren$next \core_msr__ren - assign \core_msr__ren$next 2'00 - attribute \src "simple/issuer.py:160" + attribute \src "simple/issuer.py:184" + wire width 1 $33 + attribute \src "simple/issuer.py:184" + cell $not $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $33 + end + attribute \src "simple/issuer.py:184" + wire width 1 $35 + attribute \src "simple/issuer.py:184" + cell $and $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $31 + connect \B $33 + connect \Y $35 + end + process $group_17 + assign \core_msr__ren 2'00 + assign \core_msr__ren 2'00 + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:165" - switch { $13 } - attribute \src "simple/issuer.py:165" + attribute \src "simple/issuer.py:184" + switch { $35 } + attribute \src "simple/issuer.py:184" case 1'1 - assign \core_msr__ren$next 2'10 + assign \core_msr__ren 2'10 + attribute \src "simple/issuer.py:198" + case end - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \core_msr__ren$next 2'00 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 end sync init - update \core_msr__ren 2'00 - sync posedge \clk - update \core_msr__ren \core_msr__ren$next end - attribute \src "simple/issuer.py:116" - wire width 1 \pc_changed - attribute \src "simple/issuer.py:116" - wire width 1 \pc_changed$next + process $group_18 + assign \dbg_terminate_i 1'0 + assign \dbg_terminate_i \core_core_terminate_o + sync init + end + process $group_19 + assign \dbg_core_dbg_pc 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \dbg_core_dbg_pc \pc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \cur_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \cur_msr$next + process $group_20 + assign \dbg_core_dbg_msr 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \dbg_core_dbg_msr \cur_msr + sync init + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $15 + wire width 1 $37 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $16 + cell $reduce_bool $38 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \core_state_nia_wen - connect \Y $15 + connect \Y $37 end - process $group_19 + process $group_21 assign \pc_changed$next \pc_changed - attribute \src "simple/issuer.py:160" + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 assign \pc_changed$next 1'0 - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:211" - switch { $15 } - attribute \src "simple/issuer.py:211" + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + attribute \src "simple/issuer.py:236" + switch { $37 } + attribute \src "simple/issuer.py:236" case 1'1 assign \pc_changed$next 1'1 end @@ -160713,147 +291167,546 @@ module \test_issuer sync posedge \clk update \pc_changed \pc_changed$next end - attribute \src "simple/issuer.py:165" - wire width 1 $17 - attribute \src "simple/issuer.py:165" - cell $not $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" + wire width 8 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" + wire width 8 \asmcode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \rego_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \rego_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \ea_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \spro_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83" + wire width 1 \xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:83" + wire width 1 \xer_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fasto1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \fasto2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 1 \cr_out_ok$next + attribute \src "simple/issuer.py:238" + wire width 1 $39 + attribute \src "simple/issuer.py:238" + cell $not $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $39 + end + process $group_22 + assign \asmcode$next \asmcode + assign \core_rego$next \core_rego + assign \rego_ok$next \rego_ok + assign \core_ea$next \core_ea + assign \ea_ok$next \ea_ok + assign \core_reg1$next \core_reg1 + assign \core_reg1_ok$next \core_reg1_ok + assign \core_reg2$next \core_reg2 + assign \core_reg2_ok$next \core_reg2_ok + assign \core_reg3$next \core_reg3 + assign \core_reg3_ok$next \core_reg3_ok + assign \core_spro$next \core_spro + assign \spro_ok$next \spro_ok + assign \core_spr1$next \core_spr1 + assign \core_spr1_ok$next \core_spr1_ok + assign \core_xer_in$next \core_xer_in + assign \xer_out$next \xer_out + assign \core_fast1$next \core_fast1 + assign \core_fast1_ok$next \core_fast1_ok + assign \core_fast2$next \core_fast2 + assign \core_fast2_ok$next \core_fast2_ok + assign \core_fasto1$next \core_fasto1 + assign \fasto1_ok$next \fasto1_ok + assign \core_fasto2$next \core_fasto2 + assign \fasto2_ok$next \fasto2_ok + assign \core_cr_in1$next \core_cr_in1 + assign \core_cr_in1_ok$next \core_cr_in1_ok + assign \core_cr_in2$next \core_cr_in2 + assign \core_cr_in2_ok$next \core_cr_in2_ok + assign \core_cr_in2$1$next \core_cr_in2$1 + assign \core_cr_in2_ok$2$next \core_cr_in2_ok$2 + assign \core_cr_out$next \core_cr_out + assign \cr_out_ok$next \cr_out_ok + assign \core_msr$next \core_msr + assign \core_cia$next \core_cia + assign \core_insn$next \core_insn + assign \core_insn_type$next \core_insn_type + assign \core_fn_unit$next \core_fn_unit + assign \core_imm$next \core_imm + assign \core_imm_ok$next \core_imm_ok + assign \core_lk$next \core_lk + assign \core_rc$next \core_rc + assign \core_rc_ok$next \core_rc_ok + assign \core_oe$next \core_oe + assign \core_oe_ok$next \core_oe_ok + assign \core_invert_in$next \core_invert_in + assign \core_zero_a$next \core_zero_a + assign \core_input_carry$next \core_input_carry + assign \core_output_carry$next \core_output_carry + assign \core_input_cr$next \core_input_cr + assign \core_output_cr$next \core_output_cr + assign \core_invert_out$next \core_invert_out + assign \core_is_32bit$next \core_is_32bit + assign \core_is_signed$next \core_is_signed + assign \core_data_len$next \core_data_len + assign \core_byte_reverse$next \core_byte_reverse + assign \core_sign_extend$next \core_sign_extend + assign \core_ldst_mode$next \core_ldst_mode + assign \core_traptype$next \core_traptype + assign \core_trapaddr$next \core_trapaddr + assign \core_read_cr_whole$next \core_read_cr_whole + assign \core_write_cr_whole$next \core_write_cr_whole + assign \core_write_cr0$next \core_write_cr0 + attribute \src "simple/issuer.py:178" + switch \fsm_state + attribute \src "simple/issuer.py:181" + attribute \nmigen.decoding "IDLE/0" + case 2'00 + assign { \core_write_cr0$next \core_write_cr_whole$next \core_read_cr_whole$next \core_trapaddr$next \core_traptype$next \core_ldst_mode$next \core_sign_extend$next \core_byte_reverse$next \core_data_len$next \core_is_signed$next \core_is_32bit$next \core_invert_out$next \core_output_cr$next \core_input_cr$next \core_output_carry$next \core_input_carry$next \core_zero_a$next \core_invert_in$next \core_oe_ok$next \core_oe$next \core_rc_ok$next \core_rc$next \core_lk$next \core_imm_ok$next \core_imm$next \core_fn_unit$next \core_insn_type$next \core_insn$next \core_cia$next \core_msr$next { \cr_out_ok$next \core_cr_out$next } { \core_cr_in2_ok$2$next \core_cr_in2$1$next } { \core_cr_in2_ok$next \core_cr_in2$next } { \core_cr_in1_ok$next \core_cr_in1$next } { \fasto2_ok$next \core_fasto2$next } { \fasto1_ok$next \core_fasto1$next } { \core_fast2_ok$next \core_fast2$next } { \core_fast1_ok$next \core_fast1$next } \xer_out$next \core_xer_in$next { \core_spr1_ok$next \core_spr1$next } { \spro_ok$next \core_spro$next } { \core_reg3_ok$next \core_reg3$next } { \core_reg2_ok$next \core_reg2$next } { \core_reg1_ok$next \core_reg1$next } { \ea_ok$next \core_ea$next } { \rego_ok$next \core_rego$next } \asmcode$next } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "simple/issuer.py:203" + attribute \nmigen.decoding "INSN_READ/1" + case 2'01 + attribute \src "simple/issuer.py:206" + switch { \imem_f_busy_o } + attribute \src "simple/issuer.py:206" + case 1'1 + attribute \src "simple/issuer.py:210" + case + assign { \core_write_cr0$next \core_write_cr_whole$next \core_read_cr_whole$next \core_trapaddr$next \core_traptype$next \core_ldst_mode$next \core_sign_extend$next \core_byte_reverse$next \core_data_len$next \core_is_signed$next \core_is_32bit$next \core_invert_out$next \core_output_cr$next \core_input_cr$next \core_output_carry$next \core_input_carry$next \core_zero_a$next \core_invert_in$next \core_oe_ok$next \core_oe$next \core_rc_ok$next \core_rc$next \core_lk$next \core_imm_ok$next \core_imm$next \core_fn_unit$next \core_insn_type$next \core_insn$next \core_cia$next \core_msr$next { \cr_out_ok$next \core_cr_out$next } { \core_cr_in2_ok$2$next \core_cr_in2$1$next } { \core_cr_in2_ok$next \core_cr_in2$next } { \core_cr_in1_ok$next \core_cr_in1$next } { \fasto2_ok$next \core_fasto2$next } { \fasto1_ok$next \core_fasto1$next } { \core_fast2_ok$next \core_fast2$next } { \core_fast1_ok$next \core_fast1$next } \xer_out$next \core_xer_in$next { \core_spr1_ok$next \core_spr1$next } { \spro_ok$next \core_spro$next } { \core_reg3_ok$next \core_reg3$next } { \core_reg2_ok$next \core_reg2$next } { \core_reg1_ok$next \core_reg1$next } { \ea_ok$next \core_ea$next } { \rego_ok$next \core_rego$next } \asmcode$next } { \dec2_write_cr0 \dec2_write_cr_whole \dec2_read_cr_whole \dec2_trapaddr \dec2_traptype \dec2_ldst_mode \dec2_sign_extend \dec2_byte_reverse \dec2_data_len \dec2_is_signed \dec2_is_32bit \dec2_invert_out \dec2_output_cr \dec2_input_cr \dec2_output_carry \dec2_input_carry \dec2_zero_a \dec2_invert_in \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_imm_ok \dec2_imm \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr { \dec2_cr_out_ok \dec2_cr_out } { \dec2_cr_in2_ok$4 \dec2_cr_in2$3 } { \dec2_cr_in2_ok \dec2_cr_in2 } { \dec2_cr_in1_ok \dec2_cr_in1 } { \dec2_fasto2_ok \dec2_fasto2 } { \dec2_fasto1_ok \dec2_fasto1 } { \dec2_fast2_ok \dec2_fast2 } { \dec2_fast1_ok \dec2_fast1 } \dec2_xer_out \dec2_xer_in { \dec2_spr1_ok \dec2_spr1 } { \dec2_spro_ok \dec2_spro } { \dec2_reg3_ok \dec2_reg3 } { \dec2_reg2_ok \dec2_reg2 } { \dec2_reg1_ok \dec2_reg1 } { \dec2_ea_ok \dec2_ea } { \dec2_rego_ok \dec2_rego } \dec2_asmcode } + end + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" + case 2'10 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + attribute \src "simple/issuer.py:238" + switch { $39 } + attribute \src "simple/issuer.py:238" + case 1'1 + assign { \core_write_cr0$next \core_write_cr_whole$next \core_read_cr_whole$next \core_trapaddr$next \core_traptype$next \core_ldst_mode$next \core_sign_extend$next \core_byte_reverse$next \core_data_len$next \core_is_signed$next \core_is_32bit$next \core_invert_out$next \core_output_cr$next \core_input_cr$next \core_output_carry$next \core_input_carry$next \core_zero_a$next \core_invert_in$next \core_oe_ok$next \core_oe$next \core_rc_ok$next \core_rc$next \core_lk$next \core_imm_ok$next \core_imm$next \core_fn_unit$next \core_insn_type$next \core_insn$next \core_cia$next \core_msr$next { \cr_out_ok$next \core_cr_out$next } { \core_cr_in2_ok$2$next \core_cr_in2$1$next } { \core_cr_in2_ok$next \core_cr_in2$next } { \core_cr_in1_ok$next \core_cr_in1$next } { \fasto2_ok$next \core_fasto2$next } { \fasto1_ok$next \core_fasto1$next } { \core_fast2_ok$next \core_fast2$next } { \core_fast1_ok$next \core_fast1$next } \xer_out$next \core_xer_in$next { \core_spr1_ok$next \core_spr1$next } { \spro_ok$next \core_spro$next } { \core_reg3_ok$next \core_reg3$next } { \core_reg2_ok$next \core_reg2$next } { \core_reg1_ok$next \core_reg1$next } { \ea_ok$next \core_ea$next } { \rego_ok$next \core_rego$next } \asmcode$next } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \rego_ok$next 1'0 + assign \ea_ok$next 1'0 + assign \core_reg1_ok$next 1'0 + assign \core_reg2_ok$next 1'0 + assign \core_reg3_ok$next 1'0 + assign \spro_ok$next 1'0 + assign \core_spr1_ok$next 1'0 + assign \core_fast1_ok$next 1'0 + assign \core_fast2_ok$next 1'0 + assign \fasto1_ok$next 1'0 + assign \fasto2_ok$next 1'0 + assign \core_cr_in1_ok$next 1'0 + assign \core_cr_in2_ok$next 1'0 + assign \core_cr_in2_ok$2$next 1'0 + assign \cr_out_ok$next 1'0 + assign \core_imm_ok$next 1'0 + assign \core_rc_ok$next 1'0 + assign \core_oe_ok$next 1'0 + end + sync init + update \asmcode 8'00000000 + update \core_rego 5'00000 + update \rego_ok 1'0 + update \core_ea 5'00000 + update \ea_ok 1'0 + update \core_reg1 5'00000 + update \core_reg1_ok 1'0 + update \core_reg2 5'00000 + update \core_reg2_ok 1'0 + update \core_reg3 5'00000 + update \core_reg3_ok 1'0 + update \core_spro 10'0000000000 + update \spro_ok 1'0 + update \core_spr1 10'0000000000 + update \core_spr1_ok 1'0 + update \core_xer_in 1'0 + update \xer_out 1'0 + update \core_fast1 3'000 + update \core_fast1_ok 1'0 + update \core_fast2 3'000 + update \core_fast2_ok 1'0 + update \core_fasto1 3'000 + update \fasto1_ok 1'0 + update \core_fasto2 3'000 + update \fasto2_ok 1'0 + update \core_cr_in1 3'000 + update \core_cr_in1_ok 1'0 + update \core_cr_in2 3'000 + update \core_cr_in2_ok 1'0 + update \core_cr_in2$1 3'000 + update \core_cr_in2_ok$2 1'0 + update \core_cr_out 3'000 + update \cr_out_ok 1'0 + update \core_msr 64'0000000000000000000000000000000000000000000000000000000000000000 + update \core_cia 64'0000000000000000000000000000000000000000000000000000000000000000 + update \core_insn 32'00000000000000000000000000000000 + update \core_insn_type 7'0000000 + update \core_fn_unit 11'00000000000 + update \core_imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \core_imm_ok 1'0 + update \core_lk 1'0 + update \core_rc 1'0 + update \core_rc_ok 1'0 + update \core_oe 1'0 + update \core_oe_ok 1'0 + update \core_invert_in 1'0 + update \core_zero_a 1'0 + update \core_input_carry 2'00 + update \core_output_carry 1'0 + update \core_input_cr 1'0 + update \core_output_cr 1'0 + update \core_invert_out 1'0 + update \core_is_32bit 1'0 + update \core_is_signed 1'0 + update \core_data_len 4'0000 + update \core_byte_reverse 1'0 + update \core_sign_extend 1'0 + update \core_ldst_mode 2'00 + update \core_traptype 5'00000 + update \core_trapaddr 13'0000000000000 + update \core_read_cr_whole 1'0 + update \core_write_cr_whole 1'0 + update \core_write_cr0 1'0 + sync posedge \clk + update \asmcode \asmcode$next + update \core_rego \core_rego$next + update \rego_ok \rego_ok$next + update \core_ea \core_ea$next + update \ea_ok \ea_ok$next + update \core_reg1 \core_reg1$next + update \core_reg1_ok \core_reg1_ok$next + update \core_reg2 \core_reg2$next + update \core_reg2_ok \core_reg2_ok$next + update \core_reg3 \core_reg3$next + update \core_reg3_ok \core_reg3_ok$next + update \core_spro \core_spro$next + update \spro_ok \spro_ok$next + update \core_spr1 \core_spr1$next + update \core_spr1_ok \core_spr1_ok$next + update \core_xer_in \core_xer_in$next + update \xer_out \xer_out$next + update \core_fast1 \core_fast1$next + update \core_fast1_ok \core_fast1_ok$next + update \core_fast2 \core_fast2$next + update \core_fast2_ok \core_fast2_ok$next + update \core_fasto1 \core_fasto1$next + update \fasto1_ok \fasto1_ok$next + update \core_fasto2 \core_fasto2$next + update \fasto2_ok \fasto2_ok$next + update \core_cr_in1 \core_cr_in1$next + update \core_cr_in1_ok \core_cr_in1_ok$next + update \core_cr_in2 \core_cr_in2$next + update \core_cr_in2_ok \core_cr_in2_ok$next + update \core_cr_in2$1 \core_cr_in2$1$next + update \core_cr_in2_ok$2 \core_cr_in2_ok$2$next + update \core_cr_out \core_cr_out$next + update \cr_out_ok \cr_out_ok$next + update \core_msr \core_msr$next + update \core_cia \core_cia$next + update \core_insn \core_insn$next + update \core_insn_type \core_insn_type$next + update \core_fn_unit \core_fn_unit$next + update \core_imm \core_imm$next + update \core_imm_ok \core_imm_ok$next + update \core_lk \core_lk$next + update \core_rc \core_rc$next + update \core_rc_ok \core_rc_ok$next + update \core_oe \core_oe$next + update \core_oe_ok \core_oe_ok$next + update \core_invert_in \core_invert_in$next + update \core_zero_a \core_zero_a$next + update \core_input_carry \core_input_carry$next + update \core_output_carry \core_output_carry$next + update \core_input_cr \core_input_cr$next + update \core_output_cr \core_output_cr$next + update \core_invert_out \core_invert_out$next + update \core_is_32bit \core_is_32bit$next + update \core_is_signed \core_is_signed$next + update \core_data_len \core_data_len$next + update \core_byte_reverse \core_byte_reverse$next + update \core_sign_extend \core_sign_extend$next + update \core_ldst_mode \core_ldst_mode$next + update \core_traptype \core_traptype$next + update \core_trapaddr \core_trapaddr$next + update \core_read_cr_whole \core_read_cr_whole$next + update \core_write_cr_whole \core_write_cr_whole$next + update \core_write_cr0 \core_write_cr0$next + end + attribute \src "simple/issuer.py:184" + wire width 1 $41 + attribute \src "simple/issuer.py:184" + cell $not $42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $17 + connect \Y $41 end - process $group_20 + attribute \src "simple/issuer.py:184" + wire width 1 $43 + attribute \src "simple/issuer.py:184" + cell $not $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $43 + end + attribute \src "simple/issuer.py:184" + wire width 1 $45 + attribute \src "simple/issuer.py:184" + cell $and $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $41 + connect \B $43 + connect \Y $45 + end + process $group_85 assign \imem_a_pc_i 48'000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:160" + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:165" - switch { $17 } - attribute \src "simple/issuer.py:165" + attribute \src "simple/issuer.py:184" + switch { $45 } + attribute \src "simple/issuer.py:184" case 1'1 assign \imem_a_pc_i \pc [47:0] + attribute \src "simple/issuer.py:198" + case end - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 end sync init end - attribute \src "simple/issuer.py:165" - wire width 1 $19 - attribute \src "simple/issuer.py:165" - cell $not $20 + attribute \src "simple/issuer.py:184" + wire width 1 $47 + attribute \src "simple/issuer.py:184" + cell $not $48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $19 + connect \Y $47 end - process $group_21 + attribute \src "simple/issuer.py:184" + wire width 1 $49 + attribute \src "simple/issuer.py:184" + cell $not $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $49 + end + attribute \src "simple/issuer.py:184" + wire width 1 $51 + attribute \src "simple/issuer.py:184" + cell $and $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $47 + connect \B $49 + connect \Y $51 + end + process $group_86 assign \imem_a_valid_i 1'0 - attribute \src "simple/issuer.py:160" + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:165" - switch { $19 } - attribute \src "simple/issuer.py:165" + attribute \src "simple/issuer.py:184" + switch { $51 } + attribute \src "simple/issuer.py:184" case 1'1 assign \imem_a_valid_i 1'1 + attribute \src "simple/issuer.py:198" + case end - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" case 1'1 assign \imem_a_valid_i 1'1 - attribute \src "simple/issuer.py:187" + attribute \src "simple/issuer.py:210" case end - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 end sync init end - attribute \src "simple/issuer.py:165" - wire width 1 $21 - attribute \src "simple/issuer.py:165" - cell $not $22 + attribute \src "simple/issuer.py:184" + wire width 1 $53 + attribute \src "simple/issuer.py:184" + cell $not $54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $21 + connect \Y $53 end - process $group_22 + attribute \src "simple/issuer.py:184" + wire width 1 $55 + attribute \src "simple/issuer.py:184" + cell $not $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $55 + end + attribute \src "simple/issuer.py:184" + wire width 1 $57 + attribute \src "simple/issuer.py:184" + cell $and $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $53 + connect \B $55 + connect \Y $57 + end + process $group_87 assign \imem_f_valid_i 1'0 - attribute \src "simple/issuer.py:160" + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:165" - switch { $21 } - attribute \src "simple/issuer.py:165" + attribute \src "simple/issuer.py:184" + switch { $57 } + attribute \src "simple/issuer.py:184" case 1'1 assign \imem_f_valid_i 1'1 + attribute \src "simple/issuer.py:198" + case end - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" case 1'1 assign \imem_f_valid_i 1'1 - attribute \src "simple/issuer.py:187" + attribute \src "simple/issuer.py:210" case end - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 end sync init end - attribute \src "simple/issuer.py:165" - wire width 1 $23 - attribute \src "simple/issuer.py:165" - cell $not $24 + attribute \src "simple/issuer.py:184" + wire width 1 $59 + attribute \src "simple/issuer.py:184" + cell $not $60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $23 + connect \Y $59 end - process $group_23 + attribute \src "simple/issuer.py:184" + wire width 1 $61 + attribute \src "simple/issuer.py:184" + cell $not $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $61 + end + attribute \src "simple/issuer.py:184" + wire width 1 $63 + attribute \src "simple/issuer.py:184" + cell $and $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $59 + connect \B $61 + connect \Y $63 + end + process $group_88 assign \cur_pc$next \cur_pc - attribute \src "simple/issuer.py:160" + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:165" - switch { $23 } - attribute \src "simple/issuer.py:165" + attribute \src "simple/issuer.py:184" + switch { $63 } + attribute \src "simple/issuer.py:184" case 1'1 assign \cur_pc$next \pc + attribute \src "simple/issuer.py:198" + case end - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst @@ -160865,96 +291718,85 @@ module \test_issuer sync posedge \clk update \cur_pc \cur_pc$next end - attribute \src "simple/issuer.py:165" - wire width 1 $25 - attribute \src "simple/issuer.py:165" - cell $not $26 + attribute \src "simple/issuer.py:184" + wire width 1 $65 + attribute \src "simple/issuer.py:184" + cell $not $66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $25 + connect \Y $65 end - process $group_24 - assign \cur_msr$next \cur_msr - attribute \src "simple/issuer.py:160" - switch \fsm_state - attribute \src "simple/issuer.py:163" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:165" - switch { $25 } - attribute \src "simple/issuer.py:165" - case 1'1 - assign \cur_msr$next \core_msr__data_o - end - attribute \src "simple/issuer.py:182" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" - case 2'10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \cur_msr$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \cur_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \clk - update \cur_msr \cur_msr$next + attribute \src "simple/issuer.py:184" + wire width 1 $67 + attribute \src "simple/issuer.py:184" + cell $not $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $67 end - attribute \src "simple/issuer.py:165" - wire width 1 $27 - attribute \src "simple/issuer.py:165" - cell $not $28 + attribute \src "simple/issuer.py:184" + wire width 1 $69 + attribute \src "simple/issuer.py:184" + cell $and $70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $27 + connect \A $65 + connect \B $67 + connect \Y $69 end - attribute \src "simple/issuer.py:213" - wire width 1 $29 - attribute \src "simple/issuer.py:213" - cell $not $30 + attribute \src "simple/issuer.py:238" + wire width 1 $71 + attribute \src "simple/issuer.py:238" + cell $not $72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $29 + connect \Y $71 end - process $group_25 + process $group_89 assign \fsm_state$next \fsm_state - attribute \src "simple/issuer.py:160" + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:165" - switch { $27 } - attribute \src "simple/issuer.py:165" + attribute \src "simple/issuer.py:184" + switch { $69 } + attribute \src "simple/issuer.py:184" case 1'1 assign \fsm_state$next 2'01 + attribute \src "simple/issuer.py:198" + case end - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" case 1'1 - attribute \src "simple/issuer.py:187" + attribute \src "simple/issuer.py:210" case assign \fsm_state$next 2'10 end - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:213" - switch { $29 } - attribute \src "simple/issuer.py:213" + assign \fsm_state$next 2'11 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + attribute \src "simple/issuer.py:238" + switch { $71 } + attribute \src "simple/issuer.py:238" case 1'1 assign \fsm_state$next 2'00 end @@ -160969,347 +291811,413 @@ module \test_issuer sync posedge \clk update \fsm_state \fsm_state$next end - attribute \src "simple/issuer.py:115" - wire width 32 \current_insn - attribute \src "simple/issuer.py:193" - wire width 32 $31 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 $32 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87" + wire width 1 \core_stopped_i + attribute \src "simple/issuer.py:184" + wire width 1 $73 + attribute \src "simple/issuer.py:184" + cell $not $74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \cur_pc [2] - connect \B 6'100000 - connect \Y $32 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $73 end - attribute \src "simple/issuer.py:193" - cell $shift $34 + attribute \src "simple/issuer.py:184" + wire width 1 $75 + attribute \src "simple/issuer.py:184" + cell $not $76 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $75 + end + attribute \src "simple/issuer.py:184" + wire width 1 $77 + attribute \src "simple/issuer.py:184" + cell $and $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 32 - connect \A \imem_f_instr_o - connect \B $32 - connect \Y $31 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $73 + connect \B $75 + connect \Y $77 end - process $group_26 - assign \current_insn 32'00000000000000000000000000000000 - attribute \src "simple/issuer.py:160" + process $group_90 + assign \core_stopped_i 1'0 + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:182" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:183" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:184" + switch { $77 } + attribute \src "simple/issuer.py:184" case 1'1 - attribute \src "simple/issuer.py:187" + attribute \src "simple/issuer.py:198" case - assign \current_insn $31 + assign \core_stopped_i 1'1 end - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:203" + attribute \nmigen.decoding "INSN_READ/1" + case 2'01 + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 end sync init end - attribute \src "simple/issuer.py:207" - wire width 1 $35 - attribute \src "simple/issuer.py:207" - cell $ne $36 + attribute \src "simple/issuer.py:184" + wire width 1 $79 + attribute \src "simple/issuer.py:184" + cell $not $80 parameter \A_SIGNED 0 - parameter \A_WIDTH 7 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $79 + end + attribute \src "simple/issuer.py:184" + wire width 1 $81 + attribute \src "simple/issuer.py:184" + cell $not $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $81 + end + attribute \src "simple/issuer.py:184" + wire width 1 $83 + attribute \src "simple/issuer.py:184" + cell $and $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \core_insn_type - connect \B 7'0000001 - connect \Y $35 + connect \A $79 + connect \B $81 + connect \Y $83 end - process $group_27 - assign \core_valid 1'0 - attribute \src "simple/issuer.py:160" + process $group_91 + assign \dbg_core_stopped_i 1'0 + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:182" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:183" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:184" + switch { $83 } + attribute \src "simple/issuer.py:184" case 1'1 - attribute \src "simple/issuer.py:187" + attribute \src "simple/issuer.py:198" case - assign \core_valid 1'1 + assign \dbg_core_stopped_i 1'1 end - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:203" + attribute \nmigen.decoding "INSN_READ/1" + case 2'01 + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:207" - switch { $35 } - attribute \src "simple/issuer.py:207" - case 1'1 - assign \core_valid 1'1 - end + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 end sync init end - process $group_28 - assign \core_issue_i 1'0 - attribute \src "simple/issuer.py:160" + process $group_92 + assign \cur_msr$next \cur_msr + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:183" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:183" - case 1'1 - attribute \src "simple/issuer.py:187" - case - assign \core_issue_i 1'1 - end - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + assign \cur_msr$next \core_msr__data_o + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \cur_msr$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init + update \cur_msr 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \cur_msr \cur_msr$next end - attribute \src "simple/issuer.py:118" - wire width 32 \ilatch - attribute \src "simple/issuer.py:118" - wire width 32 \ilatch$next - process $group_29 - assign \core_raw_opcode_in 32'00000000000000000000000000000000 - attribute \src "simple/issuer.py:160" + attribute \src "simple/issuer.py:216" + wire width 32 $85 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 $86 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \cur_pc [2] + connect \B 6'100000 + connect \Y $86 + end + attribute \src "simple/issuer.py:216" + cell $shift $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 32 + connect \A \imem_f_instr_o + connect \B $86 + connect \Y $85 + end + process $group_93 + assign \dec2_raw_opcode_in 32'00000000000000000000000000000000 + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" case 1'1 - attribute \src "simple/issuer.py:187" + attribute \src "simple/issuer.py:210" case - assign \core_raw_opcode_in \current_insn + assign \dec2_raw_opcode_in $85 end - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 - assign \core_raw_opcode_in \ilatch + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 end sync init end - process $group_30 - assign \ilatch$next \ilatch - attribute \src "simple/issuer.py:160" + process $group_94 + assign \dec2_dec2_pc 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \dec2_dec2_msr 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" case 1'1 - attribute \src "simple/issuer.py:187" + attribute \src "simple/issuer.py:210" case - assign \ilatch$next \current_insn + assign { \dec2_dec2_msr \dec2_dec2_pc } { \cur_msr \cur_pc } end - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ilatch$next 32'00000000000000000000000000000000 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 end sync init - update \ilatch 32'00000000000000000000000000000000 - sync posedge \clk - update \ilatch \ilatch$next end - process $group_31 - assign \core_dec2_pc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_dec2_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:160" + attribute \src "simple/issuer.py:130" + wire width 32 \ilatch + attribute \src "simple/issuer.py:130" + wire width 32 \ilatch$next + attribute \src "simple/issuer.py:216" + wire width 32 $89 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 $90 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \cur_pc [2] + connect \B 6'100000 + connect \Y $90 + end + attribute \src "simple/issuer.py:216" + cell $shift $92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 32 + connect \A \imem_f_instr_o + connect \B $90 + connect \Y $89 + end + process $group_96 + assign \ilatch$next \ilatch + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:183" + attribute \src "simple/issuer.py:206" case 1'1 - attribute \src "simple/issuer.py:187" + attribute \src "simple/issuer.py:210" case - assign { \core_dec2_msr \core_dec2_pc } { \cur_msr \cur_pc } + assign \ilatch$next $89 end - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 - assign { \core_dec2_msr \core_dec2_pc } { \cur_msr \cur_pc } + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \ilatch$next 32'00000000000000000000000000000000 end sync init + update \ilatch 32'00000000000000000000000000000000 + sync posedge \clk + update \ilatch \ilatch$next end - attribute \src "simple/issuer.py:213" - wire width 1 $37 - attribute \src "simple/issuer.py:213" - cell $not $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $37 - end - attribute \src "simple/issuer.py:217" - wire width 1 $39 - attribute \src "simple/issuer.py:217" - cell $not $40 + attribute \src "simple/issuer.py:234" + wire width 1 $93 + attribute \src "simple/issuer.py:234" + cell $ne $94 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $39 + connect \A \core_insn_type + connect \B 7'0000001 + connect \Y $93 end - process $group_33 - assign \core_wen 2'00 - attribute \src "simple/issuer.py:160" + process $group_97 + assign \core_ivalid_i 1'0 + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:213" - switch { $37 } - attribute \src "simple/issuer.py:213" + assign \core_ivalid_i 1'1 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 + attribute \src "simple/issuer.py:234" + switch { $93 } + attribute \src "simple/issuer.py:234" case 1'1 - attribute \src "simple/issuer.py:217" - switch { $39 } - attribute \src "simple/issuer.py:217" - case 1'1 - assign \core_wen 2'01 - end + assign \core_ivalid_i 1'1 end end sync init end - attribute \src "simple/issuer.py:213" - wire width 1 $41 - attribute \src "simple/issuer.py:213" - cell $not $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $41 - end - attribute \src "simple/issuer.py:217" - wire width 1 $43 - attribute \src "simple/issuer.py:217" - cell $not $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $43 - end - process $group_34 - assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:160" + process $group_98 + assign \core_issue_i 1'0 + attribute \src "simple/issuer.py:178" switch \fsm_state - attribute \src "simple/issuer.py:163" + attribute \src "simple/issuer.py:181" attribute \nmigen.decoding "IDLE/0" case 2'00 - attribute \src "simple/issuer.py:182" + attribute \src "simple/issuer.py:203" attribute \nmigen.decoding "INSN_READ/1" case 2'01 - attribute \src "simple/issuer.py:206" - attribute \nmigen.decoding "INSN_ACTIVE/2" + attribute \src "simple/issuer.py:225" + attribute \nmigen.decoding "INSN_START/2" case 2'10 - attribute \src "simple/issuer.py:213" - switch { $41 } - attribute \src "simple/issuer.py:213" - case 1'1 - attribute \src "simple/issuer.py:217" - switch { $43 } - attribute \src "simple/issuer.py:217" - case 1'1 - assign \core_data_i \nia - end - end + assign \core_issue_i 1'1 + attribute \src "simple/issuer.py:233" + attribute \nmigen.decoding "INSN_ACTIVE/3" + case 2'11 end sync init end - attribute \src "simple/issuer.py:229" - wire width 128 $45 - attribute \src "simple/issuer.py:229" - wire width 128 $46 - attribute \src "simple/issuer.py:229" - cell $sshl $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 128 - connect \A 1'1 - connect \B \dbg_dbg_gpr_addr - connect \Y $46 + process $group_99 + assign \core_dmi__addr 5'00000 + attribute \src "simple/issuer.py:250" + switch { \dbg_dbg_gpr_req } + attribute \src "simple/issuer.py:250" + case 1'1 + assign \core_dmi__addr \dbg_dbg_gpr_addr [4:0] + end + sync init end - connect $45 $46 - process $group_35 + process $group_100 assign \core_dmi__ren 1'0 - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:250" switch { \dbg_dbg_gpr_req } - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:250" case 1'1 - assign \core_dmi__ren $45 [0] + assign \core_dmi__ren 1'1 end sync init end - process $group_36 + attribute \src "simple/issuer.py:258" + wire width 1 \d_reg_delay + attribute \src "simple/issuer.py:258" + wire width 1 \d_reg_delay$next + process $group_101 + assign \d_reg_delay$next \d_reg_delay + assign \d_reg_delay$next \dbg_dbg_gpr_req + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \d_reg_delay$next 1'0 + end + sync init + update \d_reg_delay 1'0 + sync posedge \clk + update \d_reg_delay \d_reg_delay$next + end + process $group_102 assign \dbg_dbg_gpr_data 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:225" - switch { \dbg_dbg_gpr_req } - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:260" + switch { \d_reg_delay } + attribute \src "simple/issuer.py:260" case 1'1 assign \dbg_dbg_gpr_data \core_dmi__data_o end sync init end - process $group_37 + process $group_103 assign \dbg_dbg_gpr_ack 1'0 - attribute \src "simple/issuer.py:225" - switch { \dbg_dbg_gpr_req } - attribute \src "simple/issuer.py:225" + attribute \src "simple/issuer.py:260" + switch { \d_reg_delay } + attribute \src "simple/issuer.py:260" case 1'1 assign \dbg_dbg_gpr_ack 1'1 end